JP2013235948A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2013235948A
JP2013235948A JP2012107151A JP2012107151A JP2013235948A JP 2013235948 A JP2013235948 A JP 2013235948A JP 2012107151 A JP2012107151 A JP 2012107151A JP 2012107151 A JP2012107151 A JP 2012107151A JP 2013235948 A JP2013235948 A JP 2013235948A
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conductor
electrode pad
convex portion
semiconductor device
pad
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JP5884625B2 (en
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Toshinori Miura
敏徳 三浦
Shinichi Yamada
真一 山田
Tetsuya Nishiguchi
哲也 西口
Tsuyoshi Noyori
剛示 野寄
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Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
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Meidensha Electric Manufacturing Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]

Abstract

PROBLEM TO BE SOLVED: To reduce contact resistance between an electrode pad and a conductor in a pressure-contact semiconductor device.SOLUTION: A semiconductor device 1 comprises a conductor 4 brought into pressure contact with an electrode pad 3 on a semiconductor element 2 and harder than the electrode pad 3. A concave-convex part 5 is formed on an end surface of the conductor 4 bonded to the electrode pad 3. A salient 53 having a spiry longitudinal surface is formed at an edge part of a salient 51 in the concave-convex part 5. The end surface of the conductor 4 having the concave-convex part 5 is preferably covered with a conductive material softer than the electrode pad 3 and the conductor 4 and having low electric resistance.

Description

本発明は半導体デバイスにおける圧接構造、特に半導体素子上の電極パッドと導体との圧接構造に関する。   The present invention relates to a pressure contact structure in a semiconductor device, and more particularly to a pressure contact structure between an electrode pad on a semiconductor element and a conductor.

代表的な絶縁型パワー半導体モジュールとして、インバータ等の電力変換装置に用いられるIGBT(Insulated Gate Bipolar Transistor:絶縁ゲートバイポーラトランジスタ)モジュールがある。また、このIGBTモジュールに代表される「絶縁型パワー半導体モジュール」若しくは「Isolated power semiconductor devices」はそれぞれJEC−2407−2007、IEC60747−15にて規格が制定されている。   As a typical insulated power semiconductor module, there is an IGBT (Insulated Gate Bipolar Transistor) module used in a power converter such as an inverter. In addition, standards for “insulated power semiconductor modules” or “Isolated power semiconductor devices” typified by this IGBT module are established in JEC-2407-2007 and IEC60747-15, respectively.

非特許文献1に開示された一般的な絶縁型パワー半導体モジュールの構造について説明する。図4(a)に示された絶縁型パワー半導体モジュール60において、図4(b)に示されたスイッチング素子であるIGBTやダイオード等の半導体素子61はその下面電極層を介してDBC(Direct Bond Copper)基板62の銅回路箔63上にはんだ付けされる。DBC基板62はセラミックス等からなる絶縁板64の両面に銅回路箔63を直接接合したものである。DBC基板62は放熱のための銅ベース65に、はんだ部66を介して接続される。   The structure of a general insulated power semiconductor module disclosed in Non-Patent Document 1 will be described. In the insulated power semiconductor module 60 shown in FIG. 4A, the semiconductor element 61 such as an IGBT or a diode which is the switching element shown in FIG. 4B is connected to a DBC (Direct Bond) via its lower electrode layer. Copper) Soldered onto the copper circuit foil 63 of the substrate 62. The DBC substrate 62 is obtained by directly bonding a copper circuit foil 63 to both surfaces of an insulating plate 64 made of ceramics or the like. The DBC substrate 62 is connected to a copper base 65 for heat dissipation via a solder portion 66.

半導体素子61の上面電極層はアルミワイヤー67を超音波でボンディングされ、例えばDBC基板62上のもう一つの銅回路箔63と電気的に接続される。そして、DBC基板62の銅回路箔63から外部へ電気を接続するための銅端子68は銅回路箔63とはんだ付けにより接続されている。さらにこの周りをプラスチックのケース69で囲み、その中を電気絶縁のためのシリコーンゲル等が充填されている。ここで、一般に半導体素子61,DBC基板62間のはんだ接合部はDBC基板62,銅ベース65間のはんだ接合部に対し、融点が高く、2回のリフローにより接合されている。   The upper electrode layer of the semiconductor element 61 is bonded with an aluminum wire 67 with ultrasonic waves and is electrically connected to, for example, another copper circuit foil 63 on the DBC substrate 62. A copper terminal 68 for connecting electricity from the copper circuit foil 63 of the DBC substrate 62 to the outside is connected to the copper circuit foil 63 by soldering. Further, this is surrounded by a plastic case 69 and filled with silicone gel or the like for electrical insulation. Here, generally, the solder joint between the semiconductor element 61 and the DBC substrate 62 has a high melting point and is joined by two reflows to the solder joint between the DBC substrate 62 and the copper base 65.

近年、半導体素子の動作温度の高温化が進んでおり、動作温度が175℃〜200℃となっており、汎用的なはんだ材料の融点に近い。このため、代替的な材料として金属系高温はんだ(Bi,Zn,Au)、化合物系高温はんだ(Sn−Cu)、低温焼結金属(Agナノペースト)等が提案されている。また、次世代の半導体素子であるSiCは250〜300℃での動作が報告されている。   In recent years, the operating temperature of semiconductor elements has been increased, and the operating temperature is 175 to 200 ° C., which is close to the melting point of general-purpose solder materials. For this reason, metal-based high-temperature solder (Bi, Zn, Au), compound-based high-temperature solder (Sn—Cu), low-temperature sintered metal (Ag nanopaste), and the like have been proposed as alternative materials. Further, SiC, which is a next-generation semiconductor element, has been reported to operate at 250 to 300 ° C.

一方、はんだ接続を採用していない半導体モジュールとして図5(a)に例示した平型圧接構造パッケージ70が知られている(非特許文献1,2等)。図5(b)に示したように平型圧接構造パッケージ70内の半導体素子71の上面電極層はコンタクト端子72に接触した状態でMo板73上に備えられている。そして、半導体素子71の端部には半導体素子71及びコンタクト端子72の位置決めをするガイド74が備えられている。   On the other hand, a flat pressure contact structure package 70 illustrated in FIG. 5A is known as a semiconductor module that does not employ solder connection (Non-Patent Documents 1, 2, etc.). As shown in FIG. 5B, the upper electrode layer of the semiconductor element 71 in the flat pressure contact structure package 70 is provided on the Mo plate 73 in contact with the contact terminals 72. A guide 74 for positioning the semiconductor element 71 and the contact terminal 72 is provided at the end of the semiconductor element 71.

平型圧接構造パッケージ70は半導体素子71を両面から冷却できると共にはんだを用いないで電気的、熱的に外部と接続できる。このため、一般的に平型圧接構造パッケージ70の両端をヒートシンクで圧接することで当該パッケージ70の両面を冷却すると共にそのヒートシンクを導電部材として用いている。   The flat pressure contact structure package 70 can cool the semiconductor element 71 from both sides and can be electrically and thermally connected to the outside without using solder. For this reason, both sides of the flat pressure contact structure package 70 are generally pressed by heat sinks to cool both surfaces of the package 70 and the heat sink is used as a conductive member.

前記圧接は平型圧接構造パッケージ70の上下のヒートシンク間とで電気的に絶縁する必要があること、当該圧接は板バネで行うがその設計圧接力が平型圧接構造パッケージ70の電極ポストに均等にかかるようにする必要がある。圧接が不良であった場合は半導体素子71の破壊につながる。また、回路を構成するのに、このヒートシンクや圧接のため板バネが小型化の妨げとなるなど使いこなすには熟練を要する。   The pressure contact must be electrically insulated between the upper and lower heat sinks of the flat pressure contact structure package 70, and the pressure contact is performed by a leaf spring, but the design pressure contact force is equal to the electrode post of the flat pressure contact structure package 70. It is necessary to make it take. If the pressure contact is poor, the semiconductor element 71 is destroyed. In addition, skill is required for constructing the circuit, for example, because the heat sink and the pressure spring contact the leaf spring to prevent downsizing.

このことから平型圧接構造パッケージ70は限られた装置への適用となり、代わりに使い勝手のよい前記絶縁型パワー半導体モジュールが広く用いられていた。   For this reason, the flat type pressure contact structure package 70 is applied to a limited apparatus, and the above-described insulating power semiconductor module which is easy to use has been widely used instead.

温度サイクル、パワーサイクル等への信頼性を向上するには半導体モジュールを構成する各部材(半導体、金属、セラミックス等)の熱膨張の違いにより生じる課題がある。すなわち、DBC基板‐銅ベース間、DBC基板‐銅端子間において、銅とセラミックスの熱膨張係数の差から間のはんだにせん断応力が働き、はんだに亀裂が生じて熱抵抗が増大し、端子が剥離する虞がある。さらに、半導体素子‐DBC基板間のはんだにも亀裂が生じる場合がある。条件によっては半導体素子上のアルミワイヤーの接続部でも、アルミニウムと半導体素子の熱膨張の差で応力が発生してアルミワイヤーが疲労破断する。   In order to improve the reliability to temperature cycle, power cycle, etc., there is a problem caused by the difference in thermal expansion of each member (semiconductor, metal, ceramics, etc.) constituting the semiconductor module. That is, between the DBC substrate and the copper base, and between the DBC substrate and the copper terminal, a shear stress acts on the solder between the copper and ceramics due to the difference in thermal expansion coefficient. There is a risk of peeling. Furthermore, cracks may also occur in the solder between the semiconductor element and the DBC substrate. Depending on the conditions, even at the connection portion of the aluminum wire on the semiconductor element, stress is generated due to the difference in thermal expansion between the aluminum and the semiconductor element, and the aluminum wire is fatigued.

近年、年々電力密度が増すこと及び半導体素子内部の接合温度が高くなっていることから、はんだ接合部のせん断応力、アルミワイヤーにかかる応力が大きくなってきている。これに対して熱膨張の影響が半導体モジュールの設計寿命に至るまでの期間の間は顕在化しないようにする必要がある。SiCやGaNのような高温で使用できるワイドバンドキャップ半導体素子の出現によりさらに熱膨張の影響の低減が要求される。   In recent years, since the power density increases year by year and the bonding temperature inside the semiconductor element increases, the shear stress at the solder joint and the stress applied to the aluminum wire have increased. On the other hand, it is necessary to prevent the influence of thermal expansion from becoming apparent during the period until the design life of the semiconductor module is reached. With the advent of wide-band cap semiconductor elements that can be used at high temperatures such as SiC and GaN, further reduction of the effect of thermal expansion is required.

電気学会高性能高機能パワーデバイス・パワーIC調査専門委員会編,「パワーデバイス・パワーICハンドブック」,コロナ社,1996.7,p.289,p.336The Institute of Electrical Engineers, High Performance and High Functionality Power Device / Power IC Research Special Edition, “Power Device / Power IC Handbook”, Corona, 1996. 6.7, p.289, p.336 森 睦宏、関 康和,「大容量IGBTの最近の進歩」,電気学会誌Vol.118,1998,p276Akihiro Mori, Yasukazu Seki, “Recent Advances in Large Capacity IGBTs”, The Institute of Electrical Engineers of Japan, Vol. 118, 1998, p276

特開平5−13409号公報Japanese Patent Laid-Open No. 5-13409

高信頼性、環境性、利便性を同時に実現するために、圧接のようにはんだ接合、あるいはワイヤーボンドを用いず、且つ使い勝手の良い絶縁形パワー半導体モジュールの実現が求められている。また、SiC、GaN等の高温で使用可能な半導体素子の性能を活かす半導体モジュールとしても、温度サイクル、パワーサイクル等の信頼性の向上が求められている。   In order to achieve high reliability, environmental friendliness, and convenience at the same time, there is a need to realize an easy-to-use insulated power semiconductor module that does not use solder bonding or wire bonding like pressure welding. Further, semiconductor modules that make use of the performance of semiconductor elements that can be used at high temperatures, such as SiC and GaN, are also required to have improved reliability such as temperature cycle and power cycle.

しかしながら、圧接構造は半導体チップ上の電極パッドに導体が直接接触しているが、この接触面を介した電流経路には、図6(a)に示したように、電極パッド81と導体82との界面状態に起因する接触抵抗が存在する。この原因として、図6(b)に示したように、表面の汚れ、吸着物、表面酸化物等の皮膜、加工に伴う変質層、表面粗さに応じた空隙層83等が挙げられる。これらの接触面では圧接力によって接触部分が摺動、皮膜の一部が破れ、押し付けられることによって抵抗の低い部材が接触すると導通状態となるが、電極の材質本来の抵抗率と比べると著しく大きくなる。   However, in the pressure contact structure, the conductor is in direct contact with the electrode pad on the semiconductor chip. However, as shown in FIG. 6A, the electrode pad 81 and the conductor 82 There is a contact resistance due to the interface state. As this cause, as shown in FIG. 6 (b), surface contamination, adsorbed material, surface oxide film, altered layer accompanying processing, void layer 83 according to surface roughness, and the like can be mentioned. On these contact surfaces, the contact portion slides due to the pressure contact force, and a part of the film is broken and pressed, and when a low resistance member comes into contact, it becomes conductive, but it is significantly larger than the original resistivity of the electrode material. Become.

そこで、請求項1の半導体デバイスは、半導体素子上の電極パッドに圧接する当該パッドよりも硬質の導体を備え、前記パッドと接合する導体の端面には凹凸部が形成され、この凹凸部における凸部の縁部には縦断面尖塔状の凸部が形成されたことを特徴とする。本発明によれば、電極パッドと導体との接合面積が拡大し、当該パッドと導体との接触抵抗が低減する。特に、電極パッドへの導体の圧接時に、より小さな圧接力で当該パッドと導体との接触抵抗を低減できる。また、圧接力のばらつきに対して電極パッドと導体との間の抵抗分布を抑制し易くなる。   Accordingly, the semiconductor device according to claim 1 includes a conductor harder than the pad pressed against the electrode pad on the semiconductor element, and an uneven portion is formed on an end surface of the conductor joined to the pad. A convex part having a spire-like longitudinal section is formed at the edge of the part. According to the present invention, the bonding area between the electrode pad and the conductor is increased, and the contact resistance between the pad and the conductor is reduced. In particular, when the conductor is pressed against the electrode pad, the contact resistance between the pad and the conductor can be reduced with a smaller pressing force. Moreover, it becomes easy to suppress the resistance distribution between the electrode pad and the conductor with respect to the variation in the pressure contact force.

請求項2の半導体デバイスは、請求項1の半導体デバイスにおいて、前記凹凸部を有する導体の端面は前記パッド及び導体よりも軟質で電気抵抗の低い導電性材料によって被覆されたことを特徴とする。本発明によれば電極パッドと導体との接触抵抗がさらに低減する。   A semiconductor device according to a second aspect is characterized in that, in the semiconductor device according to the first aspect, an end face of the conductor having the concavo-convex portion is covered with a conductive material that is softer and lower in electrical resistance than the pad and the conductor. According to the present invention, the contact resistance between the electrode pad and the conductor is further reduced.

請求項3の半導体デバイスは、請求項2の半導体デバイスにおいて、前記被覆の膜厚が前記端面の表面粗さよりも厚いことを特徴とする。本発明によれば電極パッドと当接する導体の端面の表面粗さに起因する微細な凹凸間の空隙が導電性材料によって充足されるので当該パッドと導体との接触抵抗がさらに一層低減する。   According to a third aspect of the present invention, in the semiconductor device of the second aspect, the film thickness of the coating is larger than the surface roughness of the end face. According to the present invention, since the gap between the fine irregularities due to the surface roughness of the end face of the conductor in contact with the electrode pad is filled with the conductive material, the contact resistance between the pad and the conductor is further reduced.

請求項4の半導体デバイスは、請求項1から3のいずれかの半導体デバイスにおいて、前記凸部の下端から前記縦断面尖塔状の凸部の頂点までの距離は前記パッドの厚さ以下であることを特徴とする。本発明によれば電極パッドと導体とが接合した際に当該導体の凹凸部が当該パッドの厚さの範囲内に納まる。   The semiconductor device according to claim 4 is the semiconductor device according to any one of claims 1 to 3, wherein a distance from a lower end of the convex portion to an apex of the convex portion having a spire shape in the longitudinal section is equal to or less than a thickness of the pad. It is characterized by. According to the present invention, when the electrode pad and the conductor are joined, the uneven portion of the conductor falls within the thickness range of the pad.

請求項5の半導体デバイスは、請求項1から4のいずれかの半導体デバイスにおいて、前記縦断面尖塔状の凸部を有する凹凸部はイオンミリングによって形成されることを特徴とする。本発明によれば凹凸部における凸部の縁部に縦断面尖塔状の凸部を効率的に形成できる。   A semiconductor device according to a fifth aspect is the semiconductor device according to any one of the first to fourth aspects, wherein the concavo-convex part having the convex part having a spire shape in the longitudinal section is formed by ion milling. According to the present invention, a convex portion having a spire shape in the longitudinal section can be efficiently formed at the edge of the convex portion in the concave and convex portion.

したがって、以上の発明によれば圧接型の半導体デバイスにおける電極パッドと導体との接触抵抗を低減できる。   Therefore, according to the above invention, the contact resistance between the electrode pad and the conductor in the pressure contact type semiconductor device can be reduced.

本発明の実施形態の導体と電極パッドとの接合状態を示した縦断面図。The longitudinal cross-sectional view which showed the joining state of the conductor and electrode pad of embodiment of this invention. (a)は本発明の実施形態における半導体デバイスの縦断面図,(b)は同デバイスの斜視図。(A) is a longitudinal cross-sectional view of the semiconductor device in embodiment of this invention, (b) is a perspective view of the device. 凸部の縁部に縦断面尖塔状の凸部を形成させる工程(a)〜(d)の説明図。Explanatory drawing of the process (a)-(d) which forms the convex part of a longitudinal cross-section spire in the edge of a convex part. (a)ははんだ接続型半導体モジュールの斜視図,(b)は同モジュールにおける半導体素子上の電極パッド周辺の縦断面図。(A) is a perspective view of a solder connection type semiconductor module, (b) is a longitudinal cross-sectional view around an electrode pad on a semiconductor element in the module. (a)は圧接型半導体モジュールの斜視図,(b)は同モジュールの縦断面図。(A) is a perspective view of a press-contact type semiconductor module, (b) is a longitudinal cross-sectional view of the module. (a)は従来の導体と電極パッドとの接触状態を説明した縦断面図,(b)は同状態の拡大縦断面図。(A) is the longitudinal cross-sectional view explaining the contact state of the conventional conductor and electrode pad, (b) is an expanded longitudinal cross-sectional view of the same state.

以下に図面を参照しながら本発明の実施形態の半導体デバイスについて説明する。尚、本発明はこの実施形態に限定されるものではなく特許請求の範囲内で種々変形して実施することができる。   A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. The present invention is not limited to this embodiment, and can be implemented with various modifications within the scope of the claims.

図1に示された本実施形態の半導体デバイス1は半導体素子2上の電極パッド3に圧接する当該パッド3よりも硬質の導体4を備える。電極パッド3と接合する導体4の端面には凸部51,凹部52から成る凹凸部5が複数形成されている。また、凸部51の縁部には縦断面尖塔状の凸部53が形成されている。   The semiconductor device 1 of the present embodiment shown in FIG. 1 includes a conductor 4 that is harder than the pad 3 that presses against the electrode pad 3 on the semiconductor element 2. A plurality of concave and convex portions 5 including convex portions 51 and concave portions 52 are formed on the end face of the conductor 4 to be joined to the electrode pad 3. Further, a convex portion 53 having a spire-like longitudinal section is formed at the edge of the convex portion 51.

導体4の態様としては図2(a)に例示された圧接型の半導体モジュール20に具備された導体41〜43が挙げられる。導体41〜43は半導体素子2上の電極パッド21〜23をそれぞれ引出電極24〜26と導通させるための導体である。特に、導体43は、半導体素子2上にてゲートパッドとして機能している電極パッド23に接続される導体であって、針状に形成されている。   Examples of the conductor 4 include the conductors 41 to 43 provided in the pressure contact type semiconductor module 20 illustrated in FIG. The conductors 41 to 43 are conductors for electrically connecting the electrode pads 21 to 23 on the semiconductor element 2 to the extraction electrodes 24 to 26, respectively. In particular, the conductor 43 is a conductor connected to the electrode pad 23 functioning as a gate pad on the semiconductor element 2 and is formed in a needle shape.

パワー半導体チップにおいては、電極パッド3の材質として数%のSiを含有するAl合金が数ミクロン〜十ミクロン程度の厚さに製膜加工して用いられている。これに対して圧接型のパワー半導体チップにおいて、コンタクト電極として適用される導体4には温度変化時の半導体チップとの熱膨張差による界面応力発生を低減させ、圧接力を完全に半導体チップに伝えるために、Mo合金やW合金等の低熱膨張、高硬度金属を主成分とするもの用いられている。その他には大電流を流さないゲート電極等には前記低熱膨張、高硬度金属を主成分とする先端径1mm以下の針状の導体4が適用されている。   In the power semiconductor chip, an Al alloy containing several percent of Si is used as a material for the electrode pad 3 after being formed into a thickness of several microns to about 10 microns. On the other hand, in the pressure contact type power semiconductor chip, the conductor 4 applied as a contact electrode reduces the generation of interface stress due to the difference in thermal expansion with the semiconductor chip when the temperature changes, and the pressure contact force is completely transmitted to the semiconductor chip. For this reason, a material mainly composed of a low thermal expansion, high hardness metal such as Mo alloy or W alloy is used. In addition, the needle-like conductor 4 having a tip diameter of 1 mm or less, the main component of which is the low thermal expansion and high hardness metal, is applied to a gate electrode or the like that does not flow a large current.

以上の半導体素子2,導体41〜43,引出電極24〜26から成る積層体は図2(b)に示したようにセラミックケース27に収納される。そして、引出電極24,26には絶縁部材28aを介して冷却部材29aが、引出電極25には絶縁部材28bを介して冷却部材29bが配置される。   The laminated body composed of the semiconductor element 2, the conductors 41 to 43, and the lead electrodes 24 to 26 is housed in the ceramic case 27 as shown in FIG. A cooling member 29a is disposed on the extraction electrodes 24 and 26 via an insulating member 28a, and a cooling member 29b is disposed on the extraction electrode 25 via an insulating member 28b.

凸部53を有する凹凸部5はイオンミリング法によって導体4の端面に形成される。具体的には、電極パッド3を構成する材料(例えばAl合金)よりも硬質の材料(例えばMo合金,W合金等)から成る導体4の端面に、この導体4の材料から成る凹凸部5がイオンミリング法によって形成される。この方法には例えば特許文献1(段落[0003])に開示されたイオンミリング法が適用される。イオンミリング法はAr等の不活性ガスのプラズマを被加工物に物理的に衝突させて対象物を除去する方法である。尚、凸部51の下端から縦断面尖塔状の凸部53の頂点までの距離H1は電極パッド3の厚さH2以下に設定すると、導体4と電極パッド3とが接合した際に導体4の凹凸部5を電極パッド3の厚さH2の範囲内に納めることができる。   The concave / convex portion 5 having the convex portion 53 is formed on the end face of the conductor 4 by an ion milling method. Specifically, the uneven portion 5 made of the material of the conductor 4 is formed on the end face of the conductor 4 made of a material (for example, Mo alloy, W alloy) harder than the material (for example, Al alloy) constituting the electrode pad 3. It is formed by an ion milling method. For example, the ion milling method disclosed in Patent Document 1 (paragraph [0003]) is applied to this method. The ion milling method is a method of removing a target object by physically causing plasma of an inert gas such as Ar to collide with a workpiece. When the distance H1 from the lower end of the convex portion 51 to the apex of the convex portion 53 having a spire-like vertical section is set to be equal to or less than the thickness H2 of the electrode pad 3, the conductor 4 and the electrode pad 3 are joined when the conductor 4 and the electrode pad 3 are joined. The uneven portion 5 can be accommodated within the range of the thickness H <b> 2 of the electrode pad 3.

図3を参照しながらイオンミリング法の具体的な工程(a)〜(d)について説明する。   Specific steps (a) to (d) of the ion milling method will be described with reference to FIG.

工程(a):電極パッド3を構成する材料(例えばAl合金)よりも硬質の材料(例えばMo合金,W合金等)から成る導体4の端面上に当該導体4と同じ材料から成る金属層501が形成される。尚、導体4の端面は平坦であり、予め、表面粗さRaが例えば0.5μm以下に加工される。   Step (a): A metal layer 501 made of the same material as the conductor 4 on the end face of the conductor 4 made of a material (for example, Mo alloy, W alloy, etc.) harder than the material (for example, Al alloy) constituting the electrode pad 3 Is formed. The end face of the conductor 4 is flat, and the surface roughness Ra is processed in advance to, for example, 0.5 μm or less.

工程(b):前記形成された金属層501上に感光性樹脂から成るレジスト層502が直接形成され、このレジスト層502がパターンニングされる。具体的には、感光性樹脂が電極パッド3の厚さ以下に塗布され、既知のフォトリソグラフィ技術により、導体4の端面の形状(例えば円形)に応じて例えば直径数ミクロン〜数十ミクロンの円形パターンのレジスト層502が均等に配置される。   Step (b): A resist layer 502 made of a photosensitive resin is directly formed on the formed metal layer 501, and this resist layer 502 is patterned. Specifically, a photosensitive resin is applied to the thickness of the electrode pad 3 or less, and a circular shape having a diameter of several microns to several tens of microns, for example, according to the shape (for example, circular shape) of the end face of the conductor 4 by a known photolithography technique. The resist layer 502 of the pattern is evenly arranged.

工程(c):前記パターンニングされたレジスト層502をマスクとしたイオンミリング法によるエッチングにより金属層501がパターンニングされる。この工程で金属層501から飛散した当該層501の成分はレジスト層502の側壁に衝突して付着する。   Step (c): The metal layer 501 is patterned by etching by an ion milling method using the patterned resist layer 502 as a mask. In this step, the component of the layer 501 scattered from the metal layer 501 collides with and adheres to the side wall of the resist layer 502.

工程(d):そして、有機溶剤を用いたウェットエッチングまたはオゾンガスを用いたドライエッチングによりレジスト層502が除去されることで、パターンニングされた金属層501が導体4の端面上に形成される。この金属層501の縁部には工程(c)で飛散した同層501の成分から成る縦断面尖塔状のバリ層503が残留した状態となっている。この金属層501,バリ層503がそれぞれ図1に示された凹凸部5の凸部51,凸部53となる。   Step (d): Then, the patterned metal layer 501 is formed on the end face of the conductor 4 by removing the resist layer 502 by wet etching using an organic solvent or dry etching using ozone gas. At the edge of the metal layer 501, a burr layer 503 having a spire-like longitudinal section made of the components of the same layer 501 scattered in the step (c) remains. The metal layer 501 and the burr layer 503 become the convex part 51 and the convex part 53 of the concave-convex part 5 shown in FIG.

上記の工程(a)〜(d)により、縁部にバリ層503を有する複数の金属層501がパターンニングされることで、半導体素子2上の電極パッド3と接合する導体4の端面にて凸部51,53,凹部52から成る複数の凹凸部5が効率的に形成される。   By patterning the plurality of metal layers 501 having the burr layer 503 at the edge by the above-described steps (a) to (d), at the end face of the conductor 4 joined to the electrode pad 3 on the semiconductor element 2. A plurality of concave and convex portions 5 including the convex portions 51 and 53 and the concave portion 52 are efficiently formed.

また、導体4の端面の表面粗さに起因する空隙をなくすため、工程(d)の後に導体4の端面上を導電性材料にて被膜すると、電極パッド3と導体4との接触抵抗がさらに低減する。例えば、電極パッド3がAl合金から成り、導体4がMo合金またはW合金から成る場合、この電極パッド3,導体4よりも軟質で電気抵抗の低い導電性材料として例えばAg合金が真空蒸着法によって導体4の端面に所定の膜厚(例えば約0.5μm)で被膜される。製膜はメッキ法、スパッタ蒸着法等の他の方法によって行ってもよい。尚、前記被覆の膜厚は電極パッド3と当接する導体4の端面の表面粗さよりも厚くすると、当該端面の表面粗さに起因する微細な凹凸間の空隙が導電性材料により充足され、電極パッド3と導体4との接触抵抗をさらに低減させることができる。   Moreover, in order to eliminate the space | gap resulting from the surface roughness of the end surface of the conductor 4, when the end surface of the conductor 4 is coated with a conductive material after the step (d), the contact resistance between the electrode pad 3 and the conductor 4 is further increased. To reduce. For example, when the electrode pad 3 is made of an Al alloy and the conductor 4 is made of an Mo alloy or a W alloy, an Ag alloy, for example, is formed by a vacuum deposition method as a conductive material that is softer and lower in electrical resistance than the electrode pad 3 and the conductor 4. The end face of the conductor 4 is coated with a predetermined film thickness (for example, about 0.5 μm). The film formation may be performed by other methods such as a plating method and a sputter deposition method. When the film thickness of the coating is made thicker than the surface roughness of the end face of the conductor 4 in contact with the electrode pad 3, the gap between the fine irregularities due to the surface roughness of the end face is filled with the conductive material. The contact resistance between the pad 3 and the conductor 4 can be further reduced.

工程(a)〜(d)で製造された導体4が半導体素子2上の電極パッド3に圧接すると、図1に示したように導体4の凹凸部5が電極パッド3の酸化膜や吸着被膜等を突き破りパッド3の内部に食い込む。電極パッド3に圧接する導体4の端面に凹凸部5が形成されたことで、電極パッド3と導体4との接合面積が拡大した状態となる。これにより、導体4は凹凸部5を有しない導体と比べて電極パッド3との接触抵抗が低減したものとなる。   When the conductor 4 manufactured in the steps (a) to (d) is in pressure contact with the electrode pad 3 on the semiconductor element 2, the uneven portion 5 of the conductor 4 becomes an oxide film or an adsorption coating on the electrode pad 3 as shown in FIG. Etc. and dig into the inside of the pad 3. By forming the concavo-convex portion 5 on the end face of the conductor 4 in pressure contact with the electrode pad 3, the bonding area between the electrode pad 3 and the conductor 4 is expanded. As a result, the contact resistance between the conductor 4 and the electrode pad 3 is reduced as compared with a conductor that does not have the uneven portion 5.

特に、凹凸部5における凸部51の縁部には凸部53が形成されることで、電極パッド3と導体4との接合面積がさらに拡大し、電極パッド3と導体4との接触抵抗がさらに低減する。そして、電極パッド3への導体4の圧接時に、より小さな圧接力で電極パッド3と導体4との接触抵抗を低減できる。また、圧接力のばらつきに対して電極パッド3と導体4との間の抵抗分布を抑制し易くなる。   In particular, the convex portion 53 is formed at the edge of the convex portion 51 in the concave and convex portion 5, so that the bonding area between the electrode pad 3 and the conductor 4 is further expanded, and the contact resistance between the electrode pad 3 and the conductor 4 is reduced. Further reduction. When the conductor 4 is pressed against the electrode pad 3, the contact resistance between the electrode pad 3 and the conductor 4 can be reduced with a smaller pressing force. Moreover, it becomes easy to suppress the resistance distribution between the electrode pad 3 and the conductor 4 with respect to the variation in the pressure contact force.

さらに、凹凸部5を有する導体4の端面に電極パッド3及び導体4よりも軟質で電気抵抗の低い導電性材料が被覆されることで、電極パッド3と導体4の接触抵抗がさらに低減する。   Furthermore, the end surface of the conductor 4 having the concavo-convex portion 5 is covered with a conductive material that is softer and lower in electrical resistance than the electrode pad 3 and the conductor 4, thereby further reducing the contact resistance between the electrode pad 3 and the conductor 4.

また、前記被覆の膜厚が前記端面の表面粗さよりも厚く設定されることで、電極パッド3と当接する導体4の端面の表面粗さに起因する微細な凹凸間の空隙が導電性材料によって充足され、当該パッド3と導体4との接触抵抗をさらに一層低減させることができる。   In addition, since the film thickness of the coating is set to be thicker than the surface roughness of the end surface, the gap between the fine irregularities due to the surface roughness of the end surface of the conductor 4 in contact with the electrode pad 3 is caused by the conductive material. As a result, the contact resistance between the pad 3 and the conductor 4 can be further reduced.

さらに、凸部51の下端から凸部53の頂点までの距離H1が電極パッド3の厚さ以下に設定されることで、電極パッド3と導体4とが接合した際に導体4の凹凸部5が電極パッド3の厚さの範囲内に納まる。   Furthermore, when the distance H1 from the lower end of the convex portion 51 to the apex of the convex portion 53 is set to be equal to or less than the thickness of the electrode pad 3, the concave and convex portion 5 of the conductor 4 when the electrode pad 3 and the conductor 4 are joined. Falls within the thickness range of the electrode pad 3.

また、凸部53を有する凹凸部5は、イオンミリング法により、凹凸部5における凸部51の縁部に凸部53を効率的に形成できる。   Moreover, the uneven | corrugated | grooved part 5 which has the convex part 53 can form the convex part 53 efficiently in the edge part of the convex part 51 in the uneven | corrugated | grooved part 5 by the ion milling method.

1…半導体デバイス
2…半導体素子
3…電極パッド
4…導体
5…凹凸部,51,53…凸部,52…凹部
DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 2 ... Semiconductor element 3 ... Electrode pad 4 ... Conductor 5 ... Uneven part, 51, 53 ... Convex part, 52 ... Concave part

Claims (5)

半導体素子上の電極パッドに圧接する当該パッドよりも硬質の導体を備え、
前記パッドと接合する導体の端面には凹凸部が形成され、この凹凸部における凸部の縁部には縦断面尖塔状の凸部が形成されたこと
を特徴とする半導体デバイス。
Provided with a harder conductor than the pad pressed against the electrode pad on the semiconductor element,
A semiconductor device, wherein an uneven portion is formed on an end face of a conductor to be joined to the pad, and a convex portion having a spire shape in the longitudinal section is formed at an edge of the convex portion in the uneven portion.
前記凹凸部を有する導体の端面は前記パッド及び導体よりも軟質で電気抵抗の低い導電性材料によって被覆されたこと
を特徴とする請求項1に記載の半導体デバイス。
2. The semiconductor device according to claim 1, wherein an end face of the conductor having the concavo-convex portion is covered with a conductive material that is softer and lower in electrical resistance than the pad and the conductor.
前記被覆の膜厚が前記端面の表面粗さよりも厚いこと
を特徴とする請求項2に記載の半導体デバイス。
The semiconductor device according to claim 2, wherein a film thickness of the coating is thicker than a surface roughness of the end face.
前記凸部の下端から前記縦断面尖塔状の凸部の頂点までの距離は前記パッドの厚さ以下であること
を特徴とする請求項1から3のいずれかに記載の半導体デバイス。
The semiconductor device according to any one of claims 1 to 3, wherein a distance from a lower end of the convex portion to a vertex of the convex portion having a spire shape in the longitudinal section is equal to or less than a thickness of the pad.
前記縦断面尖塔状の凸部を有する凹凸部はイオンミリングによって形成されること
を特徴とする請求項1から4のいずれかに記載の半導体デバイス。
5. The semiconductor device according to claim 1, wherein the concavo-convex portion having the convex portion having a spire shape in the longitudinal section is formed by ion milling.
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US20220278060A1 (en) * 2020-12-07 2022-09-01 Infineon Technologies Ag Molded semiconductor package with high voltage isolation

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Publication number Priority date Publication date Assignee Title
CN110416187A (en) * 2019-06-28 2019-11-05 西安中车永电电气有限公司 A kind of novel crimping Formulas I GBT internal enclosing structure
CN110416187B (en) * 2019-06-28 2021-07-09 西安中车永电电气有限公司 Novel crimping type IGBT (insulated gate bipolar transistor) internal packaging structure
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