TW201712840A - Semiconductor package structure - Google Patents

Abstract

A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.

Description

Semiconductor package structure

The disclosure relates to a semiconductor package structure.

Through power electronics technology, power can be transformed and controlled under instantaneous large voltage, and the digitalization of power control has become a future trend, making power electronics technology increasingly important. Among them, the power component module has a considerable impact on the development of the power electronics market, and its application range not only plays a pivotal role in new energy equipment, wind power generation, solar energy, electric vehicles, green buildings, etc., used in daily life. High-speed railways, smart grids, and inverter home appliances are also closely related to power electronics technology.

Power component module packaging technologies include: power component package electrical, thermal analog technology and power module system package (SiP) process integration, die attach process and wire bonding technology. As the size and thickness of power semiconductor wafers continue to shrink and thin with advances in technology, there are even metal oxide semi-transistors (MOSFETs) measuring 50 micrometers (μm). In other words, today's thin wafer assemblies actually Face a more severe test. Therefore, relevant industry players are committed to research and development of power component module packaging technology to improve assembly yield and reliability.

The disclosure relates to a semiconductor package structure. Example The glue layer is located between the guard ring and the first lead frame, thereby reducing the electric field effect around the guard ring, thereby maintaining a higher withstand voltage of the integral component, and at the same time having the effect of protecting the semiconductor wafer and supporting the overall structure.

According to an embodiment of the present disclosure, a semiconductor package is proposed Loading structure. The semiconductor package structure includes a semiconductor wafer, a guard ring, a glue layer, and a first lead frame. The guard ring is disposed on the semiconductor wafer, and the glue layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor wafer, and the glue layer is located between the guard ring and the first lead frame.

According to another embodiment of the present disclosure, a semiconductor is proposed Package structure. The semiconductor package structure includes a semiconductor wafer, a guard ring, a solder, a first lead frame, and a glue layer. The guard ring and solder are disposed on the semiconductor wafer. The first lead frame is electrically connected to the semiconductor wafer via solder. The glue layer is disposed on the semiconductor wafer and between the semiconductor wafer and the first lead frame, and the height of the glue layer is equal to or greater than the height of the solder.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below in detail as follows:

10, 20, 30, 40, 50, 60, 70, 80‧‧‧ semiconductor package structure

100‧‧‧Semiconductor wafer

100G‧‧‧ gate contacts

100s‧‧‧ side

200‧‧‧protection ring

200a‧‧‧ top surface

200s‧‧‧ side

300‧‧ ‧ adhesive layer

400‧‧‧First lead frame

500, 510, 520‧‧‧ solder

600‧‧‧Second lead frame

700‧‧‧Shell

710‧‧‧electrode layer

800‧‧‧ third lead frame

900‧‧‧Substrate

910‧‧‧metal layer

920‧‧‧Ceramic layer

930‧‧‧ patterned metal layer

960‧‧‧floor

980‧‧‧Package layer

1B-1B', 2B-2B', 3B-3B', 4B-4B', 8B-8B'‧‧‧ hatching

H1, H2, H3‧‧‧ height

L‧‧‧ length

W1‧‧‧ first width

W2‧‧‧ second width

W3‧‧‧ third width

FIG. 1A is a top view of a semiconductor package structure according to an embodiment of the present disclosure.

Fig. 1B is a schematic cross-sectional view along section line 1B-1B'.

FIG. 2A is a diagram showing a semiconductor package structure according to another embodiment of the disclosure. Top view.

Fig. 2B is a schematic cross-sectional view along section line 2B-2B'.

FIG. 3A is a top view of a semiconductor package structure according to still another embodiment of the disclosure.

Fig. 3B is a schematic cross-sectional view along section line 3B-3B'.

FIG. 4A is a top view of a semiconductor package structure according to still another embodiment of the present disclosure.

Fig. 4B is a schematic cross-sectional view along section line 4B-4B'.

FIG. 5 is a schematic diagram of a semiconductor package structure according to a further embodiment of the disclosure.

FIG. 6 is a schematic diagram of a semiconductor package structure according to still another embodiment of the present disclosure.

FIG. 7 is a top view of a semiconductor package structure according to still another embodiment of the present disclosure.

FIG. 8A is a top view of a semiconductor package structure according to still another embodiment of the present disclosure.

Fig. 8B is a schematic cross-sectional view along section line 8B-8B'.

In an embodiment of the present disclosure, the glue layer is located between the guard ring and the first lead frame, thereby reducing the electric field effect around the guard ring, thereby maintaining a higher withstand voltage of the integral component, and simultaneously protecting the semiconductor wafer and supporting The effect of the overall structure. The embodiments of the present disclosure are described in detail below. The details of the embodiments are for illustrative purposes and are not intended to limit the scope of the disclosure. Those who have the usual knowledge can be based on the actual implementation of the group Modification or change.

FIG. 1A illustrates a semiconductor package in accordance with an embodiment of the present disclosure Above the structure, Figure 1B shows a schematic cross-sectional view along section line 1B-1B'. As shown in FIGS. 1A-1B, the semiconductor package structure 10 includes a semiconductor wafer 100, a guard ring 200, a glue layer 300, and a first lead frame 400. The guard ring 200 is disposed on the semiconductor wafer 100, and the glue layer 300 is disposed on the guard ring 400. The first lead frame 400 is electrically connected to the semiconductor wafer 100, and the glue layer 300 is located between the guard ring 200 and the first lead frame 400.

In a common process, it is usually electrically connected to the wire by wire bonding. The conductor wafer, in this way, the contact area between the wire and the wafer is relatively small (the wire diameter is about 280-380 micrometers (μm)), and the wire diameter is the contact point between the wire and the wafer, when the area is too small, not only The uneven heat dissipation of the semiconductor wafer causes the current to be distributed only in local areas (for example, lines and contact points), and also causes the current density of the local area of the component to be too high, and also causes the heat dissipation of the line to be difficult. In contrast, according to the embodiment of the present disclosure, the first lead frame 400 is electrically connected to the semiconductor wafer 100, and the soldering area between the first lead frame 400 and the semiconductor wafer 100 is relatively large, and the large contact area not only makes the heat dissipation It is fast and relatively uniform, and the current density of the large-area contact area can also be small, and the smaller current density also makes the resistance and the thermal resistance can be reduced, and the average temperature and the average current of the component can be achieved, thereby improving the overall The performance and stability of the components.

Moreover, according to an embodiment of the present disclosure, the glue layer 300 is located in the insurance Between the guard ring 200 and the first lead frame 400, the electric field effect around the guard ring 200 can be reduced, thereby maintaining a higher withstand voltage of the integral component, and at the same time having the effect of protecting the semiconductor wafer 100 and supporting the overall structure. Further, the glue layer 300 The fabrication requires only an additional dispensing process and does not require additional development of new processes, so it can be easily adjusted using existing semiconductor processes and variability in accordance with the size or shape of different semiconductor wafers 100, and can also be supported. A lead frame 400 is not tilted, thereby improving current transfer characteristics and thermal conductivity.

In some embodiments, the semiconductor wafer 100 can be a gold oxide semi-electric crystal. Body (MOSFET), insulated gate bipolar transistor (IGBT), junction field effect transistor (JFET) or a diode.

In an embodiment, the material of the adhesive layer 300 is an insulating material, for example, It includes at least one of a silicone gel and an epoxy resin.

As shown in FIGS. 1A to 1B, in the embodiment, the semiconductor package structure 10 further includes a solder 500. The solder 500 is disposed on the semiconductor wafer 100, and the semiconductor wafer 100 is electrically connected to the first lead frame 400 via the solder 500.

In an embodiment, the material of the solder 500 may include lead-free solder, high lead At least one of solder, nano silver sintered material, and dual-phase solid-liquid interdiffusion bonding (dual-phase SLID bonding).

As shown in FIG. 1A, in the embodiment, the first lead frame 400 has A first width W1, the region of the semiconductor wafer 100 exposed to the guard ring 200 has a second width W2 in the direction of the first width W1, and the first width W1 is, for example, 40 to 100% of the second width W2. For example, the total width of the semiconductor wafer 100 along the first width W1 is, for example, about 3 millimeters (mm), the width of the guard ring 200 is about 30 to 700 micrometers (μm), and the first width W1 is, for example, 2.3 to 2.97 mm. .

In an embodiment, the material of the first lead frame 400 is, for example, a conductive gold. Genus. For example, the first lead frame 400 may include copper, or aluminum or iron whose surface is nickel plated.

As shown in FIG. 1A, the adhesive layer 300 is oriented along the first width W1. Has a length L. In some embodiments, the length L is equal to or smaller than the first width W1, so the first lead frame 400 and the guard ring 200 may be completely separated by the glue layer 300. In the embodiment shown in FIG. 1A, the length L of the glue layer 300 extending along the guard ring 200 is substantially equal to the first width W1 of the first lead frame 400. In another embodiment, the length L of the adhesive layer 300 may also be smaller than the first width W1 of the first lead frame 400 (not shown).

FIG. 2A illustrates a semiconductor package of another embodiment of the disclosure. The top view of the structure is shown in Fig. 2B, which is a cross-sectional view taken along section line 2B-2B'. The same or similar components as those of the above-mentioned embodiments are denoted by the same or similar components, and the related descriptions of the same or similar components are referred to the foregoing, and are not described herein again. The difference between this embodiment and the embodiment shown in FIGS. 1A to 1B is mainly in the design of the adhesive layer 300.

As shown in the embodiment shown in FIGS. 2A-2B, the semiconductor package structure The glue layer 300 of 20 covers one side 200s of the guard ring 200 and one side 100s of the semiconductor wafer 100.

According to an embodiment of the present disclosure, the glue layer 300 wraps the guard ring 200 The side 200s and the side 100s of the semiconductor wafer 100 can prevent the solder under the semiconductor wafer 100 from being squeezed to the side 100s of the semiconductor wafer 100, avoiding the solder 500 over the semiconductor wafer 100 and the solder bridge underneath, and avoiding The solder 500 or the first lead frame 400 contacts or is too close to the guard ring 200 to affect the operational function of the semiconductor wafer 100, thereby improving the solder 500/solder contact half. The problem of bridging the side faces 100s of the conductor wafer 100 can further regulate the soldering area and height of the solder 500 over the semiconductor wafer 100 and the first lead frame 400.

In an embodiment, as shown in FIGS. 2A-2B, the glue layer 300 is along the guard ring. The length L of the extension 200 is greater than the first width W1 of the first lead frame 400 such that the first lead frame 400 and the guard ring 200 can be completely separated by the glue layer 300. Also, in the range extending along the length L, the glue layer 300 covers the top surface 200a of the guard ring 200 and the two side faces 200s.

FIG. 3A is a diagram showing a semiconductor package according to still another embodiment of the disclosure. Figure 3B shows a cross-sectional view along section line 3B-3B'. The same or similar components as those of the above-mentioned embodiments are denoted by the same or similar components, and the related descriptions of the same or similar components are referred to the foregoing, and are not described herein again. The difference between this embodiment and the foregoing embodiment lies mainly in the design of the glue layer 300.

As shown in the embodiment shown in FIGS. 3A-3B, the semiconductor package structure The glue layer 300 of 30 completely covers the guard ring 200. The adhesive layer 300 made of an insulating material completely covers the guard ring 200 and the semiconductor wafer 100. Thus, the solder 500/solder bridge short circuit of the solder 500 extruded to the side of the semiconductor wafer 100, above and below the semiconductor wafer 100 can be solved. And the problem that the solder 500 or the first lead frame 400 is in contact with or too close to the electrical influence of the guard ring 200 can not only effectively control the solder 500/solder area of the semiconductor wafer 100, but also control the tin-over problem of the semiconductor wafer 100. It can greatly improve assembly yield and reliability.

As shown in FIG. 3A, the semiconductor wafer 100 is exposed to the adhesive layer 300. The outer region has a third width W3 in the direction of the first width W1. In some embodiments, the first width W1 is equal to or smaller than the third width W3. In the embodiment shown in FIG. 3A, the first width W1 is smaller than the third width W3. In another embodiment, The first width W1 may also be equal to the third width W3 (not shown in the figure).

FIG. 4A illustrates a semiconductor package of still another embodiment of the disclosure. Figure 4B shows a cross-sectional view along section line 4B-4B'. The same or similar components as those of the above-mentioned embodiments are denoted by the same or similar components, and the related descriptions of the same or similar components are referred to the foregoing, and are not described herein again.

As shown in the embodiment shown in FIGS. 4A-4B, the semiconductor package structure The 40 further includes a substrate 900 and a second lead frame 600. One of the gate contacts 100G of the semiconductor wafer 100 is electrically connected to the substrate 900 via the second lead frame 600.

In an embodiment, the semiconductor wafer 100 is, for example, a gold oxide semi-transistor. (MOSFET) or insulated gate bipolar transistor (IGBT), the semiconductor package structure 40 may further include an additional lead frame (not shown in the figure), and the emitter contact of the semiconductor chip 100 may be additionally via this The lead frame is electrically connected to the substrate 900.

In an embodiment, the substrate 900 is, for example, direct plating copper (direct plated) A copper, DPC) substrate, a direct bonded copper (DBC) substrate, a metal substrate, or a printed circuit (PCB) substrate, and the material of the metal substrate may include copper, aluminum, or stainless steel. The substrate 900 may have a single layer or a multilayer structure.

FIG. 5 is a diagram showing a semiconductor package according to a further embodiment of the disclosure. Schematic diagram of the structure. The same or similar components as those of the above-mentioned embodiments are denoted by the same or similar components, and the related descriptions of the same or similar components are referred to the foregoing, and are not described herein again.

In the embodiment shown in FIG. 5, the semiconductor package structure 50 is further included. A substrate 900, a housing 700, an electrode layer 710, and a third lead frame 800 are included. The outer casing 700 is used to house the substrate 900 and the semiconductor wafer 100. Electrode layer The 710 is disposed on the outer casing 700, and the substrate 900 is electrically connected to the electrode layer 710 on the outer casing 700 via the third lead frame 800.

In an embodiment, the substrate 900 is, for example, a multilayer structure including a metal layer 910, ceramic layer 920 and patterned metal layer 930, semiconductor wafer 100 is connected to patterned metal layer 930 via solder 510. Moreover, the semiconductor package structure 50 further selectively includes a bottom plate 960 disposed on the bottom plate 960 via the solder 520. The bottom plate 960 is, for example, a metal substrate, and the material thereof may include copper, aluminum, or stainless steel.

FIG. 6 is a diagram showing a semiconductor package of still another embodiment of the present disclosure. Schematic diagram of the structure. The same or similar components as those of the above-mentioned embodiments are denoted by the same or similar components, and the related descriptions of the same or similar components are referred to the foregoing, and are not described herein again.

In the embodiment shown in FIG. 6, in the semiconductor package structure 60, The substrate 900 is electrically connected to an external power source (not shown) via the third lead frame 800.

And, as shown in FIG. 6, in the embodiment, the semiconductor package structure The package 60 further includes an encapsulant layer 980 that encapsulates the semiconductor wafer 100, the guard ring 200, the glue layer 300, the first lead frame 400, and a portion of the third lead frame 800.

FIG. 7 is a diagram showing a semiconductor package according to still another embodiment of the present disclosure. The top view of the structure. The same or similar components as those of the above-mentioned embodiments are denoted by the same or similar components, and the related descriptions of the same or similar components are referred to the foregoing, and are not described herein again.

In the embodiment shown in FIG. 7, the base of the semiconductor package structure 70 The board 900 is a printed circuit board.

FIG. 8A is a diagram showing a semiconductor of still another embodiment of the disclosure. The top view of the package structure, and Fig. 8B shows a schematic cross-sectional view along section line 8B-8B'. The same or similar components as those of the above-mentioned embodiments are denoted by the same or similar components, and the related descriptions of the same or similar components are referred to the foregoing, and are not described herein again. The difference between this embodiment and the embodiment shown in FIGS. 1A to 1B is mainly in the design of the adhesive layer 300.

As shown in FIGS. 8A-8B, the semiconductor package structure 80 includes a semiconductor The body wafer 100, the guard ring 200, the solder 500, the first lead frame 400, and the glue layer 300. The guard ring 200 and the solder 500 are disposed on the semiconductor wafer 100, and the first lead frame 400 is electrically connected to the semiconductor wafer 100 via the solder 500. The glue layer 300 is disposed on the semiconductor wafer 100 and between the semiconductor wafer 100 and the first lead frame 400. In some embodiments, the height H1 of the glue layer 300 is, for example, equal to or greater than the height H2 of the solder 500.

As in the embodiment shown in Figures 8A-8B, the height of the glue layer 300 H1 is substantially equal to the height H2 of the solder 500. In another embodiment, the height H1 of the glue layer 300 may be greater than the height H2 of the solder 500 (not shown). Further, in the embodiment shown in FIGS. 8A-8B, the height H1 of the glue layer 300 is greater than the height H3 of the guard ring 200.

In the embodiment, as shown in Figures 8A-8B, the glue layer 300 is protected. Between the ring 200 and the solder 500.

In some embodiments, the length L of the glue layer 300 may be equal to or greater than The first width W1 of the first lead frame 400. As shown in FIG. 8A, in the present embodiment, the length L of the adhesive layer 300 is greater than the first width W1 of the first lead frame 400.

As shown in FIGS. 8A-8B, in the embodiment, the guard ring 200, the adhesive layer 300, and the solder 500 are separated from each other. In some embodiments, any two of the guard ring 200, the glue layer 300, and the solder 500 may also be in contact with one another (not shown).

It should be noted that the structural configuration of the substrate 900, the outer casing 700, the electrode layer 710, the third lead frame 800, the solders 510 and 520, and the encapsulant layer 980 in the embodiments described in FIGS. 5-7 are the same as those herein. The structural configurations of the embodiments described in the drawings 1A to 4B and 8A to 8B can be replaced with each other according to actual conditions.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10‧‧‧Semiconductor package structure

100‧‧‧Semiconductor wafer

200‧‧‧protection ring

300‧‧ ‧ adhesive layer

400‧‧‧First lead frame

500‧‧‧ solder

Claims (20)

A semiconductor package structure comprising: a semiconductor wafer; a guard ring disposed on the semiconductor wafer; a glue layer disposed on the guard ring; and a first lead frame, electrical Connected to the semiconductor wafer, wherein the glue layer is between the guard ring and the first lead frame. The semiconductor package structure of claim 1, wherein the adhesive layer covers a side of the guard ring and a side of the semiconductor wafer. The semiconductor package structure of claim 1, wherein the adhesive layer completely covers the guard ring. The semiconductor package structure of claim 1, wherein the adhesive layer comprises at least one of a silicon gel and an epoxy resin. The semiconductor package structure of claim 1, wherein the semiconductor wafer is a metal oxide semi-transistor (MOSFET), an insulated gate bipolar transistor (IGBT), and a junction field effect transistor (JFET). ) or a diode. The semiconductor package structure of claim 1, further comprising: a solder disposed on the semiconductor wafer, wherein the semiconductor crystal The sheet is electrically connected to the first lead frame via the solder. The semiconductor package structure of claim 6, wherein the solder comprises a lead-free solder, a high-lead solder, a nano-silver sintered material, and a dual-phase solid-liquid interdiffusion bonding (dual-phase solid-liquid interdiffusion bonding) (dual-phase SLID bonding) at least one of them. The semiconductor package structure of claim 1, wherein the first lead frame has a first width, and a region of the semiconductor wafer exposed to the guard ring has a second width along a direction of the first width The first width is 40 to 100% of the second width. The semiconductor package structure of claim 1, further comprising: a substrate; and a second lead frame, wherein a gate contact of the semiconductor chip is electrically connected to the substrate via the second lead frame. The semiconductor package structure of claim 1, further comprising: a substrate; and a housing for accommodating the substrate and the semiconductor wafer; an electrode layer disposed on the housing; And a third lead frame, the substrate is electrically connected to the electrode layer on the outer casing via the third lead frame. The semiconductor package structure of claim 1, further comprising: a substrate; and a third lead frame electrically connected to the external power source via the third lead frame. A semiconductor package structure comprising: a semiconductor wafer; a guard ring disposed on the semiconductor wafer; a solder disposed on the semiconductor wafer; and a first lead frame via The solder is electrically connected to the semiconductor wafer; and a glue layer is disposed on the semiconductor wafer and located between the semiconductor wafer and the first lead frame, wherein a height of the adhesive layer is equal to or greater than one of the solder height. The semiconductor package structure of claim 12, wherein the adhesive layer is between the guard ring and the solder. The semiconductor package structure of claim 12, wherein the adhesive layer comprises at least one of a silicon gel and an epoxy resin. The semiconductor package structure of claim 12, wherein the semiconductor wafer is a metal oxide semi-transistor (MOSFET), an insulated gate bipolar A crystal (IGBT), a junction field effect transistor (JFET) or a diode. The semiconductor package structure of claim 12, wherein the solder comprises a lead-free solder, a high-lead solder, a nano-silver sintered material, and a dual-phase solid-liquid interdiffusion bonding (dual-phase solid-liquid interdiffusion bonding) (dual-phase SLID bonding) at least one of them. The semiconductor package structure of claim 12, wherein the first lead frame has a first width, and a region of the semiconductor wafer exposed to the guard ring has a second width along a direction of the first width The first width is 40 to 100% of the second width. The semiconductor package structure of claim 12, further comprising: a substrate; and a second lead frame, wherein a gate contact of the semiconductor chip is electrically connected to the substrate via the second lead frame. The semiconductor package structure of claim 12, further comprising: a substrate; and a housing for accommodating the substrate and the semiconductor wafer; an electrode layer disposed on the housing; a third lead frame, the substrate is electrically connected to the outer casing via the third lead frame The electrode layer on it. The semiconductor package structure of claim 12, further comprising a substrate; and a third lead frame electrically connected to the external power source via the third lead frame.