TWI666754B - Semiconductor package structure - Google Patents

Abstract

The disclosure provides a semiconductor package structure. The semiconductor package structure includes a semiconductor wafer, a guard ring, an adhesive layer, and a first lead frame. The protection ring is disposed on the semiconductor wafer, and the adhesive layer is disposed on the protection ring. The first lead frame is electrically connected to the semiconductor wafer, and an adhesive layer is located between the protection ring and the first lead frame.

Description

Semiconductor packaging structure

This disclosure relates to a semiconductor package structure.

Through power electronics technology, electrical energy can be transformed and controlled under instantaneous large voltages, and the digitization of power supply control has become a future trend, making power electronics technology increasingly important. Among them, the power element module has a considerable impact on the development of the power electronics market. Its application scope not only plays a pivotal role in the fields of new energy equipment, wind power, solar energy, electric vehicles, green buildings, etc. High-speed railways, smart grids, and variable frequency appliances are also closely related to power electronics technology.

Power device module packaging technology includes: power device package electrical and thermal simulation technology and power module system in package (SiP) process integration, die attach process, and wire bonding process. As the size and thickness of power semiconductor wafers continue to shrink and become thinner with the advancement of science and technology, at present, even metal oxide semiconductors (MOSFETs) with a size of 50 micrometers (μm) have come out. In other words, the assembly of thin wafers today is actually Facing more severe tests. Therefore, relevant industry players are committed to research and development of power component module packaging technology to improve assembly yield and reliability.

This disclosure relates to a semiconductor package structure. In the embodiment, the adhesive layer is located between the protection ring and the first lead frame, so that the electric field effect around the protection ring can be reduced, thereby maintaining a higher withstand voltage of the overall component, and simultaneously protecting the semiconductor wafer and supporting the overall structure. .

According to an embodiment of the present disclosure, a semiconductor package structure is proposed. The semiconductor package structure includes a semiconductor wafer, a guard ring, an adhesive layer, and a first lead frame. The protection ring is disposed on the semiconductor wafer, and the adhesive layer is disposed on the protection ring. The first lead frame is electrically connected to the semiconductor wafer, and an adhesive layer is located between the protection ring and the first lead frame.

According to another embodiment of the present disclosure, a semiconductor package structure is proposed. The semiconductor package structure includes a semiconductor wafer, a protection ring, a solder, a first lead frame, and an adhesive layer. A guard ring and solder are provided on the semiconductor wafer. The first lead frame is electrically connected to the semiconductor wafer via solder. The adhesive layer is disposed on the semiconductor wafer and located between the semiconductor wafer and the first lead frame, and the height of the adhesive layer is equal to or greater than the height of the solder.

In order to have a better understanding of the above and other aspects of the present invention, preferred embodiments are described below in detail as follows:

10, 20, 30, 40, 50, 60, 70, 80‧‧‧ semiconductor package structure

100‧‧‧ semiconductor wafer

100G‧‧‧Gate contact

100s‧‧‧side

200‧‧‧ protection ring

200a‧‧‧Top surface

200s‧‧‧side

300‧‧‧ Adhesive layer

400‧‧‧first lead frame

500, 510, 520‧‧‧ solder

600‧‧‧Second Lead Frame

700‧‧‧ shell

710‧‧‧electrode layer

800‧‧‧Third Lead Frame

900‧‧‧ substrate

910‧‧‧metal layer

920‧‧‧ceramic layer

930‧‧‧patterned metal layer

960‧‧‧ floor

980‧‧‧ encapsulant

1B-1B ’, 2B-2B’, 3B-3B ’, 4B-4B’, 8B-8B’‧‧‧ hatching

H1, H2, H3‧‧‧‧ height

L‧‧‧ length

W1‧‧‧first width

W2‧‧‧Second width

W3‧‧‧ Third width

FIG. 1A is a top view of a semiconductor package structure according to an embodiment of the disclosure.

Figure 1B is a schematic cross-sectional view taken along the section line 1B-1B '.

FIG. 2A illustrates a semiconductor package structure according to another embodiment of the present disclosure. Top view.

Figure 2B is a schematic cross-sectional view taken along the section line 2B-2B '.

FIG. 3A is a top view of a semiconductor package structure according to another embodiment of the disclosure.

Figure 3B is a schematic cross-sectional view taken along the section line 3B-3B '.

FIG. 4A is a top view of a semiconductor package structure according to another embodiment of the disclosure.

Figure 4B is a schematic cross-sectional view taken along the section line 4B-4B '.

FIG. 5 is a schematic diagram of a semiconductor package structure according to another embodiment of the present disclosure.

FIG. 6 is a schematic diagram of a semiconductor package structure according to another embodiment of the present disclosure.

FIG. 7 is a top view of a semiconductor package structure according to another embodiment of the disclosure.

FIG. 8A is a top view of a semiconductor package structure according to another embodiment of the disclosure.

Figure 8B is a schematic cross-sectional view taken along section line 8B-8B '.

In the embodiment disclosed in this disclosure, the adhesive layer is located between the protection ring and the first lead frame, so that the electric field effect around the protection ring can be reduced, thereby maintaining a higher withstand voltage of the overall component, and simultaneously protecting the semiconductor wafer and supporting The effect of the overall structure. The following are detailed examples of the disclosure. The detailed composition proposed in the embodiment is for illustrative purposes, and is not intended to limit the scope of the disclosure content to be protected. Those with ordinary knowledge should Results are modified or changed.

FIG. 1A is a top view of a semiconductor package structure according to an embodiment of the disclosure, and FIG. 1B is a schematic cross-sectional view taken along a section line 1B-1B ′. As shown in FIGS. 1A to 1B, the semiconductor package structure 10 includes a semiconductor wafer 100, a guard ring 200, an adhesive layer 300, and a first lead frame 400. The guard ring 200 is disposed on the semiconductor wafer 100, and the adhesive layer 300 is disposed on the guard ring 400. The first lead frame 400 is electrically connected to the semiconductor wafer 100, and the adhesive layer 300 is located between the protection ring 200 and the first lead frame 400.

In a common process, the semiconductor wafer is usually electrically connected by wire bonding. In this way, the contact area between the wire and the wafer is relatively small (the diameter of the wire is about 280 ~ 380 microns (μm)), and the area of this wire diameter is also The contact point between the wire and the wafer. When this area is too small, not only the heat dissipation of the semiconductor wafer is not uniform, but also the current is only distributed in the local area (such as the line and the contact point), and the current density in the local area of the component is also caused. Too high, it also makes the heat dissipation of the wire difficult. In contrast, according to the embodiment of the present disclosure, the first lead frame 400 is electrically connected to the semiconductor wafer 100. The soldering area between the first lead frame 400 and the semiconductor wafer 100 is relatively large. The large contact area not only makes the heat dissipation easier. Fast and relatively uniform, and the current density of the large area contact area can also be smaller, and the smaller current density can also reduce the resistance and thermal resistance, and can achieve the effect of the average temperature and current of the components, thereby improving the overall Component performance and stability.

Furthermore, according to the embodiment of the present disclosure, the adhesive layer 300 is located between the guard ring 200 and the first lead frame 400, so that the electric field effect around the guard ring 200 can be reduced, thereby maintaining a higher withstand voltage of the entire component, and It also has the effect of protecting the semiconductor wafer 100 and supporting the overall structure. Further, the adhesive layer 300 Production requires only one additional dispensing process, and does not require additional development of new processes. Therefore, existing semiconductor processes can be used, and adjustments can be easily made according to the size or shape of different semiconductor wafers 100. It can also support the first stage. The lead frame 400 has the effect of preventing the lead frame 400 from being inclined, thereby achieving the improvement of current transmission characteristics and heat conduction characteristics.

In some embodiments, the semiconductor wafer 100 may be a metal-oxide-semiconductor (MOSFET), an insulated-gate bipolar transistor (IGBT), a junction field-effect transistor (JFET), or a diode.

In the embodiment, the material of the adhesive layer 300 is an insulating material, for example, it may include at least one of a silicon gel and an epoxy resin.

As shown in FIGS. 1A to 1B, in the embodiment, the semiconductor package structure 10 further includes a solder 500. The solder 500 is disposed on the semiconductor wafer 100, and the semiconductor wafer 100 is electrically connected to the first lead frame 400 via the solder 500.

In an embodiment, the material of the solder 500 may include at least one of lead-free solder, high-lead solder, nano-silver sintered material, and dual-phase solid-liquid interdiffusion bonding (dual-phase SLID bonding). one.

As shown in FIG. 1A, in the embodiment, the first lead frame 400 has a first width W1, and the area of the semiconductor wafer 100 exposed outside the guard ring 200 has a second width W2 in the direction of the first width W1. The one width W1 is, for example, 40 to 100% of the second width W2. For example, the total width of the semiconductor wafer 100 along the first width W1 is, for example, about 3 millimeters (mm), the width of the guard ring 200 is about 30 to 700 micrometers (μm), and the first width W1 is, for example, 2.3 to 2.97 mm. .

In the embodiment, the material of the first lead frame 400 is, for example, conductive gold. Genus. For example, the first lead frame 400 may include copper, or nickel-plated aluminum or iron.

As shown in FIG. 1A, the adhesive layer 300 has a length L along the direction of the first width W1. In some embodiments, the length L is equal to or smaller than the first width W1, so the first lead frame 400 and the protection ring 200 may be completely separated by the adhesive layer 300. As shown in FIG. 1A, the length L of the adhesive layer 300 along the protective ring 200 is substantially equal to the first width W1 of the first lead frame 400. In another embodiment, the length L of the adhesive layer 300 may be smaller than the first width W1 of the first lead frame 400 (not shown in the figure).

FIG. 2A is a top view of a semiconductor package structure according to another embodiment of the disclosure, and FIG. 2B is a schematic cross-sectional view taken along a section line 2B-2B '. In this embodiment, the same or similar components are denoted by the same or similar component numbers, and related descriptions of the same or similar components are referred to the foregoing, and will not be repeated here. The difference between this embodiment and the embodiment shown in FIGS. 1A-1B is mainly in the design of the adhesive layer 300.

As shown in FIGS. 2A to 2B, the adhesive layer 300 of the semiconductor package structure 20 covers one side 200s of the protective ring 200 and one side 100s of the semiconductor wafer 100.

According to the embodiment of the disclosure, the adhesive layer 300 covers the side surface 200s of the protective ring 200 and the side surface 100s of the semiconductor wafer 100. In this way, the solder under the semiconductor wafer 100 can be prevented from being squeezed to the side surface 100s of the semiconductor wafer 100, and the semiconductor can be prevented. The solder 500 above the wafer 100 and the solder below it are short-circuited, and avoiding the contact of the solder 500 or the first lead frame 400 or being too close to the guard ring 200 to affect the operation function of the semiconductor wafer 100, thereby improving the solder 500 / solder contact half. The problem of the side 100s and bridging of the conductor wafer 100 can further regulate the soldering area and height of the solder 500 and the first lead frame 400 above the semiconductor wafer 100.

In the embodiment, as shown in FIGS. 2A to 2B, the length L of the adhesive layer 300 along the protective ring 200 is greater than the first width W1 of the first lead frame 400, so that the first lead frame 400 and the protective ring 200 can be completely glued. The layers 300 are separated. In addition, in a range extending along the length L, the adhesive layer 300 covers the top surface 200 a and the two side surfaces 200 s of the protective ring 200.

FIG. 3A is a top view of a semiconductor package structure according to another embodiment of the present disclosure, and FIG. 3B is a schematic cross-sectional view taken along a section line 3B-3B ′. In this embodiment, the same or similar components are denoted by the same or similar component numbers, and related descriptions of the same or similar components are referred to the foregoing, and will not be repeated here. The difference between this embodiment and the foregoing embodiment mainly lies in the design of the adhesive layer 300.

As shown in FIGS. 3A to 3B, the adhesive layer 300 of the semiconductor package structure 30 completely covers the protection ring 200. The adhesive layer 300 made of insulating material completely covers the protective ring 200 and the semiconductor wafer 100. In this way, the solder 500 can be squeezed to the side of the semiconductor wafer 100, and the solder 500 / solder bridge short circuit above and below the semiconductor wafer 100 can be solved. , And the problem that the solder 500 is in contact with the first lead frame 400 or is too close to the guard ring 200 affects electrical properties, not only can effectively control the solder 500 / solder area of the semiconductor wafer 100, but also control the problem of solder overflow of the semiconductor wafer 100 And can greatly improve assembly yield and reliability.

As shown in FIG. 3A, an area of the semiconductor wafer 100 exposed outside the adhesive layer 300 has a third width W3 in a direction of the first width W1. In some embodiments, the first width W1 is equal to or smaller than the third width W3. As shown in FIG. 3A, the first width W1 is smaller than the third width W3. In another embodiment, The first width W1 may also be equal to the third width W3 (not shown in the figure).

FIG. 4A is a top view of a semiconductor package structure according to another embodiment of the disclosure, and FIG. 4B is a schematic cross-sectional view taken along a section line 4B-4B '. In this embodiment, the same or similar components are denoted by the same or similar component numbers, and related descriptions of the same or similar components are referred to the foregoing, and will not be repeated here.

As shown in FIGS. 4A to 4B, the semiconductor package structure 40 further includes a substrate 900 and a second lead frame 600. A gate contact 100G of one of the semiconductor wafers 100 is electrically connected to the second lead frame 600 via the second lead frame 600. Substrate 900.

In the embodiment, the semiconductor wafer 100 is, for example, a metal-oxide-semiconductor (MOSFET) or an insulated-gate bipolar transistor (IGBT). The semiconductor package structure 40 may further include an additional lead frame (not shown in the figure). The semiconductor wafer The emitter contact of 100 can be electrically connected to the substrate 900 through the additional lead frame.

In the embodiment, the substrate 900 is, for example, a direct plated copper (DPC) substrate, a direct bonded copper (DBC) substrate, a metal substrate, or a printed circuit (PCB) substrate. The material of the metal substrate may include Copper, aluminum or stainless steel. The substrate 900 may have a single-layer or multi-layer structure.

FIG. 5 is a schematic diagram of a semiconductor package structure according to another embodiment of the present disclosure. In this embodiment, the same or similar components are denoted by the same or similar component numbers, and related descriptions of the same or similar components are referred to the foregoing, and will not be repeated here.

As shown in FIG. 5, the semiconductor package structure 50 further includes a substrate 900, a housing 700, an electrode layer 710, and a third lead frame 800. The casing 700 is used to house the substrate 900 and the semiconductor wafer 100. Electrode layer 710 is disposed on the casing 700, and the substrate 900 is electrically connected to the electrode layer 710 on the casing 700 through the third lead frame 800.

In the embodiment, the substrate 900 is, for example, a multilayer structure including a metal layer 910, a ceramic layer 920, and a patterned metal layer 930. The semiconductor wafer 100 is connected to the patterned metal layer 930 via a solder 510. In addition, the semiconductor package structure 50 may optionally include a bottom plate 960, and the substrate 900 is disposed on the bottom plate 960 through the solder 520. The bottom plate 960 is, for example, a metal substrate, and a material thereof may include copper, aluminum, or stainless steel.

FIG. 6 is a schematic diagram of a semiconductor package structure according to another embodiment of the present disclosure. In this embodiment, the same or similar components are denoted by the same or similar component numbers, and related descriptions of the same or similar components are referred to the foregoing, and will not be repeated here.

As shown in FIG. 6, in the semiconductor package structure 60, the substrate 900 is electrically connected to an external power source (not shown in the figure) through the third lead frame 800.

Moreover, as shown in FIG. 6, in the embodiment, the semiconductor packaging structure 60 may further include a packaging adhesive layer 980, which encapsulates the semiconductor wafer 100, the protection ring 200, the adhesive layer 300, the first lead frame 400, and Parts of the third lead frame 800.

FIG. 7 is a top view of a semiconductor package structure according to another embodiment of the disclosure. In this embodiment, the same or similar components are denoted by the same or similar component numbers, and related descriptions of the same or similar components are referred to the foregoing, and will not be repeated here.

In the embodiment shown in FIG. 7, the base of the semiconductor package structure 70 The board 900 is a printed circuit board.

FIG. 8A is a top view of a semiconductor package structure according to another embodiment of the present disclosure, and FIG. 8B is a schematic cross-sectional view taken along section line 8B-8B '. In this embodiment, the same or similar components are denoted by the same or similar component numbers, and related descriptions of the same or similar components are referred to the foregoing, and will not be repeated here. The difference between this embodiment and the embodiment shown in FIGS. 1A-1B is mainly in the design of the adhesive layer 300.

As shown in FIGS. 8A to 8B, the semiconductor package structure 80 includes a semiconductor wafer 100, a protection ring 200, a solder 500, a first lead frame 400, and an adhesive layer 300. The guard ring 200 and the solder 500 are disposed on the semiconductor wafer 100, and the first lead frame 400 is electrically connected to the semiconductor wafer 100 via the solder 500. The adhesive layer 300 is disposed on the semiconductor wafer 100 and is located between the semiconductor wafer 100 and the first lead frame 400. In some embodiments, the height H1 of the adhesive layer 300 is, for example, equal to or greater than the height H2 of the solder 500.

As shown in FIGS. 8A to 8B, the height H1 of the adhesive layer 300 is substantially equal to the height H2 of the solder 500. In another embodiment, the height H1 of the adhesive layer 300 may be greater than the height H2 of the solder 500 (not shown in the figure). Furthermore, in the embodiment shown in FIGS. 8A to 8B, the height H1 of the adhesive layer 300 is greater than the height H3 of the protection ring 200.

In the embodiment, as shown in FIGS. 8A to 8B, the adhesive layer 300 is located between the protection ring 200 and the solder 500.

In some embodiments, the length L of the adhesive layer 300 may be equal to, less than or greater than the first width W1 of the first lead frame 400. As shown in FIG. 8A, in this embodiment, the length L of the adhesive layer 300 is greater than the first width W1 of the first lead frame 400.

As shown in FIGS. 8A to 8B, in the embodiment, the protection ring 200, the adhesive layer 300 and the solder 500 are separated from each other. In some embodiments, the protective ring 200 may contact the adhesive layer 300, the adhesive layer 300 may contact the solder 500, and the protective ring 200, the adhesive layer 300, and the solder 500 may also contact each other (not shown in the figure).

It should be noted that the structural configuration of the substrate 900, the housing 700, the electrode layer 710, the third lead frame 800, the solders 510 and 520, and the packaging adhesive layer 980 in the embodiments described in FIGS. The structural configurations of the embodiments described in FIGS. 1A to 4B and 8A to 8B can be replaced and changed according to actual conditions.

In summary, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (18)

A semiconductor package structure includes: a semiconductor wafer; a guard ring disposed on the semiconductor wafer; an adhesive layer disposed on the guard ring; and a solder disposed on the semiconductor wafer; And a first lead frame electrically connected to the semiconductor wafer, wherein the adhesive layer is located between the protection ring and the first lead frame, and a top surface of the entire adhesive layer is in contact and adheres On a bottom surface of the first lead frame so that the first lead frame and the protection ring are completely separated by the adhesive layer, wherein the first lead frame has a first width and the semiconductor wafer is exposed to the protection The areas outside the ring, outside the adhesive layer, and outside the solder have a second width along the direction of the first width, and the first width is 40-100% of the second width. According to the semiconductor package structure described in the first item of the patent application scope, wherein the adhesive layer covers one side of the protection ring and one side of the semiconductor wafer. The semiconductor package structure according to item 1 of the patent application scope, wherein the adhesive layer completely covers the protection ring. The semiconductor package structure according to item 1 of the scope of the patent application, wherein the adhesive layer includes at least one of a silicon gel and an epoxy resin. The semiconductor package structure described in item 1 of the scope of the patent application, wherein the semiconductor wafer is a metal oxide semiconductor (MOSFET), an insulated gate bipolar transistor (IGBT), and a junction field effect transistor (JFET ) Or a diode. The semiconductor package structure described in item 1 of the patent application scope further includes: a solder disposed on the semiconductor wafer, wherein the semiconductor wafer is electrically connected to the first lead frame via the solder. The semiconductor package structure according to item 6 of the patent application scope, wherein the solder includes a lead-free solder, high-lead solder, nano-silver sintered material, and a dual-phase solid-liquid interdiffusion bonding ; At least one of dual-phase SLID bonding). The semiconductor package structure according to item 1 of the patent application scope further includes: a substrate; and a second lead frame, and a gate contact of the semiconductor wafer is electrically connected to the substrate through the second lead frame. The semiconductor package structure according to item 1 of the patent application scope further includes: a substrate; and a housing for receiving the substrate and the semiconductor wafer; an electrode layer disposed on the casing; and A third lead frame, the substrate is electrically connected to the electrode layer on the casing through the third lead frame. The semiconductor package structure according to item 1 of the patent application scope further includes: a substrate; and a third lead frame, the substrate is electrically connected to an external power source through the third lead frame. A semiconductor package structure includes: a semiconductor wafer; a guard ring disposed on the semiconductor wafer; a solder disposed on the semiconductor wafer; and a first lead frame through The solder is electrically connected to the semiconductor wafer; and an adhesive layer is disposed on the semiconductor wafer and located between the semiconductor wafer and the first lead frame, wherein a height of the adhesive layer is equal to or greater than that of the solder. Height, and a top surface of the entire adhesive layer is in contact with and adheres to a bottom surface of the first lead frame, so that the first lead frame and the protection ring are completely separated by the adhesive layer, wherein the first A lead frame has a first width, and areas of the semiconductor wafer exposed outside the protective ring, outside the adhesive layer, and outside the solder have a second width along the direction of the first width. The first width is It is 40 to 100% of the second width. The semiconductor package structure according to item 11 of the application, wherein the adhesive layer is located between the guard ring and the solder. The semiconductor package structure according to item 11 of the patent application scope, wherein the adhesive layer includes at least one of a silicon gel and an epoxy resin. The semiconductor package structure according to item 11 of the scope of the patent application, wherein the semiconductor wafer is a metal oxide semiconductor (MOSFET), an insulated gate bipolar transistor (IGBT), and a junction field effect transistor (JFET) ) Or a diode. The semiconductor package structure according to item 11 of the patent application scope, wherein the solder includes a lead-free solder, high-lead solder, nano-silver sintered material, and a dual-phase solid-liquid interdiffusion bonding ; At least one of dual-phase SLID bonding). The semiconductor package structure according to item 11 of the patent application scope further includes: a substrate; and a second lead frame, and a gate contact of the semiconductor wafer is electrically connected to the substrate through the second lead frame. The semiconductor package structure according to item 11 of the scope of patent application, further comprising: a substrate; and a housing for housing the substrate and the semiconductor wafer; an electrode layer disposed on the casing; and A third lead frame, the substrate is electrically connected to the electrode layer on the casing through the third lead frame. The semiconductor package structure according to item 11 of the patent application scope further includes: a substrate; and a third lead frame, the substrate is electrically connected to an external power source through the third lead frame.