JP5725886B2 - Device storage package and mounting structure - Google Patents

Device storage package and mounting structure Download PDF

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JP5725886B2
JP5725886B2 JP2011016168A JP2011016168A JP5725886B2 JP 5725886 B2 JP5725886 B2 JP 5725886B2 JP 2011016168 A JP2011016168 A JP 2011016168A JP 2011016168 A JP2011016168 A JP 2011016168A JP 5725886 B2 JP5725886 B2 JP 5725886B2
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substrate
input
output terminal
dielectric layer
peripheral edge
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JP2012156432A (en
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亮太 利
亮太 利
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Kyocera Corp
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

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Description

本発明は、素子収納用パッケージおよびその素子収納用パッケージを用いる実装構造体に関する。   The present invention relates to an element storage package and a mounting structure using the element storage package.

従来から、基板と、誘電体層の一主面に信号線路を形成し、誘電体層の他主面にグランド層を形成した入出力端子と、を有する素子収納用パッケージが知られている（下記特許文献１参照）。そして、マイクロ波、ミリ波等の高周波で用いられる入出力端子においては、高周波の信号を効率良く伝送するために、比誘電率が低く誘電損失が小さい誘電体層を使用する必要がある。   Conventionally, an element storage package having a substrate and an input / output terminal in which a signal line is formed on one main surface of a dielectric layer and a ground layer is formed on the other main surface of the dielectric layer is known ( See Patent Document 1 below). In input / output terminals used at high frequencies such as microwaves and millimeter waves, it is necessary to use a dielectric layer having a low relative dielectric constant and a low dielectric loss in order to efficiently transmit high frequency signals.

特開平８−２２７９４９号公報JP-A-8-227949

ところで、誘電体層の比誘電率を下げることで、入出力端子の熱膨張率と基板の熱膨張率の違いが大きくなることがあった。そして、基板と入出力端子の両者の接合部において剥離が発生し、パッケージの気密性が損なわれる虞があった。   By the way, by lowering the dielectric constant of the dielectric layer, the difference between the thermal expansion coefficient of the input / output terminals and the thermal expansion coefficient of the substrate may be increased. Then, peeling occurs at the joint portion between the substrate and the input / output terminal, which may impair the airtightness of the package.

本発明は、上記に鑑みてなされたものであって、気密性に優れた素子収納用パッケージおよびその素子収納用パッケージを用いる実装構造体を提供することを目的とする。   The present invention has been made in view of the above, and an object of the present invention is to provide an element housing package excellent in airtightness and a mounting structure using the element housing package.

本発明の一実施形態に係る素子収納用パッケージは、上面に素子の実装領域を有する基板と、前記基板上に前記実装領域を取り囲むように設けられた、一部に貫通孔を有する枠体と、前記基板上に前記貫通孔を通って前記枠体の内外にわたって設けられた入出力端子とを備え、前記基板の上面の外周縁には、前記基板の上面の外周縁の曲率が、前記基板の下面の外周縁の曲率よりも小さい湾曲部が設けられており、前記湾曲部の直上に、前記枠体
で囲まれない領域に位置する前記入出力端子の端面が位置していることを特徴とする。 An element storage package according to an embodiment of the present invention includes a substrate having an element mounting region on an upper surface thereof, a frame body provided on the substrate so as to surround the mounting region, and having a through hole in part. An input / output terminal provided on the substrate through the through-hole and inside and outside of the frame body, and the outer peripheral edge of the upper surface of the substrate has a curvature of the outer peripheral edge of the upper surface of the substrate. A curved portion that is smaller than the curvature of the outer peripheral edge of the lower surface is provided, and an end face of the input / output terminal located in a region not surrounded by the frame body is located immediately above the curved portion. Features.

また、本発明の一実施形態に係る実装構造体は、前記素子収納用パッケージと、前記素子収納用パッケージの前記実装領域に実装された素子とを備えたことを特徴とする。   In addition, a mounting structure according to an embodiment of the present invention includes the element storage package and an element mounted in the mounting region of the element storage package.

本発明によれば、気密性に優れた素子収納用パッケージおよびその素子収納用パッケージを用いる実装構造体を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the mounting structure which uses the element storage package excellent in airtightness and the element storage package can be provided.

本実施形態に係る実装構造体の概観を示す斜視図である。It is a perspective view showing the appearance of the mounting structure concerning this embodiment. 本実施形態に係る実装構造体の入出力端子の概観を示す斜視図である。It is a perspective view which shows the external appearance of the input / output terminal of the mounting structure which concerns on this embodiment. 図１に示すＸ−Ｘ’に沿った実装構造体の断面図である。It is sectional drawing of the mounting structure along X-X 'shown in FIG.

以下に添付図面を参照して、本発明にかかる素子収納用パッケージおよび実装構造体の実施形態を詳細に説明する。なお、本発明は以下の実施形態に限定されないものである。   Exemplary embodiments of an element storage package and a mounting structure according to the present invention will be described below in detail with reference to the accompanying drawings. In addition, this invention is not limited to the following embodiment.

＜実装構造体の概略構成＞
図１は、本実施形態に係る実装構造体１を示す概観斜視図である。図２は、図１の実装構造体１に用いられる入出力端子の概観を示す斜視図である。実装構造体１は、テレビ等の家電機器、携帯電話またはコンピュータ機器等の電子機器に用いるものである。特に、マイクロ波、ミリ波等の高周波で用いられる電子機器の高周波回路に用いられる。 <Schematic configuration of mounting structure>
FIG. 1 is a schematic perspective view showing a mounting structure 1 according to the present embodiment. FIG. 2 is a perspective view showing an overview of input / output terminals used in the mounting structure 1 of FIG. The mounting structure 1 is used for home appliances such as a television, and electronic devices such as a mobile phone or a computer device. In particular, it is used for a high-frequency circuit of an electronic device used at a high frequency such as a microwave and a millimeter wave.

実装構造体１は、素子収納用パッケージ２と、素子収納用パッケージ２に実装された素子３とを備えている。素子収納用パッケージ２は、例えば、半導体素子、光半導体素子、トランジスタ、ダイオードまたはサイリスタ等の能動素子、あるいは抵抗器、コンデンサ、太陽電池、圧電素子、水晶振動子またはセラミック発振子等の受動素子からなる素子３を実装するのに用いるものである。   The mounting structure 1 includes an element storage package 2 and an element 3 mounted on the element storage package 2. The element storage package 2 includes, for example, an active element such as a semiconductor element, an optical semiconductor element, a transistor, a diode, or a thyristor, or a passive element such as a resistor, a capacitor, a solar cell, a piezoelectric element, a crystal oscillator, or a ceramic oscillator. Used to mount the element 3.

素子収納用パッケージ２は、上面に素子３の実装領域Ｒを有する基板４と、基板４上に実装領域Ｒを取り囲むように設けられた、一部に貫通孔Ｈを有する枠体５と、貫通孔Ｈを通って枠体５の内外にわたって設けられた入出力端子６とを備えている。なお、素子収納用パッケージ２は、基板４の実装領域Ｒに素子３を実装し、素子３と入出力端子６とを電気的に接続することで、実装構造体１として用いることができる。   The element storage package 2 includes a substrate 4 having a mounting region R of the element 3 on the upper surface, a frame 5 provided on the substrate 4 so as to surround the mounting region R, and a part having a through hole H, and a through hole. And an input / output terminal 6 provided through the hole H over the inside and outside of the frame body 5. The element storage package 2 can be used as the mounting structure 1 by mounting the element 3 in the mounting region R of the substrate 4 and electrically connecting the element 3 and the input / output terminal 6.

基板４は、平面視したとき四角形状に形成された部材である。基板４は、例えば、銅、鉄、タングステン、モリブデン、ニッケルまたはコバルト等の金属材料、あるいはこれらの金属材料を含有する合金から成る。基板４は、熱伝導率を良好にして、実装領域Ｒに実装した素子３から発生する熱を効率良く基板４を介して外部に放散させる機能を備えている。なお、基板４の熱伝導率は、例えば１５Ｗ／（ｍ・Ｋ）以上４５０Ｗ／（ｍ・Ｋ）以下に設定されている。また、基板４の熱膨張率は、例えば４以上１８以下に設定されている。   The substrate 4 is a member formed in a square shape when viewed in plan. The substrate 4 is made of, for example, a metal material such as copper, iron, tungsten, molybdenum, nickel, or cobalt, or an alloy containing these metal materials. The substrate 4 has a function of improving heat conductivity and dissipating heat generated from the element 3 mounted in the mounting region R to the outside efficiently through the substrate 4. The thermal conductivity of the substrate 4 is set to, for example, 15 W / (m · K) or more and 450 W / (m · K) or less. Moreover, the thermal expansion coefficient of the board | substrate 4 is set to 4-18, for example.

また、基板４は、例えば、溶融した金属材料を型枠に鋳込んで固化させたインゴットに対して、従来周知の圧延加工または打ち抜き加工等の金属加工法を用いることで、所定形状に製作される。なお、基板４の一辺の長さは、例えば３ｍｍ以上５０ｍｍ以下に設定されている。また、基板４の厚みは、例えば０．３ｍｍ以上５ｍｍ以下に設定されている。   Further, the substrate 4 is manufactured in a predetermined shape by using a conventionally known metal processing method such as rolling or stamping for an ingot obtained by casting a molten metal material into a mold and solidifying it. The The length of one side of the substrate 4 is set to, for example, 3 mm or more and 50 mm or less. Moreover, the thickness of the board | substrate 4 is set to 0.3 mm or more and 5 mm or less, for example.

また、基板４の表面は、酸化腐食の防止、あるいは実装領域Ｒに素子３をろう付けしやすくするために、電気めっき法または無電解めっき法を用いて、ニッケルまたは金等の鍍金層が形成されている。基板４の実装領域Ｒは、基板４の上面に枠体５を接続したときに、枠体５と接続されない領域である。なお、本実施形態では、基板４の形状は、平面視したときに四角形状としているが、素子３を実装することが可能であれば、平面視したときに四角形状に限られず、多角形状または楕円形状等であってもよい。   Further, a plating layer such as nickel or gold is formed on the surface of the substrate 4 by using an electroplating method or an electroless plating method in order to prevent oxidative corrosion or to easily braze the element 3 to the mounting region R. Has been. The mounting region R of the substrate 4 is a region that is not connected to the frame body 5 when the frame body 5 is connected to the upper surface of the substrate 4. In the present embodiment, the shape of the substrate 4 is a quadrangle when viewed in plan, but is not limited to a quadrangle when viewed in plan, as long as the element 3 can be mounted. An elliptical shape or the like may be used.

基板４の上面の外周縁には、基板４の厚み方向の断面で断面視したとき、基板４の上面の外周縁の曲率（上面から側面にかけての曲率）が、基板４の下面の外周縁の曲率（下面から側面にかけての曲率）よりも小さい湾曲部４Ａが形成されている。そして、この湾曲部４Ａによって、基板４の上面の外周縁と、その直上に設けられる入出力端子６の下面との間に、基板４の上面の外周縁に沿って空隙を設けることができる。基板４は、基板４の上面の外周縁が滑らかに形成されることで、基板４上の外周の一部に設けられる入出力端子６との接触面積を減らすことができる。基板４に熱が加わり温度が上昇すると、基板４に反りが発生することがあるが、基板４が熱変形することによって、基板４の上面の外周縁が入出力端子６に対して応力が加わる。そこで、もっとも反りが大きくなる基板４の上面の外周縁に湾曲部４Ａを形成することにより、熱膨張を起こした基板４の上面の外周縁が入出力端子６に当接してから入出力端子６に応力が加わるようになるため、湾曲部４Ａ
がなく最初から基板４の外周縁が入出力端子６に当接している場合に比べて、入出力端子６に加わる応力を小さくすることができる。 At the outer peripheral edge of the upper surface of the substrate 4, the curvature of the outer peripheral edge of the upper surface of the substrate 4 (the curvature from the upper surface to the side surface) when viewed in cross section in the thickness direction of the substrate 4 is 4 A of curved parts smaller than a curvature (curvature from a lower surface to a side surface) are formed. The curved portion 4A can provide a gap along the outer peripheral edge of the upper surface of the substrate 4 between the outer peripheral edge of the upper surface of the substrate 4 and the lower surface of the input / output terminal 6 provided immediately above the curved portion 4A. The substrate 4 is formed such that the outer peripheral edge of the upper surface of the substrate 4 is smoothly formed, so that the contact area with the input / output terminals 6 provided on a part of the outer periphery on the substrate 4 can be reduced. When heat is applied to the substrate 4 and the temperature rises, the substrate 4 may be warped. However, when the substrate 4 is thermally deformed, the outer peripheral edge of the upper surface of the substrate 4 applies stress to the input / output terminals 6. . Therefore, the curved portion 4A is formed on the outer peripheral edge of the upper surface of the substrate 4 where the warpage is the largest, so that the outer peripheral edge of the upper surface of the substrate 4 that has caused thermal expansion comes into contact with the input / output terminal 6 and then the input / output terminal 6 Since the stress is applied to the bending portion 4A,
Compared to the case where the outer peripheral edge of the substrate 4 is in contact with the input / output terminal 6 from the beginning, the stress applied to the input / output terminal 6 can be reduced.

また、湾曲部４Ａは、基板４の上面の外周全周にわたって連続して設けられていることが好ましい。基板４の上面の外周全周にわたって連続して湾曲部４Ａが設けられることで、素子収納用パッケージの製造工程において、基板４または枠体５、入出力端子６の熱膨張率差に起因して生じる応力を、基板４の上面の外周縁において局所的に集中しにくくすることができる。さらに、素子収納用パッケージ２の製造工程において、基板４または枠体５、入出力端子６の熱膨張率差に起因して生じる基板４の反りが実装構造体１を外部電気回路基板に実装する際に矯正されることによって生じる応力を、基板４の外周縁において局所的に集中しにくくすることができる。仮に、基板４の外周縁において、湾曲部４Ａが形成される部位と、湾曲部４Ａが形成されない部位とが設けられる場合は、基板４の外周縁への応力は、湾曲部４Ａが形成される部位と、湾曲部４Ａが形成されない部位との境界部で集中することとなる。同様に、実装構造体１を作動させる際に素子３から発生する熱による、基板４または枠体５、入出力端子６の熱膨張率差に起因して生じる応力を、基板４の上面の外周縁において局所的に集中しにくくすることができる。   Further, the curved portion 4 </ b> A is preferably provided continuously over the entire outer periphery of the upper surface of the substrate 4. By providing the curved portion 4A continuously over the entire outer periphery of the upper surface of the substrate 4, due to the difference in thermal expansion coefficient between the substrate 4 or the frame 5 and the input / output terminal 6 in the manufacturing process of the element storage package. The generated stress can be made difficult to concentrate locally at the outer peripheral edge of the upper surface of the substrate 4. Further, in the manufacturing process of the element housing package 2, the mounting structure 1 is mounted on the external electric circuit board due to warpage of the board 4 caused by the difference in thermal expansion coefficient between the board 4 or the frame 5 and the input / output terminal 6. It is possible to make it difficult for the stress generated by the correction at the time to be locally concentrated on the outer peripheral edge of the substrate 4. If a portion where the curved portion 4A is formed and a portion where the curved portion 4A is not formed are provided on the outer peripheral edge of the substrate 4, the stress on the outer peripheral edge of the substrate 4 causes the curved portion 4A to be formed. It will concentrate in the boundary part of a site | part and the site | part in which the curved part 4A is not formed. Similarly, the stress caused by the difference in thermal expansion coefficient between the substrate 4 or the frame 5 and the input / output terminal 6 due to the heat generated from the element 3 when the mounting structure 1 is operated is applied to the outside of the upper surface of the substrate 4. It is possible to make it difficult to concentrate locally at the periphery.

基板４の上面の外周縁の湾曲部４Ａの曲率は、例えば１以上１０以下に設定されている。また、基板４の下面の外周縁の曲率は、例えば５以上２０以下に設定されている。そして、基板４の上面の外周縁の曲率が、基板４の下面の外周縁の曲率よりも小さく形成されている。なお、曲率とは、基板４の外周縁における湾曲部の円周の半径をｒ（ｍｍ）とする場合に、１／ｒにて表される数値である。   The curvature of the curved portion 4A on the outer peripheral edge of the upper surface of the substrate 4 is set to 1 or more and 10 or less, for example. Further, the curvature of the outer peripheral edge of the lower surface of the substrate 4 is set to, for example, 5 or more and 20 or less. The curvature of the outer peripheral edge of the upper surface of the substrate 4 is formed to be smaller than the curvature of the outer peripheral edge of the lower surface of the substrate 4. The curvature is a numerical value represented by 1 / r when the radius of the circumference of the curved portion at the outer peripheral edge of the substrate 4 is r (mm).

また、基板４の下面の外周縁の曲率を基板４の上面の外周縁の曲率よりも大きくすることで、基板４の下面の平らな面積を基板４の上面の平らな面積よりも大きくすることができる。そして、基板４を実装する外部基板との接触面積を大きくすることができ、基板４と外部基板との接着力を向上させることができる。   Further, the flat area of the lower surface of the substrate 4 is made larger than the flat area of the upper surface of the substrate 4 by making the curvature of the outer peripheral edge of the lower surface of the substrate 4 larger than the curvature of the outer peripheral edge of the upper surface of the substrate 4. Can do. And the contact area with the external board | substrate which mounts the board | substrate 4 can be enlarged, and the adhesive force of the board | substrate 4 and an external board | substrate can be improved.

枠体５は、基板４の実装領域Ｒを取り囲むように設けられ、素子３を外部から保護するための部材である。また、枠体５は、側面の一部に入出力端子６を設ける貫通孔Ｈが形成されている。枠体５は、ろう材を介して基板４にろう付けされる。なお、ろう材は、例えば、銀、銅、金、アルミ二ウムまたはマグネシウム等からなり、ニッケル、カドミウムまたは燐等の添加物を含有してもよい。   The frame 5 is a member that is provided so as to surround the mounting region R of the substrate 4 and protects the element 3 from the outside. Further, the frame body 5 is formed with a through hole H provided with the input / output terminal 6 in a part of the side surface. The frame 5 is brazed to the substrate 4 via a brazing material. The brazing material is made of, for example, silver, copper, gold, aluminum, or magnesium, and may contain additives such as nickel, cadmium, or phosphorus.

また、枠体５は、例えば、銅、鉄、タングステン、モリブデン、ニッケルまたはコバルト等の金属材料、あるいはこれらの金属材料を含有する合金から成る。枠体５は、実装領域Ｒに素子３が実装されている状態で、素子３から発生する熱を効率良く枠体５の外部に発散させる機能を備えている。なお、枠体５の熱伝導率は、例えば１５Ｗ／（ｍ・Ｋ）以上４５０Ｗ／（ｍ・Ｋ）以下に設定されている。また、枠体５の熱膨張率は、例えば４ｐｐｍ／℃以上１８ｐｐｍ／℃以下に設定されている。   The frame 5 is made of, for example, a metal material such as copper, iron, tungsten, molybdenum, nickel, or cobalt, or an alloy containing these metal materials. The frame 5 has a function of efficiently dissipating heat generated from the element 3 to the outside of the frame 5 in a state where the element 3 is mounted in the mounting region R. The thermal conductivity of the frame 5 is set to, for example, 15 W / (m · K) or more and 450 W / (m · K) or less. Moreover, the thermal expansion coefficient of the frame 5 is set to, for example, 4 ppm / ° C. or more and 18 ppm / ° C. or less.

入出力端子６は、枠体５の貫通孔Ｈに設けられる。入出力端子６は、マイクロ波、ミリ波等の高周波の信号を伝送するためのものである。入出力端子６は、第１誘電体層６ａと、第１誘電体層６ａ上の一部に設けられる第２誘電体層６ｂを有している。さらに、入出力端子６は、第１誘電体層６ａと第２誘電体層６ｂの間に形成され、枠体５の内外を電気的に接続する信号線路７と、第１誘電体層６ａの下面に形成される第１接地導体８と、第１誘電体６ａの側面、第２誘電体層６ｂの側面および第２誘電体層６ｂの上面に連続して設けられる第２接地導体９を有している。   The input / output terminal 6 is provided in the through hole H of the frame body 5. The input / output terminal 6 is for transmitting high-frequency signals such as microwaves and millimeter waves. The input / output terminal 6 includes a first dielectric layer 6a and a second dielectric layer 6b provided on a part of the first dielectric layer 6a. Furthermore, the input / output terminal 6 is formed between the first dielectric layer 6a and the second dielectric layer 6b, and electrically connects the signal line 7 between the inside and outside of the frame 5 and the first dielectric layer 6a. The first ground conductor 8 formed on the lower surface and the second ground conductor 9 provided continuously on the side surface of the first dielectric 6a, the side surface of the second dielectric layer 6b, and the upper surface of the second dielectric layer 6b are provided. doing.

信号線路７は、所定の電気信号を伝達する機能を備えている。信号線路７は、例えば、
マイクロストリップ線路またはコプレーナ線路として用いる。信号線路７は、例えば、タングステン、モリブデンまたはマンガン等で形成されたメタライズ金属層上に、ニッケルメッキ層または金メッキ層が形成されてなる。また、信号線路７の線路幅は、信号線路７に伝わる信号の波長の４分の１以下であって、例えば０．０５ｍｍ以上０．５ｍｍ以下に設定されている。 The signal line 7 has a function of transmitting a predetermined electrical signal. The signal line 7 is, for example,
Used as a microstrip line or coplanar line. The signal line 7 is formed by forming a nickel plating layer or a gold plating layer on a metallized metal layer formed of tungsten, molybdenum, manganese, or the like. Further, the line width of the signal line 7 is not more than one-fourth of the wavelength of the signal transmitted to the signal line 7, and is set to, for example, 0.05 mm or more and 0.5 mm or less.

信号線路７には、リード端子１０が形成される。リード端子１０は、外部の電子機器等と素子３とを電気的に接続するための部材である。リード端子１０は、ろう材を介して、信号線路７上に接続される。そして、信号線路７とリード端子１０とが電気的に接続される。   A lead terminal 10 is formed on the signal line 7. The lead terminal 10 is a member for electrically connecting an external electronic device or the like to the element 3. The lead terminal 10 is connected to the signal line 7 through a brazing material. The signal line 7 and the lead terminal 10 are electrically connected.

第１接地導体８および第２接地導体９は、共通の電位、例えばアース電位にする機能を備えている。また、第１接地導体８および第２接地導体９は、例えば、タングステン、モリブデンまたはマンガン等で形成されたメタライズ金属層上に、ニッケルメッキ層が形成されてなる。第１接地導体８は、平面視して信号線路７と重なる領域に形成されている。枠体５は、金属材料からなり、第１接地導体８、第２接地導体９および枠体５は電気的に接続されている。   The first ground conductor 8 and the second ground conductor 9 have a function of setting a common potential, for example, a ground potential. The first ground conductor 8 and the second ground conductor 9 are formed by forming a nickel plating layer on a metallized metal layer made of tungsten, molybdenum, manganese, or the like, for example. The first ground conductor 8 is formed in a region overlapping the signal line 7 in plan view. The frame 5 is made of a metal material, and the first ground conductor 8, the second ground conductor 9, and the frame 5 are electrically connected.

また、入出力端子６は、第１誘電体層６ａおよび第２誘電体層６ｂを取り囲む第２接地導体９を有しており、信号線路７と枠体５とが重なる領域において信号線路７に伝達される信号が反射するのを抑制することができる。   The input / output terminal 6 has a second ground conductor 9 that surrounds the first dielectric layer 6a and the second dielectric layer 6b, and is connected to the signal line 7 in a region where the signal line 7 and the frame 5 overlap. It is possible to suppress reflection of the transmitted signal.

第１誘電体層６ａおよび第２誘電体層６ｂは、絶縁性の基板であって、例えば、酸化アルミニウム、窒化アルミニウムまたは窒化珪素等の無機材料、あるいはエポキシ樹脂、ポリイミド樹脂またはエチレン樹脂等の有機材料、あるいはアルミナまたはムライト等のセラミック材料、あるいはガラスセラミック材料等から成る。または、これらの材料のうち複数の材料を混合した複合系材料から成る。なお、第１誘電体層６ａおよび第２誘電体層６ｂの厚みは、信号線路７に伝わる信号の波長の２分の１以下であって、例えば０．１ｍｍ以上１ｍｍ以下に設定されている。   The first dielectric layer 6a and the second dielectric layer 6b are insulating substrates, for example, inorganic materials such as aluminum oxide, aluminum nitride, or silicon nitride, or organic materials such as epoxy resin, polyimide resin, or ethylene resin. It is made of a material, a ceramic material such as alumina or mullite, or a glass ceramic material. Or it consists of a composite material which mixed several materials among these materials. The thicknesses of the first dielectric layer 6a and the second dielectric layer 6b are not more than one half of the wavelength of the signal transmitted to the signal line 7, and are set to, for example, not less than 0.1 mm and not more than 1 mm.

また、第１誘電体層６ａまたは第２誘電体層６ｂには、多数のフィラーが含有されていても構わない。第１誘電体層６ａまたは第２誘電体層６ｂが有機材料からなる場合は、第１誘電体層６ａまたは第２誘電体層６ｂにフィラーが含有されていることによって、第１誘電体層６ａまたは第２誘電体層６ｂの硬化前の粘度を調整することができ、第１誘電体層６ａまたは第２誘電体層６ｂの厚み寸法を所望の値に近づけることができる。フィラーは、例えば球状であって、フィラーの径は、例えば０．０５μｍ以上６μｍ以下に設定されており、熱膨張率は、例えば−５ｐｐｍ／℃以上５ｐｐｍ／℃以下である。なお、フィラーは、例えば、酸化珪素、炭化珪素、酸化アルミニウム、窒化アルミニウムまたは水酸化アルミニウム等から成る。   The first dielectric layer 6a or the second dielectric layer 6b may contain a large number of fillers. When the first dielectric layer 6a or the second dielectric layer 6b is made of an organic material, a filler is contained in the first dielectric layer 6a or the second dielectric layer 6b, whereby the first dielectric layer 6a. Or the viscosity before hardening of the 2nd dielectric material layer 6b can be adjusted, and the thickness dimension of the 1st dielectric material layer 6a or the 2nd dielectric material layer 6b can be brought close to a desired value. The filler is, for example, spherical, the filler diameter is set to, for example, 0.05 μm to 6 μm, and the coefficient of thermal expansion is, for example, −5 ppm / ° C. to 5 ppm / ° C. The filler is made of, for example, silicon oxide, silicon carbide, aluminum oxide, aluminum nitride, or aluminum hydroxide.

また、第１誘電体層６ａまたは第２誘電体層６ｂに含有されるフィラーの比誘電率は、第１誘電体層６ａまたは第２誘電体層６ｂを構成する材料の比誘電率よりも小さく設定することができる。このように、第１誘電体層６ａまたは第２誘電体層６ｂの比誘電率よりも小さい低誘電率のフィラーとすることで、入出力端子６をさらに低誘電率化することができ、信号線路７に伝送される信号の伝送効率を向上させることができる。   The relative dielectric constant of the filler contained in the first dielectric layer 6a or the second dielectric layer 6b is smaller than the relative dielectric constant of the material constituting the first dielectric layer 6a or the second dielectric layer 6b. Can be set. Thus, by using a filler having a low dielectric constant smaller than the relative dielectric constant of the first dielectric layer 6a or the second dielectric layer 6b, the input / output terminal 6 can be further reduced in dielectric constant, The transmission efficiency of the signal transmitted to the line 7 can be improved.

また、フィラーは、絶縁性のフィラーとすることができる。フィラーを絶縁性とすることで、信号線路７に伝わる信号の特性インピーダンスへの影響を低減することができる。   The filler can be an insulating filler. By making the filler insulative, the influence on the characteristic impedance of the signal transmitted to the signal line 7 can be reduced.

信号線路７に伝達される信号は、信号線路７の直上または直下に位置する材料に起因し
て、伝送特性が変化するが、伝送特性の変化が大きいと信号線路７に伝達される信号の反射量が大きくなる。そして、信号線路７は、枠体５の内外を電気的に接続するために、枠体５の内外に延在して形成されている。そのため、平面視して信号線路７と枠体５とが重なる領域が、信号線路７に伝達される信号の伝送特性の変化が大きい。本実施形態においては、信号線路７と枠体５とが重なる領域において、信号線路７の直上および直下に誘電体層の一部を貼り合わせて、信号線路７が大気と接する領域を低減する。その結果、信号線路７に伝達される信号の伝送特性の変化を抑制し、信号線路７に伝送される高周波の反射を低減することができる。 The signal transmitted to the signal line 7 changes in transmission characteristics due to the material located directly above or below the signal line 7, but when the change in transmission characteristics is large, the reflection of the signal transmitted to the signal line 7 The amount increases. The signal line 7 is formed to extend in and out of the frame 5 in order to electrically connect the inside and outside of the frame 5. Therefore, in the area where the signal line 7 and the frame 5 overlap in plan view, the change in transmission characteristics of the signal transmitted to the signal line 7 is large. In the present embodiment, in the region where the signal line 7 and the frame 5 overlap, a part of the dielectric layer is bonded directly above and directly below the signal line 7 to reduce the region where the signal line 7 is in contact with the atmosphere. As a result, it is possible to suppress a change in transmission characteristics of the signal transmitted to the signal line 7 and reduce high-frequency reflection transmitted to the signal line 7.

入出力端子６の下面の外周縁は、平らに形成されている。そして、湾曲部４Ａは、入出力端子６の下面の外周縁よりも湾曲して形成されている。入出力端子６の下面を平らに形成することで、信号線路７と第１接地導体８との間における電磁波の反射の変化を小さくし、入出力端子６の伝送特性を良好に維持することができる。   The outer peripheral edge of the lower surface of the input / output terminal 6 is formed flat. The curved portion 4 </ b> A is curved from the outer peripheral edge of the lower surface of the input / output terminal 6. By forming the lower surface of the input / output terminal 6 flat, the change in the reflection of electromagnetic waves between the signal line 7 and the first ground conductor 8 can be reduced, and the transmission characteristics of the input / output terminal 6 can be maintained well. it can.

入出力端子６の枠体５で囲まれない領域に位置する端面は、平面視して基板４の湾曲部４Ａと重なるように設定されている。入出力端子６の端面と基板４の端面を合わせることで、入出力端子６の伝送特性の劣化、入出力端子６の割れまたはカケといった損傷の発生を抑制できる。仮に、入出力端子６の端面が、平面視して基板４の外周より内側に設けられた場合は、リード端子１０と基板４の外周縁との間に容量成分が生じるため、信号線路７における特性インピーダンスが変動する。その結果、入出力端子６における反射損失が増加し、信号線路７の伝送特性が劣化する。また、仮に、入出力端子６の端面が、基板４の外周より外側に突出して設けられる場合は、入出力端子６が平面視して基板４より外側に位置しているため、素子収納用パッケージ２の組立、実装構造体１の外部電気回路基板へ実装する際に、入出力端子６がピンセット等の工具または搬送治具に直接接触する可能性が生じる。その結果、入出力端子６に割れまたは欠けといった損傷が発生し、素子収納用パッケージ２および実装構造体１の信頼性とともに歩留まりが低下する傾向がある。   An end face located in a region not surrounded by the frame 5 of the input / output terminal 6 is set so as to overlap the curved portion 4A of the substrate 4 in plan view. By matching the end face of the input / output terminal 6 and the end face of the substrate 4, it is possible to suppress the deterioration of the transmission characteristics of the input / output terminal 6 and the occurrence of damage such as cracking or chipping of the input / output terminal 6. If the end face of the input / output terminal 6 is provided on the inner side of the outer periphery of the substrate 4 in plan view, a capacitance component is generated between the lead terminal 10 and the outer peripheral edge of the substrate 4. The characteristic impedance varies. As a result, the reflection loss at the input / output terminal 6 increases, and the transmission characteristics of the signal line 7 deteriorate. If the end face of the input / output terminal 6 protrudes outside the outer periphery of the substrate 4, the input / output terminal 6 is positioned outside the substrate 4 in a plan view. When the assembly 2 and the mounting structure 1 are mounted on the external electric circuit board, there is a possibility that the input / output terminal 6 directly contacts a tool such as tweezers or a conveying jig. As a result, damage such as cracking or chipping occurs in the input / output terminal 6, and the yield tends to decrease with the reliability of the element housing package 2 and the mounting structure 1.

素子収納用パッケージ２に、素子３を半田等を介して基体４の実装領域Ｒに実装することで、実装構造体１を構成することができる。ＩＣまたはＬＳＩ等の半導体素子を実装する場合、半導体素子としては、例えばシリコン、ゲルマニウム、ガリウム砒素、ガリウム砒素リン、窒化ガリウムまたは炭化珪素等を用いることができる。また、素子３の上面と、枠体５内に位置する入出力端子６の信号線路７とをボンディングワイヤを介して電気的に接続されている。   The mounting structure 1 can be configured by mounting the element 3 in the mounting region R of the base body 4 via solder or the like in the element storage package 2. When a semiconductor element such as an IC or LSI is mounted, for example, silicon, germanium, gallium arsenide, gallium arsenide phosphorus, gallium nitride, or silicon carbide can be used as the semiconductor element. Further, the upper surface of the element 3 and the signal line 7 of the input / output terminal 6 located in the frame 5 are electrically connected via a bonding wire.

枠体５上には、蓋体１１が設けられる。蓋体１１は、枠体５内の気密性を保つための機能を備えている。蓋体１１は、例えば、銅、タングステン、鉄、ニッケルまたはコバルト等の金属、あるいはこれらの金属を複数種含む合金、あるいは酸化アルミニウム質焼結体、ムライト質焼結体、炭化珪素質焼結体、窒化アルミニウム質焼結体、窒化珪素質焼結体またはガラスセラミック等のセラミックスから成る。また、蓋体１１は、枠体６の上面に、例えば半田またはろう材等の接合部材を介して接合される。   A lid 11 is provided on the frame 5. The lid 11 has a function for maintaining the airtightness in the frame 5. The lid 11 is made of, for example, a metal such as copper, tungsten, iron, nickel, or cobalt, or an alloy containing a plurality of these metals, an aluminum oxide sintered body, a mullite sintered body, or a silicon carbide sintered body. And made of ceramics such as an aluminum nitride sintered body, a silicon nitride sintered body, or a glass ceramic. The lid 11 is joined to the upper surface of the frame 6 via a joining member such as solder or brazing material.

本実施形態によれば、基板４の熱膨張率と入出力端子６の熱膨張率の違いにより、両者が熱膨張したときであっても、基板４の外周縁に湾曲部４Ａを設けることで、基板４から入出力端子６に熱応力が加わりにくいようにすることができ、入出力端子６が破壊されるのを抑制することができ、パッケージの気密性を良好に保つことができる。また、入出力端子６が変形しにくいようにすることによって、信号線路７の伝送特性が低下するのを抑制することができ、電気的特性が優れた素子収納用パッケージ２および実装構造体１を提供することができる。   According to the present embodiment, due to the difference between the thermal expansion coefficient of the substrate 4 and the thermal expansion coefficient of the input / output terminal 6, even when both are thermally expanded, the curved portion 4A is provided on the outer peripheral edge of the substrate 4. Further, it is possible to make it difficult for thermal stress to be applied from the substrate 4 to the input / output terminals 6, to prevent the input / output terminals 6 from being broken, and to maintain good airtightness of the package. Further, by making the input / output terminal 6 difficult to be deformed, it is possible to prevent the transmission characteristics of the signal line 7 from being deteriorated, and to provide the element housing package 2 and the mounting structure 1 having excellent electrical characteristics. Can be provided.

なお、本発明は上述の形態に限定されるものではなく、本発明の要旨を逸脱しない範囲
において種々の変更、改良等が可能である。例えば、基体４と素子３との間に配線基板を介在させる構造であってもよい。 In addition, this invention is not limited to the above-mentioned form, A various change, improvement, etc. are possible in the range which does not deviate from the summary of this invention. For example, a structure in which a wiring board is interposed between the base 4 and the element 3 may be used.

＜実装構造体の製造方法＞
ここで、図１に示す実装構造体１の製造方法を説明する。まず、基板４、枠体５のそれぞれを準備する。基板４、枠体５のそれぞれは、溶融した金属材料を型枠に鋳込んだ固化させたインゴットに対して、金属研磨等の金属加工法を用いることで、所定形状に製作される。なお、基板４は、型枠から取り出したインゴットに対して、基板４の上面の外周縁に相当する個所を研磨して、湾曲部４Ａを形成することができる。また、枠体５は、貫通孔Ｈに相当する個所を研磨して、入出力端子６を接続可能な大きさの貫通孔Ｈを形成することができる。 <Method for manufacturing mounting structure>
Here, a manufacturing method of the mounting structure 1 shown in FIG. 1 will be described. First, each of the substrate 4 and the frame 5 is prepared. Each of the substrate 4 and the frame 5 is manufactured in a predetermined shape by using a metal processing method such as metal polishing on a solidified ingot obtained by casting a molten metal material into a mold. In addition, the board | substrate 4 can grind | polish the location corresponding to the outer periphery of the upper surface of the board | substrate 4 with respect to the ingot taken out from the formwork, and can form the curved part 4A. Further, the frame body 5 can polish a portion corresponding to the through hole H to form a through hole H having a size capable of connecting the input / output terminal 6.

次に、入出力端子６を準備する。ここでは、誘電体層６の材料が、酸化アルミニウム質焼結体、窒化アルミニウム質焼結体またはムライト質焼結体等を用いることができる。   Next, the input / output terminal 6 is prepared. Here, the material of the dielectric layer 6 can be an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body, or the like.

誘電体層６の材料が酸化アルミニウム質焼結体から成る場合、まず、酸化アルミニウム、酸化珪素、酸化マグネシウムまたは酸化カルシウム等の原料粉末に有機バインダー、可塑剤または溶剤等を添加混合して泥漿状と成す。   When the material of the dielectric layer 6 is made of an aluminum oxide sintered body, first, an organic binder, a plasticizer, a solvent, or the like is added to and mixed with raw material powders such as aluminum oxide, silicon oxide, magnesium oxide, or calcium oxide to form a slurry. And

そして、第１誘電体層６ａおよび第２誘電体層６ｂの型枠を準備し、枠体内に、泥漿状の酸化アルミ二ウム質の材料を充填し、焼結前の第１誘電体層６ａおよび第２誘電体層６ｂを取り出す。   Then, molds of the first dielectric layer 6a and the second dielectric layer 6b are prepared, and the frame body is filled with a slurry-like aluminum oxide material, and the first dielectric layer 6a before sintering is filled. Then, the second dielectric layer 6b is taken out.

また、タングステンまたはモリブデン等の高融点金属粉末を準備し、この粉末に有機バインダー、可塑剤または溶剤等を添加混合して金属ペーストを得る。   Moreover, a high melting point metal powder such as tungsten or molybdenum is prepared, and an organic binder, a plasticizer, a solvent, or the like is added to and mixed with the powder to obtain a metal paste.

そして、取り出した焼結前の第１誘電体層６ａの上面に対して、例えばスクリーン印刷法を用いて、金属ペーストを塗って信号線路７を形成する。また、第１誘電体層６ａの下面に対して、例えばスクリーン印刷法を用いて、金属ペーストを塗って第１接地導体８を形成する。さらに、第１誘電体層６ａおよび第２誘電体層６ｂを組み合わせたときに、両者を取り囲む箇所に、例えばスクリーン印刷法を用いて第２接地導体９を形成する。   Then, the signal line 7 is formed by applying a metal paste to the upper surface of the taken out first dielectric layer 6a before sintering using, for example, a screen printing method. The first ground conductor 8 is formed on the lower surface of the first dielectric layer 6a by applying a metal paste, for example, using a screen printing method. Further, when the first dielectric layer 6a and the second dielectric layer 6b are combined, the second ground conductor 9 is formed at a location surrounding both by using, for example, a screen printing method.

次に、焼結前の第１誘電体層６ａ上に焼結前の第２誘電体層６ｂを載せて加圧することで、両者を密着させる。そして、金属ペーストを印刷塗布した積層体を約１６００℃の温度で焼成することにより、信号線路７、第１接地導体８および第２接地導体９が形成されたセラミックスからなる入出力端子６を作製することができる。   Next, the second dielectric layer 6b before sintering is placed on the first dielectric layer 6a before sintering and pressed, thereby bringing them into close contact with each other. Then, the laminated body on which the metal paste is printed is fired at a temperature of about 1600 ° C., thereby producing the input / output terminal 6 made of ceramics on which the signal line 7, the first ground conductor 8 and the second ground conductor 9 are formed. can do.

そして、準備した枠体５の貫通孔Ｈに、入出力端子６をろう材を介して嵌めて接続する。このようにして、素子収納用パッケージ２を作製することができる。   Then, the input / output terminal 6 is fitted and connected to the through hole H of the prepared frame 5 through a brazing material. In this way, the element storage package 2 can be manufactured.

次に、素子収納用パッケージ２の実装領域Ｒに半田を介して素子３を実装し、素子３の電極を入出力端子６の信号線路７にボンディングワイヤを介して電気的に接続する。さらに、枠体５上に、例えば半田またはろう材等の接合部材を介して蓋体１１を接合することで、実装構造体１を作製することができる。   Next, the element 3 is mounted on the mounting region R of the element storage package 2 via solder, and the electrode of the element 3 is electrically connected to the signal line 7 of the input / output terminal 6 via a bonding wire. Furthermore, the mounting structure 1 can be produced by joining the lid 11 on the frame 5 via a joining member such as solder or brazing material.

１ 実装構造体
２ 素子収納用パッケージ
３ 素子
４ 基板
４Ａ 湾曲部
５ 枠体
６ 入出力端子
６ａ 第１誘電体層
６ｂ 第２誘電体層
７ 信号線路
８ 第１接地導体
９ 第２接地導体
１０ リード端子
１１ 蓋体
Ｒ 実装領域
Ｈ 貫通孔 DESCRIPTION OF SYMBOLS 1 Mounting structure 2 Element accommodation package 3 Element 4 Board | substrate 4A Bending part 5 Frame 6 Input / output terminal 6a First dielectric layer 6b Second dielectric layer 7 Signal line 8 First ground conductor 9 Second ground conductor 10 Lead Terminal 11 Lid R Mounting area H Through hole

Claims (4)

上面に素子の実装領域を有する基板と、
前記基板上に前記実装領域を取り囲むように設けられた、一部に貫通孔を有する枠体と、前記基板上に前記貫通孔を通って前記枠体の内外にわたって設けられた入出力端子とを備え、
前記基板の上面の外周縁には、前記基板の上面の外周縁の曲率が、前記基板の下面の外周縁の曲率よりも小さい湾曲部が設けられており、
前記湾曲部の直上に、前記枠体で囲まれない領域に位置する前記入出力端子の端面が位置していることを特徴とする素子収納用パッケージ。 A substrate having an element mounting region on the upper surface;
A frame having a part of a through hole provided on the substrate so as to surround the mounting region, and an input / output terminal provided on the substrate through the through hole and inside and outside the frame. Prepared,
The outer peripheral edge of the upper surface of the substrate is provided with a curved portion in which the curvature of the outer peripheral edge of the upper surface of the substrate is smaller than the curvature of the outer peripheral edge of the lower surface of the substrate,
An element storage package, wherein an end face of the input / output terminal located in a region not surrounded by the frame is located immediately above the bending portion. 請求項１に記載の素子収納用パッケージであって、
前記基板の上面の外周縁の曲率は、前記入出力端子の下面の外周縁の曲率よりも小さいことを特徴とする素子収納用パッケージ。 The device storage package according to claim 1,
The element storage package, wherein the curvature of the outer peripheral edge of the upper surface of the substrate is smaller than the curvature of the outer peripheral edge of the lower surface of the input / output terminal. 請求項１または請求項２に記載の素子収納用パッケージであって、
前記湾曲部は、前記基板の外周縁の全周にわたって連続して設けられていることを特徴とする素子収納用パッケージ。 The element storage package according to claim 1 or 2,
The package for storing elements, wherein the curved portion is continuously provided over the entire outer periphery of the substrate. 請求項１乃至請求項３のいずれかに記載の素子収納用パッケージと、
前記素子収納用パッケージの前記実装領域に実装された素子とを備えたことを特徴とする実装構造体。
The element storage package according to any one of claims 1 to 3,
A mounting structure comprising: an element mounted in the mounting region of the element storage package.
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