WO2021077332A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2021077332A1
WO2021077332A1 PCT/CN2019/112786 CN2019112786W WO2021077332A1 WO 2021077332 A1 WO2021077332 A1 WO 2021077332A1 CN 2019112786 W CN2019112786 W CN 2019112786W WO 2021077332 A1 WO2021077332 A1 WO 2021077332A1
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WIPO (PCT)
Prior art keywords
layer
insulating layer
contact pad
display area
display
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Application number
PCT/CN2019/112786
Other languages
English (en)
French (fr)
Inventor
都蒙蒙
董向丹
马宏伟
颜俊
程博
刘彪
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP23209143.9A priority Critical patent/EP4297552A3/en
Priority to CN201980002086.2A priority patent/CN113099731A/zh
Priority to US16/768,323 priority patent/US11515379B2/en
Priority to CN202211098029.9A priority patent/CN115768197B/zh
Priority to EP19945403.4A priority patent/EP4050658B1/en
Priority to EP23164060.8A priority patent/EP4221484A1/en
Priority to PCT/CN2019/112786 priority patent/WO2021077332A1/zh
Publication of WO2021077332A1 publication Critical patent/WO2021077332A1/zh
Priority to US17/957,151 priority patent/US11980074B2/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors

Definitions

  • the embodiments of the present disclosure relate to a display substrate, a preparation method thereof, and a display device.
  • At least one embodiment of the present disclosure provides a display substrate, including a base substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of leads, at least one contact pad, and a first insulating layer.
  • the base substrate includes a display area and a bonding area located on at least one side of the display area; multiple sub-pixels located in the display area; multiple data lines located in the display area and configured to Sub-pixels provide data signals; multiple data leads are located in the bonding area and electrically connected to the multiple data lines; at least one set of contact pads located in the bonding area, the at least one set of contact pads includes A plurality of contact pads, at least one of the plurality of contact pads includes a first contact pad metal layer and a second contact pad metal layer, and the first contact pad metal layer is located on the plurality of data leads away from the substrate One side of the substrate is electrically connected to one of the plurality of data leads, and the second contact pad metal layer is located on the side of the first contact pad metal layer away from
  • the vertical distance between the surface of the first insulating layer on the side away from the base substrate and the base substrate is not greater than that of the plurality of contact pads away from the base substrate.
  • the vertical distance between the surface of one side of the base substrate and the base substrate is not greater than that of the plurality of contact pads away from the base substrate.
  • the edge of the second contact pad metal layer is covered by the first insulating layer.
  • the at least one set of contact pads includes a first set of contact pads and a second set of contact pads, and the first set of contact pads and the second set of contact pads are respectively It includes a plurality of contact pads, the second set of contact pads is located on a side of the first set of contact pads close to the display area, and the plurality of data leads are connected to the first set of contact pads and the second set of contact pads.
  • the contact pads are electrically connected in a one-to-one correspondence.
  • At least part of the first insulating layer is located in the gap between the adjacent contact pads of the first set of contact pads.
  • At least part of the first insulating layer is located in a gap between adjacent contact pads in the second set of contact pads.
  • At least part of the first insulating layer is located in the gap between adjacent contact pads in the first set of contact pads and located in the second set of contact pads. In the gap between adjacent contact pads in the pad.
  • the plurality of contact pads of the first group of contact pads are arranged in at least a first row, and the plurality of contact pads of the second group of contact pads are arranged in at least The second row; the row direction of the first row and the second row is parallel to the extending direction of the side of the display area facing the bonding area, and at least part of the first insulating layer is located in the The gap between the first row and the second row.
  • At least one of the plurality of sub-pixels includes a pixel driving circuit, a first planarization layer, a first transfer electrode, a second planarization layer, and a light-emitting element.
  • the first planarization layer is on the side of the pixel driving circuit away from the base substrate to provide a first planarized surface and includes a first via hole, and the first transfer electrode is on the first planarized surface , And electrically connected to the pixel driving circuit through the first via hole, the second planarization layer is provided on the side of the first transfer electrode away from the base substrate to provide a second planarization surface and Comprising a second via hole, the light emitting element is on the second planarized surface and is electrically connected to the first transfer electrode through the second via hole, wherein the first insulating layer is connected to the first
  • the two planarization layers are arranged in the same layer.
  • the pixel driving circuit includes a first display area metal layer, the first display area metal layer and the first contact pad metal layer are arranged in the same layer, and the The first transfer electrode and the second contact pad metal layer are arranged in the same layer.
  • the pixel driving circuit includes a thin film transistor, the thin film transistor includes a source and a drain, and the source and the drain are located in the metal layer of the first display area. In the same layer as the metal layer in the first display area.
  • At least one of the plurality of sub-pixels further includes a passivation layer, and the passivation layer is located between the pixel driving circuit and the first planarization layer and Including a passivation layer via, wherein the pixel driving circuit and the first transfer electrode are also electrically connected through the passivation layer via;
  • the display substrate further includes a second An insulating layer, wherein the second insulating layer is between the first contact pad metal layer and the second contact pad metal layer and covers the edge of the first contact pad metal layer, and the second insulating layer There is a first contact pad via hole, and the second contact pad metal layer is electrically connected to the first contact pad metal layer through the first contact pad via hole; wherein, the second insulating layer and the passivation Same layer settings.
  • At least one of the plurality of sub-pixels further includes a storage capacitor
  • the storage capacitor includes two capacitor electrodes
  • the thin film transistor further includes a gate
  • the plurality of At least one of the data leads and one of the two capacitor electrodes of the storage capacitor are arranged in the same layer as the gate electrode.
  • the display substrate provided by at least one embodiment of the present disclosure further includes: an interlayer insulating layer in the bonding area, located in the bonding area, and located between the plurality of contact pads and the leads and the first Between an insulating layer and the base substrate; the first gate insulating layer in the bonding area is located in the bonding area and on the side of the interlayer insulating layer of the bonding area close to the base substrate; And a second gate insulating layer in the bonding region, located in the bonding region and between the first gate insulating layer in the bonding region and the interlayer insulating layer in the bonding region, and the bonding region layer
  • the interlayer insulating layer is stacked; wherein the second gate insulating layer of the bonding region includes a first contact pad via hole, the interlayer insulating layer of the bonding region includes a second contact pad via hole, and at least one of the plurality of data leads One line is electrically connected to the contact pad through the first contact pad via hole and the second contact pad via hole.
  • At least one of the plurality of sub-pixels further includes an interlayer insulating layer in the display area, a first gate insulating layer in the display area, and a second gate insulating layer in the display area.
  • the interlayer insulating layer in the display area, the first gate insulating layer in the display area, and the second gate insulating layer in the display area are connected to the interlayer insulating layer in the bonding area, the first gate insulating layer in the bonding area, and the second gate insulating layer in the bonding area, respectively.
  • the two gate insulating layers are arranged in the same layer; the display area interlayer insulating layer is located between the gate and the source and drain electrodes, and the first gate insulating layer in the display area is located between the display area layers
  • the insulating layer is close to one side of the base substrate, and the second gate insulating layer in the display area is located between the interlayer insulating layer in the display area and the first gate insulating layer in the display area;
  • the two capacitor electrodes include The first capacitor electrode and the second capacitor electrode, the first capacitor electrode and the gate electrode are arranged in the same layer, and the second capacitor electrode is arranged on the interlayer insulating layer in the display area to be insulated from the second gate electrode in the display area Between layers.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a third insulating layer in a bonding area, wherein the third insulating layer in the bonding area is located in the bonding area and is disposed on the first insulating layer.
  • Layer and the contact pad on a side away from the base substrate to cover the first insulating layer and the contact pad, and the third insulating layer of the bonding area has a third contact pad via hole to expose the contact The surface of the pad.
  • the display substrate provided by at least one embodiment of the present disclosure further includes an encapsulation layer located in the display area and a third insulating layer in the display area.
  • the encapsulation layer is located on a side of the light-emitting element away from the base substrate, so
  • the third insulating layer in the display area is located on a side of the packaging layer away from the base substrate, wherein the third insulating layer in the bonding area and the third insulating layer in the display area are located in the same layer.
  • the display substrate provided by at least one embodiment of the present disclosure further includes an auxiliary conductive layer, wherein the auxiliary conductive layer is located in the bonding area, and the third insulating layer is disposed in the bonding area away from the liner.
  • the auxiliary conductive layer includes a second transfer electrode pattern located in the bonding area, wherein the second transfer electrode pattern is in contact with the contact through the third contact pad via hole Pad electrical connection.
  • the display substrate provided by at least one embodiment of the present disclosure further includes an auxiliary electrode layer disposed on the third insulating layer of the display area, wherein the auxiliary electrode layer and the second connecting electrode pattern are disposed in the same layer.
  • the height of the second transfer electrode pattern relative to the surface of the base substrate is not greater than that of the first bonding area.
  • At least one embodiment of the present disclosure provides a display device including the display substrate provided in any embodiment of the present disclosure.
  • At least one embodiment of the present disclosure provides a method for preparing a display substrate, including: providing a base substrate, wherein the base substrate includes a display area and a bonding area located on at least one side of the display area; A plurality of sub-pixels are formed in the region; a plurality of data lines are formed in the display region, and the plurality of data lines are configured to provide data signals to the plurality of sub-pixels; and a plurality of data leads are formed in the bonding region , The plurality of data leads are electrically connected to the plurality of data lines; at least one set of contact pads is formed in the bonding area, the at least one set of contact pads includes a plurality of contact pads, and the plurality of contact pads At least one of them is formed to include a first contact pad metal layer and a second contact pad metal layer, and the first contact pad metal layer is formed to be located on the side of the plurality of data leads away from the base substrate and connected to the One of the plurality of data leads is electrically connected, and the second contact pad
  • forming the first insulating layer includes: making the height of the first insulating layer relative to the surface of the base substrate not greater than that of the contact pad. The height relative to the surface of the base substrate.
  • forming a plurality of sub-pixels in the display area includes: forming a plurality of sub-pixels in the display area, wherein at least one of the plurality of sub-pixels includes pixel driving A circuit, a first planarization layer, and a light-emitting element, and forming the sub-pixels in the display area includes: forming the pixel driving circuit on the base substrate, where the pixel driving circuit is away from the base substrate Forming the first planarization layer to provide a first planarization surface and forming a first via hole in the first planarization layer, and forming the first transition on the first planarization surface Electrode, wherein the first transfer electrode is electrically connected to the pixel driving circuit through the first via hole, and the second flat is formed on the side of the first transfer electrode away from the base substrate.
  • a second flattened surface and a second via is formed in the second flattened layer, wherein the first insulating layer and the second flattened layer are formed by the same second insulating material layer;
  • the light-emitting element is formed on the second planarized surface, wherein the light-emitting element is electrically connected to the first transfer electrode through the second via hole.
  • forming the first insulating layer and the second planarization layer through the same first insulating material layer includes: forming the contact pads and the pixel driver After the circuit is completed, a first insulating material layer is deposited on the base substrate; a patterning process is performed on the first insulating material layer so that the portion of the first insulating material layer located in the display area is formed as the A second planarization layer and the second via hole is formed in the second planarization layer, the portion of the first insulating material layer overlapping with the contact pad is removed, and the first insulating material is thinned The part of the layer located in the bonding area and located at the edge of the contact pad to form the first insulating layer.
  • forming the first insulating layer and the second planarization layer through the same first insulating material layer includes: forming the contact pads and the pixel driver After the circuit is completed, a first insulating material layer is deposited on the base substrate, wherein the first insulating material layer includes a photosensitive resin; a gray tone mask or a halftone mask is used to expose the first insulating material layer, After the exposed photoresist is developed, the portion of the first insulating material layer located in the display region is formed as the second planarization layer and the second planarization layer is formed in the second planarization layer.
  • the second via hole removes the part of the first insulating material layer that overlaps the contact pad, and thins the part of the first insulating material layer that is located in the bonding area and located at the edge of the contact pad. Forming the first insulating layer.
  • the patterning process on the first insulating material layer includes: patterning the first insulating material layer using a gray tone mask or a halftone mask patterning process .
  • FIG. 1A is a schematic diagram of a three-layer metal stack (Ti/Al/Ti) used in the electrode layer;
  • FIG. 1B is a schematic diagram of the edge peeling off of the three-layer metal laminate (Ti/Al/Ti);
  • FIG. 2A is a schematic plan view of a display substrate provided by an embodiment of the present disclosure.
  • 2B is a schematic plan view of a bonding area of a display substrate provided by an embodiment of the present disclosure
  • 3A is a schematic cross-sectional view of the display substrate shown in FIG. 2B along M1-N1;
  • 3B is a schematic cross-sectional view of the display substrate shown in FIG. 2B along M2-N2;
  • 3C is a schematic cross-sectional view of the display substrate shown in FIG. 2B along M3-N3;
  • FIG. 4 is a schematic cross-sectional view of the display area of the display substrate shown in FIG. 2B;
  • FIG. 5A is a schematic cross-sectional view of the display substrate shown in FIG. 2B along M1-N1 according to another embodiment of the present disclosure
  • FIG. 5B is a schematic cross-sectional view of the display area of the display substrate shown in FIG. 2B according to another embodiment of the present disclosure
  • FIG. 6 is a schematic plan view of still another bonding area of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 7A is a schematic cross-sectional view of the display substrate shown in FIG. 6 along M4-N4 according to an embodiment of the present disclosure
  • FIG. 7B is a schematic cross-sectional view of the display area of the display substrate shown in FIG. 6 provided by an embodiment of the present disclosure
  • FIG. 8A is a schematic cross-sectional view of the display substrate shown in FIG. 6 along M4-N4 according to another embodiment of the present disclosure
  • FIG. 8B is a schematic cross-sectional view of the display area of the display substrate shown in FIG. 6 according to another embodiment of the present disclosure.
  • 9A to 9M are process diagrams of a method for preparing a display substrate provided by some embodiments of the present disclosure.
  • the resolution of organic light emitting diode (OLED) display devices is getting higher and higher, and the frame of the display device is getting narrower and narrower, so that the pixel size of the backplane circuit of the display device is gradually reduced. Since the width of the circuit traces in the backplane circuit and the line spacing of the circuit traces are reduced, the metal residue and etching loss of the backplane circuit in the etching process in the actual production process can easily cause the backplane circuit to short-circuit, thereby affecting the display The yield of the device.
  • the anode of the OLED adopts a wet etching process.
  • the acid etching solution used is likely to cause a serious over-etching phenomenon on other metal layers that have been formed under the anode.
  • the display device includes a transfer electrode metal layer or a source/drain metal layer located under the OLED, the transfer electrode metal layer is electrically connected to the anode, and the source/drain metal layer is electrically connected to the transfer electrode layer.
  • the over-etching phenomenon of the anode is likely to have a greater impact on the transition electrode metal layer or the source/drain metal layer.
  • the transfer electrode metal layer or the source/drain metal layer is made of a multi-metal laminate layer (such as a titanium, aluminum, and titanium three-layer metal laminate (Ti/Al/Ti)), the metal layer in the middle The aluminum metal layer is easily overetched by the acid etching solution, and an undercut phenomenon occurs, which in turn causes the titanium metal layer on the aluminum metal layer at the edge of the electrode pattern to appear floating.
  • the titanium metal in the suspended part is likely to peel off.
  • the detached titanium metal is generally in the shape of a long strip, and it is easy to remain in the display device, thereby causing a signal short-circuit phenomenon in the backplane circuit of the display device.
  • the display device displays a screen
  • the remaining titanium metal that has fallen off is likely to cause poor brightness of the display device.
  • the problem of poor brightness and darkness is particularly prominent.
  • At least one embodiment of the present disclosure provides a display substrate, a preparation method thereof, and a display device.
  • the display substrate includes a base substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of leads, at least one contact pad and a first insulating layer.
  • the base substrate includes a display area and a bonding area located on at least one side of the display area; multiple sub-pixels located in the display area; multiple data lines located in the display area and configured to provide data signals to the multiple sub-pixels; multiple The data lead is located in the bonding area and electrically connected to a plurality of data lines; at least one set of contact pads is located in the bonding area, the at least one set of contact pads includes a plurality of contact pads, and at least one of the plurality of contact pads includes a first A contact pad metal layer and a second contact pad metal layer.
  • the first contact pad metal layer is located on the side of the multiple data leads away from the base substrate and is electrically connected to one of the multiple data leads.
  • the second contact pad metal layer is located in the first The contact pad metal layer is far away from the base substrate and is electrically connected to the first contact pad metal layer.
  • the second contact pad metal layer covers the edge of the first contact pad metal layer.
  • the first insulating layer is located in the bonding area. The layer is located in the gaps between the contact pads and covers the edges of the contact pads, and is configured to expose the surfaces of the contact pads facing away from the base substrate.
  • the first insulating layer located in the bonding area of the display substrate is located in the gap between the contact pads and covers the edges of the contact pads, so that the first insulating layer can be Protect the edge of the metal layer in the contact pad, avoid subsequent etching of the metal layer in the exposed contact pad by the etching solution used when forming the transfer metal layer, and prevent the titanium metal in the suspended part from peeling off, thereby improving the display The product yield and reliability of the substrate.
  • a spatial rectangular coordinate system is established based on the base substrate of the display substrate, and the position of each structure in the display substrate is described based on this.
  • the X axis and the Y axis are parallel to the plane where the base substrate is located, and the Z axis is perpendicular to the plane where the base substrate is located.
  • FIG. 2A is a schematic plan view of a display substrate provided by an embodiment of the present disclosure.
  • 2B is a schematic plan view of a bonding area of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate is used in, for example, an organic light emitting diode (OLED) display device or a quantum dot light emitting diode (QLED) display device.
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • the display substrate 100 includes a base substrate 1000, and the base substrate 1000 includes a display area 1100 and a peripheral area surrounding the display area 1100, and the peripheral area includes at least one bonding area 1200.
  • the figure shows four bonding zones, but the embodiments of the present disclosure are not limited thereto.
  • the display area 1100 includes a pixel array and scan lines (gate lines), data lines, power lines, detection lines, etc. that provide control signals, data signals, voltage signals, etc. for the pixel array.
  • the display area 1100 includes a plurality of sub-pixels and a plurality of data lines 1101, and the plurality of data lines 1101 includes a signal line 1102 (for example, gate line G) extending along a first direction (the X-axis direction in the figure) and The signal lines 1103 (for example, the data line D) extending in the second direction (the Y-axis direction in the figure).
  • the display substrate includes a plurality of leads 1220 (ie, data leads) located in the bonding area 1200.
  • the signal line 1103 is electrically connected to the corresponding lead, so that it can be electrically connected to the driving chip, flexible circuit board, etc. of the bonding area.
  • the bonding area 1200 is located at one side of the display area 1100 and is used to electrically connect the external circuit and the display substrate through the bonding process.
  • the external circuit may include a chip-mounted flexible circuit board (for example, Chip On Film, COF for short), and a control chip or a driving chip, etc., are arranged on the flexible circuit board.
  • the bonding area can also be used for direct electrical connection with the chip.
  • the display substrate 100 may further include at least one set of contact pads, the at least one set of contact pads includes a plurality of contact pads 1210, and the plurality of contact pads 1210 are disposed on the bonding region 1200.
  • the plurality of leads 1220 are electrically connected to the plurality of contact pads 1210 in a one-to-one correspondence.
  • One end of the lead 1220 extends to the display area 1100 to be electrically connected to a signal line (such as a data line) in the display area 1100, and the other end of the lead 1220 extends to the bonding area 1200 to be electrically connected to the contact pad 1210.
  • the lead 1220 is formed in the same layer as the signal line in the display area 1100, for example, and thus can be formed integrally or formed in a different layer, and thus needs to be electrically connected to each other through a via hole in the insulating layer between the two.
  • At least one set of contact pads includes a plurality of contact pads 1210.
  • the plurality of contact pads can also be divided into a first contact pad 1210 and a second group of contact pads 1210'.
  • the second set of contact pads 1210' is located on the side of the first set of contact pads 1210 close to the display area 1100, and at least one of the plurality of leads 1220 is connected to the first set of contact pads 1210 and the second set of contact pads 1210'.
  • the plurality of contact pads 1210 are arranged in the direction of the display area 1100 facing the side of the bonding area 1200, and may be in a single row or multiple rows, for example, arranged in two rows, that is, the L1 row (that is, the first row) and the L2 row (Ie, the second row), where the L2 row is located between the L1 row and the display area.
  • the embodiments of the present disclosure are not limited to the number of rows of contact pads. There are spaces between the contact pads 1210 in the same row, and there are also spaces between the contact pads 1210 in different rows.
  • section line M1-N1 passes through the contact pad 1211 and the contact pad 1212 in the L1 row
  • section line M2-N2 passes through the contact pad 1213 and the contact pad 1214 in the L2 row
  • section line M3-N3 passes through The contact pad 1212 located in the L1 row and the contact pad 1214 located in the L2 row.
  • the display substrate further includes a first insulating layer, and at least a part of the first insulating layer is located in a gap between adjacent contact pads of the first group of contact pads.
  • at least part of the first insulating layer is located in the gap between adjacent contact pads in the second set of contact pads.
  • at least part of the first insulating layer is located in the gap between adjacent contact pads in the first group of contact pads and in the gap between adjacent contact pads in the second group of contact pads.
  • the height of the first insulating layer relative to the surface of the base substrate is not greater than the height of the contact pad relative to the surface of the base substrate.
  • the display substrate may further include a first insulating layer 1230, which is disposed on the bonding area 1200.
  • the first insulating layer 1230 covers at least part of the edges of the plurality of contact pads 1210.
  • the contact pad 1210 includes at least one contact pad metal layer, for example, a plurality of contact pad metal layers.
  • the top metal layer of at least one contact pad metal layer of the contact pad 1210 is exposed for electrical connection.
  • 3A is a schematic cross-sectional view of the display substrate shown in FIG. 2B along M1-N1.
  • 3B is a schematic cross-sectional view of the display substrate shown in FIG. 2B along M2-N2.
  • 3C is a schematic cross-sectional view of the display substrate shown in FIG. 2B along M3-N3.
  • the at least one contact pad metal layer of the contact pad 1210 may include a first contact pad metal layer 1215 and a second contact pad metal layer 1217, and the second contact pad metal layer 1217 is laminated on the first contact pad metal layer 1215.
  • a contact pad metal layer 1215 is away from the side of the base substrate 1000.
  • the top metal layer of the contact pad is the second contact pad metal layer 1217.
  • the first insulating layer 1230 includes a gap corresponding to each contact pad 1210, and is thus configured to expose the surface of the contact pad 1210 facing away from the base substrate 1000.
  • the area outside the contact pads 1210 in the bonding region 1200 is covered by the first insulating layer 1230, and this area includes, but is not limited to, gaps between contact pads in the same row and gaps between contact pads in different rows. Therefore, during the preparation process of the display substrate, the first insulating layer can protect the edges of the contact pads, and prevent the etching solution from etching the edges of the exposed contact pads in the subsequent patterning process, thereby improving the product yield and reliability of the display substrate. Sex.
  • the base substrate 1000 may be a glass plate, a quartz plate, a metal plate, or a resin-based plate.
  • the material of the base substrate may include an organic material.
  • the organic material may be polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, and polyethylene terephthalate.
  • resin materials such as polyethylene naphthalate
  • the base substrate 1000 may be a flexible substrate or a non-flexible substrate, which is not limited in the embodiments of the present disclosure.
  • the thickness of the first insulating layer is large, the surface of the first insulating layer relative to the base substrate and the surface of the contact pad will have a large step difference. It is easy to bond the external circuit in the bonding area. Causes poor contact between the external circuit and the contact pad in the bonding area.
  • the metal laminate layer of the contact pad in the bonding area is thick, when the external circuit is bonded, the groove on the top metal layer of the contact pad is more likely to cause the external circuit Poor contact with the contact pads in the bonding area further affects the product yield of the display device. Therefore, in at least one example of this embodiment, in order to avoid poor contact in the bonding area, the thickness of the contact pad is further controlled.
  • the edge of the contact pad includes the edge of the contact pad in the circumferential direction, that is, in a cross-sectional view obtained by a section line passing through the contact pad in any direction, the edge of the contact pad is covered by the first insulating layer.
  • the first insulating layer 1230 covers the edge of the second contact pad metal layer 1217.
  • the second contact pad metal layer 1217 is located on the first contact pad metal layer 1215 and covers the edge of the first contact metal layer 1215 to prevent the first contact pad metal layer 1215 from being exposed and corroded by the etching solution in the subsequent patterning process
  • the second contact pad metal layer 1217 can form a step, which increases the contact area between the first insulating layer 1230 and the second contact pad metal layer 1217 and prevents peeling.
  • the height H1 of the first insulating layer 1230 relative to the surface of the base substrate 1000 is not greater than that of the second contact pad metal layer 1217 of the contact pad 1210.
  • the distance H2 from the surface to the surface of the base substrate 1000 Limiting the height of the first insulating layer 1230, that is, the thickness of the first insulating layer 1230, can improve the poor contact phenomenon in the bonding area and improve the product yield.
  • the second insulating layer 1250 is disposed between the first contact pad metal layer 1215 and the second contact pad metal layer 1217.
  • the second insulating layer 1250 covers the edge of the first contact pad metal layer 1215 to prevent the edge of the first contact pad metal layer 2215 from being corroded by the etching solution in the subsequent patterning process.
  • the second contact pad metal layer 1217 compared to the edge of the first contact pad metal layer 1215, the second contact pad metal layer 1217 further extends outward on the second insulating layer 1250 to cover the edge of the first contact pad metal layer 1215, That is, on the surface of the base substrate 1000, the orthographic projection of the second contact pad metal layer 1217 covers the orthographic projection of the first contact pad metal layer 1215.
  • Such a structure can reduce the step difference at the edge of the contact pad, and is beneficial for the first insulating layer 1230 to cover the edge of the second contact pad metal layer 1217.
  • the height H1 of the first insulating layer 1230 relative to the surface of the base substrate 1000 is not greater than The distance H2 from the surface of the contact pad 1210 to the surface of the base substrate 1000.
  • the surface of the contact pad 1210 is the surface of the second contact pad metal 1217 that is farthest from the base substrate 1000. Controlling the height of the first insulating layer 1230, that is, the thickness of the first insulating layer 1230, can improve the poor contact phenomenon in the bonding area and improve the product yield.
  • the multiple leads 1220 of the display substrate 100 are respectively located under the corresponding contact pads 1210.
  • the display substrate 100 further includes a bonding region buffer layer 1241 on the base substrate 1000 and a bonding region first gate insulating layer 1242 on the side of the bonding region buffer layer 1241 away from the base substrate 1000.
  • the lead 1220 is located on the first gate insulating layer 1242 in the bonding area. One end of the lead 1220 is electrically connected to the contact pad 1210.
  • the contact pad 1211 in row L1, the contact pad 1212, and the contact pad 1213 and contact pad 1214 in row L2 are electrically connected to one of the plurality of leads 1220, and in this example, the plurality of leads 1220 are located in the same layer Therefore, multiple leads 1220 can be prepared in the same patterning process.
  • multiple leads 1220 may also be located in different layers.
  • the lead of the contact pad 1210 used for the L1 row is located at a layer closer to the base substrate
  • the lead of the contact pad 1210 used for the L2 row is located in a layer closer to the base substrate.
  • the spacing between the multiple leads 1220 in the same layer can be increased, which reduces the risk of interference and short circuits between the leads, which is beneficial to forming a display device with high pixel resolution.
  • multiple leads 1220 in the same layer can be prepared in the same patterning process.
  • the display substrate 100 may further include a second gate insulating layer 1243 in the bonding area and an interlayer insulating layer 1244 in the bonding area.
  • the interlayer insulating layer 1244 in the bonding area is located at at least one lead 1220 away from the base substrate 1000.
  • the contact pad 1210 is disposed on the interlayer insulating layer 1244 in the bonding area.
  • the bonding area interlayer insulating layer 1244 is located in the bonding area, and between the plurality of contact pads 1210 and the first insulating layer 1230 and the base substrate 1000.
  • the second gate insulating layer 1243 of the bonding region is located between the first gate insulating layer 1242 of the bonding region and the interlayer insulating layer 1244 of the bonding region, and is laminated with the interlayer insulating layer 1244 of the bonding region.
  • the second gate insulating layer 1243 of the bonding region includes a first contact pad via 1216
  • the interlayer insulating layer 1244 of the bonding region includes a second contact pad via 1219, and at least one of the plurality of leads 1220 passes through the first contact pad.
  • the hole 1216 and the second contact pad via hole 1219 are electrically connected to the contact pad.
  • the lead 1220 connecting the contact pad 1210 of the L1 row extends through the gap of the contact pad of the L2 row in the bonding area, and then extends to the display area 1100, so that the contact pad 1210 has a larger arrangement space and can avoid connecting with the L2 row
  • the leads 1220 of the contact pads 1210' interfere with each other or short-circuit.
  • the second gate insulating layer 1243 of the bonding region includes a plurality of first contact pad vias 1216
  • the interlayer insulating layer 1244 of the bonding region includes a plurality of second contact pad vias 1219, as shown in FIG. 3C.
  • the contact pad 1212 and the contact pad 1214 include three first contact pad via holes 1216 and three second contact pad via holes 1219.
  • the number of the first contact pad via hole 1216 and the second contact pad via hole 1219 can also be multiple, for example, two or four. The present disclosure does not use the first contact pad via hole 1216. And the number of second contact pad via holes 1219 is limited.
  • multiple leads 1220 may also be located in different layers.
  • the leads of the contact pads 1210 used in the L1 row are located in a layer closer to the base substrate, and the leads of the contact pads 1210 used in the L2 row are located opposite to each other. A layer further away from the base substrate (but still between the contact pad and the base substrate). Therefore, the spacing between the multiple leads 1220 in the same layer can be increased, which reduces the risk of interference and short circuits between the leads, which is beneficial to forming a display device with high pixel resolution.
  • multiple leads 1220 in the same layer can be prepared in the same patterning process; multiple leads 1220 in different layers can be prepared in different patterning processes.
  • the material of the first insulating layer 1230 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or may include polyimide, polyphthalimide, polyphthalamide, acrylic resin, and benzocyclobutyl. Organic insulating materials such as olefin or phenolic resin.
  • the embodiment of the present disclosure does not specifically limit the material of the first insulating layer.
  • the material of the lead may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum, and titanium.
  • the material of the first contact pad metal layer may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, and titanium.
  • the sub-pixel of each pixel unit in the pixel array of the display area of the display substrate includes a pixel driving circuit, a first planarization layer, a first transfer electrode, a second planarization layer, and a light emitting element.
  • the first planarization layer is on the side of the pixel driving circuit away from the base substrate to provide a first planarized surface and includes a first via hole.
  • the first transfer electrode is on the first planarized surface and passes through the first via hole.
  • the pixel driving circuit is electrically connected.
  • the second planarization layer is provided on the side of the first transfer electrode away from the base substrate to provide a second planarized surface and includes a second via hole.
  • the light-emitting element is on the second planarized surface and passes through the second planarized surface.
  • the two via holes are electrically connected to the first transfer electrode, and the first insulating layer and the second planarization layer are arranged in the same layer.
  • the pixel driving circuit may include thin film transistors, storage capacitors, etc., and may be implemented in various types, such as 2T1C type (that is, including two thin film transistors and a storage capacitor), and may further include more than 2T1C type.
  • 2T1C type that is, including two thin film transistors and a storage capacitor
  • Many transistors and/or capacitors can have functions of compensation, reset, light emission control, detection, etc.
  • the embodiments of the present disclosure do not impose limitations on the pixel driving circuit.
  • the thin film transistor directly electrically connected to the light-emitting element may be a driving transistor, a light-emitting control transistor, or the like.
  • “same-layer arrangement” means that two functional layers (for example, the first insulating layer and the second planarization layer) are formed in the same layer and with the same material in the hierarchical structure of the display substrate, that is, in the manufacturing process
  • the two structural layers can be formed of the same material layer, and the required patterns and structures can be formed by the same patterning process.
  • the material layer can be formed by the patterning process after the material layer is formed first.
  • FIG. 4 is a schematic cross-sectional view of the display area of the display substrate shown in FIG. 2B according to an embodiment of the present disclosure.
  • the sub-pixel 110 of each pixel unit in the pixel array of the display area of the display substrate is used to realize light emission driving and control.
  • the sub-pixel 110 includes a pixel driving circuit 1120, a first planarization layer 1130, a first transition electrode 1180, a second planarization layer 1190, and a light-emitting element 1140.
  • the sub-pixel further includes a buffer layer 1121 located on the base substrate 1000
  • the pixel driving circuit 1120 includes an active layer 1122 located on the buffer layer 1121 of the display area, and a display located on the side of the active layer 1122 away from the base substrate 1000.
  • the gate 11211 may be arranged in the same layer as the lead 1220 in the bonding area 1200. Therefore, the gate 11211 and the lead 1220 can be formed in the same layer during the preparation process, for example, the same material layer is used to form the same layer through a patterning process.
  • the display area buffer layer 1121 in the display area and the bonding area buffer layer 1241 in the bonding area are arranged in the same layer, and the display area buffer layer 1121 and the bonding area buffer layer 1241 can be formed in the same layer in the manufacturing process.
  • the first gate insulating layer 1128 of the display area in the display area is arranged in the same layer as the first gate insulating layer 1242 of the bonding area in the bonding area, and the second gate insulating layer 1129 of the display area in the display area is the same as the bonding area of the bonding area.
  • the second gate insulating layer 1243 in the fixed area is arranged in the same layer, and the interlayer insulating layer 11211 in the display area in the display area is arranged in the same layer as the interlayer insulating layer 1244 in the bonding area.
  • the display area buffer layer 1121 serves as a transition layer, which can prevent harmful substances in the base substrate from intruding into the interior of the display substrate, and can increase the adhesion of the film layer in the display substrate on the base substrate 1000.
  • the material of the buffer layer 1121 in the display area may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the material of one or more of the interlayer insulating layer 11210 in the display area, the second gate insulating layer 1129 in the display area, and the first gate insulating layer 1128 in the display area may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the materials of the interlayer insulating layer 11210 in the display area, the second gate insulating layer 1129 in the display area, and the first gate insulating layer 1128 in the display area may be the same or different.
  • the active layer 1122 may include a source region 1123 and a drain region 1124, and a trench located between the source region 1123 and the drain region 1124.
  • the interlayer insulating layer 11210 in the display area, the second gate insulating layer 1129 in the display area, and the first gate insulating layer 1128 in the display area have via holes to expose the source region 1123 and the drain region 1124.
  • the source electrode 1125 and the drain electrode 1126 are electrically connected to the source region 1123 and the drain region 1124 through via holes, respectively.
  • the gate 11211 overlaps the channel region between the source region 1123 and the drain region 1124 in the active layer 1122 in a direction perpendicular to the base substrate 1000.
  • the first planarization layer 1130 is located above the source electrode 1125 and the drain electrode 1126, and is used to planarize the surface of the pixel driving circuit away from the base substrate.
  • a first via hole 1131 is formed in the first planarization layer 1130 to expose the source electrode 1125 or the drain electrode 1126 (the case shown in the figure).
  • a passivation layer 11110 is formed between the pixel driving circuit 1120 and the first planarization layer 1130, and the passivation layer 11110 includes a passivation layer via 11111.
  • the passivation layer can protect the source and drain of the pixel drive circuit from being corroded by water vapor.
  • a first connecting electrode 1180 is formed on the first planarization layer 1130.
  • the first transfer electrode 1180 is electrically connected to the drain 1126 through the first via hole 1131 and the passivation layer via hole 11111.
  • the first transfer electrode can avoid directly forming an aperture in the first planarization layer and the second planarization layer A relatively large straight through hole improves the quality of the electrical connection of the via.
  • the first transfer electrode can also be formed in the same layer as other signal lines (such as power lines), which will not increase the number of process steps.
  • the first transfer electrode 1180 and the second contact pad metal layer 1217 of the contact pad 1210 are arranged in the same layer. Therefore, the first transfer electrode 1180 and the second contact pad metal layer 1217 can be formed in the same layer during the preparation process, for example, the same layer is used.
  • the material layer is formed by a patterning process, thereby simplifying the preparation process.
  • the material of the first transfer electrode 1180 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum, and titanium.
  • the material of the active layer 1122 may include polysilicon or oxide semiconductor (for example, indium gallium zinc oxide).
  • the material of the gate 11211 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum, and titanium.
  • the multi-layer structure is a multi-metal laminated layer (such as three layers of titanium, aluminum, and titanium). Metal stack (Ti/Al/Ti).
  • the material of the source electrode 1125 and the drain electrode 1126 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, and titanium.
  • the layer structure is a multi-metal laminate layer (such as a three-layer metal laminate of titanium, aluminum, and titanium (Ti/Al/Ti)). The embodiments of the present disclosure do not specifically limit the material of each functional layer.
  • the material of the passivation layer may include an organic insulating material or an inorganic insulating material, for example, silicon nitride material. Due to its high dielectric constant and good hydrophobic function, it can well protect the pixel drive circuit from being damaged. Corroded by water vapor.
  • the pixel driving circuit 1120 may further include a first display metal layer 1127, and the first display area metal layer 1127 and the first contact pad metal layer 1215 are provided in the same layer.
  • the first display metal layer 1127 includes the source electrode 1125 and the drain electrode 1126 of the above-mentioned thin film transistor in the pixel driving circuit.
  • the source electrode 1125 and the drain electrode 1126 are arranged in the same layer as the first contact pad metal layer 1215.
  • the source electrode 1125 and the drain electrode 1126 and the first contact pad metal layer 1215 can be formed in the same layer during the manufacturing process, for example, the same material layer is formed through a patterning process, thereby simplifying the manufacturing process and reducing the manufacturing cost of the product.
  • the second planarization layer 1190 is disposed on the side of the first transfer electrode 1180 away from the base substrate 1000, so as to provide the first transfer electrode 1180 away from the substrate 1000.
  • a flattened surface is provided on one side of the base substrate 1000.
  • a second via 1191 is formed in the second planarization layer 1190.
  • the second planarization layer 1190 is formed in the same layer as the first insulating layer 1230 in the bonding region 1200. Therefore, the second planarization layer 1190 and the first insulating layer 1230 can be formed in the same layer during the preparation process, for example, the same material layer is used to pass The patterning process is formed, thereby simplifying the preparation process.
  • the light-emitting element 1140 is formed on the second planarization layer, that is, the light-emitting element 1140 is disposed on the side of the second planarization layer 1190 away from the base substrate.
  • the light emitting element 1140 includes a first electrode 1141, a light emitting layer 1142, and a second electrode 1143.
  • the first electrode 1141 of the light-emitting element is electrically connected to the first transfer electrode 1180 through the second via 1191 in the second planarization layer 1140.
  • a pixel defining layer 1144 is formed on the first electrode 1141, and the pixel defining layer 1144 includes a plurality of openings to define a plurality of pixel units.
  • Each of the plurality of openings exposes the corresponding first electrode 1141; after that, the light-emitting layer 1142 is disposed in the plurality of openings of the pixel defining layer 1144, and the second electrode 1143 is disposed on the pixel defining layer 1144 and the light-emitting layer 1142, for example, the first electrode 1142.
  • the two electrodes 1143 may be disposed in a part or the entire display area, so that they may be formed on the entire surface during the manufacturing process.
  • the material of the second planarization layer 1190 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc., and may also include polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzo Organic insulating materials such as cyclobutene or phenolic resin are not limited in the embodiments of the present disclosure.
  • the first electrode 1141 may include a reflective layer
  • the second electrode 1143 may include a transparent layer or a semi-transparent layer.
  • the first electrode 1141 can reflect the light emitted from the light-emitting layer 1142, and this part of the light is emitted into the external environment through the second electrode 1143, so that the light emission rate can be improved.
  • the second electrode 1143 includes a semi-transmissive layer, some light reflected by the first electrode 1141 is reflected again by the second electrode 1143, so the first electrode 1141 and the second electrode 1143 form a resonance structure, so that light emission efficiency can be improved.
  • the material of the first electrode 1141 may include at least one transparent conductive oxide material, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and the like.
  • the first electrode 1141 may include a metal having high reflectivity as a reflective layer, such as silver (Ag).
  • the light-emitting layer 1142 may include small molecular organic materials or polymer molecular organic materials, which may be fluorescent light-emitting materials or phosphorescent light-emitting materials, which can emit red light, green light, blue light, or white light; and, as required
  • the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the light-emitting layer may include quantum dot materials, for example, silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, selenium Lead fluoride quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc.
  • the particle size of the quantum dots is 2-20nm.
  • the second electrode 1143 may include various conductive materials.
  • the second electrode 1143 may include metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).
  • the material of the pixel defining layer 1144 may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or inorganic materials such as silicon oxide and silicon nitride.
  • organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or inorganic materials such as silicon oxide and silicon nitride.
  • the insulating material is not limited in the embodiment of the present disclosure.
  • the display substrate further includes a storage capacitor 1160
  • the storage capacitor 1160 may include a first capacitor electrode 1161 and a second capacitor electrode 1162.
  • the first capacitor electrode 1161 is arranged between the first gate insulating layer 1128 in the display area and the second gate insulating layer 1129 in the display area
  • the second capacitor electrode 1162 is arranged between the second gate insulating layer 1129 in the display area and the interlayer insulating layer 11210 in the display area. between.
  • the first capacitor electrode 1161 and the second capacitor electrode 1162 overlap and at least partially overlap in a direction perpendicular to the base substrate 1000.
  • the first capacitor electrode 1161 and the second capacitor electrode 1162 use the second gate insulating layer 1129 of the display area as a dielectric material to form a storage capacitor.
  • the first storage capacitor electrode 1161 is arranged in the same layer as the gate 11211 in the pixel driving circuit 1120 and the lead 1220 in the bonding region 1200. Similarly, as described above, in the modification of the above example, the first capacitor electrode and the second capacitor electrode of the storage capacitor 1160 may also be located in other layers, so as to obtain sub-pixels with different structures.
  • the first capacitance electrode of the storage capacitor is still arranged in the same layer as the gate electrode 11211, and the second capacitance electrode of the storage capacitor is the same as the source electrode 1125 and the drain electrode of the thin film transistor.
  • 1126 is arranged in the same layer (that is, it is also located in the first display metal layer 1127), so the first capacitor electrode and the second capacitor electrode use the stack of the second gate insulating layer 1129 in the display area and the interlayer insulating layer 11210 in the display area as Dielectric materials to form storage capacitors.
  • the first capacitor electrode of the storage capacitor is no longer arranged in the same layer as the gate electrode 11211, but is located in the display area between the second gate insulating layer 1129 and the display area.
  • the second capacitor electrode of the storage capacitor is arranged in the same layer as the source electrode 1125 and drain electrode 1126 of the thin film transistor (that is, it is also located in the first display metal layer 1127), so that the first capacitor electrode and the second capacitor electrode are located in the same layer as the source electrode 1125 and drain electrode 1126 of the thin film transistor.
  • the capacitor electrode uses the display area interlayer insulating layer 11210 as a dielectric material to form a storage capacitor.
  • the display substrate may further include an encapsulation layer 1150 provided on the light emitting element 1140.
  • the encapsulation layer 1150 seals the light emitting element 1140, so that deterioration of the light emitting element 1140 caused by moisture and/or oxygen included in the environment can be reduced or prevented.
  • the encapsulation layer 1150 may be a single layer structure or a composite layer structure.
  • the composite layer structure includes a stacked structure of an inorganic layer and an organic layer.
  • the encapsulation layer 1150 may include a first inorganic encapsulation layer 1151 and a first organic layer arranged in sequence.
  • the encapsulation layer 1150 may extend to the bonding area. In the above example, the encapsulation layer does not cover the contact pads.
  • the material of the encapsulation layer may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin.
  • insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin.
  • Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water and oxygen;
  • the material of the organic encapsulation layer can be a polymer material containing a desiccant or a polymer material that can block water vapor, etc.
  • polymer resins are used to flatten the surface of the display substrate, and can relieve the stress of the first inorganic encapsulation layer and the second inorganic encapsulation layer, and can also include water-absorbing materials such as desiccant to absorb water intruding into the interior, Oxygen and other substances.
  • FIG. 5A is a schematic cross-sectional view of the display substrate shown in FIG. 2B along M1-N1 according to another embodiment of the present disclosure.
  • the structure of the bonding region shown in FIG. 5A is compared with the structure of the bonding region shown in FIG. 3A, and the second insulating layer 1250 is removed in the bonding region 1200 of the display substrate.
  • the second contact pad metal layer 1217 directly covers the edge of the first contact metal layer 1215, which can reduce the thickness of the film layer of the contact pad 1210, thereby reducing the step difference of the film layer, thereby further improving the poor contact phenomenon in the bonding area.
  • FIG. 5B is a schematic cross-sectional view of the display area of the display substrate shown in FIG. 2B according to another embodiment of the present disclosure.
  • the structure of the display substrate shown in FIG. 5B is that the passivation layer 11110 is removed in the sub-pixel (110) of the display area of the display substrate.
  • the display substrate further includes a third insulating layer in the bonding area, and the third insulating layer in the bonding area is located in the bonding area and disposed on the first insulating layer and the contact pad away from the base substrate.
  • One side covers the first insulating layer and the contact pad, and the third insulating layer in the bonding area has a third contact pad via hole to expose the surface of the contact pad.
  • the display substrate further includes an auxiliary conductive layer.
  • the auxiliary conductive layer is located in the bonding area and is arranged on the side of the third insulating layer in the bonding area away from the base substrate.
  • the auxiliary conductive layer includes a second transfer electrode pattern located in the bonding area, wherein the second transfer The electrode pattern is electrically connected to the contact pad through the third contact pad via hole.
  • FIG. 6 is a schematic plan view of another bonding area of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 7A is a schematic cross-sectional view of the display substrate shown in FIG. 6 along M4-N4 according to an embodiment of the present disclosure.
  • the display substrate includes a base substrate 2000, which includes a display area and a peripheral area surrounding the display area, and the peripheral area includes at least one bonding area.
  • the display area includes a pixel array and scanning lines (gate lines), data lines, power lines, detection lines, etc. that provide control signals, data signals, voltage signals, and the like for the pixel array.
  • the display substrate may further include a plurality of leads 2220 and at least one set of contact pads.
  • the at least one set of contact pads includes a plurality of contact pads 2210.
  • the plurality of contact pads can also be divided into a first contact pad 2210 and a second group of contact pads 2210'.
  • the second set of contact pads 2210' is located on the side of the first set of contact pads 2210 close to the display area 1100.
  • the display substrate further includes a bonding region buffer layer 2241 on the base substrate 2000, and a bonding region first gate insulating layer 2242 on the side of the bonding region buffer layer 2241 away from the base substrate 2000.
  • the lead 2220 is located on the first gate insulating layer 2242 in the bonding area.
  • the plurality of leads 2220 are electrically connected to the plurality of contact pads 2210 in a one-to-one correspondence.
  • One end of the lead 2220 extends to the display area to be electrically connected to a signal line (such as a data line) on the display area, and the other end of the lead 2210 extends to the bonding area 2200 to be electrically connected to the contact pad 2210.
  • the plurality of contact pads 2210 are arranged in a single row or in multiple rows.
  • the contact pads are arranged in, for example, two rows, namely, L3 row (first row) and L4 row (second row). ), the L4 line is located between the L3 line and the display area.
  • multiple leads 2220 may also be located in different layers.
  • the lead of the contact pad 2210 used for the L3 row is located at a layer closer to the base substrate
  • the lead of the contact pad 2210 used for the L4 row is located in a layer closer to the base substrate.
  • the leads are located on a layer relatively farther away from the base substrate (but still between the contact pad and the base substrate). Therefore, the spacing between the multiple leads 2220 in the same layer can be increased, which reduces the risk of interference and short circuits between the leads, which is beneficial to forming a display device with high pixel resolution.
  • multiple leads 2220 in the same layer can be prepared in the same patterning process.
  • the display substrate may further include a first insulating layer 2230 and a third insulating layer 2260 in the bonding area, which are disposed on the bonding area 2200.
  • the first insulating layer 2230 covers at least part of the edges of the plurality of contact pads 2210.
  • the contact pad 2210 includes at least one contact pad metal layer, for example, a plurality of contact pad metal layers.
  • the at least one contact pad metal layer of the contact pad 2210 may include a first contact pad metal layer 2215 and a second contact pad metal layer 2217.
  • the second contact pad metal layer 2217 is laminated on the first contact pad metal layer. 2215 is away from the side of the base substrate 2000.
  • the third insulating layer 2260 in the bonding area covers the first insulating layer 2230 and the plurality of contact pads 2210. Therefore, during the manufacturing process of the display substrate, the first insulating layer can protect the edges of the contact pads and prevent the edges of the exposed contact pads from being etched by the etching solution, thereby improving the product yield and reliability of the display substrate.
  • the display substrate may further include a second gate insulating layer 2243 in the bonding area and an interlayer insulating layer 2244 in the bonding area.
  • the bonding area interlayer insulating layer 2240 is located in the bonding area, and between the plurality of contact pads 2210 and the first insulating layer 2230 and the base substrate 2000.
  • the second gate insulating layer 2243 of the bonding region is located between the first gate insulating layer 2242 of the bonding region and the interlayer insulating layer 2244 of the bonding region, and is laminated with the interlayer insulating layer 2244 of the bonding region.
  • the second gate insulating layer 2243 of the bonding region includes a first contact pad via 2216, and the interlayer insulating layer 2244 of the bonding region includes a second contact pad via 2219. At least one of the plurality of leads 2220 passes through the first contact pad. The hole 2216 and the second contact pad via 2219 are electrically connected to the contact pad.
  • the lead 2220 connecting the contact pad 2210 of the L3 row extends through the gap of the contact pad of the L4 row in the bonding area, and then extends to the display area, so that the contact pad 2210 has a larger arrangement space and can avoid the contact with the L3 row.
  • the leads 2220 of the contact pad 2210 interfere with each other or short-circuit.
  • the second contact pad metal layer 2217 is formed on the first contact pad metal layer 2215 and covers the edge of the first contact pad metal layer 2215, so as to prevent the first contact pad metal layer 2215 from being exposed.
  • the etching solution in the subsequent patterning process is corroded.
  • the first insulating layer 2230 covers at least part of the edge of the second contact pad metal layer 2217 of the contact pad 2210.
  • the height of the first insulating layer 2230 relative to the surface of the base substrate 2000 that is, the vertical distance from the surface of the first insulating layer 2230 to the surface of the base substrate 2000, is not greater than the surface of the second contact pad metal layer 2217 of the contact pad 2210 The distance to the surface of the base substrate 2000.
  • Limiting the height of the first insulating layer 2230 that is, the thickness of the first insulating layer 2230, can improve the poor contact phenomenon in the bonding area and improve the product yield.
  • the second contact pad metal layer 2217 directly covers the edge of the first contact metal layer 2215, which can reduce the thickness of the film layer of the contact pad 2210, thereby reducing the step difference of the film layer, thereby further improving the poor contact of the bonding area.
  • the display substrate may further include an auxiliary conductive layer.
  • the auxiliary conductive layer is located in the bonding area and the display area and is disposed on the third insulating layer 2260 in the bonding area.
  • the auxiliary conductive layer includes a second transfer electrode pattern 2270 located in the bonding area.
  • the second transfer electrode pattern 2270 is implemented as a bonding process with an external circuit.
  • a third contact pad via 2218 is formed in the third insulating layer 2260 of the bonding area.
  • the second transfer electrode pattern 2270 is electrically connected to the contact pad through the third contact pad via 2218 to transmit electrical signals.
  • the first insulating layer 2230 is configured to expose the surface of the contact pad 2210 facing away from the base substrate 2000. That is, the area outside the contact pads 2210 in the bonding area 2200 is covered by the first insulating layer 2230, and this area includes, but is not limited to, gaps between contact pads in the same row and gaps between contact pads in different rows.
  • the height of the second transfer electrode pattern 2270 relative to the surface of the base substrate 2000 is not greater than the height of the third insulating layer 2260 in the bonding area relative to the surface of the base substrate 2000 to avoid Poor contact in Bonding District.
  • FIG. 7B is a schematic cross-sectional view of the display area of the display substrate shown in FIG. 6 provided by an embodiment of the present disclosure.
  • the sub-pixel 210 of each pixel unit in the pixel array of the display area of the display substrate may include a pixel driving circuit 2120, a first planarization layer 2130, a first transfer electrode 2180, and a second planarization layer 2190.
  • light-emitting element 2140 may include a pixel driving circuit 2120, a first planarization layer 2130, a first transfer electrode 2180, and a second planarization layer 2190.
  • the sub-pixel also includes a buffer layer 2121 located on the base substrate 2000, and the pixel driving circuit 2120 includes an active layer 2122 located on the buffer layer 2121 of the display area, and a second display area located on the side of the active layer 2122 away from the base substrate 2000.
  • the gate 21211 may be provided in the same layer as the lead 2220 in the bonding region 2200.
  • the display area buffer layer 2121 in the display area and the bonding area buffer layer 2241 in the bonding area are arranged in the same layer, and the display area buffer layer 2121 and the bonding area buffer layer 2241 can be formed in the same layer in the manufacturing process.
  • the first gate insulating layer 2128 of the display area in the display area is arranged in the same layer as the first gate insulating layer 2242 of the bonding area in the bonding area, and the second gate insulating layer 2129 of the display area in the display area is insulated from the second gate of the bonding area.
  • the layers 2243 are arranged in the same layer, and the interlayer insulating layer 21210 in the display area in the display area and the interlayer insulating layer 2244 in the bonding area are arranged in the same layer.
  • the display area buffer layer 2121 serves as a transition layer, which can prevent harmful substances in the base substrate from intruding into the interior of the display substrate, and can increase the adhesion of the film layer in the display substrate on the base substrate 2000.
  • the active layer 2122 includes a source region 2123 and a drain region 2124, and a channel region located between the source region 2123 and the drain region 2124.
  • the display area interlayer insulating layer 21210, the display area second gate insulating layer 2129, and the display area first gate insulating layer 2128 have via holes to expose the source region 2123 and the drain region 2124.
  • the source 2125 and the drain 2126 are electrically connected to the source region 2123 and the drain region 2124 through via holes, respectively.
  • the gate 21211 overlaps with the channel region located between the source region 2123 and the drain region 2124 in the active layer 2122 in a direction perpendicular to the base substrate 2000.
  • the first planarization layer 2130 is located above the source electrode 2125 and the drain electrode 2126, and a first via 2131 is formed in the first planarization layer 2130 to expose the source electrode 2125 or the drain electrode 2126 (the case shown in the figure) ,
  • a first connecting electrode 2180 is formed on the first planarization layer 2130.
  • the first transfer electrode 2180 is electrically connected to the drain 2126 through the first via 2131.
  • the first transfer electrode can avoid directly forming a straight through hole with a relatively large diameter in the first planarization layer and the second planarization layer, thereby improving the quality of the electrical connection of the via hole.
  • the first transfer electrode can also be connected to other The signal lines (for example, power lines, etc.) are formed in the same layer, which will not lead to an increase in process steps.
  • the first transfer electrode 2180 and the second contact pad metal layer 2217 are arranged in the same layer.
  • the pixel driving circuit 2120 may further include a first display metal layer 2127, and the first display area metal layer 2127 and the first contact pad metal layer 2215 are provided in the same layer.
  • the first display metal layer 2127 includes the source 2125 and the drain 2126 of the above-mentioned thin film transistor in the pixel driving circuit.
  • the source electrode 2125 and the drain electrode 2126 and the first contact pad metal layer 2215 are arranged in the same layer.
  • the source electrode 2125 and the drain electrode 2126 and the first contact pad metal layer 2215 can be formed in the same layer during the manufacturing process, for example, the same material layer is formed through a patterning process, thereby simplifying the manufacturing process and reducing the manufacturing cost of the product.
  • the second planarization layer 2190 is disposed on the side of the first transfer electrode 2180 away from the base substrate 2000, and is used when the first transfer electrode 2180 is away from the substrate 2000.
  • One side of the base substrate 2000 provides a flattened surface.
  • a second via 2191 is formed in the second planarization layer 2190.
  • the second planarization layer 2190 is formed in the same layer as the first insulating layer 2230 in the bonding region 2200.
  • the light-emitting element 2140 is formed on the second planarization layer 2190, that is, the light-emitting element 2140 is disposed on the side of the second planarization layer 2190 away from the base substrate.
  • the light emitting element 2140 includes a first electrode 2141, a light emitting layer 2142, and a second electrode 2143.
  • a pixel defining layer 2144 is formed on the first electrode 2141, and the pixel defining layer 2144 includes a plurality of openings to define a plurality of pixel units. Each of the plurality of openings exposes the first electrode 2141, and the light emitting layer 2142 is disposed in the plurality of openings of the pixel defining layer 2144.
  • the second electrode 2143 may be disposed in a part or the entire display area, so that it may be formed on the entire surface during the manufacturing process.
  • the first electrode 2141 of the light-emitting element is electrically connected to the first transfer electrode 2180 through the second via 2191 in the second planarization layer 2140.
  • the display substrate further includes a storage capacitor 2160
  • the storage capacitor 2160 may include a first capacitor electrode 2161 and a second capacitor electrode 2162.
  • the first capacitor electrode 2161 is arranged between the first gate insulating layer 2128 in the display area and the second gate insulating layer 2129 in the display area
  • the second capacitor electrode 2162 is arranged between the second gate insulating layer 2129 in the display area and the interlayer insulating layer 21210 in the display area. between.
  • the first capacitor electrode 2161 and the second capacitor electrode 2162 overlap and at least partially overlap in a direction perpendicular to the base substrate 2000.
  • the first capacitor electrode 2161 and the second capacitor electrode 2162 use the gate insulating layer 2129 as a dielectric material to form a storage capacitor.
  • the first storage capacitor electrode 2161 is arranged in the same layer as the gate 21211 in the pixel driving circuit 2120 and the lead 2220 in the bonding region 2200. Similarly, as described above, in the modification of the above example, the first capacitor electrode and the second capacitor electrode of the storage capacitor 2160 may also be located in other layers, so as to obtain sub-pixels with different structures.
  • the display substrate may further include an encapsulation layer 2150 provided on the light emitting element 2140.
  • the encapsulation layer 2150 seals the light emitting element 2140, so that the deterioration of the light emitting element 2140 caused by moisture and/or oxygen included in the environment can be reduced or prevented.
  • the encapsulation layer 2150 may have a single-layer structure or a composite layer structure.
  • the composite layer structure includes a stacked structure of an inorganic layer and an organic layer.
  • the encapsulation layer 2150 may include a first inorganic encapsulation layer 2151 that is sequentially arranged.
  • the encapsulation layer 2150 may extend to the bonding area. In the above example, the encapsulation layer does not cover the contact pads.
  • the display substrate further includes a third insulating layer 21120 in the display area of the display area.
  • the third insulating layer 21120 in the display area is disposed on the encapsulation layer 2150 to cover the encapsulation layer 2150.
  • the third insulating layer 21120 in the display area and the third insulating layer 2260 in the bonding area are provided in the same layer.
  • the display substrate may further include an auxiliary electrode layer 21130 located in the display area.
  • the auxiliary electrode layer 21130 is disposed on the third insulating layer 21120 in the display area, and the auxiliary electrode layer 21130 can be used for other auxiliary functions, such as a touch function.
  • the auxiliary electrode layer 21130 has an opening in the area of one sub-pixel.
  • the material of the third insulating layer 21120 in the display area may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or include silicon oxide, silicon nitride, etc. Inorganic insulating materials, the embodiments of the present disclosure do not limit this.
  • the auxiliary electrode layer used to implement the touch function can be used to implement a capacitive touch structure, and the capacitive touch structure is a self-capacitance type or a mutual-capacitance type.
  • the self-capacitive touch structure includes a plurality of self-capacitance electrodes arranged in an array (on the same layer), and each self-capacitance electrode is electrically connected to a touch processing circuit (touch chip) through a touch lead.
  • the position detection is achieved by detecting the change in capacitance of the self-capacitance electrode due to, for example, the approach of a finger during touch.
  • the mutual capacitance type touch structure includes a plurality of first touch signal lines extending in a first direction and a plurality of second touch signal lines extending in a second direction, the first touch signal line and the second touch signal line All are electrically connected to the touch processing circuit (touch chip) through the touch lead.
  • the first direction and the second direction cross each other and form an opening, thereby forming a touch capacitance at the crossing position of the first touch signal line and the second touch signal line, which is caused by, for example, the approach of a finger during touch.
  • the change of touch capacitance realizes position detection.
  • the embodiments of the present disclosure are described by taking a mutual capacitance type touch structure as an example.
  • the mutual capacitance type touch structure includes excitation electrodes and sensing electrodes intersecting each other and arranged in the same layer to realize the touch function of the display substrate.
  • the induction electrode includes multiple segments, and the excitation electrode is continuous.
  • a bridging electrode is provided on a different layer from the induction electrode and the excitation electrode to separate the two phases of the induction electrode.
  • the adjacent segments are electrically connected to each other.
  • the material forming the auxiliary electrode layer 21130 may include indium tin oxide (ITO), and a transparent electrode may be obtained therefrom, or the material forming the auxiliary electrode layer 21130 may include a metal mesh, or a transparent electrode may be obtained therefrom.
  • ITO indium tin oxide
  • the material forming the auxiliary electrode layer 21130 may include a metal mesh, or a transparent electrode may be obtained therefrom.
  • the structure of the display area of the display substrate shown in FIG. 7B is different from the structure of the display area of the display substrate shown in FIG. 4 in that the display substrate in FIG. 7B is provided on the packaging layer
  • the third insulating layer 21120 and the auxiliary electrode layer 21130 in the display area are not provided with a passivation layer. Based on this, the structure of the film layer of the display substrate in FIG. 7B and the material used in the film layer that are the same as those in FIG. 4 will not be described in detail.
  • FIG. 8A is a schematic cross-sectional view of the display substrate shown in FIG. 6 along M4-N4 according to another embodiment of the present disclosure.
  • the structure of the bonding region shown in FIG. 8A is compared with the structure of the bonding region shown in FIG. 7A, and a second insulating layer 2250 is added in the bonding region 2200 of the display substrate.
  • the second insulating layer 2250 is between the first contact pad metal 2215 and the second contact pad metal 2217.
  • the second insulating layer 2250 covers the edge of the first contact pad metal layer 2215 to prevent the edge of the first contact pad metal layer 2215 from being corroded by the etching solution in the subsequent patterning process.
  • the first insulating layer 2230 covers the edge of the second contact pad metal 2217 to prevent the edge of the second contact pad metal layer 2217 from being corroded by the etching solution in the subsequent patterning process.
  • the second insulating layer 2250 is located between the first insulating layer 2230 and the bonding interlayer insulating layer 2244.
  • the second insulating layer 2250 has a first contact pad via 2251, and the second contact pad metal layer 2217 is electrically connected to the first contact pad metal layer 2217 through the first contact pad via 2251.
  • the second contact pad metal 2217 compared to the edge of the first contact pad metal 2215, the second contact pad metal 2217 further extends outward on the second insulating layer 2250, covering the first contact pad metal 2215. That is, on the surface of the base substrate 2000, the orthographic projection of the second contact pad metal 2217 covers the orthographic projection of the first contact pad metal 2215.
  • Such a structure can reduce the step difference of the edge of the contact pad, and is beneficial for the first insulating layer 2230 to cover the edge of the second contact pad metal 2217.
  • FIG. 8B is a schematic cross-sectional view of the display area of the display substrate shown in FIG. 6 according to another embodiment of the present disclosure.
  • the structure of the display substrate shown in FIG. 8B has a passivation layer 21110 added to the sub-pixels (210) in the display area of the display substrate.
  • the passivation layer 21110 is located between the pixel driving circuit and the first planarization layer 2130 and includes a passivation layer via 21111.
  • the passivation layer can protect the source and drain of the pixel drive circuit from being corroded by water vapor.
  • the pixel driving circuit and the first transfer electrode 2180 may also be electrically connected through the passivation layer via 21111.
  • the second insulating layer 2250 and the passivation layer 21110 are provided in the same layer.
  • At least one embodiment of the present disclosure provides a display device, which may include the display substrate of any one of the above-mentioned embodiments.
  • the display device may further include a flexible circuit board and a control chip.
  • the flexible circuit board is bonded to the bonding area of the display substrate, and the control chip is mounted on the flexible circuit board to be electrically connected to the display area; or, the control chip is directly bonded to the bonding area, thereby connecting to the display area. Electric connection.
  • control chip may be a central processing unit, a digital signal processor, a system chip (SoC), and so on.
  • the control chip may also include a memory, and may also include a power supply module, etc., and the functions of power supply and signal input and output are realized through separately provided wires, signal lines, and the like.
  • the control chip may also include hardware circuits and computer executable codes.
  • Hardware circuits can include conventional very large-scale integration (VLSI) circuits or gate arrays, and existing semiconductors such as logic chips, transistors, or other discrete components; hardware circuits can also include field programmable gate arrays, programmable array logic, Programmable logic equipment, etc.
  • VLSI very large-scale integration
  • the display device provided by at least one embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • At least one embodiment of the present disclosure further provides a method for preparing a display substrate.
  • the method includes: providing a base substrate, wherein the base substrate includes a display area and a bonding area located on at least one side of the display area; Multiple sub-pixels; multiple data lines are formed in the display area, and multiple data lines are configured to provide data signals to multiple sub-pixels; multiple data leads are formed in the bonding area, and multiple data leads are connected to multiple data lines.
  • At least one set of contact pads in the bonding area at least one set of contact pads includes a plurality of contact pads, at least one of the plurality of contact pads is formed to include a first contact pad metal layer and a second contact pad metal layer,
  • the first contact pad metal layer is formed to be located on the side of the multiple data leads away from the base substrate and electrically connected to one of the multiple data leads
  • the second contact pad metal layer is formed to be located on the first contact pad metal layer away from the base substrate Is electrically connected to the first contact pad metal layer, the second contact pad metal layer covers the edge of the first contact pad metal layer;
  • a first insulating layer is formed in the bonding area, and the first insulating layer is located among the plurality of contact pads The gap between them covers the edges of the plurality of contact pads, and is configured to expose the surfaces of the plurality of contact pads facing away from the base substrate.
  • the first insulating layer located in the bonding area of the display substrate is configured to expose the surface of the contact pad facing away from the base substrate and cover the edge of the contact pad, so that the display substrate During the manufacturing process, the first insulating layer can protect the edge of the metal layer in the contact pad, avoiding the etching solution in the subsequent patterning process to etch the edge of the exposed contact pad, thereby improving the product yield and reliability of the display substrate Sex.
  • forming the first insulating layer includes making the height of the first insulating layer relative to the surface of the base substrate not greater than the height of the contact pad relative to the surface of the base substrate.
  • the first insulating layer in the bonding area can be formed in the same layer as the different insulating layers in the display area, thereby obtaining different laminated structures in the bonding area.
  • the manufacturing method further includes: forming a plurality of sub-pixels in the display area includes: forming a plurality of sub-pixels in the display area, wherein at least one of the plurality of sub-pixels includes a pixel driving circuit, Forming sub-pixels in the display area includes: forming a pixel drive circuit on a base substrate, and forming a first planarization layer on the side of the pixel drive circuit away from the base substrate to provide a first planarized surface; A first via hole is formed in the first planarization layer, and a first transfer electrode is formed on the first planarized surface, wherein the first transfer electrode is electrically connected to the pixel driving circuit through the first via hole, and is electrically connected to the pixel driving circuit through the first via hole.
  • a second planarization layer is formed on the side of the connection electrode away from the base substrate to provide a second planarization surface and a second via hole is formed in the second planarization layer, wherein the first insulating layer and the second planarization layer pass through the same
  • a second insulating material layer is formed; a light-emitting element is formed on the second planarized surface, wherein the light-emitting element is electrically connected to the first transfer electrode through the second via hole.
  • forming the first insulating layer and the second planarization layer through the same first insulating material layer includes: after forming the contact pads and the pixel driving circuit, depositing the first insulating layer on the base substrate. An insulating material layer; performing a patterning process on the first insulating material layer so that the portion of the first insulating material layer located in the display area is formed as a second planarization layer and the second via is formed in the second planarization layer, The portion of the first insulating material layer overlapping with the contact pad is removed, and the portion of the first insulating material layer located in the bonding area and located at the edge of the contact pad is thinned to form the first insulating layer.
  • performing a patterning process on the first insulating material layer includes: patterning the first insulating material layer using a gray tone mask or a halftone mask patterning process.
  • a base substrate 1000 is provided, the base substrate 1000 includes a display area and a peripheral area located at the periphery of the display area, and the peripheral area includes at least one bonding area located on at least one side of the display area.
  • the display area buffer layer 1121 is formed in the display area of the base substrate 1000 by deposition, and the bonding area buffer layer 1241 is formed in the bonding area at the same time.
  • the base substrate 1000 may include an organic material, for example, the organic material may be polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and
  • the base substrate 1000 may be a flexible substrate or a non-flexible substrate, which is not limited in the embodiments of the present disclosure.
  • the material of the display area buffer layer 1121 and the bonding area buffer layer 1241 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • an active layer is formed on the buffer layer 1121 in the display area.
  • a semiconductor material layer is deposited on the base substrate 1000, and then a patterning process is performed on the semiconductor material layer to form the active layer 1122.
  • the active layer 1121 includes a source region 1123 and a drain region 1124.
  • the semiconductor material of the active layer 1122 may include polysilicon or oxide semiconductor (for example, indium gallium zinc oxide) or the like.
  • the first gate insulating layer 1128 of the display area may be formed on the active layer 1212 by deposition or the like, and the first gate insulating layer 1128 of the bonding area may be formed on the bonding area buffer layer 1241 of the bonding area. Insulation layer 1242.
  • the material of the first gate insulating layer 1128 in the display area and the first gate insulating layer 1242 in the bonding area may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the gate 11211 and the first capacitor electrode 1161 can be formed on the first gate insulating layer 1128 in the display area through a patterning process, and A plurality of leads 1220 are formed on the base substrate 1000 in the bonding area.
  • a first metal material layer 1410 is deposited on the base substrate 1000, and then a patterning process is performed on the first metal material layer 1410 to form a gate 11211, a first capacitor electrode 1161, and a plurality of leads 1220.
  • the first metal material layer 1410 may include metal materials or alloy materials such as metal materials such as molybdenum, aluminum, and titanium or alloys thereof.
  • the multi-layer structure is a multi-metal laminate layer (such as a three-layer metal laminate of titanium, aluminum and titanium ( Ti/Al/Ti)).
  • the gate electrode can be used as a mask to form a conductive source region 1123 and a drain region 1124 by doping the active layer, and the source region 1123 and the drain region 1123 The channel region between the regions 1124 is undoped due to the blocking effect of the gate.
  • an insulating material can be deposited on the base substrate by deposition or the like to form a second display area on the gate 11211.
  • the gate insulating layer 1129 is formed, and a second gate insulating layer 1243 of the bonding region is formed on the plurality of leads 1220 through a patterning process in the bonding region.
  • the second gate insulating layer 1243 of the bonding area has a first contact pad via 1216.
  • the material of the second gate insulating layer in the bonding region may include, for example, insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the second capacitor electrode 1162 is formed on the second gate insulating layer 1129 in the display area, a metal material layer is deposited on the base substrate, and the second capacitor electrode 1162 is formed on the overlapped portion with the first capacitor electrode 1161 through a patterning process.
  • the first capacitance electrode 1161 and the second capacitance electrode 1162 are implemented as a storage capacitor 1160.
  • the display area interlayer insulating layer 11210 may be formed in the display area by deposition or the like, and the bonding area and the interlayer insulating layer 1244 may be formed in the bonding area.
  • the interlayer insulating layer 1244 in the bonding area has a second contact pad via 1219.
  • the material of the interlayer insulating layer 1244 in the bonding region may include, for example, insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the second metal material layer 1150 is formed on the base substrate by deposition or the like.
  • the second metal material layer 1150 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, and titanium.
  • the multi-layer structure is a multi-metal laminated layer (such as titanium, aluminum, and titanium). Three-layer metal stack (Ti/Al/Ti)).
  • the source electrode 1125 and the drain electrode 1126 are formed in the display area through a patterning process, and the first contact pad metal layer 1215 is formed in the bonding area.
  • the source electrode 1125 and the drain electrode 1126 are electrically connected to the source region 1123 and the drain region 1124 through the first gate insulating layer 1128 in the display area, the second gate insulating layer 1129 in the display area, and the interlayer insulating layer 11210 in the display area, respectively.
  • the first contact pad metal layer 1215 is electrically connected to the lead 1220 through the first contact pad via 1216 in the second gate insulating layer 1243 of the bonding region and the second contact pad via 1219 in the interlayer insulating layer of the bonding region. For example, as shown in FIG.
  • a first insulating material layer 1710 is deposited on the base substrate to cover the source electrode 1125 and the drain electrode 1126, and the interlayer insulating layer 11210 in the display area.
  • a photolithography process is performed on the first insulating material layer 1710 to form a first planarization layer 1130 in the display area to provide a planarized surface, and the first planarization layer 1130 has a first via 1131.
  • the first insulating material layer 1710 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or the like, or may include polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin. Organic insulating materials such as resins.
  • a pixel driving circuit 1120, a storage capacitor 1160, a first planarization layer 1130 in the display area, a lead 1220 in a bonding area, an interlayer insulating layer 1244 in a bonding area, and a first contact pad metal are formed on the display substrate.
  • a third metal material layer 1510 is deposited on the base substrate.
  • the third metal material layer 1510 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum, and titanium.
  • a patterning process is performed on the third metal material layer 1510 to form a first transfer electrode 1180 in the display area and a second contact pad metal layer 1217 in the bonding area.
  • the second contact pad metal layer 1217 covers the edge of the first contact pad metal layer 1215 to prevent the first contact pad metal layer 1215 from being corroded.
  • the first contact pad metal layer 1215 and the second contact pad metal layer 1217 are stacked to realize the contact pad 1210.
  • a first insulating material layer 1710 is deposited on the base substrate, and a photoresist 1720 is deposited on the first insulating material layer 1710.
  • the first insulating material layer 1710 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • a first mask 1610 is provided to expose the photoresist 1720, and the first mask 1610 includes a completely transparent area, a partially transparent area, and an opaque area.
  • the first mask 1610 includes a first light-transmitting pattern 1611 overlapping the gap between the contact pads 1210 and a second light-transmitting pattern 1612 overlapping the contact pad 1210 in the bonding area.
  • the first mask 1610 includes a second light-transmitting pattern 1612 and a non-light-transmitting pattern 1613 in the display area.
  • the first light-transmitting pattern 1611 is located in a partially light-transmitting area
  • the second light-transmitting pattern 1612 is located in a completely light-transmitting area
  • the non-light-transmitting pattern 1613 is located in an opaque area. That is, the first mask 1610 is a gray mask or a halftone mask.
  • the photoresist is a positive photoresist.
  • the light transmittance of the first light-transmitting pattern 1611 is lower than the light transmittance of the second light-transmitting pattern 1612.
  • the part of the photoresist 1720 corresponding to the second light-transmitting pattern 1612 may be completely exposed, and the part of the photoresist 1720 corresponding to the first light-transmitting pattern 1611 may be partially exposed.
  • the portion of the photoresist 1720 corresponding to the non-transmissive pattern 1613 in the display area is not exposed to light.
  • a negative photoresist can also be used, and the mask used is, for example, a mask complementary to the second mask 1610, so that the photoresist can be obtained after exposure and development.
  • the photoresist 1720 is developed, and the completely exposed part of the photoresist 1720 is removed, that is, in the bonding region, the photoresist 1720 overlapping with the contact pad 1210 is removed, and the photoresist 1720 is removed.
  • the partially exposed portion of the resist 1720 is thinned, and the thickness of the unexposed portion of the photoresist 1720 is, for example, substantially unchanged.
  • the photoresist 1720 is formed as a photoresist pattern 1721 in the bonding area.
  • the photoresist 1720 overlapping with the drain electrode 1126 is removed.
  • the photoresist 1720 is formed as a photoresist pattern 1722 in the display area.
  • the first insulating material layer 1710 in the bonding area and the display area is etched to remove the insulating material layer overlapping the contact pads in the bonding area, and a second via 1191 is formed in the display area. .
  • an ashing process is performed to remove the photoresist pattern 1721 in the bonding area and thin the photoresist pattern 1722 in the display area, where the photoresist pattern 1722 in the display area is retained.
  • the remaining first insulating material layer 1710 in the bonding area is etched and the etching thickness is controlled to form the first insulating layer 1230, and the first insulating layer formed after the etching is
  • the height of 1230 relative to the surface of the base substrate 1000 is not greater than the height of the second contact pad metal layer 1217 of the contact pad 1210 relative to the surface of the base substrate 1000.
  • the photoresist pattern 1722 in the display area is removed.
  • a second planarization layer 1190 is formed in the display area to provide a planarized surface.
  • the first electrode 1141 of the light emitting element 1140 is formed on the second planarization 1190 of the display area; the pixel defining layer 1144 is formed on the second planarization 1190 and the first electrode 1141, and the pixel defining layer 1144 is formed on the second planarization 1190 and the first electrode 1141.
  • a plurality of openings are included to define a plurality of pixel units. Each of the plurality of openings exposes the corresponding first electrode 1141.
  • the light emitting layer 1142 is formed in the plurality of openings of the pixel defining layer 1144 by, for example, an evaporation process, and then the second electrode 1143 is formed on the pixel defining layer 1144 and the light emitting layer 1142.
  • the second electrode 1143 may be formed on Part or the entire display area can be formed on the entire surface during the manufacturing process.
  • the first electrode 1141 of the light emitting element 1140 is electrically connected to the first transfer electrode 1180 through the second via 1191.
  • the material of the first electrode 1141 may include at least one transparent conductive oxide material, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and the like.
  • the first electrode 1141 may include a metal having high reflectivity as a reflective layer, such as silver (Ag).
  • the light-emitting layer 1142 may include small molecular organic materials or polymer molecular organic materials, which may be fluorescent light-emitting materials or phosphorescent light-emitting materials, which can emit red light, green light, blue light, or white light; and, as required
  • the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the light-emitting layer 1142 may include quantum dot materials, for example, silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, Lead selenide quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc.
  • the particle size of the quantum dots is 2-20nm.
  • the second electrode 1143 may include various conductive materials.
  • the second electrode 2143 may include metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).
  • the material of the pixel defining layer 1144 may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or inorganic materials such as silicon oxide and silicon nitride.
  • organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or inorganic materials such as silicon oxide and silicon nitride.
  • the insulating material is not limited in the embodiment of the present disclosure.
  • an encapsulation layer 1150 is formed on the light emitting element 1140 in the display area.
  • the encapsulation layer 1150 seals the light emitting element 1140, so that the deterioration of the light emitting element 1140 caused by moisture and/or oxygen included in the environment can be reduced or prevented.
  • the encapsulation layer 1150 may be a single layer structure or a composite layer structure.
  • the composite layer structure includes a stacked structure of an inorganic layer and an organic layer.
  • the encapsulation layer 1150 may include a first inorganic encapsulation layer 1151 and a first organic layer arranged in sequence.
  • the encapsulation layer 1150 may extend to the bonding area. In the above example, the encapsulation layer does not cover the contact pads.
  • the material of the encapsulation layer may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin.
  • insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin.
  • Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water and oxygen;
  • the material of the organic encapsulation layer can be a polymer material containing a desiccant or a polymer material that can block water vapor, etc.
  • polymer resins are used to flatten the surface of the display substrate, and can relieve the stress of the first inorganic encapsulation layer and the second inorganic encapsulation layer, and can also include water-absorbing materials such as desiccant to absorb water intruding into the interior, Oxygen and other substances.
  • the method for preparing the display substrate as shown in FIG. 5B may include FIGS. 9F to 9K, and the process shown in FIGS. 9F to 9K can be referred to the relevant description of the above example.
  • the first insulating material layer 1710 may be a photosensitive resin material, such as photoresist.
  • the photosensitive resin material is a positive photoresist.
  • exposure is performed using, for example, the above-mentioned first mask 1610.
  • the first mask 1610 includes completely transparent Area, part of the light-transmitting area and opaque area.
  • the first mask 1610 includes a first light-transmitting pattern 1611 overlapping the gap between the contact pads 1210 and a second light-transmitting pattern 1612 overlapping the contact pad 1210 in the bonding area.
  • the first mask 1610 includes a second light-transmitting pattern 1612 and a non-light-transmitting pattern 1613 that overlap with the drain electrode 1126 in the display area.
  • the first light-transmitting pattern 1611 is located in a partially light-transmitting area
  • the second light-transmitting pattern 1612 is located in a completely light-transmitting area
  • the non-light-transmitting pattern 1613 is located in an opaque area.
  • the part of the first insulating material layer 1710 corresponding to the second light-transmitting pattern 1612 is completely exposed, the part corresponding to the first light-transmitting pattern 1611 is partially exposed, and the non-light-transmitting pattern in the display area is partially exposed.
  • the part corresponding to 1613 has not been exposed.
  • the unexposed first insulating material layer 1710 in the display area forms a second planarization layer 1190.
  • a first insulating layer 1230 is formed for the partially exposed first insulating material layer 1710 in the bonding area, and the height of the formed first insulating layer 1230 relative to the surface of the base substrate 1000 is not greater than the second contact pad of the contact pad 1210 The height of the metal layer 1217 relative to the surface of the base substrate 1000.
  • the completely exposed first insulating material layer 1710 in the display area and the bonding area is removed, forming a second via 1191 in the display area and exposing the contact pads in the bonding area.
  • the above preparation method can also obtain the display substrate of the embodiment shown in FIG. 9K.
  • the photosensitive resin material may also be a negative photoresist
  • the mask used at this time is, for example, a mask complementary to the first mask 1160, so that the second mask is also formed in the display area after exposure and development.
  • the planarization layer exposes the contact pad in the bonding area and the first insulating layer covering the edge of the contact pad.
  • the first insulating layer located in the bonding area of the display substrate is configured to expose the surface of the contact pad facing away from the base substrate and cover the edge of the contact pad, so that during the preparation process of the display substrate
  • the first insulating layer can protect the edge of the metal layer in the contact pad, and prevent the etching solution used in the subsequent formation of the transition metal layer from etching the metal layer in the exposed contact pad, thereby further improving the display substrate Product yield and reliability.
  • a manufacturing method corresponding to the display substrate shown in FIG. 4 is provided.
  • the structure of the bonding region shown in FIG. 4 is compared with the structure of the bonding region shown in FIG. 5B, and a second insulating layer 1250 is added in the bonding region 1200 of the display substrate.
  • the second insulating layer 1250 is disposed between the first contact pad metal layer 1215 and the second contact pad metal layer 1217.
  • the second insulating layer 1250 covers the edge of the first contact pad metal layer 1215 to prevent the edge of the first contact pad metal layer 1215 from being corroded by the etching solution in the subsequent patterning process.
  • the second contact pad metal layer 1217 further extends outward on the second insulating layer 1250 to cover the edge of the first contact pad metal layer 1215, that is, On the surface of the base substrate 1000, the orthographic projection of the second contact pad metal layer 1217 covers the orthographic projection of the first contact pad metal layer 1215.
  • a passivation layer 11110 is added to the sub-pixels in the display area of the display substrate.
  • the passivation layer 11110 is located between the pixel driving circuit 1120 and the first planarization layer 1130 and includes a passivation layer via 11111.
  • the passivation layer can protect the source and drain of the pixel drive circuit from being corroded by water vapor.
  • the pixel driving circuit and the first transfer electrode 1180 are also electrically connected through the passivation layer via 11111.
  • the second insulating layer 1250 and the passivation layer 11110 are provided in the same layer.
  • a step of forming a passivation layer may be added between the steps of FIG. 9C and FIG. 9D.
  • a passivation layer film is formed to cover the source electrode 1125 and the drain electrode 1126 and the interlayer insulating layer 11210 in the display area, and then the passivation layer film is patterned to display The region forms a via hole exposing the drain electrode 1126 and a passivation layer via hole 11111 exposing the first contact pad metal layer 1215 during passivation.
  • the first insulating material layer 1710 is continuously deposited on the base substrate to cover the passivation layer.
  • the material of the passivation layer may include an organic insulating material or an inorganic insulating material, for example, silicon nitride material. Due to its high dielectric constant and good hydrophobic function, it can well protect the pixel drive circuit from being damaged. Corroded by water vapor.
  • a preparation method corresponding to the display substrate shown in FIG. 7A and FIG. 7B is provided.
  • the third insulating layer 21120 in the display area is disposed on the light-emitting element 2140 to cover the light-emitting element 2140, and a flattened surface is provided on the side of the light-emitting element 2140 away from the base substrate 2000.
  • an auxiliary conductive layer is formed in the third insulating layer 21120 in the display area, and the auxiliary conductive layer may include an auxiliary electrode layer 21130 in the display area.
  • the auxiliary electrode layer 21130 is disposed on the third insulating layer 21120 in the display area, and the auxiliary electrode layer 21130 can be used for other auxiliary functions, such as a touch function.
  • the material of the third insulating layer 21120 in the display area may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or include silicon oxide, silicon nitride, etc.
  • organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or include silicon oxide, silicon nitride, etc.
  • the auxiliary electrode used to implement the touch function can be used to implement a capacitive touch structure, and the capacitive touch structure is a self-capacitance type or a mutual-capacitance type.
  • the flow of the method for manufacturing the display device may include more or fewer operations, and these operations may be performed sequentially or in parallel.
  • the flow of the preparation method described above includes multiple operations appearing in a specific order, it should be clearly understood that the order of the multiple operations is not limited.
  • the preparation method described above can be executed once, or can be executed multiple times according to predetermined conditions.

Abstract

一种显示基板及其制备方法、显示装置。该显示基板包括衬底基板(1000)、多个子像素(110)、多条数据线(1101)、多条引线(1220)、至少一个接触垫(1210)及第一绝缘层(1230)。衬底基板(1000)，包括显示区(1100)和位于显示区(1100)至少一侧的邦定区(1200)；多条数据线(1101)配置为向多个子像素(110)提供数据信号；多条数据引线(1220)位于邦定区(1200)中且与多条数据线(1101)电连接；至少一组接触垫包括多个接触垫(1210)，多个接触垫(1210)中的至少一个包括第一接触垫金属层(1215)和第二接触垫金属层(1217)，第二接触垫金属层(1217)覆盖第一接触垫金属层(1215)的边缘；第一绝缘层(1230)，位于邦定区(1200)，第一绝缘层(1230)位于多个接触垫(1210)之间的间隙并覆盖多个接触垫(1210)的边缘，且被配置为露出多个接触垫(1210)的背离衬底基板的表面。

Description

显示基板及其制备方法、显示装置 技术领域
本公开的实施例涉及一种显示基板及其制备方法、显示装置。
背景技术
随着用户对有机发光二极管(Organic Light-Emitting Diode,OLED)的显示装置的需求越来越大、产品质量要求越来越高，推动了显示装置的快速发展。近年来，显示装置的分辨率越来越高，其边框越来越窄，从而使得显示装置的背板电路的像素尺寸逐渐减小。
发明内容
本公开至少一实施例提供一种显示基板，包括衬底基板、多个子像素、多条数据线、多条引线、至少一个接触垫及第一绝缘层。衬底基板，包括显示区和位于所述显示区至少一侧的邦定区；多个子像素，位于所述显示区中；多条数据线，位于所述显示区中，配置为向所述多个子像素提供数据信号；多条数据引线，位于所述邦定区中且与所述多条数据线电连接；至少一组接触垫，位于所述邦定区，所述至少一组接触垫包括多个接触垫，所述多个接触垫中的至少一个包括第一接触垫金属层和第二接触垫金属层，所述第一接触垫金属层位于所述多条数据引线远离所述衬底基板一侧且与所述多条数据引线中的一条电连接，所述第二接触垫金属层位于所述第一接触垫金属层远离所述衬底基板的一侧且与所述第一接触垫金属层电连接，所述第二接触垫金属层覆盖所述第一接触垫金属层的边缘；第一绝缘层，位于所述邦定区，所述第一绝缘层位于所述多个接触垫之间的间隙并覆盖所述多个接触垫的边缘，且被配置为露出所述多个接触垫的背离所述衬底基板的表面。
例如，本公开至少一实施例提供的显示基板中，所述第一绝缘层远离所述衬底基板一侧的表面距离所述衬底基板的垂直距离不大于所述多个接触垫远离所述衬底基板一侧的表面距离所述衬底基板的垂直距离。
例如，本公开至少一实施例提供的显示基板，所述第二接触垫金属层的边缘被所述第一绝缘层覆盖。
例如，本公开至少一实施例提供的显示基板中，所述至少一组接触垫包括第一组接触垫和第二组接触垫，所述第一组接触垫和所述第二组接触垫分别包括多个接触垫，所述第二组接触垫位于所述第一组接触垫靠近所述显示区的一侧，所述多条数据引线与所述第一组接触垫和所述第二组接触垫一一对应电连接。
例如，本公开至少一实施例提供的显示基板中，所述第一绝缘层的至少部分位于所述第一组接触垫相邻的接触垫之间的间隙中。
例如，本公开至少一实施例提供的显示基板，所述第一绝缘层的至少部分位于所述第二组接触垫中相邻的接触垫之间的间隙中。
例如，本公开至少一实施例提供的显示基板中，所述第一绝缘层的至少部分位于所述第一组接触垫中相邻的接触垫之间的间隙中和位于所述第二组接触垫中相邻的接触垫之间的间隙中。
例如，本公开至少一实施例提供的显示基板中，所述第一组接触垫的多个接触垫排布为至少第一行，所述第二组接触垫的多个接触垫排布为至少第二行；所述第一行和所述第二行的行方向与所述显示区的面向所述邦定区的侧边的延伸方向平行，所述第一绝缘层的至少部分位于所述第一行与所述第二行之间的间隙。
例如，本公开至少一实施例提供的显示基板中，所述多个子像素中至少一个包括像素驱动电路、第一平坦化层、第一转接电极、第二平坦化层以及发光元件，所述第一平坦化层在所述像素驱动电路远离所述衬底基板的一侧以提供第一平坦化表面且包括第一过孔，所述第一转接电极在所述第一平坦化表面上，且通过所述第一过孔与所述像素驱动电路电连接，所述第二平坦化层在所述第一转接电极远离所述衬底基板的一侧以提供第二平坦化表面且包括第二过孔，所述发光元件在所述第二平坦化表面上且通过所述第二过孔与所述第一转接电极电连接，其中，所述第一绝缘层与所述第二平坦化层同层设置。
例如，本公开至少一实施例提供的显示基板中，所述像素驱动电路包括第一显示区金属层，所述第一显示区金属层和所述第一接触垫金属层同层设置，所述第一转接电极与所述第二接触垫金属层同层设置。
例如，本公开至少一实施例提供的显示基板中，所述像素驱动电路包括薄膜晶体管，所述薄膜晶体管包括源极和漏极，所述源极和漏极位于所述第一显示区金属层中，且与所述第一显示区金属层位于同层。
例如，本公开至少一实施例提供的显示基板中，所述多个子像素中至少一个还包括钝化层，所述钝化层位于所述像素驱动电路和所述第一平坦化层之间且包括钝化层过孔，其中，所述像素驱动电路和所述第一转接电极还通过所述钝化层过孔电连接；所述显示基板还包括在所述邦定区中的第二绝缘层，其中，所述第二绝缘层在所述第一接触垫金属层与所述第二接触垫金属层之间且覆盖所述第一接触垫金属层的边缘，所述第二绝缘层具有第一接触垫过孔，所述第二接触垫金属层通过所述第一接触垫过孔与所述第一接触垫金属层电连接；其中，所述第二绝缘层和所述钝化层同层设置。
例如，本公开至少一实施例提供的显示基板中，所述多个子像素中至少一个还包括存储电容，所述存储电容包括两个电容电极，所述薄膜晶体管还包括栅极，所述多条数据引线中至少一条、所述存储电容的两个电容电极之一与所述栅极同层设置。
例如，本公开至少一实施例提供的显示基板，还包括：邦定区层间绝缘层，位于所述邦定区中，并且位于所述多个接触垫与所述引线之间和所述第一绝缘层与所述衬底基板之间；邦定区第一栅绝缘层，位于所述邦定区中，且位于所述邦定区层间绝缘层靠近所述衬底基板的一侧；以及邦定区第二栅绝缘层，位于所述邦定区中，且位于所述邦定区第一栅绝缘层及所述邦定区层间绝缘层之间，与所述邦定区层间绝缘层层叠；其中，所述邦定区第二栅绝缘层包括第一接触垫过孔，所述邦定区层间绝缘层包括第二接触垫过孔，所述多条数据引线中至少一条通过所述第一接触垫过孔及所述第二接触垫过孔与所述接触垫电连接。
例如，本公开至少一实施例提供的显示基板中，所述多个子像素中至少一个还包括显示区层间绝缘层、显示区第一栅绝缘层以及显示区第二栅绝缘层，所述显示区层间绝缘层、显示区第一栅绝缘层和所述显示区第二栅绝缘层分别与所述邦定区层间绝缘层、邦定区第一栅绝缘层和所述邦定区第二栅绝缘层同层设置；所述显示区层间绝缘层位于所述栅极与所述源极和所述漏极之间，所述显示区第一栅绝缘层位于所述显示 区层间绝缘层靠近所述衬底基板的一侧，所述显示区第二栅绝缘层位于所述显示区层间绝缘层与所述显示区第一栅绝缘层之间；所述两个电容电极包括第一电容电极和第二电容电极，所述第一电容电极与所述栅极同层设置，所述第二电容电极设置在所述显示区层间绝缘层与所述显示区第二栅绝缘层之间。
例如，本公开至少一实施例提供的显示基板，还包括邦定区第三绝缘层，其中，所述邦定区第三绝缘层位于所述邦定区中，并且设置在所述第一绝缘层和所述接触垫远离所述衬底基板的一侧以覆盖所述第一绝缘层及所述接触垫，所述邦定区第三绝缘层具有第三接触垫过孔以露出所述接触垫的表面。
例如，本公开至少一实施例提供的显示基板，还包括位于显示区的封装层及显示区第三绝缘层，所述封装层位于所述发光元件的远离所述衬底基板的一侧，所述显示区第三绝缘层位于所述封装层的远离所述衬底基板的一侧，其中，所述邦定区第三绝缘层与所述显示区第三绝缘层位于同层。
例如，本公开至少一实施例提供的显示基板，还包括辅助导电层，其中，所述辅助导电层位于所述邦定区中，且设置在所述邦定区第三绝缘层远离所述衬底基板的一侧，所述辅助导电层包括位于所述邦定区中的第二转接电极图案，其中，所述第二转接电极图案通过所述第三接触垫过孔与所述接触垫电连接。
例如，本公开至少一实施例提供的显示基板还包括辅助电极层，设置在所述显示区第三绝缘层上，其中，所述辅助电极层与所述第二转接电极图案同层设置。
例如，本公开至少一实施例提供的显示基板中，在所述邦定区中，所述第二转接电极图案相对于所述衬底基板的表面的高度不大于与所述邦定区第三绝缘层相对于所述衬底基板的表面的高度。
本公开至少一实施例提供一种显示装置，包括本公开任一实施例提供的显示基板。
本公开至少一实施例提供一种显示基板的制备方法，包括：提供衬底基板，其中，所述衬底基板包括显示区和位于所述显示区至少一侧的邦定区；在所述显示区中形成多个子像素；在所述显示区中形成多条数 据线，所述多条数据线被配置为向所述多个子像素提供数据信号；在所述邦定区中形成多条数据引线，所述多条数据引线与所述多条数据线电连接；在所述邦定区中形成至少一组接触垫，所述至少一组接触垫包括多个接触垫，所述多个接触垫中的至少一个形成为包括第一接触垫金属层和第二接触垫金属层，所述第一接触垫金属层形成为位于所述多条数据引线远离所述衬底基板一侧且与所述多条数据引线中的一条电连接，所述第二接触垫金属层形成为位于所述第一接触垫金属层远离所述衬底基板的一侧且与所述第一接触垫金属层电连接，所述第二接触垫金属层覆盖所述第一接触垫金属层的边缘；在所述邦定区形成第一绝缘层，所述第一绝缘层位于所述多个接触垫之间的间隙并覆盖所述多个接触垫的边缘，且被配置为露出所述多个接触垫的背离所述衬底基板的表面。
例如，在本公开至少一实施例提供的制备方法中，形成所述第一绝缘层包括：使得所述第一绝缘层相对于所述衬底基板的表面的高度不大于与所述接触垫的相对于所述衬底基板的表面的高度。
例如，在本公开至少一实施例提供的制备方法，在所述显示区中形成多个子像素包括：在所述显示区中形成多个子像素，其中，所述多个子像素中至少一个包括像素驱动电路、第一平坦化层以及发光元件，在所述显示区中形成所述子像素包括：在所述衬底基板上形成所述像素驱动电路，在所述像素驱动电路远离所述衬底基板的一侧形成所述第一平坦化层以提供第一平坦化表面且在所述第一平坦化层中形成第一过孔，在所述第一平坦化表面上形成所述第一转接电极，其中，所述第一转接电极通过所述第一过孔与所述像素驱动电路电连接，在所述第一转接电极远离所述衬底基板的一侧形成所述第二平坦化层以提供第二平坦化表面且在所述第二平坦化层中形成第二过孔，其中，所述第一绝缘层与所述第二平坦化层通过同一第二绝缘材料层形成；在所述第二平坦化表面上形成所述发光元件，其中，所述发光元件通过所述第二过孔与所述第一转接电极电连接。
例如，在本公开至少一实施例提供的制备方法中，所述第一绝缘层与所述第二平坦化层通过同一第一绝缘材料层形成包括：在形成所述接触垫和所述像素驱动电路之后，在所述衬底基板上沉积第一绝缘材料 层；对所述第一绝缘材料层进行构图工艺，以使得所述第一绝缘材料层的位于所述显示区的部分形成为所述第二平坦化层且在所述第二平坦化层中形成所述第二过孔，去除所述第一绝缘材料层的与所述接触垫重叠的部分，并且减薄所述第一绝缘材料层的位于所述邦定区且位于所述接触垫边缘的部分以形成所述第一绝缘层。
例如，在本公开至少一实施例提供的制备方法中，所述第一绝缘层与所述第二平坦化层通过同一第一绝缘材料层形成包括：在形成所述接触垫和所述像素驱动电路之后，在所述衬底基板上沉积第一绝缘材料层，其中所述第一绝缘材料层包括光敏树脂；使用灰色调掩模板或半色调掩模板对所述第一绝缘材料层进行曝光，对曝光之后的光刻胶进行显影后，以使得所述第一绝缘材料层的位于所述显示区的部分形成为所述第二平坦化层且在所述第二平坦化层中形成所述第二过孔，去除所述第一绝缘材料层的与所述接触垫重叠的部分，并且减薄所述第一绝缘材料层的位于所述邦定区且位于所述接触垫边缘的部分以形成所述第一绝缘层。
例如，在本公开至少一实施例提供的制备方法中，对所述第一绝缘材料层进行构图工艺包括：使用灰色调掩模板或半色调掩模板构图工艺对所述第一绝缘材料层进行构图。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为电极层采用的三层金属叠层(Ti/Al/Ti)的示意图；
图1B为三层金属叠层(Ti/Al/Ti)的边缘脱落的示意图；
图2A为本公开实施例提供的一种显示基板的平面示意图；
图2B为本公开一实施例提供的一种显示基板的邦定区的平面示意图；
图3A为图2B所示显示基板沿M1-N1的截面示意图；
图3B为图2B所示显示基板沿M2-N2的截面示意图；
图3C为图2B所示显示基板沿M3-N3的截面示意图；
图4为图2B所示显示基板的显示区的截面示意图；
图5A为本公开另一实施例提供的图2B所示显示基板沿M1-N1的截面示意图；
图5B为本公开另一实施例提供的图2B所示显示基板的显示区的截面示意图；
图6为本公开一实施例提供的再一种显示基板的邦定区的平面示意图；
图7A为本公开一实施例提供的图6所示显示基板沿M4-N4的截面示意图；
图7B为本公开一实施例提供的图6所示显示基板的显示区的截面示意图；
图8A为本公开另一实施例提供的图6所示显示基板沿M4-N4的截面示意图；
图8B为本公开另一实施例提供的图6所示显示基板的显示区的截面示意图；以及
图9A至图9M本公开一些实施例提供的一种显示基板的制备方法的过程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后， 则该相对位置关系也可能相应地改变。
目前，有机发光二极管(OLED)显示装置的分辨率越来越高，其边框越来越窄，从而使得显示装置的背板电路的像素尺寸逐渐减小。由于背板电路中的电路走线的宽度及电路走线的线间距减小，实际工艺生产中背板电路在刻蚀工艺中的金属残留、刻蚀损失容易造成背板电路短路，从而影响显示装置的良率。
发明人在研究中注意到，在显示装置的背板电路在制备工艺中，OLED的阳极采用湿式刻蚀工艺。在刻蚀工艺进行过程中，所使用的酸性刻蚀液对阳极下方的已经形成的其它金属层容易造成较严重的过刻现象。例如，显示装置包括位于OLED下方的转接电极金属层或源漏金属层，该转接电极金属层与阳极电连接，源漏金属层与转接电极层电连接。在形成阳极图案的构图工艺中，阳极的过刻现象容易对转接电极金属层或源漏金属层产生较大的影响。
如图1A所示，例如，当转接电极金属层或源漏金属层采用多金属层叠层(如钛、铝及钛三层金属叠层(Ti/Al/Ti))制备时，位于中间的铝金属层容易被酸性刻蚀液过刻从而出现底切(undercut)现象，进而造成电极图案边缘的位于铝金属层上的钛金属层出现悬空现象。如图1B所示，在显示装置后续的其它制备工艺中，例如高压喷淋制备工艺，容易出现悬空部分的钛金属的剥离现象。脱落的钛金属一般呈长条状，很容易残留在显示装置内，从而造成显示装置的背板电路中出现信号短路现象。
此外，显示装置在显示画面时，脱落的钛金属的残留容易导致显示装置的亮暗不良。特别是在显示装置的用于邦定外部电路的邦定区，亮暗不良问题尤为突出。
针对上述问题，本公开至少一实施例提供一种显示基板及其制备方法、显示装置。该显示基板包括衬底基板、多个子像素、多条数据线、多条引线、至少一个接触垫及第一绝缘层。衬底基板，包括显示区和位于显示区至少一侧的邦定区；多个子像素，位于显示区中；多条数据线，位于显示区中，配置为向多个子像素提供数据信号；多条数据引线，位于邦定区中且与多条数据线电连接；至少一组接触垫，位于邦定区，至少一组接触垫包括多个接触垫，多个接触垫中的至少一个包括第一接触垫金属层和第二接触垫金属层，第一接触垫金属层位于多条数据引线远离衬底基板一侧且与多条数据引线 中的一条电连接，第二接触垫金属层位于第一接触垫金属层远离衬底基板的一侧且与第一接触垫金属层电连接，第二接触垫金属层覆盖第一接触垫金属层的边缘第一绝缘层，位于邦定区，第一绝缘层位于多个接触垫之间的间隙并覆盖多个接触垫的边缘，且被配置为露出多个接触垫的背离衬底基板的表面。
上述显示基板中，位于显示基板的邦定区的第一绝缘层位于多个接触垫之间的间隙并覆盖多个接触垫的边缘，从而在显示基板的制备工艺过程中，第一绝缘层可以保护接触垫中的金属层的边缘，避免后续例如形成转接金属层等时使用的刻蚀液刻蚀裸露的接触垫中的金属层，防止悬空部分的钛金属的剥离现象，由此提高显示基板的产品良率和可靠性。
下面，结合附图对根据本公开实施例提供的显示基板及其制备方法、显示装置进行说明。
需要说明的是，在本公开的各个附图中，为了清楚描述，基于显示基板的衬底基板建立空间直角坐标系，并以此对显示基板中的各个结构的位置进行说明。在该空间直角坐标系中，X轴和Y轴平行于衬底基板所在平面，Z轴垂直于衬底基板所在平面。
本公开至少一实施例提供一种显示基板，图2A为本公开实施例提供的一种显示基板的平面示意图。图2B为本公开一实施例提供的一种显示基板的邦定区的平面示意图。显示基板例如用于有机发光二极管(OLED)显示装置或量子点发光二极管(QLED)显示装置。
例如，如图2A及图2B所示，显示基板100包括衬底基板1000，衬底基板1000包括显示区1100和围绕显示区1100的周边区，该周边区包括至少一个邦定区1200。图中示出了四个邦定区，但是本公开的实施例不限于此。显示区1100包括像素阵列以及为像素阵列提供控制信号、数据信号、电压信号等的扫描线(栅线)、数据线、电源线、检测线等。
在该实施例中，显示区1100包括多个子像素以及多条数据线1101，多条数据线1101包括沿第一方向(图中X轴方向)延伸的信号线1102(例如栅线G)和沿第二方向(图中Y轴方向)延伸的信号线1103(例如数据线D。显示基板包括位于邦定区1200中的多条引线1220(即，数据引线)。这些信号线延伸或走线到位于显示区1100至少一侧的邦定区，例如，信号线1103与对应的引线电连接，由此可以与邦定区的驱动芯片、柔性电路板等电连接。
例如，邦定区1200位于显示区1100的一侧，用于通过邦定工艺将外部电路与显示基板电连接。例如，外部电路可以包括安装芯片的柔性电路板(例如，Chip On Film,简称COF)，该柔性电路板上设置控制芯片或驱动芯片等。该邦定区也可以用于直接与芯片电连接。显示基板100还可以包括至少一组接触垫，至少一组接触垫包括多个接触垫1210，多个接触垫1210设置在邦定区1200上。多条引线1220与多个接触垫1210一一对应电连接。引线1220的一端部延伸至显示区1100与显示区1100中的信号线(例如数据线)电连接，引线1220的另一端部延伸至邦定区1200与接触垫1210电连接。引线1220例如与显示区1100中的信号线同层形成，由此可以一体形成，或者形成在不同层，由此需要通过二者之间的绝缘层中的过孔彼此电连接。
例如，如图2B所示，在每个邦定区1200中，至少一组接触垫包括多个接触垫1210。多个接触垫还可以被分为第一接触垫1210和第二组接触垫1210’。第二组接触垫1210’位于第一组接触垫1210靠近显示区1100的一侧，多条引线1220中至少一条与第一组接触垫1210和第二组接触垫1210’连接。多个接触垫1210在显示区1100面向邦定区1200的侧边的方向上排布，可以为单行或多行，例如，排布两行，即L1行(即，第一行)和L2行(即，第二行)，其中L2行位于L1行与显示区之间。如上所述，本公开实施例不以接触垫的行数为限。同一行中多个接触垫1210之间存在间隔，不同行的多个接触垫1210之间也存在间隔。如图所示，截线M1-N1穿过位于L1行的接触垫1211和接触垫1212，截线M2-N2穿过位于L2行的接触垫1213和接触垫1214，截线M3-N3穿过位于L1行的接触垫1212和位于L2行的接触垫1214。
例如，显示基板还包括第一绝缘层，第一绝缘层的至少部分位于第一组接触垫相邻的接触垫之间的间隙中。例如，第一绝缘层的至少部分位于第二组接触垫中相邻的接触垫之间的间隙中。又例如，第一绝缘层的至少部分位于第一组接触垫中相邻的接触垫之间的间隙中和位于第二组接触垫中相邻的接触垫之间的间隙中。
例如，在本公开的一些示例中，第一绝缘层相对于衬底基板的表面的高度不大于接触垫的相对于衬底基板的表面的高度。如图2B所示，显示基板还可以包括第一绝缘层1230，设置在邦定区1200上。第一绝缘层1230覆盖多个接触垫1210的至少部分边缘。接触垫1210包括至少一个接触垫金属层，例如多个接触垫金属层。接触垫1210的至少一个接触垫金属层的顶层金属层被露 出以用于实现电连接。
图3A为图2B所示显示基板沿M1-N1的截面示意图。图3B为图2B所示显示基板沿M2-N2的截面示意图。图3C为图2B所示显示基板沿M3-N3的截面示意图。如图3A、图3B及图3C所示，接触垫1210的至少一个接触垫金属层可以包括第一接触垫金属层1215及第二接触垫金属层1217，第二接触垫金属层1217层叠在第一接触垫金属层1215远离衬底基板1000一侧。该结构中，接触垫的顶层金属层为第二接触垫金属层1217。第一绝缘层1230包括对应于每个接触垫1210之间的间隙，由此被配置为露出接触垫1210的背离衬底基板1000的表面。邦定区1200中接触垫1210之外的区域被第一绝缘层1230所覆盖，该区域包括但不限于同一行接触垫之间的间隙以及不同行接触垫之间的间隙。从而，在显示基板的制备工艺过程中，第一绝缘层可以保护接触垫的边缘，避免后续构图工艺中的刻蚀液刻蚀裸露的接触垫的边缘，进而提高显示基板的产品良率和可靠性。
例如，衬底基板1000可以为玻璃板、石英板、金属板或树脂类板件等。例如，衬底基板的材料可以包括有机材料，例如该有机材料可以为聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料，衬底基板1000可以为柔性基板或非柔性基板，本公开的实施例对此不作限制。
若第一绝缘层的厚度较大，则第一绝缘层的相对于衬底基板的表面与接触垫的表面之间具有较大的段差，在邦定区对外部电路进行邦定工艺时，容易造成外部电路与邦定区的接触垫接触不良。尤其是对于柔性触控显示装置，由于其邦定区的接触垫的金属层叠层较厚，对外部电路进行邦定工艺时，在接触垫的顶层金属层上的凹槽处更容易造成外部电路与邦定区的接触垫接触不良，进一步影响显示装置的产品良率。因此，在该实施例的至少一个示例中，为了避免邦定区的接触不良现象，进一步对接触垫的厚度进行控制。
在本实施例中，接触垫的边缘包括接触垫沿周向的边缘，即，沿任一方向的截线穿过接触垫所得到的截面图中，接触垫的边缘都被第一绝缘层覆盖。
例如，如图3A、图3B及图3C所示，第一绝缘层1230覆盖第二接触垫金属层1217的边缘。第二接触垫金属层1217位于第一接触垫金属层1215上且覆盖第一接触金属层1215的边缘，以避免第一接触垫金属层1215被暴露而被后 续的构图工艺中的刻蚀液腐蚀，同时第二接触垫金属层1217能够形成台阶，增大第一绝缘层1230与第二接触垫金属层1217的接触面积，防止剥离。第一绝缘层1230相对于衬底基板1000的表面的高度H1，即第一绝缘层1230的表面至衬底基板1000的表面的垂直距离，不大于接触垫1210的第二接触垫金属层1217的表面至衬底基板1000的表面的距离H2。限定第一绝缘层1230的高度，即第一绝缘层1230的厚度，可以改善邦定区的接触不良现象，提高产品良率。此外，第二绝缘层1250设置在第一接触垫金属层1215与第二接触垫金属层1217之间。并且第二绝缘层1250覆盖第一接触垫金属层1215的边缘，以防止第一接触垫金属层2215的边缘被后续的构图工艺中的刻蚀液腐蚀。
在至少一个示例中，相比于第一接触垫金属层1215的边缘，第二接触垫金属层1217在第二绝缘层1250上进一步向外延伸，覆盖了第一接触垫金属层1215的边缘，也即，在衬底基板1000的表面上，第二接触垫金属层1217的正投影覆盖了第一接触垫金属层1215的正投影。这样的结构可以降低接触垫边缘的段差，有利于第一绝缘层1230覆盖第二接触垫金属层1217的边缘。
如图3A、图3B及图3C所示，第一绝缘层1230相对于衬底基板1000的表面的高度H1，即第一绝缘层1230的表面至衬底基板1000的表面的垂直距离，不大于接触垫1210的表面至衬底基板1000的表面的距离H2。需要说明的是，在如图所示的示例中，接触垫1210的表面为第二接触垫金属1217的距离衬底基板1000最远的表面。控制第一绝缘层1230的高度，即第一绝缘层1230的厚度，可以改善邦定区的接触不良现象，提高产品良率。
例如，继续如图3A、图3B及图3C所示，显示基板100的多条引线1220分别位于对应的接触垫1210下方。显示基板100还包括位于衬底基板1000上的邦定区缓冲层1241，及位于邦定区缓冲层1241远离衬底基板1000一侧的邦定区第一栅绝缘层1242。引线1220位于邦定区第一栅绝缘层1242上。引线1220的一端与接触垫1210电连接。例如，L1行的接触垫1211、接触垫1212及L2行的接触垫1213、接触垫1214分别与多条引线1220中的其中一条电连接，并且在该示例中，多条引线1220位于同一层中，因此，多条引线1220可以在同一构图工艺中制备。
例如，在其他示例中，多条引线1220也可以位于不同层中，例如用于L1行的接触垫1210的引线位于更靠近衬底基板的一层，而用于L2行的接触垫1210的引线位于相对更远离衬底基板的一层(但仍然在接触垫和衬底基板之 间)。因此，同一层中的多条引线1220之间的间距得以加大，降低了引线的之间干扰以及短路的风险，有利于形成高像素分辨率的显示装置。而且，同一层中的多条引线1220可以在同一构图工艺中制备。例如，显示基板100还可以包括位于邦定区的邦定区第二栅绝缘层1243以及邦定区层间绝缘层1244，邦定区层间绝缘层1244位于至少一条引线1220远离衬底基板1000的一侧。接触垫1210设置在邦定区层间绝缘层1244上。邦定区层间绝缘层1244位于邦定区中，并且位于多个接触垫1210和第一绝缘层1230与所述衬底基板1000之间。邦定区第二栅绝缘层1243位于邦定区第一栅绝缘层1242及邦定区层间绝缘层1244之间，与邦定区层间绝缘层1244层叠。邦定区第二栅绝缘层1243包括第一接触垫过孔1216，邦定区层间绝缘层1244包括第二接触垫过孔1219，多条引线1220中至少一条通过所述第一接触垫过孔1216及所述第二接触垫过孔1219与所述接触垫电连接。连接L1行的接触垫1210的引线1220在邦定区延伸经过L2行的接触垫的间隙，然后再延伸到显示区1100，从而使得接触垫1210具有更大的排列空间并且可以避免与连接L2行的接触垫1210’的引线1220相互干扰或短路。
如图3C所示，邦定区第二栅绝缘层1243包括多个第一接触垫过孔1216，邦定区层间绝缘层1244包括多个第二接触垫过孔1219，图3C中示出沿截线M3-N3接触垫1212及接触垫1214中包括3个第一接触垫过孔1216以及3个第二接触垫过孔1219。在本公开的其它示例中，第一接触垫过孔1216及第二接触垫过孔1219的数量也可以为多个，例如，2个或4个，本公开不以第一接触垫过孔1216及第二接触垫过孔1219的数量为限。
在其他示例中，多条引线1220也可以位于不同层中，例如用于L1行的接触垫1210的引线位于更靠近衬底基板的一层，而用于L2行的接触垫1210的引线位于相对更远离衬底基板的一层(但仍然在接触垫和衬底基板之间)。因此，同一层中的多条引线1220之间的间距得以加大，降低了引线的之间干扰以及短路的风险，有利于形成高像素分辨率的显示装置。而且，同一层中的多条引线1220可以在同一构图工艺中制备；不同层中的多条引线1220可以在不同构图工艺中制备。
例如，第一绝缘层1230的材料可以包括氧化硅、氮化硅、氮氧化硅等无机绝缘材料，或者可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料。本公开的实施例对第一绝缘层的材料 不做具体限定。引线的材料可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构。第一接触垫金属层的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构。
例如，在本公开的一些示例中，显示基板的显示区的像素阵列中每个像素单元的子像素包括像素驱动电路、第一平坦化层、第一转接电极、第二平坦化层以及发光元件。第一平坦化层在像素驱动电路远离衬底基板的一侧以提供第一平坦化表面且包括第一过孔，第一转接电极在第一平坦化表面上，且通过第一过孔与像素驱动电路电连接，第二平坦化层在第一转接电极远离衬底基板的一侧以提供第二平坦化表面且包括第二过孔，发光元件在第二平坦化表面上且通过第二过孔与第一转接电极电连接，所第一绝缘层与第二平坦化层同层设置。
例如，像素驱动电路可以包括薄膜晶体管、存储电容等，可以实现为各种不同类型，例如为2T1C型(即包括两个薄膜晶体管和一个存储电容)，还可以在2T1C型的基础上进一步包括更多的晶体管和/或电容以具有补偿、复位、发光控制、检测等功能，本公开的实施例对于像素驱动电路不作限制。例如，在一些实施例中，与发光元件直接电连接的薄膜晶体管可以为驱动晶体管或发光控制晶体管等。
在本公开的实施例中，“同层设置”为两个功能层(例如第一绝缘层与第二平坦化层)在显示基板的层级结构中同层且同材料形成，即在制备工艺中，该两个结构层可以由同一个材料层形成，且可以通过同一构图工艺形成所需要的图案和结构，例如可以在先形成该材料层后，由该材料层经过构图工艺形成。
例如，在本公开的一些示例中，图4为本公开一实施例提供的图2B所示显示基板的显示区的截面示意图。显示基板的显示区的像素阵列中每个像素单元的子像素110用于实现发光驱动、控制。该子像素110包括像素驱动电路1120、第一平坦化层1130、第一转接电极1180、第二平坦化层1190及发光元件1140。
例如，该子像素还包括位于衬底基板1000上的缓冲层1121，像素驱动电路1120包括位于显示区缓冲层1121上的有源层1122、位于有源层1122远离衬底基板1000一侧的显示区第一栅绝缘层1128、位于显示区第一栅绝缘层1128上的栅极11211，位于栅极11211远离衬底基板1000一侧的显示区第二栅绝缘 层1129，位于显示区第二栅绝缘层1129上的显示区层间绝缘层11210以及位于显示区层间绝缘层11210上的源极1125及漏极1126。栅极11211可以与邦定区1200中的引线1220同层设置。因此，栅极11211和引线1220可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成。显示区中的显示区缓冲层1121与邦定区中的邦定区缓冲层1241同层设置，显示区缓冲层1121与邦定区缓冲层1241可以在制备工艺中同层形成。显示区中的显示区第一栅绝缘层1128与邦定区中的邦定区第一栅绝缘层1242同层设置，显示区中的显示区第二栅绝缘层1129与邦定区中的邦定区第二栅绝缘层1243同层设置，显示区中的显示区层间绝缘层11211与邦定区层间绝缘层1244同层设置。显示区缓冲层1121作为过渡层，其即可以防止衬底基板中的有害物质侵入显示基板的内部，又可以增加显示基板中的膜层在衬底基板1000上的附着力。
例如，显示区缓冲层1121的材料可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料。显示区层间绝缘层11210、显示区第二栅绝缘层1129及显示区第一栅绝缘层1128中的一种或多种的材料可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料。显示区层间绝缘层11210、显示区第二栅绝缘层1129及显示区第一栅绝缘层1128的材料可以相同也可以不相同。
例如，在本公开上述实施例一些示例中，如图6B所示，有源层1122可以包括源极区1123和漏极区1124，以及包括位于源极区1123和漏极区1124之间的沟道区。显示区层间绝缘层11210、显示区第二栅绝缘层1129及显示区第一栅绝缘层1128具有过孔，以暴露源极区1123和漏极区1124。源极1125及漏极1126分别通过过孔与源极区1123和漏极区1124电连接。栅极11211在垂直于衬底基板1000的方向上与有源层1122中位于源极区1123和漏极区1124之间的沟道区重叠。第一平坦化层1130位于源极1125及漏极1126的上方，用于平坦化像素驱动电路远离衬底基板一侧的表面。第一平坦化层1130中形成第一过孔1131，以暴露源极1125或漏极1126(图中示出的情况)。在像素驱动电路1120和第一平坦化层1130之间形成钝化层11110且钝化层11110包括钝化层过孔11111。钝化层可以保护像素驱动电路的源极和漏极不被水汽腐蚀。第一平坦化层1130上形成第一转接电极1180。第一转接电极1180通过第一过孔1131以及钝化层过孔11111与漏极1126电连接，该第一转接电极可以避免直接在第一平坦化层和第二平坦化层中形成孔径比较大的直通过孔，从而改善过孔电连接的质量，同时第一转接电极还可以与其他信号线(例如电源线等) 等同层形成，由此不会导致工艺步骤增加。第一转接电极1180与接触垫1210的第二接触垫金属层1217同层设置，因此，第一转接电极1180与第二接触垫金属层1217可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成，从而简化制备工艺。
例如，第一转接电极1180的材料可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构。
例如，有源层1122的材料可以包括多晶硅或氧化物半导体(例如，氧化铟镓锌)。栅极11211的材料可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Ti/Al/Ti)。源极1125及漏极1126的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Ti/Al/Ti)。本公开的实施例对各功能层的材料不做具体限定。
例如，钝化层的材料可以包括有机绝缘材料或无机绝缘材料，例如，氮化硅材料，由于其具有较高的介电常数且具有很好的疏水功能，能够很好的保护像素驱动电路不被水汽腐蚀。
例如，在本公开的一些示例中，如图4所示，像素驱动电路1120还可以包括第一显示金属层1127，第一显示区金属层1127与第一接触垫金属层1215同层设置。第一显示金属层1127包括像素驱动电路中上述薄膜晶体管的源极1125和漏极1126。源极1125和漏极1126与第一接触垫金属层1215同层设置。因此，源极1125和漏极1126与第一接触垫金属层1215可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成，从而简化制备工艺，减少产品的制备成本。
例如，在本公开的一些示例中，如图4所示，第二平坦化层1190设置在第一转接电极1180远离衬底基板1000的一侧，用以在第一转接电极1180远离衬底基板1000一侧提供平坦化表面。并且，在第二平坦化层1190中形成第二过孔1191。第二平坦化层1190与邦定区1200中的第一绝缘层1230同层形成，因此第二平坦化层1190与第一绝缘层1230可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成，从而简化制备工艺。
例如，在第二平坦化层上形成发光元件1140，即发光元件1140设置在第二平坦化层1190远离衬底基板一侧。发光元件1140包括第一电极1141、发光 层1142及第二电极1143。发光元件的第一电极1141通过第二平坦化层1140中的第二过孔1191与第一转接电极1180电连接。第一电极1141上形成像素限定层1144，像素限定层1144包括多个开口，以限定多个像素单元。多个开口的每个暴露对应的第一电极1141；之后，发光层1142设置在像素限定层1144的多个开口中，第二电极1143设置在像素限定层1144以及发光层1142上，例如该第二电极1143可以设置在部分或整个显示区域中，从而在制备工艺中可以整面形成。
例如，第二平坦化层1190的材料可以包括括氧化硅、氮化硅、氮氧化硅等无机绝缘材料，也可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料，本公开的实施例对此不做限定。
例如，第一电极1141可以包括反射层，第二电极1143可以包括透明层或半透明层。由此，第一电极1141可以反射从发光层1142发射的光，该部分光通过第二电极1143发射到外界环境中，从而可以提供光出射率。当第二电极1143包括半透射层时，由第一电极1141反射的一些光通过第二电极1143再次反射，因此第一电极1141和第二电极1143形成共振结构，从而可以改善光出射效率。
例如，第一电极1141的材料可以包括至少一种透明导电氧化物材料，包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)等。此外，第一电极1141可以包括具有高反射率的金属作为反射层，诸如银(Ag)。
例如，对于OLED，发光层1142可以包括小分子有机材料或聚合物分子有机材料，可以为荧光发光材料或磷光发光材料，可以发红光、绿光、蓝光，或可以发白光；并且，根据需要发光层还可以进一步包括电子注入层、电子传输层、空穴注入层、空穴传输层等功能层。对于QLED，发光层可以包括量子点材料，例如，硅量子点、锗量子点、硫化镉量子点、硒化镉量子点、碲化镉量子点、硒化锌量子点、硫化铅量子点、硒化铅量子点、磷化铟量子点和砷化铟量子点等，量子点的粒径为2-20nm。
例如，第二电极1143可以包括各种导电材料。例如，第二电极1143可以包括锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料。
例如，像素限定层1144的材料可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料，或者包括氧化硅、氮化硅等无机绝缘材料，本公开的实施例对此不做限定。
此外，显示基板还包括存储电容器1160，存储电容器1160可以包括第一电容电极1161和第二电容电极1162。第一电容电极1161设置在显示区第一栅绝缘层1128与显示区第二栅绝缘层1129之间，第二电容电极1162设置在显示区第二栅绝缘层1129与显示区层间绝缘层11210之间。第一电容电极1161和第二电容电极1162叠置，在垂直于衬底基板1000的方向上至少部分重叠。第一电容电极1161和第二电容电极1162使用显示区第二栅绝缘层1129作为介电材料来形成存储电容器。第一存储电容电极1161与像素驱动电路1120中的栅极11211、邦定区1200中的引线1220同层设置。同样地，如上所述，在上述示例的变型中，存储电容器1160的第一电容电极和第二电容电极还可以位于其他层中，从而得到不同结构的子像素。
在另一示例中，作为图4所示示例的变型，存储电容器的第一电容电极仍然与栅极11211同层设置，而存储电容器的第二电容电极与薄膜晶体管中的源极1125和漏极1126同层设置(即也位于第一显示金属层1127中)，由此第一电容电极和第二电容电极使用显示区第二栅绝缘层1129以及显示区层间绝缘层11210的叠层来作为介电材料来形成存储电容器。
在再一示例中，作为图4所示示例的变型，存储电容器的第一电容电极不再与栅极11211同层设置，而是位于在显示区第二栅绝缘层1129与显示区层间绝缘层11210之间，而存储电容器的第二电容电极与薄膜晶体管中的源极1125和漏极1126同层设置(即也位于第一显示金属层1127中)，由此第一电容电极和第二电容电极使用显示区层间绝缘层11210来作为介电材料来形成存储电容器。
例如，在本公开的一些示例中，如图4所示，显示基板还可以包括设置在发光元件1140上的封装层1150。封装层1150将发光元件1140密封，从而可以减少或防止由环境中包括的湿气和/或氧引起的发光元件1140的劣化。封装层1150可以为单层结构，也可以为复合层结构，该复合层结构包括无机层和有机层堆叠的结构，例如，封装层1150可以包括依次设置的第一无机封装层1151、第一有机封装层1152、第二无机封装层1153。封装层1150可以延伸至邦定区，在上述示例中，该封装层未覆盖接触垫。
例如，该封装层的材料可以包括氮化硅、氧化硅、氮氧化硅、高分子树脂等绝缘材料。氮化硅、氧化硅、氮氧化硅等无机材料的致密性高，可以防止水、氧等的侵入；有机封装层的材料可以为含有干燥剂的高分子材料或可 阻挡水汽的高分子材料等，例如高分子树脂等以对显示基板的表面进行平坦化处理，并且可以缓解第一无机封装层和第二无机封装层的应力，还可以包括干燥剂等吸水性材料以吸收侵入内部的水、氧等物质。
例如，在本公开的一些示例中，图5A为本公开另一实施例提供的图2B所示显示基板沿M1-N1的截面示意图。
图5A中示出的邦定区的结构与图3A中出的邦定区的结构相比，在显示基板的邦定区1200中去除第二绝缘层1250。第二接触垫金属层1217直接覆盖第一接触金属层1215的边缘，可以减少接触垫1210的膜层的厚度，进而减少膜层的段差，从而进一步改善邦定区的接触不良现象。
例如，在本公开的一些示例中，图5B为本公开另一实施例提供的图2B所示显示基板的显示区的截面示意图。
图5B中示出的显示基板的结构与图4中示出的显示基板的结构相比，在显示基板的显示区的子像素(110)中去除钝化层11110。
例如，本公开的一些示例中，显示基板还包括邦定区第三绝缘层，该邦定区第三绝缘层位于邦定区中，并且设置在第一绝缘层和接触垫远离衬底基板的一侧以覆盖第一绝缘层及接触垫，邦定区第三绝缘层具有第三接触垫过孔以露出接触垫的表面。
例如，在本公开的一些示例中，显示基板还包括辅助导电层。该辅助导电层位于邦定区中，且设置在邦定区第三绝缘层远离衬底基板的一侧，辅助导电层包括位于邦定区中的第二转接电极图案，其中，第二转接电极图案通过第三接触垫过孔与接触垫电连接。
例如，图6为本公开一实施例提供的再一种显示基板的邦定区的平面示意图。图7A为本公开一实施例提供的图6所示显示基板沿M4-N4的截面示意图。
例如，该显示基板包括衬底基板2000，衬底基板2000包括显示区和围绕显示区的周边区，该周边区包括至少一个邦定区。同样地，显示区包括像素阵列以及为像素阵列提供控制信号、数据信号、电压信号等的扫描线(栅线)、数据线、电源线、检测线等。
如图6所示及图7A所示，显示基板还可以包括多条引线2220及至少一组接触垫。至少一组接触垫包括多个接触垫2210。多个接触垫还可以被分第一接触垫2210和第二组接触垫2210’。第二组接触垫2210’位于第一组接触垫 2210靠近显示区1100的一侧。显示基板还包括位于衬底基板2000上的邦定区缓冲层2241，及位于邦定区缓冲层2241远离衬底基板2000一侧的邦定区第一栅绝缘层2242。引线2220位于邦定区第一栅绝缘层2242上。多条引线2220与多个接触垫2210一一对应电连接。引线2220的一端部延伸至显示区与显示区上的信号线(例如数据线)电连接，引线2210的另一端部延伸至邦定区2200与接触垫2210电连接。多个接触垫2210排布为单行或多行，例如，在图中所示的示例中，接触垫排布为，例如，两行，即L3行(第一行)和L4行(第二行)，L4行位于L3行和显示区之间。同一行中的多个接触垫2210之间存在间隔，不同行的多个接触垫2210之间也存在间隔，截线M4-N4穿过位于L3行的接触垫2211和接触垫2212。
同样地，在其他示例中，多条引线2220也可以位于不同层中，例如用于L3行的接触垫2210的引线位于更靠近衬底基板的一层，而用于L4行的接触垫2210的引线位于相对更远离衬底基板的一层(但仍然在接触垫和衬底基板之间)。因此，同一层中的多条引线2220之间的间距得以加大，降低了引线的之间干扰以及短路的风险，有利于形成高像素分辨率的显示装置。而且，同一层中的多条引线2220可以在同一构图工艺中制备。
该显示基板还可以包括第一绝缘层2230及邦定区第三绝缘层2260，设置在邦定区2200上。第一绝缘层2230覆盖多个接触垫2210的至少部分边缘。接触垫2210包括至少一个接触垫金属层，例如多个接触垫金属层。在图示的示例中，接触垫2210的至少一个接触垫金属层可以包括第一接触垫金属层2215及第二接触垫金属层2217，第二接触垫金属层2217层叠在第一接触垫金属层2215远离衬底基板2000一侧。邦定区第三绝缘层2260覆盖第一绝缘层2230及多个接触垫2210。从而在显示基板的制备工艺过程中，第一绝缘层可以保护接触垫的边缘，避免刻蚀液刻蚀裸露的接触垫的边缘，进而提高显示基板的产品良率和可靠性。
例如，如图7A所示，该显示基板还可以包括位于邦定区的邦定区第二栅绝缘层2243以及邦定区层间绝缘层2244。邦定区层间绝缘层2240位于邦定区中，并且位于多个接触垫2210和第一绝缘层2230与所述衬底基板2000之间。邦定区第二栅绝缘层2243位于邦定区第一栅绝缘层2242及邦定区层间绝缘层2244之间，与邦定区层间绝缘层2244层叠。邦定区第二栅绝缘层2243包括第一接触垫过孔2216，邦定区层间绝缘层2244包括第二接触垫过孔2219，多 条引线2220中至少一条通过所述第一接触垫过孔2216及所述第二接触垫过孔2219与所述接触垫电连接。连接L3行的接触垫2210的引线2220在邦定区延伸经过L4行的接触垫的间隙，然后再延伸到显示区，从而使得接触垫2210具有更大的排列空间并且可以避免与连接L3行的接触垫2210的引线2220相互干扰或短路。
例如，如图7A所示，第二接触垫金属层2217形成在第一接触垫金属层2215上且覆盖第一接触垫金属层2215的边缘，以避免第一接触垫金属层2215被暴露而被后续的构图工艺中的刻蚀液腐蚀。第一绝缘层2230覆盖接触垫2210的第二接触垫金属层2217的至少部分边缘。第一绝缘层2230相对于衬底基板2000的表面的高度，即第一绝缘层2230的表面至衬底基板2000的表面的垂直距离，不大于接触垫2210的第二接触垫金属层2217的表面至衬底基板2000的表面的距离。限定第一绝缘层2230的高度，即第一绝缘层2230的厚度，可以改善邦定区的接触不良现象，提高产品良率。此外，第二接触垫金属层2217直接覆盖第一接触金属层2215的边缘，可以减少接触垫2210的膜层的厚度，进而减少膜层的段差，从而进一步改善邦定区的接触不良现象。
例如，如图7A所示，显示基板还可以包括辅助导电层。该辅助导电层位于邦定区及显示区中且设置在邦定区第三绝缘层2260上。该辅助导电层包括位于邦定区中的第二转接电极图案2270。第二转接电极图案2270实现为与外部电路进行邦定工艺。邦定区第三绝缘层2260中形成第三接触垫过孔2218。第二转接电极图案2270通过第三接触垫过孔2218与接触垫电连接，以传递电信号。第一绝缘层2230被配置为露出接触垫2210的背离衬底基板2000的表面。即，邦定区2200中接触垫2210之外的区域被第一绝缘层2230所覆盖，该区域包括但不限于同一行接触垫之间的间隙以及不同行接触垫之间的间隙。
例如，在本公开的一些示例中，第二转接电极图案2270相对于衬底基板2000的表面的高度不大于邦定区第三绝缘层2260相对于衬底基板2000的表面的高度，以避免邦定区的接触不良现象。
例如，在本公开的一些示例中，图7B为本公开一实施例提供的图6所示显示基板的显示区的截面示意图。如图7B所示，显示基板的显示区的像素阵列中每个像素单元的子像素210可以包括像素驱动电路2120、第一平坦化层2130、第一转接电极2180、第二平坦化层2190及发光元件2140。
该子像素还包括位于衬底基板2000上的缓冲层2121，像素驱动电路2120 包括位于显示区缓冲层2121上的有源层2122、位于有源层2122远离衬底基板2000一侧的显示区第一栅绝缘层2128、位于显示区第一栅绝缘层2128上的栅极21211，位于栅极21211远离衬底基板2000一侧的显示区第二栅绝缘层2129，位于显示区第二栅绝缘层2129上的显示区层间绝缘层21210以及位于显示区层间绝缘层21210上的源极2125及漏极2126。栅极21211可以与邦定区2200中的引线2220同层设置。显示区中的显示区缓冲层2121与邦定区中的邦定区缓冲层2241同层设置，显示区缓冲层2121与邦定区缓冲层2241可以在制备工艺中同层形成。显示区中的显示区第一栅绝缘层2128与邦定区中的邦定区第一栅绝缘层2242同层设置，显示区中显示区第二栅绝缘层2129与邦定区第二栅绝缘层2243同层设置，显示区中显示区层间绝缘层21210与邦定区层间绝缘层2244同层设置。显示区缓冲层2121作为过渡层，其即可以防止衬底基板中的有害物质侵入显示基板的内部，又可以增加显示基板中的膜层在衬底基板2000上的附着力。
例如，在本公开的一些示例中，如图7B所示，有源层2122包括源极区2123和漏极区2124，以及位于源极区2123和漏极区2124之间的沟道区。显示区层间绝缘层21210、显示区第二栅绝缘层2129及显示区第一栅绝缘层2128具有过孔，以暴露源极区2123和漏极区2124。源极2125及漏极2126分别通过过孔与源极区2123和漏极区2124电连接。栅极21211在垂直于衬底基板2000的方向上与有源层2122中位于源极区2123和漏极区2124之间的沟道区重叠。第一平坦化层2130位于源极2125及漏极2126的上方，并且在第一平坦化层2130中形成第一过孔2131，以暴露源极2125或漏极2126(图中示出的情况)，第一平坦化层2130上形成第一转接电极2180。第一转接电极2180通过第一过孔2131与漏极2126电连接。该第一转接电极可以避免直接在第一平坦化层和第二平坦化层中形成孔径比较大的直通过孔，从而改善过孔电连接的质量，同时第一转接电极还可以与其他信号线(例如电源线等)等同层形成，由此不会导致工艺步骤增加。第一转接电极2180与第二接触垫金属层2217同层设置。
例如，在本公开的一些示例中，如图7B所示，像素驱动电路2120还可以包括第一显示金属层2127，第一显示区金属层2127与第一接触垫金属层2215同层设置。第一显示金属层2127包括像素驱动电路中上述薄膜晶体管的源极2125和漏极2126。源极2125和漏极2126与第一接触垫金属层2215同层设置。 因此，源极2125和漏极2126与第一接触垫金属层2215可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成，从而简化制备工艺，减少产品的制备成本。
例如，在本公开的一些实施例中，如图7B所示，第二平坦化层2190设置在第一转接电极2180远离衬底基板2000的一侧，用在第一转接电极2180远离衬底基板2000一侧以提供平坦化表面。并且，在第二平坦化层2190中形成第二过孔2191。第二平坦化层2190与邦定区2200中的第一绝缘层2230同层形成。在第二平坦化层2190上形成发光元件2140，即发光元件2140设置在第二平坦化层2190远离衬底基板一侧。发光元件2140包括第一电极2141、发光层2142及第二电极2143。第一电极2141上形成像素限定层2144，像素限定层2144包括多个开口，以限定多个像素单元。多个开口的每个暴露第一电极2141，发光层2142设置在像素限定层2144的多个开口中。第二电极2143例如可以设置在部分或整个显示区域中，从而在制备工艺中可以整面形成。发光元件的第一电极2141通过第二平坦化层2140中的第二过孔2191与第一转接电极2180电连接。
例如，显示基板还包括存储电容器2160，存储电容器2160可以包括第一电容电极2161和第二电容电极2162。第一电容电极2161设置在显示区第一栅绝缘层2128与显示区第二栅绝缘层2129之间，第二电容电极2162设置在显示区第二栅绝缘层2129与显示区层间绝缘层21210之间。第一电容电极2161和第二电容电极2162叠置，在垂直于衬底基板2000的方向上至少部分重叠。第一电容电极2161和第二电容电极2162使用栅绝缘层2129作为介电材料来形成存储电容器。第一存储电容电极2161与像素驱动电2120中的栅极21211、邦定区2200中的引线2220同层设置。同样地，如上所述，在上述示例的变型中，存储电容器2160的第一电容电极和第二电容电极还可以位于其他层中，从而得到不同结构的子像素。
例如，在本公开的一些示例中，如图4所示，显示基板还可以包括设置在发光元件2140上的封装层2150。封装层2150将发光元件2140密封，从而可以减少或防止由环境中包括的湿气和/或氧引起的发光元件2140的劣化。封装层2150可以为单层结构，也可以为复合层结构，该复合层结构包括无机层和有机层堆叠的结构，例如，封装层2150可以包括依次设置的第一无机封装层2151、第一有机封装层2152、第二无机封装层2153。封装层2150可以延伸至 邦定区，在上述示例中，该封装层未覆盖接触垫。
例如，在本公开一些示例中，如图7B所示，显示基板还包括位于显示区的显示区第三绝缘层21120。显示区第三绝缘层21120设置在封装层2150上，以覆盖封装层2150。显示区第三绝缘层21120与邦定区第三绝缘层2260同层设置。显示基板还可以包括位于显示区中的辅助电极层21130。辅助电极层21130设置在显示区第三绝缘层21120上，该辅助电极层21130可以用于其他辅助功能，例如触控功能。辅助电极层21130在一个子像素的区域上具有开口。显示区第三绝缘层21120的材料可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料，或者包括氧化硅、氮化硅等无机绝缘材料，本公开的实施例对此不做限定。
例如，用于实现触控功能的辅助电极层可以用于实现电容型触控结构，该电容型触控结构为自电容型或互电容型。自电容型触控结构包括多个阵列排布(在同一层)的自电容电极，每个自电容电极通过触控引线与触控处理电路(触控芯片)电连接。通过检测在触控时由于例如手指靠近而导致自电容电极的电容变化而实现位置检测。互电容型触控结构包括多条沿第一方向延伸的第一触控信号线和多条沿第二方向延伸的第二触控信号线，第一触控信号线和第二触控信号线均通过触控引线与触控处理电路(触控芯片)电连接。第一方向和第二方向彼此交叉并且形成开口，由此在第一触控信号线和第二触控信号线交叉位置处形成触控电容，通过检测在触控时由于例如手指靠近而导致该触控电容的变化而实现位置检测。本公开的实施例以互电容型触控结构为例进行说明。
如图所示，该互电容型触控结构包括相互交叉且同层设置的激励电极以及感应电极，以实现显示基板的触控功能。例如，感应电极包括多个分段，而激励电极为连续的，在激励电极和感应电极彼此交叉的位置，提供与感应电极及激励电极位于不同层的桥接电极，以将感应电极的两个相邻的分段彼此电连接。通过设置感应电极及激励电极可以提高显示基板触控的灵敏度。
例如，形成辅助电极层21130的材料可以包括氧化锢锡(ITO)，并且由此得到透明电极，或者形成辅助电极层21130的材料可以包括金属网格，也可以由此得到透明电极。
需要说明的是，在图7B中所示的显示基板的显示区的结构，与在图4中所示的显示基板的显示区的结构的区别在于：图7B中的显示基板在封装层上 设置显示区第三绝缘层21120及辅助电极层21130，而不设置钝化层。基于此，显示基板在图7B中与图4中相同的膜层的结构及膜层所采用的材料等将不再详细赘述。
例如，在本公开的一些示例中，图8A为本公开另一实施例提供的图6所示显示基板沿M4-N4的截面示意图。
图8A中示出的邦定区的结构与图7A中示出的邦定区的结构相比，在显示基板的邦定区2200中增加第二绝缘层2250。第二绝缘层2250在第一接触垫金属2215与第二接触垫金属2217之间。第二绝缘层2250覆盖第一接触垫金属层2215的边缘，以防止第一接触垫金属层2215的边缘在后续的构图工艺中被刻蚀液腐蚀。同时，第一绝缘层2230覆盖第二接触垫金属2217的边缘，以防止第二接触垫金属层2217的边缘在后续的构图工艺中被刻蚀液腐蚀。例如，在接触垫2211与接触垫2212之间的间隙处，第二绝缘层2250位于第一绝缘层2230与邦定区层间绝缘层2244之间。第二绝缘层2250具有第一接触垫过孔2251，第二接触垫金属层2217通过第一接触垫过孔2251与第一接触垫金属层2217电连接。
在至少一个示例中，如图8A所示，相比于第一接触垫金属2215的边缘，第二接触垫金属2217在第二绝缘层2250上进一步向外延伸，覆盖了第一接触垫金属2215的边缘，也即，在衬底基板2000的表面上，第二接触垫金属2217的正投影覆盖了第一接触垫金属2215的正投影。这样的结构可以降低接触垫边缘的段差，有利于第一绝缘层2230覆盖第二接触垫金属2217的边缘。
例如，在本公开的一些示例中，图8B为本公开另一实施例提供的图6所示显示基板的显示区的截面示意图。
图8B中示出的显示基板的结构与图7B中示出的显示基板的结构相比，在显示基板的显示区的子像素(210)中增加钝化层21110。钝化层21110位于像素驱动电路和第一平坦化层2130之间且包括钝化层过孔21111。钝化层可以保护像素驱动电路的源极和漏极不被水汽腐蚀。像素驱动电路和第一转接电极2180还可以通过钝化层过孔21111电连接。第二绝缘层2250与钝化层21110同层设置。
本公开至少一个实施例提供一种显示装置，该显示装置可以包括上述任一实施例的显示基板。
例如，在一些示例中，显示装置还可以包括柔性电路板及控制芯片。例 如，柔性电路板邦定到显示基板的邦定区，而控制芯片安装在柔性电路板上，由此与显示区电连接；或者，控制芯片直接邦定到邦定区，由此与显示区电连接。
例如，控制芯片可以为中央处理器、数字信号处理器、系统芯片(SoC)等。例如，控制芯片还可以包括存储器，还可以包括电源模块等，且通过另外设置的导线、信号线等实现供电以及信号输入输出功能。例如，控制芯片还可以包括硬件电路以及计算机可执行代码等。硬件电路可以包括常规的超大规模集成(VLSI)电路或者门阵列以及诸如逻辑芯片、晶体管之类的现有半导体或者其它分立的元件；硬件电路还可以包括现场可编程门阵列、可编程阵列逻辑、可编程逻辑设备等。
例如，本公开至少一个实施例提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开至少一个实施例还提供一种显示基板的制备方法，该方法包括：提供衬底基板，其中，衬底基板包括显示区和位于显示区至少一侧的邦定区；在显示区中形成多个子像素；在显示区中形成多条数据线，多条数据线被配置为向多个子像素提供数据信号；在邦定区中形成多条数据引线，多条数据引线与多条数据线电连接；在邦定区中形成至少一组接触垫，至少一组接触垫包括多个接触垫，多个接触垫中的至少一个形成为包括第一接触垫金属层和第二接触垫金属层，第一接触垫金属层形成为位于多条数据引线远离衬底基板一侧且与多条数据引线中的一条电连接，第二接触垫金属层形成为位于第一接触垫金属层远离衬底基板的一侧且与第一接触垫金属层电连接，第二接触垫金属层覆盖第一接触垫金属层的边缘；在邦定区形成第一绝缘层，第一绝缘层位于多个接触垫之间的间隙并覆盖多个接触垫的边缘，且被配置为露出多个接触垫的背离衬底基板的表面。
在利用上述实施例的制备方法获得的显示基板中，位于显示基板的邦定区的第一绝缘层被配置为露出接触垫的背离衬底基板的表面并且覆盖接触垫的边缘，从而在显示基板的制备工艺过程中，第一绝缘层可以保护接触垫中的金属层的边缘，避免后续的构图工艺中的刻蚀液刻蚀裸露的接触垫的边缘，进而提高显示基板的产品良率和可靠性。
例如，在本公开的一些示例中，形成所述第一绝缘层包括：使得第一绝 缘层相对于衬底基板的表面的高度不大于与接触垫的相对于衬底基板的表面的高度。
在不同的实施例中，邦定区中的第一绝缘层可以与显示区中的不同绝缘层同层形成，由此在邦定区得到不同的层叠结构。
例如，在本公开的一些示例中，制备方法还包括：在显示区中形成多个子像素包括：在显示区中形成多个子像素，其中，多个子像素中至少一个包括像素驱动电路、第一平坦化层以及发光元件，在显示区中形成子像素包括：在衬底基板上形成像素驱动电路，在像素驱动电路远离衬底基板的一侧形成第一平坦化层以提供第一平坦化表面且在第一平坦化层中形成第一过孔，在第一平坦化表面上形成第一转接电极，其中，第一转接电极通过第一过孔与像素驱动电路电连接，在第一转接电极远离衬底基板的一侧形成第二平坦化层以提供第二平坦化表面且在第二平坦化层中形成第二过孔，其中，第一绝缘层与第二平坦化层通过同一第二绝缘材料层形成；在第二平坦化表面上形成发光元件，其中，发光元件通过所述第二过孔与第一转接电极电连接。
例如，在本公开的一些示例中，第一绝缘层与第二平坦化层通过同一第一绝缘材料层形成包括：在形成接触垫和所述像素驱动电路之后，在衬底基板上沉积第一绝缘材料层；对第一绝缘材料层进行构图工艺，以使得第一绝缘材料层的位于显示区的部分形成为第二平坦化层且在第二平坦化层中形成所述第二过孔，去除第一绝缘材料层的与接触垫重叠的部分，并且减薄第一绝缘材料层的位于邦定区且位于接触垫边缘的部分以形成第一绝缘层。
例如，在本公开的一些示例中，对第一绝缘材料层进行构图工艺包括：使用灰色调掩模板或半色调掩模板构图工艺对第一绝缘材料层进行构图。
下面，以制备图5B所示的显示基板为例，结合图9A至图9M详细介绍本公开实施例中显示基板的制作方法。
例如，提供衬底基板1000，该衬底基板1000包括显示区和位于显示区周边的周边区，该周边区包括位于显示区至少一侧的至少一个邦定区。例如，在衬底基板1000的显示区中通过沉积方式形成显示区缓冲层1121，同时在邦定区中形成邦定区缓冲层1241。
例如，衬底基板1000可以包括有机材料，例如该有机材料可以为聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料，衬底基板1000可以为柔性基板或非柔 性基板，本公开的实施例对此不作限制。
显示区缓冲层1121及邦定区缓冲层1241的材料可以包括氧化硅、氮化硅、氧氮化硅等绝缘材料。
例如，在显示区缓冲层1121上形成有源层。例如，在衬底基板1000上沉积半导体材料层，然后对半导体材料层进行构图工艺形成有源层1122。有源层1121包括源极区1123和漏极区1124。
例如，有源层1122的半导体材料可以包括多晶硅或氧化物半导体(例如，氧化铟镓锌)等。
例如，在有源层1122形成后，可以通过沉积等方式在有源层1212上形成显示区第一栅绝缘层1128，在邦定区的邦定区缓冲层1241上形成邦定区第一栅绝缘层1242。显示区第一栅绝缘层1128及邦定区第一栅绝缘层1242的材料例如可以包括氧化硅、氮化硅、氧氮化硅等绝缘材料。
例如，如图9A所示，在显示区第一栅绝缘层1128形成后，可以通过构图工艺在显示区的显示区第一栅绝缘层1128上形成栅极11211及第一电容电极1161，并且在邦定区的衬底基板1000上形成多条引线1220。例如，在衬底基板1000上沉积形成第一金属材料层1410，然后对第一金属材料层1410进行构图工艺以形成栅极11211、第一电容电极1161及多条引线1220。第一金属材料层1410可以包括金属材料或者合金材料例如钼、铝及钛等金属材料或其合金，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Ti/Al/Ti))。
在该步骤中，在一些示例中，可以使用栅极进行作为掩膜，通过对有源层进行掺杂以形成导电的源极区1123及漏极区1124，而在源极区1123及漏极区1124之间的沟道区由于栅极的遮挡作用而未掺杂。
例如，如图9B所示，在栅极11211、第一电容电极1161及多条引线1220形成后，可以通过沉积等方式在衬底基板上沉积绝缘材料，在栅极11211上形成显示区第二栅绝缘层1129，并且在邦定区通过构图工艺在多条引线1220上形成邦定区第二栅绝缘层1243。邦定区第二栅绝缘层1243具有第一接触垫过孔1216。邦定区第二栅绝缘层的材料例如可以包括氧化硅、氮化硅、氧氮化硅等绝缘材料。
例如，在显示区第二栅绝缘层1129上形成第二电容电极1162，在衬底基板上沉积金属材料层，通过构图工艺在与第一电容电极1161重叠的部分形成 第二电容电极1162。第一电容电极1161和第二电容电极1162实现为存储电容器1160。
例如，在形成第二电容电极1162后，可以通过沉积等方式在显示区形成显示区层间绝缘层11210，在邦定区形成及邦定区层间绝缘层1244。邦定区层间绝缘层1244具有第二接触垫过孔1219。邦定区层间绝缘层1244的材料例如可以包括氧化硅、氮化硅、氧氮化硅等绝缘材料。
例如，如图9C所示，在显示区第一栅绝缘层1128、显示区第二栅绝缘层1129及显示区层间绝缘层11210中形成过孔，暴露有源层1122的源极区1123及漏极区1124。在衬底基板上通过沉积等方式形成第二金属材料层1150。第二金属材料层1150可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Ti/Al/Ti))。
例如，通过构图工艺在显示区形成源极1125和漏极1126，在邦定区形成第一接触垫金属层1215。源极1125和漏极1126通过显示区第一栅绝缘层1128、显示区第二栅绝缘层1129及显示区层间绝缘层11210中的分别与源极区1123及漏极区1124电连接。第一接触垫金属层1215通过邦定区第二栅绝缘层1243中的第一接触垫过孔1216以及邦定区层间绝缘层中的第二接触垫过孔1219与引线1220电连接。例如，如图9D所示，在衬底基板上沉积第一绝缘材料层1710以覆盖源极1125和漏极1126，以及覆盖显示区层间绝缘层11210。对第一绝缘材料层1710进行光刻工艺，以在显示区形成第一平坦化层1130以提供平坦化表面，第一平坦化层1130具有第一过孔1131。第一绝缘材料层1710可以包括氧化硅、氮化硅、氮氧化硅等无机绝缘材料，或者可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料。
例如，在显示基板上形成位于显示区的像素驱动电路1120、存储电容器1160、第一平坦化层1130，以及位于邦定区的引线1220、邦定区层间绝缘层1244、第一接触垫金属层1215后，在衬底基板上沉积第三金属材料层1510，第三金属材料层1510可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构。
例如，图9E所示，对第三金属材料层1510进行构图工艺，以在显示区形成第一转接电极1180，在邦定区形成第二接触垫金属层1217。第二接触垫金 属层1217覆盖第一接触垫金属层1215的边缘，以避免第一接触垫金属层1215被腐蚀。在该实施例中，第一接触垫金属层1215和第二接触垫金属层1217层叠以实现接触垫1210。
例如，如图9F所示，在衬底基板上沉积第一绝缘材料层1710，在第一绝缘材料层1710上沉积光刻胶1720。第一绝缘材料层1710可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料。
例如，如图9G所示，提供第一掩膜版1610对光刻胶1720进行曝光，第一掩膜版1610包括完全透光区、部分透光区及不透光区。第一掩膜版1610在邦定区包括与接触垫1210之间的间隙重叠的第一透光图案1611及与接触垫1210重叠的第二透光图案1612。第一掩膜版1610在显示区包括与第二透光图案1612及非透光图案1613。第一透光图案1611位于部分透光区，第二透光图案1612位于完全透光区，非透光图案1613位于不透光区。即，第一掩膜版1610为灰色掩膜版或半色调掩膜版。光刻胶为正性光刻胶，对应地，第一透光图案1611的透光率小于第二透光图案1612的透光率。在曝光过程中，可以在使得光刻胶1720中与第二透光图案1612对应的部分被完全曝光的情况下，光刻胶1720中与第一透光图案1611对应的部分被部分曝光。光刻胶1720在显示区与非透光图案1613对应的部分未被曝光。
又例如，在上述构图工艺中，也可以采用负性光刻胶，那么所采用的掩模板例如是与上述第二掩模板1610互补的掩模板，由此在曝光、显影后得到上述光刻胶图案1721及光刻胶图案1722。
例如，如图9H所示，对光刻胶1720进行显影，光刻胶1720的被完全曝光的部分去除，即，在邦定区中，与接触垫1210重叠的光刻胶1720被去除，光刻胶1720的被部分曝光的部分被减薄，而光刻胶1720的未被曝光的部分的厚度例如基本未改变。显影后，光刻胶1720在邦定区形成为光刻胶图案1721。同样地，在显示区中，与漏极1126重叠的光刻胶1720被去除。显影后，光刻胶1720在显示区形成为光刻胶图案1722。
例如，如图9I所示，对邦定区及显示区中的第一绝缘材料层1710进行刻蚀以去除在邦定区域接触垫重叠的绝缘材料层，以及在显示区形成第二过孔1191。
例如，如图9J所示，之后，进行灰化工艺去除邦定区的光刻胶图案1721和减薄显示区的光刻胶图案1722，这里显示区的光刻胶图案1722被保留。然 后，利用当前的光刻胶图案，对邦定区中剩余的第一绝缘材料层1710进行刻蚀并控制刻蚀厚度以形成第一绝缘层1230，并且使得刻蚀后形成的第一绝缘层1230相对于衬底基板1000的表面的高度不大于接触垫1210的第二接触垫金属层1217相对于衬底基板1000的表面的高度。
例如，如图9K所示，去除显示区的光刻胶图案1722。在显示区形成第二平坦化层1190以提供平坦化表面。
例如，如图9L所示，在显示区的第二平坦化1190上形成发光元件1140的第一电极1141；在第二平坦化1190以及第一电极1141上形成像素限定层1144，像素限定层1144包括多个开口，以限定多个像素单元。多个开口的每个暴露对应的第一电极1141。之后，将发光层1142通过例如蒸镀工艺形成在像素限定层1144的多个开口中，然后将第二电极1143形成在像素限定层1144以及发光层1142上，例如该第二电极1143可以形成在部分或整个显示区域中，从而在制备工艺中可以整面形成。发光元件1140的第一电极1141通过第二过孔1191与第一转接电极1180电连接。
例如，第一电极1141的材料可以包括至少一种透明导电氧化物材料，包括氧化锢锡(ITO)、氧化锢锌(IZO)、氧化锌(ZnO)等。此外，第一电极1141可以包括具有高反射率的金属作为反射层，诸如银(Ag)。
例如，对于OLED，发光层1142可以包括小分子有机材料或聚合物分子有机材料，可以为荧光发光材料或磷光发光材料，可以发红光、绿光、蓝光，或可以发白光；并且，根据需要发光层还可以进一步包括电子注入层、电子传输层、空穴注入层、空穴传输层等功能层。对于QLED，发光层1142可以包括量子点材料，例如，硅量子点、锗量子点、硫化镉量子点、硒化镉量子点、碲化镉量子点、硒化锌量子点、硫化铅量子点、硒化铅量子点、磷化铟量子点和砷化铟量子点等，量子点的粒径为2-20nm。
例如，第二电极1143可以包括各种导电材料。例如，第二电极2143可以包括锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料。
例如，像素限定层1144的材料可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料，或者包括氧化硅、氮化硅等无机绝缘材料，本公开的实施例对此不做限定。
例如，如图9M所示，在显示区的发光元件1140上形成封装层1150。封装层1150将发光元件1140密封，从而可以减少或防止由环境中包括的湿气和 /或氧引起的发光元件1140的劣化。
封装层1150可以为单层结构，也可以为复合层结构，该复合层结构包括无机层和有机层堆叠的结构，例如，封装层1150可以包括依次设置的第一无机封装层1151、第一有机封装层1152、第二无机封装层1153。封装层1150可以延伸至邦定区，在上述示例中，该封装层未覆盖接触垫。
例如，该封装层的材料可以包括氮化硅、氧化硅、氮氧化硅、高分子树脂等绝缘材料。氮化硅、氧化硅、氮氧化硅等无机材料的致密性高，可以防止水、氧等的侵入；有机封装层的材料可以为含有干燥剂的高分子材料或可阻挡水汽的高分子材料等，例如高分子树脂等以对显示基板的表面进行平坦化处理，并且可以缓解第一无机封装层和第二无机封装层的应力，还可以包括干燥剂等吸水性材料以吸收侵入内部的水、氧等物质。
在本公开的另一个示例中，如图5B所示的显示基板的制备方法可以包括图9F～图9K，如图9F～图9K所示的工艺可以参见上述示例的相关说明。
例如，在该示例中，第一绝缘材料层1710可以为光敏树脂材料，例如光刻胶。例如，该光敏树脂材料为正性光刻胶，在涂覆了该光敏树脂材料以形成第一材料层之后，使用例如上述第一掩模板1610进行曝光，第一掩膜版1610包括完全透光区、部分透光区及不透光区。第一掩膜版1610在邦定区包括与接触垫1210之间的间隙重叠的第一透光图案1611及与接触垫1210重叠的第二透光图案1612。第一掩膜版1610在显示区包括与漏极1126重合的第二透光图案1612及非透光案1613。第一透光图案1611位于部分透光区，第二透光图案1612位于完全透光区，非透光图案1613位于不透光区。
在曝光过程中，使得第一绝缘材料层1710中与第二透光图案1612对应的部分被完全曝光，与第一透光图案1611对应的部分被部分曝光，而与显示区的非透光图案1613对应的部分未被曝光。在显影后，显示区中未被曝光的第一绝缘材料层1710形成第二平坦化层1190。对邦定区中被部分曝光的第一绝缘材料层1710形成第一绝缘层1230，并且形成的第一绝缘层1230相对于衬底基板1000的表面的高度不大于接触垫1210的第二接触垫金属层1217相对于衬底基板1000的表面的高度。相应的，显示区中和邦定区中被完全曝光的第一绝缘材料层1710被去除，形成显示区中的第二过孔1191以及暴露出邦定区中的接触垫。上述制备方法同样可以得到如图9K所示的实施例的显示基板。
又例如，该光敏树脂材料也可以为负性光刻胶，此时采用的掩模板例如 与上述第一掩模板1160互补的掩模板，由此在曝光、显影之后也同样在显示区形成第二平坦化层，在邦定区露出接触垫以及覆盖接触垫的边缘第一绝缘层。
利用上述制备方法获得的显示基板中，位于显示基板的邦定区的第一绝缘层被配置为露出接触垫的背离衬底基板的表面并且覆盖接触垫的边缘，从而在显示基板的制备工艺过程中，第一绝缘层可以保护接触垫中的金属层的边缘，避免后续例如形成转接金属层等时使用的刻蚀液刻蚀裸露的接触垫中的金属层，由此进而提高显示基板的产品良率和可靠性。
又例如，在另一个实施例中，提供了在对应于图4中示出的显示基板的制备方法。图4中示出的邦定区的结构与图5B中出的邦定区的结构相比，在显示基板的邦定区1200中增加第二绝缘层1250。第二绝缘层1250设置在第一接触垫金属层1215与第二接触垫金属层1217之间。并且第二绝缘层1250覆盖第一接触垫金属层1215的边缘，以防止第一接触垫金属层1215的边缘被后续的构图工艺中的刻蚀液腐蚀。而且，相比于第一接触垫金属层1215的边缘，第二接触垫金属层1217在第二绝缘层1250上进一步向外延伸，覆盖了第一接触垫金属层1215的边缘，也即，在衬底基板1000的表面上，第二接触垫金属层1217的正投影覆盖了第一接触垫金属层1215的正投影。这样的结构可以降低接触垫边缘的段差，有利于第一绝缘层1230覆盖第二接触垫金属层1217的边缘。同样，在显示基板的显示区的子像素中增加钝化层11110。钝化层11110位于像素驱动电路1120和第一平坦化层1130之间且包括钝化层过孔11111。钝化层可以保护像素驱动电路的源极和漏极不被水汽腐蚀。像素驱动电路和第一转接电极1180还通过钝化层过孔11111电连接。在邦定区中，第二绝缘层1250与钝化层11110同层设置。
在该实施例中，可以在图9C和图9D的步骤之间，增加形成钝化层的步骤。例如，在图9C所示的结构的基础上，形成钝化层薄膜以以覆盖源极1125和漏极1126，以及覆盖显示区层间绝缘层11210，然后对于该钝化层薄膜构图以在显示区形成暴露漏极1126的过孔以及在钝化形成暴露第一接触垫金属层1215的钝化层过孔11111。然后，参考图9D所示，继续在衬底基板上沉积第一绝缘材料层1710以覆盖钝化层。
例如，钝化层的材料可以包括有机绝缘材料或无机绝缘材料，例如，氮化硅材料，由于其具有较高的介电常数且具有很好的疏水功能，能够很好的 保护像素驱动电路不被水汽腐蚀。
又例如，在另一个实施例中，提供了对应于图7A和图7B示出的显示基板的制备方法，在图9L所示结构的基础上，可以继续在衬底基板上形成位于显示区的显示区第三绝缘层21120。显示区第三绝缘层21120设置在发光元件2140上，以覆盖发光元件2140，且在发光元件2140远离衬底基板2000一侧提供平坦化表面。然后，在显示区第三绝缘层21120形成辅助导电层，辅助导电层可以包括位于显示区中的辅助电极层21130。辅助电极层21130设置在显示区第三绝缘层21120上，该辅助电极层21130可以用于其他辅助功能，例如触控功能。
显示区第三绝缘层21120的材料可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料，或者包括氧化硅、氮化硅等无机绝缘材料，本公开的实施例对此不做限定。例如，用于实现触控功能的辅助电极可以用于实现电容型触控结构，该电容型触控结构为自电容型或互电容型。
在本公开的多个实施例中，显示装置的制备方法的流程可以包括更多或更少的操作，这些操作可以顺序执行或并行执行。虽然上文描述的制备方法的流程包括特定顺序出现的多个操作，但是应该清楚地了解，多个操作的顺序并不受限制。上文描述的制备方法可以执行一次，也可以按照预定条件执行多次。
关于上述实施例提供的显示装置的制备方法的技术效果可以参考本公开的实施例中提供的显示装置的技术效果，这里不再赘述。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (22)

  1. 一种显示基板，包括：
    衬底基板，包括显示区和位于所述显示区至少一侧的邦定区；
    多个子像素，位于所述显示区中；
    多条数据线，位于所述显示区中，配置为向所述多个子像素提供数据信号；
    多条数据引线，位于所述邦定区中且与所述多条数据线电连接；
    至少一组接触垫，位于所述邦定区，所述至少一组接触垫包括多个接触垫，所述多个接触垫中的至少一个包括第一接触垫金属层和第二接触垫金属层，所述第一接触垫金属层位于所述多条数据引线远离所述衬底基板一侧，且与所述多条数据引线中的一条电连接，所述第二接触垫金属层位于所述第一接触垫金属层远离所述衬底基板的一侧，且与所述第一接触垫金属层电连接，所述第二接触垫金属层覆盖所述第一接触垫金属层的边缘；
    第一绝缘层，位于所述邦定区，所述第一绝缘层位于所述多个接触垫之间的间隙并覆盖所述多个接触垫的边缘，且被配置为露出所述多个接触垫的背离所述衬底基板的表面。
  2. 根据权利要求1所述的显示基板，其中，所述第一绝缘层远离所述衬底基板一侧的表面距离所述衬底基板的垂直距离不大于所述多个接触垫远离所述衬底基板一侧的表面距离所述衬底基板的垂直距离。
  3. 根据权利要求1或2所述的显示基板，其中，所述第二接触垫金属层的边缘被所述第一绝缘层覆盖。
  4. 根据权利要求1-3任一项所述的显示基板，其中，所述至少一组接触垫包括第一组接触垫和第二组接触垫，所述第一组接触垫和所述第二组接触垫分别包括多个接触垫，所述第二组接触垫位于所述第一组接触垫靠近所述显示区的一侧，所述多条数据引线与所述第一组接触垫和所述第二组接触垫一一对应电连接。
  5. 根据权利要求4所述的显示基板，其中，所述第一绝缘层的至少部分位于所述第一组接触垫相邻的接触垫之间的间隙中。
  6. 根据权利要求4所述的显示基板，其中，所述第一绝缘层的至少部分位于所述第二组接触垫中相邻的接触垫之间的间隙中。
  7. 根据权利要求4-6任一项所述的显示基板，其中，所述第一绝缘层的至少部分位于所述第一组接触垫中相邻的接触垫之间的间隙中和位于所述第二组接触垫中相邻的接触垫之间的间隙中。
  8. 根据权利要求4-7任一项所述的显示基板，其中，所述第一组接触垫的多个接触垫排布为至少第一行，所述第二组接触垫的多个接触垫排布为至少第二行；
    所述第一行和所述第二行的行方向与所述显示区的面向所述邦定区的侧边的延伸方向平行，
    所述第一绝缘层的至少部分位于所述第一行与所述第二行之间的间隙。
  9. 根据权利要求1-8任一项所述的显示基板，其中，所述多个子像素中至少一个包括像素驱动电路、第一平坦化层、第一转接电极、第二平坦化层以及发光元件，
    所述第一平坦化层在所述像素驱动电路远离所述衬底基板的一侧以提供第一平坦化表面且包括第一过孔，
    所述第一转接电极在所述第一平坦化表面上，且通过所述第一过孔与所述像素驱动电路电连接，
    所述第二平坦化层在所述第一转接电极远离所述衬底基板的一侧以提供第二平坦化表面且包括第二过孔，
    所述发光元件在所述第二平坦化表面上且通过所述第二过孔与所述第一转接电极电连接，
    其中，所述第一绝缘层与所述第二平坦化层同层设置。
  10. 根据权利要求9所述的显示基板，其中，所述像素驱动电路包括第一显示区金属层，
    所述第一显示区金属层和所述第一接触垫金属层同层设置，
    所述第一转接电极与所述第二接触垫金属层同层设置。
  11. 根据权利要求10所述的显示基板，其中，所述像素驱动电路包括薄膜晶体管，所述薄膜晶体管包括源极和漏极，
    所述源极和漏极位于所述第一显示区金属层中，且与所述第一显示区金属层位于同层。
  12. 根据权利要求9-11任一项所述的显示基板，其中，
    所述多个子像素中至少一个还包括钝化层，所述钝化层位于所述像素驱动电路和所述第一平坦化层之间且包括钝化层过孔，
    其中，所述像素驱动电路和所述第一转接电极还通过所述钝化层过孔电连接；
    所述显示基板还包括在所述邦定区中的第二绝缘层，其中，所述第二绝缘层在所述第一接触垫金属层与所述第二接触垫金属层之间且覆盖所述第一接触垫金属层的边缘，
    所述第二绝缘层具有第一接触垫过孔，所述第二接触垫金属层通过所述第一接触垫过孔与所述第一接触垫金属层电连接；
    其中，所述第二绝缘层和所述钝化层同层设置。
  13. 根据权利要求9-12任一项所述的显示基板，其中，所述多个子像素中至少一个还包括存储电容，所述存储电容包括两个电容电极，
    所述薄膜晶体管还包括栅极，
    所述多条数据引线中至少一条、所述存储电容的两个电容电极之一与所述栅极同层设置。
  14. 根据权利要求9-13任一项所述的显示基板，还包括：
    邦定区层间绝缘层，位于所述邦定区中，并且位于所述多个接触垫与所述引线之间和所述第一绝缘层与所述衬底基板之间；
    邦定区第一栅绝缘层，位于所述邦定区中，且位于所述邦定区层间绝缘层靠近所述衬底基板的一侧；以及
    邦定区第二栅绝缘层，位于所述邦定区中，且位于所述邦定区第一栅绝缘层及所述邦定区层间绝缘层之间，与所述邦定区层间绝缘层层叠；
    其中，所述邦定区第二栅绝缘层包括第一接触垫过孔，所述邦定区层间绝缘层包括第二接触垫过孔，所述多条数据引线中至少一条通过所述第一接触垫过孔及所述第二接触垫过孔与所述接触垫电连接。
  15. 根据权利要求14所述的显示基板，所述多个子像素中至少一个还包括显示区层间绝缘层、显示区第一栅绝缘层以及显示区第二栅绝缘层，
    所述显示区层间绝缘层、显示区第一栅绝缘层和所述显示区第二栅绝缘层分别与所述邦定区层间绝缘层、邦定区第一栅绝缘层和所述邦定区第二栅绝缘层同层设置；
    所述显示区层间绝缘层位于所述栅极与所述源极和所述漏极之间，所 述显示区第一栅绝缘层位于所述显示区层间绝缘层靠近所述衬底基板的一侧，所述显示区第二栅绝缘层位于所述显示区层间绝缘层与所述显示区第一栅绝缘层之间；
    所述两个电容电极包括第一电容电极和第二电容电极，所述第一电容电极与所述栅极同层设置，所述第二电容电极设置在所述显示区层间绝缘层与所述显示区第二栅绝缘层之间。
  16. 根据权利要求9-15任一项所述的显示基板，还包括邦定区第三绝缘层，
    其中，所述邦定区第三绝缘层位于所述邦定区中，并且设置在所述第一绝缘层和所述接触垫远离所述衬底基板的一侧以覆盖所述第一绝缘层及所述接触垫，
    所述邦定区第三绝缘层具有第三接触垫过孔以露出所述接触垫的表面。
  17. 根据权利要求16所述的显示基板，还包括位于显示区的封装层及显示区第三绝缘层，所述封装层位于所述发光元件的远离所述衬底基板的一侧，所述显示区第三绝缘层位于所述封装层的远离所述衬底基板的一侧，
    其中，所述邦定区第三绝缘层与所述显示区第三绝缘层位于同层。
  18. 根据权利要求17所述的显示基板，还包括辅助导电层，
    其中，所述辅助导电层位于所述邦定区中，且设置在所述邦定区第三绝缘层远离所述衬底基板的一侧，
    所述辅助导电层包括位于所述邦定区中的第二转接电极图案，
    其中，所述第二转接电极图案通过所述第三接触垫过孔与所述接触垫电连接。
  19. 根据权利要求18所述的显示基板，还包括辅助电极层，设置在所述显示区第三绝缘层上，
    其中，所述辅助电极层与所述第二转接电极图案同层设置。
  20. 根据权利要求19所述的显示基板，其中，在所述邦定区中，所述第二转接电极图案相对于所述衬底基板的表面的高度不大于与所述邦定区第三绝缘层相对于所述衬底基板的表面的高度。
  21. 一种显示装置，包括如权利要求1-20中任一项所述的显示基板。
  22. 一种显示基板的制备方法，包括：
    提供衬底基板，其中，所述衬底基板包括显示区和位于所述显示区至少一侧的邦定区；
    在所述显示区中形成多个子像素；
    在所述显示区中形成多条数据线，所述多条数据线被配置为向所述多个子像素提供数据信号；
    在所述邦定区中形成多条数据引线，所述多条数据引线与所述多条数据线电连接；
    在所述邦定区中形成至少一组接触垫，所述至少一组接触垫包括多个接触垫，所述多个接触垫中的至少一个形成为包括第一接触垫金属层和第二接触垫金属层，所述第一接触垫金属层形成为位于所述多条数据引线远离所述衬底基板一侧且与所述多条数据引线中的一条电连接，所述第二接触垫金属层形成为位于所述第一接触垫金属层远离所述衬底基板的一侧且与所述第一接触垫金属层电连接，所述第二接触垫金属层覆盖所述第一接触垫金属层的边缘；
    在所述邦定区形成第一绝缘层，所述第一绝缘层位于所述多个接触垫之间的间隙并覆盖所述多个接触垫的边缘，且被配置为露出所述多个接触垫的背离所述衬底基板的表面。
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