WO2021203360A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2021203360A1
WO2021203360A1 PCT/CN2020/083962 CN2020083962W WO2021203360A1 WO 2021203360 A1 WO2021203360 A1 WO 2021203360A1 CN 2020083962 W CN2020083962 W CN 2020083962W WO 2021203360 A1 WO2021203360 A1 WO 2021203360A1
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WO
WIPO (PCT)
Prior art keywords
layer
substrate
touch
area
barrier
Prior art date
Application number
PCT/CN2020/083962
Other languages
English (en)
French (fr)
Inventor
张波
董向丹
王蓉
苟结
程博
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202211023652.8A priority Critical patent/CN115172436A/zh
Priority to CN202080000494.7A priority patent/CN113892182B/zh
Priority to JP2021568085A priority patent/JP2023529243A/ja
Priority to EP20897614.2A priority patent/EP4135041A4/en
Priority to PCT/CN2020/083962 priority patent/WO2021203360A1/zh
Priority to US17/261,923 priority patent/US11696480B2/en
Publication of WO2021203360A1 publication Critical patent/WO2021203360A1/zh
Priority to US18/317,798 priority patent/US20230284505A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0446—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H10K59/8731—Encapsulations multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04111—Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel and a display device.
  • OLED display devices have been widely used.
  • the touch function layer is fabricated on the encapsulation layer of the OLED display panel.
  • the embodiment of the present disclosure provides a display panel and a display device.
  • a display panel including:
  • the substrate includes a display area, a peripheral area, and a pad area, the peripheral area surrounds the display area, and the pad area is located on a side of the peripheral area away from the display area;
  • At least one barrier is disposed on the substrate, the barrier is located in the peripheral area and surrounds the display area, and the barrier includes a single side located between the display area and the pad area Blocking structure
  • An organic insulating structure is disposed on the substrate, the organic insulating structure includes a plurality of sub-insulating structures stacked and arranged, a part of each sub-insulating structure of the plurality of sub-insulating structures is located in the display area, and the plurality of sub-insulating structures
  • Each sub-insulating structure in the structure has a first boundary between the display area and the one-sided barrier structure, wherein for any two adjacent sub-insulating structures, all the sub-insulating structures on one side of the substrate are away from each other.
  • the first boundary of the sub-insulating structure is closer to the display area than the first boundary of the sub-insulating structure on the side of the substrate; the distance between the first boundaries of any two adjacent sub-insulating structures Greater than or equal to 20 ⁇ m;
  • the touch electrode pattern is arranged on the side of the organic insulating structure away from the substrate;
  • the touch signal line is arranged on the side of the organic insulating structure away from the substrate. One end of the touch signal line is electrically connected to the touch electrode pattern, and the other end is connected to the pad area.
  • the orthographic projection of the portion of the touch signal line in the peripheral area on the substrate intersects the first boundary of each of the sub-insulating structures.
  • the distance between the first boundaries of any two adjacent sub-insulating structures is between 25 ⁇ m and 60 ⁇ m.
  • the plurality of sub-insulating structures of the organic insulating structure include:
  • the first planarization layer is provided on the substrate
  • the second planarization layer is located on the side of the first planarization layer away from the substrate;
  • the pixel defining layer is located on a side of the second planarization layer away from the substrate.
  • the display panel further includes: an encapsulation layer disposed on a side of the organic insulating structure away from the substrate; wherein the touch electrode pattern and the touch signal line are both located on the The encapsulation layer is away from the side of the substrate.
  • the encapsulation layer includes:
  • the first inorganic encapsulation layer (a) The first inorganic encapsulation layer
  • the second inorganic encapsulation layer is located on the side of the first inorganic encapsulation layer away from the substrate;
  • the organic encapsulation layer is located between the first inorganic encapsulation layer and the second inorganic encapsulation layer.
  • a groove is formed between the organic insulating structure and the single-sided barrier structure, and the orthographic projection of the encapsulation layer on the substrate simultaneously covers the orthographic projection of the organic insulating structure on the substrate.
  • the projection, the orthographic projection of the groove on the substrate, and the orthographic projection of the single-sided barrier structure on the substrate, and the single-sided barrier structure is located between the substrate and the encapsulation layer.
  • the display panel further includes: a touch insulating layer disposed on a side of the packaging layer away from the substrate;
  • the touch electrode pattern includes a plurality of touch driving electrodes and a plurality of touch sensing electrodes, the touch driving electrodes and the touch sensing electrodes are arranged to cross each other, and the touch driving electrodes intersect with the touch sensing electrodes Insulated and separated by the touch insulating layer, each of the touch driving electrodes and each of the touch sensing electrodes are correspondingly connected to one of the touch signal lines.
  • the touch driving electrode includes: a plurality of driving electrode units arranged along a first direction, and a connecting portion connected between every two adjacent driving electrode units;
  • the touch sensing electrode includes: a plurality of sensing electrode units arranged along a second direction, and a bridge portion connected between every two adjacent sensing electrode units;
  • the first direction crosses the second direction, and the driving electrode unit, the connecting portion, and the sensing electrode unit are all located on a side of the touch insulating layer away from the substrate and located on the same side.
  • Layer, the bridge portion is located between the touch insulating layer and the encapsulation layer.
  • the touch signal line includes a first transmission portion and a second transmission portion, the first transmission portion is located between the touch insulation layer and the encapsulation layer, and the second transmission portion Located on a side of the touch insulating layer away from the encapsulation layer, the second transmission portion is electrically connected to the first transmission portion through a via hole penetrating the touch insulating layer.
  • the display area includes a plurality of pixel units, each pixel unit is provided with a light-emitting element, the display panel further includes a power line, the power line is electrically connected to the light-emitting element, wherein the The power line is located between the organic insulating structure and the substrate, and the orthographic projection of the power line on the substrate overlaps the orthographic projection of the first boundary on the substrate.
  • the barrier includes:
  • the first barrier is located in the peripheral area and surrounds the display area
  • a second barrier located in the peripheral area and surrounding the first barrier
  • the portion of the first barrier between the display area and the pad area, and the portion of the second barrier between the display area and the pad area constitute the Single-sided barrier structure.
  • the substrate is a flexible substrate, which further includes a bending area between the peripheral area and the pad area.
  • the display panel further includes:
  • the first buffer layer is arranged on the substrate
  • a semiconductor layer disposed between the first buffer layer and the first planarization layer
  • a first gate insulating layer disposed between the semiconductor layer and the first planarization layer
  • a first gate electrode layer disposed between the first gate insulating layer and the first planarization layer
  • a second gate insulating layer disposed between the first gate electrode layer and the first planarization layer
  • a second gate electrode layer disposed between the second gate insulating layer and the first planarization layer
  • An interlayer insulating layer disposed between the second gate electrode layer and the first planarization layer
  • a first source-drain conductive layer disposed between the interlayer insulating layer and the first planarization layer;
  • a passivation layer disposed between the first source-drain conductive layer and the first planarization layer
  • a second source-drain conductive layer disposed between the first planarization layer and the second planarization layer;
  • the first electrode layer is disposed between the second planarization layer and the pixel defining layer, the first electrode layer includes a plurality of first electrodes, and the pixel defining layer includes one-to-one with the first electrode Corresponding pixel opening;
  • the light-emitting layer is arranged in the pixel opening
  • the second electrode layer is arranged on the side of the light-emitting layer away from the substrate;
  • the encapsulation layer is arranged on the side of the light-emitting layer away from the substrate;
  • the second buffer layer is arranged on the side of the packaging layer away from the substrate.
  • a display panel including:
  • the substrate includes a display area, a peripheral area, and a pad area, the peripheral area surrounds the display area, and the pad area is located on a side of the peripheral area away from the display area;
  • At least one barrier is disposed on the substrate, the barrier is located in the peripheral area and surrounds the display area, and the barrier includes a single side located between the display area and the pad area Blocking structure
  • An organic insulating structure is disposed on the substrate, a part of the organic insulating structure is located in the display area and the other part is located in the peripheral area, and the organic insulating structure has a bottom surface facing the substrate and opposite to the bottom surface
  • the touch electrode pattern is arranged on the side of the organic insulating structure away from the substrate;
  • the touch signal line is arranged on the side of the organic insulating structure away from the substrate. One end of the touch signal line is electrically connected to the touch electrode pattern, and the other end is connected to the pad area.
  • the orthographic projection of the portion of the touch signal line in the peripheral area on the substrate passes through the orthographic projection of the slope surface on the substrate.
  • the slope angle of the slope surface is between 25° and 35°.
  • the plurality of sub-insulating structures of the organic insulating structure include:
  • the first planarization layer is provided on the substrate
  • the second planarization layer is located on the side of the first planarization layer away from the substrate;
  • the pixel defining layer is located on a side of the second planarization layer away from the substrate.
  • the display panel further includes: an encapsulation layer disposed on a side of the organic insulating structure away from the substrate;
  • the touch electrode pattern and the touch signal line are both located on a side of the packaging layer away from the substrate.
  • the encapsulation layer includes:
  • the first inorganic encapsulation layer (a) The first inorganic encapsulation layer
  • the second inorganic encapsulation layer is located on the side of the first inorganic encapsulation layer away from the substrate;
  • the organic encapsulation layer is located between the first inorganic encapsulation layer and the second inorganic encapsulation layer.
  • a groove is formed between the organic insulating structure and the single-sided barrier structure, and the orthographic projection of the encapsulation layer on the substrate simultaneously covers the orthographic projection of the organic insulating structure on the substrate.
  • the projection, the orthographic projection of the groove on the substrate, and the orthographic projection of the single-sided barrier structure on the substrate, and the single-sided barrier structure is located between the substrate and the encapsulation layer.
  • the display panel further includes: a touch insulating layer disposed on a side of the packaging layer away from the substrate;
  • the touch electrode pattern includes a plurality of touch driving electrodes and a plurality of touch sensing electrodes, the touch driving electrodes and the touch sensing electrodes are arranged to cross each other, and the touch driving electrodes intersect with the touch sensing electrodes Insulated and separated by the touch insulating layer, each of the touch driving electrodes and each of the touch sensing electrodes are correspondingly connected to one of the touch signal lines.
  • the touch driving electrode includes: a plurality of driving electrode units arranged along a first direction, and a connecting portion connected between every two adjacent driving electrode units;
  • the touch sensing electrode includes: a plurality of sensing electrode units arranged along a second direction, and a bridge portion connected between every two adjacent sensing electrode units;
  • the first direction crosses the second direction, and the driving electrode unit, the connecting portion, and the sensing electrode unit are all located on a side of the touch insulating layer away from the substrate and located on the same side.
  • Layer, the bridge portion is located between the touch insulating layer and the encapsulation layer.
  • the touch signal line includes a first transmission portion and a second transmission portion, the first transmission portion is located between the touch insulation layer and the encapsulation layer, and the second transmission portion Located on a side of the touch insulating layer away from the encapsulation layer, the second transmission portion is electrically connected to the first transmission portion through a via hole penetrating the touch insulating layer.
  • the display area includes a plurality of pixel units, each pixel unit is provided with a light-emitting element, the display panel further includes a power line, the power line is electrically connected to the light-emitting element, wherein the The power cord is located between the organic insulating structure and the substrate, and the orthographic projection of the power cord on the substrate overlaps the orthographic projection of the first side surface on the substrate.
  • the barrier includes:
  • the first barrier is located in the peripheral area and surrounds the display area
  • a second barrier located in the peripheral area and surrounding the first barrier
  • the portion of the first barrier between the display area and the pad area, and the portion of the second barrier between the display area and the pad area constitute the Single-sided barrier structure.
  • the substrate is a flexible substrate, which further includes a bending area between the peripheral area and the pad area.
  • the display panel further includes:
  • the first buffer layer is arranged on the substrate
  • a semiconductor layer disposed between the first buffer layer and the first planarization layer
  • a first gate insulating layer disposed between the semiconductor layer and the first planarization layer
  • a first gate electrode layer disposed between the first gate insulating layer and the first planarization layer
  • a second gate insulating layer disposed between the first gate electrode layer and the first planarization layer
  • a second gate electrode layer disposed between the second gate insulating layer and the first planarization layer
  • An interlayer insulating layer disposed between the second gate electrode layer and the first planarization layer
  • a first source-drain conductive layer disposed between the interlayer insulating layer and the first planarization layer;
  • a passivation layer disposed between the first source-drain conductive layer and the first planarization layer
  • a second source-drain conductive layer disposed between the first planarization layer and the second planarization layer;
  • the first electrode layer is disposed between the second planarization layer and the pixel defining layer, the first electrode layer includes a plurality of first electrodes, and the pixel defining layer includes one-to-one with the first electrode Corresponding pixel opening;
  • the light-emitting layer is arranged in the pixel opening
  • the second electrode layer is arranged on the side of the light-emitting layer away from the substrate;
  • the encapsulation layer is arranged on the side of the light-emitting layer away from the substrate;
  • the second buffer layer is arranged on the side of the packaging layer away from the substrate.
  • a display panel including:
  • the substrate includes a display area, a peripheral area, and a pad area, the peripheral area surrounds the display area, and the pad area is located on a side of the peripheral area away from the display area;
  • At least one barrier is disposed on the substrate, the barrier is located in the peripheral area and surrounds the display area, and the barrier includes a single side located between the display area and the pad area Blocking structure
  • An organic insulating structure is arranged on the substrate, the organic insulating structure includes a plurality of sub-insulating structures arranged in a stack, a part of each of the plurality of sub-insulating structures is located in the display area, and each The sub-insulating structure has a first boundary between the display area and the one-sided barrier structure. Except for the sub-insulating structure furthest away from the substrate, each of the remaining sub-insulating structures includes Extension part; wherein, for any two adjacent sub-insulation structures, the extension part of the sub-insulation structure close to the substrate is located at the first boundary of the sub-insulation structure far away from the substrate and the Between the unilateral blocking structure;
  • the touch electrode pattern is arranged on the side of the organic insulating structure away from the substrate;
  • the touch signal line is arranged on the side of the organic insulating structure away from the substrate. One end of the touch signal line is electrically connected to the touch electrode pattern, and the other end is connected to the pad area.
  • the orthographic projection of the portion of the touch signal line in the peripheral area on the substrate overlaps the orthographic projection of the extension portion of each sub-insulation structure on the substrate;
  • the sub-insulating structure having the extension portion is formed by performing a patterning process on an organic material layer using a two-tone mask, wherein, during the patterning process, the extension portion is to be formed
  • the area corresponds to the semi-transmissive area of the two-tone mask.
  • the plurality of sub-insulating structures of the organic insulating structure include:
  • the first planarization layer is provided on the substrate
  • the second planarization layer is located on the side of the first planarization layer away from the substrate;
  • the pixel defining layer is located on a side of the second planarization layer away from the substrate.
  • a display device including the above-mentioned display panel.
  • FIG. 1 is a schematic diagram of area division of a substrate of a display panel provided by some embodiments of the present disclosure.
  • FIG. 2 is a schematic plan view of a display panel provided by some embodiments of the present disclosure.
  • Fig. 3 is an enlarged view of the area Q1 in Fig. 2.
  • Fig. 4 is a cross-sectional view taken along the line AA' in Fig. 3;
  • FIG. 5 is a schematic diagram of a groove between an organic insulating structure and a single-sided barrier structure in some embodiments of the present disclosure.
  • FIG. 6 is an equivalent schematic diagram of a pixel circuit in some embodiments of the disclosure.
  • Fig. 7 is a cross-sectional view taken along the line BB' in Fig. 2;
  • Fig. 8 is a cross-sectional view taken along the line D-D' in Fig. 2.
  • Fig. 9 is a cross-sectional view taken along the line A-A' in Fig. 3 in some other embodiments of the present disclosure.
  • FIG. 10 is one of the structural schematic diagrams of the organic insulating structure in FIG. 9.
  • FIG. 11 is a second structural diagram of the organic insulating structure in FIG. 9.
  • FIGS. 12 to 14 are schematic diagrams of the manufacturing process of one of the sub-insulating structures with extensions provided by some embodiments of the present disclosure.
  • an element or layer when an element or layer is referred to as being “on” or “connected” to another element or layer, the element or layer may be directly on the other element or layer. It is directly connected to the other element or layer, or there may be an intermediate element or an intermediate layer. However, when an element or layer is referred to as being “directly on” or “directly connected to” another element or layer, there are no intervening elements or layers.
  • the term “and/or” includes any and all combinations of one or more of the associated listed items.
  • FIG. 1 is a schematic diagram of the area division of the substrate of the display panel provided by some embodiments of the present disclosure.
  • the substrate SUB includes: a display area DA and a peripheral area.
  • the display area DA can be provided with elements for displaying images, for example, pixel circuits, scan lines GL, data lines DL, light-emitting elements, and so on.
  • the display area DA can also be provided with touch electrode patterns to realize the touch function.
  • the pad area WA is located on one side of the peripheral area PA away from the display area DA.
  • the pad area WA includes a plurality of contact pads PAD (or pads), and each contact pad PAD is configured to be electrically connected to the display area DA. Or a signal line extending from the peripheral area PA.
  • the data line DL may be connected to the contact pad through a data connection line.
  • the contact pad PAD may be exposed on the surface of the pad area WA, that is, not covered by any layer, which facilitates electrical connection to the flexible printed circuit board FPCB (Flexible Print Circuit Board).
  • the flexible printed circuit board FPCB is electrically connected to the external controller, and is configured to transmit signals from the external controller.
  • the contact pad PAD is electrically connected to each signal line, so as to realize mutual communication between the signal line and the flexible printed circuit board FPCB. It should be understood that the number and arrangement of the contact pads PAD in FIG. 1 are only schematic illustrations, and do not constitute a limitation on the contact pads PAD.
  • FIG. 2 is a schematic plan view of a display panel provided by some embodiments of the present disclosure.
  • FIG. 3 is an enlarged view of the area Q1 in FIG. 2
  • FIG. 4 is a cross-sectional view along the line A-A' in FIG. 3.
  • the display panel 100 further includes at least one barrier 10, an organic insulating structure 20, a touch electrode pattern, and a touch signal line TL.
  • the barrier 10 is disposed on the substrate SUB, and the barrier 10 is located in the peripheral area PA and surrounds the display area DA.
  • the barrier 10 is used to block external water vapor or oxygen from entering the display area DA, so as to prevent the display effect from being affected.
  • the barrier 10 includes a single-sided barrier structure located between the display area DA and the peripheral area PA.
  • the blocking portion 10 includes a first blocking object 11 and a second blocking object 12 surrounding the first blocking object 11.
  • the first blocking object 11 includes a display area DA and a peripheral area PA.
  • the first blocking portion 111 and the second blocking portion 12 include a fourth blocking portion 121 located between the display area DA and the peripheral area PA. At this time, the first blocking portion 111 and the third blocking portion 121 constitute the single side Blocking structure.
  • the organic insulating structure 20 is disposed on the substrate SUB.
  • the organic insulating structure 20 includes a plurality of sub-insulating structures 21 stacked and arranged. A part of each sub-insulating structure 21 is located in the display area DA, and the other part is located in the peripheral area PA. For example, the sub-insulating structure 21 is located in The orthographic projection on the substrate SUB extends from the display area DA to between the display area DA and the barrier 10.
  • Each sub-insulating structure 21 has a first boundary E1, and for any two adjacent sub-insulating structures 21, the first boundary E1 of the sub-insulating structure 21 on the side away from the substrate SUB is greater than the first boundary E1 of the sub-insulating structure 21 on the side close to the substrate SUB.
  • the first boundary E1 is closer to the display area DA, thereby forming a step shape (see FIG. 4).
  • the distance d between the first boundary E1 of two adjacent sub-insulating structures 21 is greater than or equal to 20 ⁇ m.
  • FIG. 3 only enlarges the Q1 area in FIG. 2, but it should be understood that each first boundary E1 is not only It is only located in the Q1 area in FIG. 2, but corresponds to the entire lower edge of the display area DA in FIG. 2, that is, the first boundary E1 extends from the left end to the right end of the Q area in FIG. 2.
  • the organic insulating structure 20 not only forms the stepped morphology in FIG. 4 in the Q1 region, but also forms a stepped morphology in the entire Q region.
  • the touch electrode pattern is disposed on the side of the organic insulating structure 20 away from the substrate SUB.
  • the touch electrode pattern is configured to detect the occurrence of touch in the display area DA.
  • the touch electrode pattern includes the touch driving electrode TX and the touch sensing electrode TX shown in FIG. 2.
  • the touch signal line TL is arranged on the side of the organic insulating structure 20 away from the substrate SUB.
  • One end of the touch signal line TL is electrically connected to the touch electrode pattern, and the other end is connected to the pad area WA, thereby being connected to the pad area WA.
  • the contact pad PAD is electrically connected.
  • the orthographic projection of the portion of the touch signal line TL in the peripheral area PA on the substrate SUB intersects the first boundary E1 of each sub-insulating structure 21.
  • the touch signal line TL is located on a steep slope.
  • the distance d between the first boundary E1 of two adjacent sub-insulation structures 21 is small (for example, d is less than or equal to 5 ⁇ m)
  • the touch signal line TL is located on a steep slope.
  • the distance d between the first boundary E1 of two adjacent sub-insulating structures 21 is larger, so that the touch signal line TL is located relatively smoothly.
  • the distance d between the first boundary E1 of two adjacent sub-insulating structures 21 is between 25 ⁇ m and 60 ⁇ m, so as to reduce the residual conductive material as much as possible while reducing the frame of the display panel 100.
  • d is 30 ⁇ m, or 35 ⁇ m, or 40 ⁇ m, or 45 ⁇ m, or 50 ⁇ m.
  • the barrier 10 includes: a first barrier 11 and a second barrier 12.
  • the first barrier 11 is located in the peripheral area PA and surrounds the display area DA.
  • the second barrier 12 is located in the peripheral area PA and surrounds the first barrier 11, so as to further prevent external water vapor or oxygen from entering the display area DA, and provide double protection for the display area DA.
  • the vertical distance from the end of the first barrier 11 away from the substrate SUB to the substrate SUB is smaller than the vertical distance from the end of the second barrier 12 away from the substrate SUB to the substrate SUB, thereby prolonging the entry of external water vapor and oxygen into the display area DA. , Thereby improving the blocking ability of the blocking object 10.
  • the first barrier 11 includes a first barrier 111 and a second barrier 112, wherein the first barrier 111 is located on the side of the display area DA close to the bending area (ie, the first barrier 11 in FIG. 2 is located in the display area The portion extending laterally below DA), the second blocking portion 112 is the rest of the first blocking portion 11 except for the first blocking portion 111, and the second blocking portion 12 includes a third blocking portion 121 and a fourth blocking portion 122.
  • the third barrier 121 is located on the side of the display area DA close to the curved area (ie, the portion of the second barrier 12 that is located below the display area DA in FIG. 2 and extends laterally), and the fourth barrier 122 is in the second barrier 12 The rest except the third blocking part 121.
  • the first blocking portion 111 and the third blocking portion 113 constitute the aforementioned single-sided blocking structure.
  • the substrate SUB is a flexible substrate, which may be made of a flexible organic material.
  • the organic materials are resins such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. Material.
  • the substrate SUB also includes a bending area BA located between the peripheral area PA and the pad area WA. The bending area BA is configured to be bent along the bending axis BX.
  • the pad area WA can be located on the back side of the display panel 100 (wherein, the display side of the display panel 100 is the front side, and the side opposite to the display side is the back side or the back side), so that Improve space utilization and reduce the frame width of the display product.
  • the display area DA includes a plurality of pixel units P, and the pixel units P are defined by the intersection of the scan line GL and the data line DL.
  • the scan line GL is connected to the gate driving circuit in the peripheral area PA, and the data line DL may be connected to the contact pad PAD of the pad area WA through the data connection line.
  • Each pixel unit P is provided with a light emitting element 50 and a pixel circuit.
  • the light-emitting element 50 may be an organic light-emitting diode (OLED), and the organic light-emitting diode OLED may emit, for example, red light, green light, blue light, or white light.
  • FIG. 6 is an equivalent schematic diagram of the pixel circuit in some embodiments of the disclosure.
  • the pixel circuit includes: a driving transistor Td, a switching transistor Ts, and a storage capacitor Cs.
  • the gate of the switching transistor Ts is connected to the scan line GL ,
  • the first electrode is connected to the data line DL, and the second electrode is connected to the gate of the driving transistor Td.
  • Both ends of the storage capacitor Cs are respectively connected to the first power supply line VDD and the gate of the driving transistor Td.
  • the first electrode of the driving transistor Td is connected to the first power line VDD
  • the second electrode is connected to the first electrode of the light emitting element 50
  • the second electrode of the light emitting element 50 is connected to the second power line VSS.
  • each transistor can be a thin film transistor or a field effect tube or other devices with the same characteristics. Since the source and drain of the transistor used are symmetrical, there is no difference between the source and drain. In order to distinguish the source and drain of the transistor, one of the poles is referred to as the first pole, and the other pole is referred to as the second pole.
  • the first power line VDD is connected from the pad area WA to the display area DA so as to transmit the voltage signal to each pixel unit.
  • the second power line VSS includes a first part and a second part, wherein the first part is located in the peripheral area PA and surrounds the display area DA in an open loop manner.
  • the second portion of the second power supply line VSS is connected between the first portion and the contact pad PAD of the pad area WA. As shown in FIGS. 2 and 4, the orthographic projection of the first boundary E1 of each sub-insulating structure 21 on the substrate SUB overlaps with the orthographic projection of the second power line VSS on the substrate SUB.
  • the touch electrode pattern may adopt a mutual capacitance type structure or a self-capacitance type structure.
  • the embodiments of the present disclosure take a mutual capacitance type structure as an example for description.
  • the touch electrode pattern includes a plurality of touch driving electrodes TX and a plurality of touch sensing electrodes RX.
  • the touch driving electrodes TX and the touch sensing electrodes RX are arranged to cross each other.
  • the touch driving electrodes TX and the touch sensing The intersection of the electrodes RX is insulated and separated by the touch insulating layer TLD.
  • FIG. 7 is a cross-sectional view along the line BB' in FIG. 2. As shown in FIG. 2 and FIG.
  • the touch driving electrode TX includes: a plurality of driving electrode units TX1 arranged along a first direction and connected to the driving electrode unit TX1
  • the touch sensing electrode RX includes a plurality of sensing electrode units RX1 and a bridge portion RX2 connected between the sensing electrode units, wherein the first direction and the second direction intersect, for example, the first direction is The up-down direction in FIG. 2 and the second direction are the left-right direction in FIG. 2.
  • the driving electrode unit TX1, the connecting portion TX2, and the sensing electrode unit RX1 are all located on the side of the touch insulating layer TLD away from the substrate SUB, and the driving electrode unit TX1, the connecting portion TX2, and the sensing electrode unit RX1 can be arranged in the same layer, and the bridge portion RX2 is located
  • the touch insulating layer TLD is close to the side of the substrate SUB.
  • the bridge portion RX2 and the connection portion TX2 are arranged across and separated by the touch insulating layer TLD.
  • the sensing electrode unit RX1 is connected to the bridge portion RX2 through the via hole on the touch insulating layer TLD. It should be noted that the touch driving electrodes TX and the touch sensing electrodes RX shown in FIG.
  • the bridge portion RX2 may be located on the side of the touch insulation layer TLD away from the substrate SUB, and the connection portion may be located on the side of the touch insulation layer TLD close to the substrate SUB.
  • the adjacent drive electrode units TX1 are connected by bridge portions provided in different layers, and the adjacent sensing electrode units RX1 are connected by the same layer connection portions.
  • each touch driving electrode TX and touch sensing electrode RX can be connected to a touch driving line TL correspondingly.
  • the touch signal line TL passes through the peripheral area PA, the orthographic projection of the portion of the touch signal line TL in the peripheral area PA on the substrate SUB crosses the first boundary E1 of each sub-insulating structure 21.
  • the touch insulating layer TLD also covers at least the peripheral area PA between the display area DA and the pad area WA, and the touch signal line TL in the peripheral area PA between the display area DA and the pad area WA is located On the touch insulation layer TLD.
  • the thickness of the touch insulating layer TLD is between 0.2 ⁇ m and 0.5 ⁇ m, for example, 0.3 ⁇ m or 0.33 ⁇ m or 0.35 ⁇ m.
  • the touch signal line TL has a double-layer structure, which includes a first transmission portion TL1 and a second transmission portion TL2.
  • the first transmission portion TL1 is located on the touch insulating layer TLD close to the substrate SUB.
  • the second transmission portion TL2 is located on the side of the touch insulating layer TLD away from the substrate SUB.
  • the second transmission portion TL2 is electrically connected to the first transmission portion TL1 through a via hole penetrating the touch insulating layer TLD.
  • FIG. 4 only illustrates one via, but in fact, multiple vias can be provided in other positions.
  • the second transmission portion TL2 is connected in parallel with the first transmission portion TL1 through a plurality of via holes.
  • the first transmission portion TL1 may be provided on the same layer as the bridge portion RX2
  • the second transmission portion TL2 may be provided on the same layer as the driving electrode unit TX1, the connecting portion TX2, and the sensing electrode unit RX1.
  • the first buffer layer BFL1 is disposed on the substrate SUB to prevent or reduce the diffusion of metal atoms and/or impurities from the substrate SUB into the active layer of the transistor.
  • the first buffer layer BFL1 may expose the upper surface of the substrate SUB at a part of the bending area BA, so as to facilitate the bending of the substrate SUB.
  • the first buffer layer BFL1 may include an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), and/or silicon oxynitride (SiON), and may be formed as a multilayer or a single layer.
  • the semiconductor layer is provided on the first buffer layer BFL1.
  • the material of the semiconductor layer may include, for example, inorganic semiconductor materials (for example, polysilicon, amorphous silicon, etc.), organic semiconductor materials, and oxide semiconductor materials.
  • the semiconductor layer includes the active layer 31 of each transistor 30.
  • the active layer 31 includes a channel portion and a source connection portion and a drain connection portion located on both sides of the channel portion.
  • the source connection portion is connected to the source 33 of the transistor 30.
  • the drain connection part is connected to the drain 34 of the transistor 30.
  • Both the source connection portion and the drain connection portion may be doped with impurities having a higher impurity concentration than the channel portion (for example, N-type impurities or P-type impurities).
  • the channel part is directly opposite to the gate 32 of the transistor 30. When the voltage signal loaded by the gate 32 reaches a certain value, a carrier path is formed in the channel part to make the source 33 and the drain 34 of the transistor 30 conductive. .
  • the first gate insulating layer GI1 is disposed on the semiconductor layer, wherein the first gate insulating layer GI1 may expose the upper surface of the substrate SUB at a part of the bending area BA, so as to facilitate the bending of the substrate SUB.
  • the material of the first gate insulating layer GI1 may include silicon compound and metal oxide.
  • the material of the first gate insulating layer GI1 includes silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx) , Aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc.
  • the first gate insulating layer GI1 may be a single layer or multiple layers.
  • the first gate electrode layer G1 is disposed on the first gate insulating layer GI1.
  • the first gate electrode layer G1 includes the gate 32 of each transistor 30 and the first electrode plate 41 of the capacitor 40.
  • the material of the first gate electrode layer G1 may include, for example, metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, and the like.
  • the first gate electrode layer G1 may include gold (Au), gold alloy, silver (Ag), silver alloy, aluminum (Al), aluminum alloy, aluminum nitride (AlNx), tungsten (W), nitrogen Tungsten (WNx), copper (Cu), copper alloys, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), molybdenum alloys, titanium (Ti), titanium nitride ( TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), oxide Indium (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc.
  • the first gate electrode layer G1 may have a single layer or multiple
  • the second gate insulating layer GI2 is disposed on the first gate electrode layer G1, and the second gate insulating layer GI2 may expose the upper surface of the substrate SUB at a part of the bending area BA.
  • the material of the second gate insulating layer GI2 may include, for example, silicon compound, metal oxide.
  • the material of the second gate insulating layer GI2 may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx).
  • the second gate insulating layer GI2 may be formed as a single layer or multiple layers.
  • the second gate electrode layer G2 is disposed on the second gate insulating layer GI2.
  • the second gate electrode layer G2 may include the second electrode plate 42 of the capacitor 40.
  • the material of the second gate electrode layer G2 may include, for example, metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, and the like.
  • the gate electrode layer may include gold (Au), gold alloy, silver (Ag), silver alloy, aluminum (Al), aluminum alloy, aluminum nitride (AlNx), tungsten (W), tungsten nitride ( WNx), copper (Cu), copper alloys, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), molybdenum alloys, titanium (Ti), titanium nitride (TiNx), Platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx) ), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc.
  • the second gate electrode layer G2 may have
  • the interlayer insulating layer ILD is disposed on the second gate electrode layer G2, and the interlayer insulating layer ILD may expose the upper surface of the substrate SUB at a part of the bending area BA.
  • the material of the interlayer insulating layer ILD may include, for example, silicon compound, metal oxide, and the like. Specifically, the silicon compounds and metal oxides listed above can be selected, which will not be repeated here.
  • the first source-drain conductive layer SD1 is disposed on the interlayer insulating layer ILD.
  • the first source-drain conductive layer SD1 may include a source 33 and a drain 34 of each transistor in the display area DA, the source 33 is electrically connected to the source connection part, and the drain 34 is electrically connected to the drain connection part.
  • the first source-drain conductive layer SD1 may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc., for example, the first source-drain conductive layer SD1 may be a single layer or multiple layers of metal, such as Mo /Al/Mo or Ti/Al/Ti.
  • the transistor 7 includes a gate 32, a source 33, a drain 34, and an active layer 31.
  • the transistor 30 shown in FIG. 7 may be the driving transistor Td of the pixel circuit shown in FIG. Yes, when the pixel circuit adopts other circuit structures, it is not necessarily the driving transistor Td that is directly connected to the light-emitting element 50. In this case, the transistor shown in FIG. 7 does not necessarily correspond to the driving transistor Td.
  • the first source-drain conductive layer SD1 may further include a first power supply line VDD and a second power supply line VSS.
  • the passivation layer PVX is disposed on the first source-drain conductive layer SD1, and the passivation layer PVX may expose the surface of the substrate SUB at a part of the bent portion BA.
  • the material of the passivation layer PVX may include a silicon compound, for example, silicon oxide, silicon nitride, or silicon oxynitride.
  • the plurality of sub-insulating structures 21 of the organic insulating structure 20 includes: a first planarization layer PLN1, a second planarization layer PLN2, and a pixel defining layer PDL.
  • the first planarization layer PLN1, the second planarization layer PLN2, and the pixel defining layer PDL all include a portion located in the display area DA and a portion located between the display area DA and the barrier 10.
  • the second planarization layer PLN2 is located on the side of the first planarization layer PLN1 away from the substrate SUB.
  • the pixel defining layer PDL is located on a side of the second planarization layer PLN2 away from the substrate SUB.
  • the above-mentioned first buffer layer BFL1, semiconductor layer, first gate insulating layer GI1, first gate electrode layer G1, second gate insulating layer GI2, second gate electrode layer G2, interlayer insulating layer ILD, and first source-drain conductive layer SD1 and the passivation layer PVX are both located between the first planarization layer PLN1 and the substrate SUB.
  • the surface of the first planarization layer PLN1 away from the substrate SUB is substantially flat.
  • the first planarization layer PLN1 is made of an organic insulating material, for example, the organic insulating material includes polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, silicon Resin materials such as oxane.
  • the organic insulating material includes elastic materials, such as urethane, thermoplastic polyurethane (TPU), and the like.
  • the thickness of the first planarization layer PLN1 and the second planarization layer PLN2 are both between 1 ⁇ m and 2 ⁇ m.
  • the thickness of the first planarization layer PLN1 and the second planarization layer PLN2 are both 1.6 ⁇ m.
  • the thickness of the pixel defining layer PDL is between 1.5 ⁇ m and 3 ⁇ m, for example, 2 ⁇ m.
  • the second source-drain conductive layer SD2 is disposed on the first planarization layer PLN1.
  • the second source-drain conductive layer SD2 may include the via electrode 60 located in the display area DA.
  • the transfer electrode 60 is electrically connected to the drain 34 through a via hole that penetrates the first planarization layer PLN1 and the passivation layer PVX, and at the same time, the transfer electrode 60 is also connected to the light-emitting element through a via hole that penetrates the second planarization layer PLN2.
  • the first electrode 51 of 50 is electrically connected.
  • the via electrode 60 can avoid directly forming via holes with relatively large diameters in the first planarization layer PLN1 and the second planarization layer PLN2, thereby improving the quality of the electrical connection of the vias.
  • the material of the second source-drain conductive layer SD2 may include metal, alloy, metal nitride, conductive metal oxide, or transparent conductive material, etc., for example, the second source-drain conductive layer SD2 may be a single layer or multiple layers of metal, such as It is Mo/Al/Mo or Ti/Al/Ti.
  • the material of the second source-drain conductive layer SD2 may be the same as or different from the material of the first source-drain conductive layer SD1.
  • the second planarization layer PLN2 is disposed on the second source-drain conductive layer SD2, the second planarization layer PLN2 covers the transfer electrode, and the upper surface of the second planarization layer PLN2 is substantially flat. It may have a substantially flat upper surface.
  • the second planarization layer PLN2 is made of an organic insulating material, for example, the organic insulating material includes polyimide, epoxy, acrylic, polyester, photoresist, polyacrylate, polyamide, silicon Resin materials such as oxane.
  • the organic insulating material includes elastic materials, such as urethane, thermoplastic polyurethane (TPU), and the like.
  • the material of the second planarization layer PLN2 may be the same as or different from the material of the first planarization layer PLN1.
  • the first electrode layer is disposed on the second planarization layer PLN2, where the first electrode layer includes a plurality of first electrodes, and the first electrode may be an anode of the light emitting element 50.
  • the light-emitting element 50 includes a first electrode 51, a light-emitting layer 53, and a second electrode 52, and the first electrode 51 is disposed on the second planarization layer PLN2.
  • the first electrode 51 is electrically connected to the transfer electrode 60 through a via hole penetrating the second planarization layer PLN2, and is further electrically connected to the drain 34 of the transistor 30.
  • the first electrode 51 may be made of materials such as metals, metal alloys, metal nitrides, conductive metal oxides, and transparent conductive materials.
  • the first electrode 51 may have a single-layer or multi-layer structure.
  • the pixel defining layer PDL is disposed on the second planarization layer PLN2.
  • the pixel defining layer PDL includes pixel openings corresponding to the pixel units one-to-one, and the pixel openings expose a part of the corresponding first electrode 51.
  • the light-emitting layers 54 are arranged in the pixel openings in a one-to-one correspondence.
  • the light-emitting layers 54 may include small molecular organic materials or polymer molecular organic materials, may be fluorescent light-emitting materials or phosphorescent light-emitting materials, and may emit red light, green light, blue light, or Can be white light.
  • the material of the pixel defining layer PDL may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenol resin.
  • spacers (not shown in FIG. 7) may be provided on the pixel defining layer PDL, and the material of the spacers and the material of the pixel defining layer PDL may be the same.
  • the second electrode 52 is located on the side of the light-emitting layer 53 away from the substrate SUB.
  • the second electrode 52 can be made of metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, or the like.
  • the light emitting element 50 may adopt a top emission type structure or a bottom emission type structure.
  • the first electrode 51 includes a conductive material with light reflection performance or includes a light reflection film
  • the second electrode 52 includes a transparent or semi-transparent conductive material.
  • the second electrode 52 is made of a conductive material with light reflective properties or includes a light reflective film
  • the first electrode 51 includes a transparent or semi-transparent conductive material.
  • the second electrode 52 of the light-emitting element 50 of each pixel unit may be connected as a whole to form a second electrode layer.
  • the light-emitting element 50 may also include other film layers.
  • it may also include: a hole injection layer and a hole transport layer between the first electrode 51 and the light-emitting layer 53, and a hole between the light-emitting layer 53 and the light-emitting layer 53.
  • the display panel 100 further includes an encapsulation layer EPL.
  • the encapsulation layer EPL is disposed on the pixel definition layer PDL.
  • the encapsulation layer EPL covers the pixel definition layer PDL and the light-emitting element 50, and is used to encapsulate the light-emitting element 50.
  • the encapsulation layer EPL includes a first inorganic encapsulation layer CVD1, a second inorganic encapsulation layer CVD2, and an organic encapsulation layer IJP.
  • the second inorganic encapsulation layer CVD2 is located on the side of the first inorganic encapsulation layer CVD1 away from the substrate SUB,
  • the organic encapsulation layer IJP is located between the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2.
  • the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 extend to the peripheral area PA and cover the barrier 10; the organic encapsulation layer IJP extends to the peripheral area PA and is located in the range surrounded by the barrier 10.
  • Both the first inorganic packaging layer CVD1 and the second inorganic packaging layer CVD2 can be made of highly dense inorganic materials such as silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx) and the like.
  • the organic encapsulation layer IJP can be made of a polymer material containing a desiccant, or a polymer material that can block water vapor.
  • the use of polymer resin can relieve the stress of the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2, and can also include water-absorbing materials such as desiccant to absorb substances such as water and oxygen that have penetrated into the interior.
  • the thicknesses of the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 are both between 0.5 ⁇ m and 1.5 ⁇ m.
  • the thickness of the first inorganic encapsulation layer CVD1 is 1.0 ⁇ m
  • the thickness of the second inorganic encapsulation layer CVD2 is 0.6 ⁇ m.
  • the thickness of the organic encapsulation layer IJP in the display area DA is between 5 ⁇ m and 10 ⁇ m, for example, 8 ⁇ m, or 7 ⁇ m, or 9 ⁇ m.
  • the second buffer layer BFL2 is disposed on the encapsulation layer EPL, and the second buffer layer BFL2 is located in the display area DA and extends to the peripheral area PA to cover the encapsulation layer EPL.
  • the second buffer layer BFL2 can be made of the same material as the aforementioned first buffer layer BFL1, which will not be repeated here.
  • the touch electrode pattern is located on the side of the packaging layer EPL away from the substrate SUB, the bridge portion RX2 of the touch electrode pattern is provided on the packaging layer EPL, and the touch insulating layer TLD is located on the side of the packaging layer EPL away from the substrate SUB, and covers the bridge portion RX2, the touch driving electrode TX and the sensing electrode unit RX1 of the touch sensing electrode RX are located on the touch insulating layer TLD.
  • both the driving electrode unit TX1 and the sensing electrode unit RX1 adopt structures with good light transmittance.
  • it is made of a transparent conductive material (such as indium tin oxide), or a metal mesh structure is used.
  • the touch electrode pattern and the touch insulating layer TLD are both located on the side of the packaging layer EPL away from the substrate SUB, and the bridge portion RX2 in the touch electrode pattern is located between the touch insulating layer TLD and the packaging layer EPL.
  • the bridge portion RX2 and the first transmission portion TL1 are both located between the touch insulating layer TLD and the second buffer layer BFL2.
  • FIG. 4 there is an interval between the first boundary of each sub-insulating structure 21 and the single-sided barrier structure, that is, each sub-insulating structure 21 does not contact the single-sided barrier structure.
  • a groove is formed between the organic insulating structure 20 and the single-sided barrier structure.
  • FIG. 5 is a schematic diagram of the groove between the organic insulating structure and the single-sided barrier structure in some embodiments of the disclosure.
  • the orthographic projection of the encapsulation layer EPL on the substrate SUB simultaneously covers the orthographic projection of the organic insulating structure 20 on the substrate SUB, the orthographic projection of the groove V1 on the substrate SUB, and the single-sided barrier structure on the substrate Orthographic projection on SUB.
  • the overcoat layer OC is disposed on the side of the touch electrode pattern away from the substrate SUB.
  • the overcladding layer OC extends from the display area DA to the peripheral area PA, and the overcladding layer OC can protect the touch signal line TL in the peripheral area PA.
  • the material of the overcoat layer OC may include an inorganic insulating material or an organic insulating material.
  • the flexible substrate SUB of the embodiment of the present disclosure is provided with a first gate insulating layer GI1, a second gate insulating layer GI2, a first buffer layer BFL1, and a second buffer layer BFL2.
  • a first gate insulating layer GI1 a second gate insulating layer GI2
  • a first buffer layer BFL1 a first buffer layer BFL2
  • a second buffer layer BFL2 a second buffer layer BFL2.
  • FIG. 8 is a cross-sectional view taken along the line D-D' in FIG. 2, in which, in order to illustrate the structure of the barrier 10 concisely and clearly, FIG. 8 only shows the cross-sectional structure of the barrier 10 and the first inorganic structure on the barrier 10.
  • the encapsulation layer and the second inorganic encapsulation layer As shown in FIG. 2, FIG. 4, and FIG. 8, the first barrier portion 111, the second barrier portion 112, the third barrier portion 113, and the fourth barrier portion 114 all include a first barrier layer 11a and a first barrier layer 11a located thereon.
  • the second barrier layer 11b above wherein the first barrier layer 11a and the second planarization layer PLN2 are provided in the same layer and have the same material, and the second barrier layer 11b and the pixel defining layer PDL are provided in the same layer and have the same material.
  • the third barrier portion 121 further includes a third barrier layer 11c, and the third barrier layer 11c is provided in the same layer as the first planarization layer PLN1 and has the same material.
  • the second barrier portion 112 includes a first barrier layer 11a, a second barrier layer 11b, and a fourth barrier layer 11d.
  • the fourth barrier layer 11d is the same as the spacer on the pixel defining layer PDL. The layers are set up and the materials are the same.
  • the fourth barrier portion 122 includes a first barrier layer 11a, a second barrier layer 11b, a third barrier layer 11c, and a fourth barrier layer 11d.
  • the "same-layer arrangement" in the embodiments of the present disclosure means that the two structures are formed from the same material layer through a patterning process, so the two structures are in the same layer in the stacking relationship; But this does not mean that the distance between the two and the substrate SUB must be the same.
  • the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 in the encapsulation layer EPL both extend to the first barrier 11 and the second barrier 12.
  • the peripheral area PA of the substrate SUB includes a first fan-out area FA1.
  • the first fan-out area FA1 is located between the display area DA and the bending area BA.
  • the fan-out area FA1 and the bending area BA extend to the pad area WA.
  • the substrate SUB also includes a second fan-out area FA2.
  • the second fan-out area FA2 is located between the bending area BA and the pad area WA and adjacent to the bending area BA, that is, the second fan-out area FA2 and the bending area BA are adjacent to each other. Direct connection, there is no other area between the two areas.
  • test area DTA a test area DTA, a control circuit area CCA, a third fan-out area FA3, and an integrated circuit area IC are also provided between the second fan-out area of the substrate SUB and the pad area WA.
  • the test area DTA is configured to be connected to an external test device to detect the disconnection of the picture, the bending area BA, and the like.
  • the control circuit area CCA includes a selector MUX for switching between the input circuit and the output circuit.
  • a display panel including: a substrate, a barrier, an organic insulating structure, a touch electrode pattern, and a touch signal line.
  • the substrate includes a display area, a peripheral area, and a pad area, the peripheral area surrounds the display area, and the pad area is located on a side of the peripheral area away from the display area.
  • a barrier is disposed on the substrate, the barrier is located in the peripheral area and surrounds the display area, and the barrier includes a single-sided barrier structure located between the display area and the pad area.
  • the organic insulating structure is disposed on the substrate, and a part of the organic insulating structure is located in the display area, and the other part is located in the peripheral area.
  • FIG. 9 is a cross-sectional view taken along the line A-A' in FIG. 3 in some other embodiments of the present disclosure
  • FIG. 10 is one of the structural schematic diagrams of the organic insulating structure in FIG. 9
  • FIG. 11 is the structure of the organic insulating structure in FIG. 9 Diagram two.
  • the organic insulating structure 20 has a bottom surface BS facing the substrate SUB, a top surface TS opposite to the bottom surface BS, and connected between the bottom surface BS and the top surface TS and facing the single side
  • the first side surface LS of the blocking structure is a slope surface, and the slope angle of the slope surface is between 0° and 40°.
  • the “slope surface” here refers to a surface gradually approaching the display area DA in a direction away from the substrate SUB.
  • the slope surface can be an inclined plane (as shown in FIG. 10) or an inclined arc surface (as shown in FIG. 11).
  • the slope angle refers to the angle ⁇ 1 between the slope surface and the bottom surface BS of the organic insulating structure 20; when the slope surface is a curved surface, the slope angle refers to the tangent of the curved surface and the organic insulation The maximum value ⁇ 2 of the included angle between the bottom surfaces BS of the structure 20.
  • the slope surface is not only located in the Q1 area, but extends from the left end to the right end of the Q area.
  • the touch electrode pattern (that is, the pattern including the touch driving electrode TX and the touch sensing electrode RX in FIG. 2) is disposed on the side of the organic insulating structure 20 away from the substrate SUB.
  • the touch signal line TL is disposed on a side of the organic insulating structure 20 away from the substrate SUB.
  • One end of the touch signal line TL is electrically connected to the touch electrode pattern, and the other end is connected to the pad area WA.
  • the orthographic projection of the portion of the touch signal line TL in the peripheral area PA on the substrate SUB passes through the orthographic projection of the slope surface on the substrate SUB.
  • the slope angle of the slope surface is between 25° and 35°, so as to reduce the residual conductive material and prevent the frame of the display product from being too wide.
  • the slope angle is 28° or 29° or 30° or 31° or 32°.
  • the organic insulating structure 20 includes a plurality of sub-insulating structures 21 stacked in layers, and the plurality of sub-insulating structures 21 include: a first planarization layer PLN1, a second planarization layer PLN2, and a pixel defining layer PDL.
  • the first planarization layer PLN1 is provided on the substrate SUB.
  • the second planarization layer PLN2 is located on a side of the first planarization layer PLN1 away from the substrate SUB.
  • the pixel defining layer PDL is located on a side of the second planarization layer PLN2 away from the substrate SUB.
  • the organic insulating structure 20 is also provided with an encapsulation layer EPL, a second buffer layer BFL2, and a touch insulating layer TLD.
  • the encapsulation layer EPL includes a first inorganic encapsulation layer CVD1, a second inorganic encapsulation layer CVD2, and an organic encapsulation layer IJP.
  • the second inorganic packaging layer CVD2 is located on the side of the first inorganic packaging layer CVD1 away from the substrate SUB; the organic packaging layer IJP is located between the first inorganic packaging layer CVD1 and the second inorganic packaging layer CVD2.
  • the touch electrode pattern includes touch drive electrodes TX and The touch sensing electrode RX, the touch driving electrode TX and the touch sensing electrode RX are arranged crosswise, and the intersection of the touch driving electrode TX and the touch sensing electrode RX is insulated and separated by the touch insulating layer TLD. Both the touch driving electrode TX and the touch sensing electrode RX are electrically connected to a touch signal line TL.
  • the touch signal line TL includes a first transmission portion TL1 and a second transmission portion TL2.
  • the first transmission portion TL1 is located between the touch insulating layer TLD and the packaging layer EPL, and the second transmission portion TL2 is located on the touch insulating layer TLD away from the substrate SUB.
  • the second transmission portion TL2 is electrically connected to the first transmission portion TL1 through a via hole penetrating the touch insulating layer TLD.
  • the touch electrode pattern and the touch signal line TL are both located on the side of the packaging layer EPL away from the substrate SUB.
  • first side surface LS and the single-sided barrier structure There is a space between the first side surface LS and the single-sided barrier structure. For example, there is a space between an end of the first side surface LS close to the substrate SUB and an end away from the substrate SUB and the single-sided barrier structure.
  • a groove is formed between the organic insulating structure 20 and the single-sided barrier structure, and the orthographic projection of the encapsulation layer EPL on the substrate SUB simultaneously covers the orthographic projection of the organic insulating structure 20 on the substrate SUB and the orthographic projection of the groove on the substrate SUB.
  • the orthographic projection of the single-sided barrier structure on the substrate SUB, the single-sided barrier structure is located between the substrate SUB and the packaging layer EPL.
  • the display area DA includes a plurality of pixel units, and each pixel unit is provided with a light-emitting element 50.
  • the display panel 100 further includes a second power line VSS.
  • the second power line VSS is electrically connected to the light-emitting element 50, wherein the second power line VSS Located between the organic insulating structure 20 and the substrate SUB, the orthographic projection of the first side surface LS on the substrate SUB overlaps with the orthographic projection of the second power line VSS on the substrate SUB.
  • the barrier 10 includes a first barrier 11 and a second barrier 12.
  • the first barrier 11 is located in the peripheral area PA and surrounds the display area DA
  • the second barrier 12 is located in the peripheral area PA and surrounds the first barrier 11.
  • the substrate SUB is also provided with a first buffer layer BFL1, a semiconductor layer, a first gate insulating layer GI1, a first gate electrode layer G1, a second gate insulating layer GI2, an interlayer insulating layer ILD, a first source-drain conductive layer SD1,
  • a first buffer layer BFL1 a semiconductor layer
  • a first gate insulating layer GI1 a first gate electrode layer G1, a second gate insulating layer GI2, an interlayer insulating layer ILD
  • a first source-drain conductive layer SD1 For the structure of the passivation layer PVX, the second source-drain conductive layer SD2, and the like, the structure and position of each film layer can be referred to the description in the foregoing embodiment, and will not be repeated here.
  • the substrate SUB in this embodiment is a flexible substrate, which also includes the bending area BA between the peripheral area PA and the pad area WA, and also includes other areas such as the test area DTA and the control circuit area CCA.
  • the first side surface of the organic insulating structure 20 is a sloped surface with a relatively small slope. Therefore, when the touch signal line is made by an etching process in the subsequent process, the residue of conductive materials can be reduced, thereby reducing Or to prevent a short circuit between the touch signal lines TL.
  • the embodiment of the present disclosure also provides a display panel, which includes a substrate, a barrier, an organic insulating structure, a touch electrode pattern, and a touch signal line.
  • the substrate includes a display area, a peripheral area, and a pad area, the peripheral area surrounds the display area, and the pad area is located on a side of the peripheral area away from the display area.
  • the barrier is disposed on the substrate, the barrier is located in the peripheral area and surrounds the display area, and the barrier includes a single-sided barrier between the display area and the pad area. structure.
  • An organic insulating structure is arranged on the substrate, and the organic insulating structure includes a plurality of sub-insulating structures stacked and arranged, a part of each sub-insulating structure is located in the display area, and the other part is located in a peripheral area.
  • Each of the sub-insulating structures has a first boundary between the display area and the one-sided barrier structure. Except for the sub-insulating structure furthest away from the substrate SUB, each of the remaining sub-insulating structures is It includes a protruding part, wherein, for any two adjacent sub-insulating structures, the protruding part of the sub-insulating structure close to the substrate SUB is located at the first boundary of the sub-insulating structure far away from the substrate SUB and the Between unilateral barrier structures.
  • the touch electrode pattern is arranged on a side of the organic insulating structure away from the substrate and located in the display area.
  • the touch signal line is arranged on the side of the organic insulating structure away from the substrate. One end of the touch signal line is electrically connected to the touch electrode pattern, and the other end is connected to the pad area.
  • the orthographic projection of the portion of the control signal line in the peripheral area on the substrate overlaps the orthographic projection of the extension of each sub-insulating structure on the substrate.
  • the sub-insulating structure having the extension portion is formed by performing a patterning process on an organic material layer using a two-tone mask, wherein when the patterning process is performed, the area where the extension portion is to be formed corresponds to In the semi-transmissive area of the two-tone mask.
  • the plurality of sub-insulating structures of the organic insulating structure include: a first planarization layer, a second planarization layer, and a pixel defining layer.
  • the first planarization layer is disposed on the substrate; the second planarization layer is located on a side of the first planarization layer away from the substrate; the pixel defining layer is located on the second planarization layer away from the substrate One side of the substrate.
  • Figures 12 to 14 are schematic diagrams of the manufacturing process of one of the sub-insulating structures with extensions provided by some embodiments of the present disclosure. The following takes one of the sub-insulating structures with extensions as an example to introduce the manufacturing process .
  • the sub-insulating structure may be a first planarization layer or a second planarization layer.
  • an organic insulating material layer 210 is formed, where the organic insulating material layer 210 is a light-sensitive organic material layer, such as a positive photoresist.
  • a two-tone mask M is used to expose the photoresist layer.
  • the two-tone mask M is a gray-tone mask or a half-tone mask.
  • the two-tone mask M includes a fully transparent area M1, an opaque area M3, and a semi-transmissive area M2.
  • the light transmittance of the semi-transmissive area M2 is less than the light transmittance of the fully transparent area M1.
  • the semi-transmissive area M2 of the two-tone mask M is corresponding to the area where the protrusion is to be formed, and the two-tone mask M
  • the full light-transmitting area M1 corresponds to the area where the organic insulating material layer 210 needs to be completely removed
  • the opaque area M3 of the two-tone mask M corresponds to other areas.
  • the part of the organic insulating material layer 210 corresponding to the opaque area is not exposed, the part of the organic insulating material layer 210 corresponding to the fully transparent area is completely exposed, and the part of the organic insulating material layer 210 corresponding to the semi-transparent area is completely exposed.
  • the corresponding part of the zone is partially exposed.
  • the organic insulating material layer 210 is developed, so that the part of the organic insulating material layer 210 corresponding to the full light-transmitting area M1 is completely removed, and the part corresponding to the partially light-transmitting area M2 is removed.
  • the corresponding part is completely retained, and the formed pattern is the sub-insulating structure 21, as shown in FIG. 14.
  • the part of the sub-insulating structure 21 corresponding to the partial light-transmitting area M2 is the extension part 21a, and the surface of the extension part 21a is a gentle slope surface.
  • negative photoresist may also be used.
  • the pattern of the mask used is complementary to the pattern of the two-tone mask M described above.
  • the sub-insulating structure 21 with the extension 21a is made by patterning the organic material layer 210 using a two-tone mask. During exposure, the area where the extension 21a is to be formed is the same as the two-tone mask.
  • the semi-transmissive area M2 of the diaphragm M corresponds to, so that the formed extension 21a can have a slope surface. Therefore, the overall side surface of the organic insulating structure 20 is relatively gentle.
  • the touch signal line is subsequently manufactured through an etching process, It can reduce the residue of conductive objects, thereby reducing or preventing short circuits between touch signal lines.
  • the structure and material of the barrier 20, the structure and material of the pixel defining layer PDL, the structure and material of the first planarization layer PLN1, and the structure and material of the second planarization layer PLN2 can all be referred to in the foregoing embodiment. Description, I won’t repeat it here.
  • an encapsulation layer and a touch insulating layer are also provided on the organic insulating structure.
  • the display area of the substrate may also be provided with a light-emitting element, and the light-emitting element is connected to the second power line.
  • the specific structure and material of the encapsulation layer, the arrangement and material of the touch insulating layer, the structure and material of the light-emitting element, the arrangement of the second power line and the touch signal line can all be referred to the description in the above-mentioned embodiment, and neither is here. Go into details again.
  • An embodiment of the present disclosure also provides a display device, which includes the display panel of any one of the foregoing embodiments.
  • the display device can be any product or component with a display function, such as an OLED panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种显示面板（100）和显示装置，显示面板（100）包括：基板（SUB），基板（SUB）包括：显示区（DA）、外围区（PA）和焊盘区（WA），焊盘区（WA）位于所述外围区（PA）远离显示区（DA）的一侧；至少一个阻挡物（10），阻挡物（10）位于外围区（PA）中且环绕显示区（DA），阻挡物（10）包括位于显示区（DA）与焊盘区（WA）之间的单侧阻挡结构；有机绝缘结构（20），有机绝缘结构（20）包括层叠设置的多个子绝缘结构（21），子绝缘结构（21）的一部分位于显示区（DA），每个子绝缘结构（21）具有位于显示区（DA）与单侧阻挡结构之间的第一边界（E1），对于任意相邻的两个子绝缘结构（21），远离基板（SUB）一侧的所述子绝缘结构（21）的第一边界（E1）比靠近基板（SUB）一侧的子绝缘结构（21）的第一边界（E1）更靠近显示区（DA）；任意相邻两个子绝缘结构（21）的第一边界（E1）之间的间距大于或等于20μm；触控电极图形；触控信号线（TL）。

Description

显示面板和显示装置 技术领域
本公开涉及显示技术领域，具体涉及一种显示面板和显示装置。
背景技术
随着有机发光二极管(Organic Light Emitting Display，OLED)显示技术的发展，OLED显示装置得到广泛应用。为了满足用户对于产品厚度及触控体验的需求，在一种生产工艺中，将触控功能层制作在OLED显示面板的封装层上。
发明内容
本公开实施例提供一种显示面板和显示装置。
根据本公开的第一方面，提供一种显示面板，包括：
基板，包括显示区、外围区和焊盘区，所述外围区环绕所述显示区，所述焊盘区位于所述外围区远离所述显示区的一侧；
至少一个阻挡物，设置在所述基板上，所述阻挡物位于所述外围区中且环绕所述显示区，所述阻挡物包括位于所述显示区与所述焊盘区之间的单侧阻挡结构；
有机绝缘结构，设置在所述基板上，所述有机绝缘结构包括层叠设置的多个子绝缘结构，所述多个子绝缘结构中的每个子绝缘结构的一部分位于所述显示区，所述多个子绝缘结构中的每个子绝缘结构具有位于所述显示区与所述单侧阻挡结构之间的第一边界，其中，对于任意相邻的两个所述子绝缘结构，远离所述基板一侧的所述子绝缘结构的第一边界比靠近所述基板一侧的所述子绝缘结构的第一边界更靠近所述显示区；任意相邻两个所述子绝缘结构的第一边界之间的间距大于或等于20μm；
触控电极图形，设置在所述有机绝缘结构远离所述基板的一侧；
触控信号线，设置在所述有机绝缘结构远离所述基板的一侧，所述触控信号线的一端与所述触控电极图形电连接，另一端连接至所 述焊盘区，所述触控信号线在所述外围区的部分在所述基板上的正投影与每个所述子绝缘结构的第一边界相交。
在一些实施例中，任意相邻两个所述子绝缘结构的第一边界之间的间距在25μm～60μm之间。
在一些实施例中，所述有机绝缘结构的多个所述子绝缘结构包括：
第一平坦化层，设置在所述基板上；
第二平坦化层，位于所述第一平坦化层远离所述基板的一侧；
像素界定层，位于所述第二平坦化层远离所述基板的一侧。
在一些实施例中，所述子绝缘结构的第一边界与所述单侧阻挡结构之间具有间隔。
在一些实施例中，所述显示面板还包括：封装层，设置在所述有机绝缘结构远离所述基板的一侧；其中，所述触控电极图形和所述触控信号线均位于所述封装层远离所述基板的一侧。
在一些实施例中，所述封装层包括：
第一无机封装层；
第二无机封装层，位于所述第一无机封装层远离所述基板的一侧；
有机封装层，位于所述第一无机封装层和所述第二无机封装层之间。
在一些实施例中，所述有机绝缘结构与所述单侧阻挡结构之间形成凹槽，所述封装层在所述基板上的正投影同时覆盖所述有机绝缘结构在所述基板上的正投影、所述凹槽在所述基板上的正投影和所述单侧阻挡结构在所述基板上的正投影，所述单侧阻挡结构位于所述基板与所述封装层之间。
在一些实施例中，所述显示面板还包括：触控绝缘层，设置在所述封装层远离所述基板的一侧；
所述触控电极图形包括多个触控驱动电极和多个触控感应电极，所述触控驱动电极与触控感应电极交叉设置，所述触控驱动电极与所述触控感应电极交叉处被所述触控绝缘层绝缘间隔开，每个所述 触控驱动电极和每个所述触控感应电极均对应连接一条所述触控信号线。
在一些实施例中，所述触控驱动电极包括：沿第一方向排列的多个驱动电极单元、以及连接在每相邻两个所述驱动电极单元之间的连接部；
所述触控感应电极包括：沿第二方向排列的多个感应电极单元、以及连接在每相邻两个所述感应电极单元之间的桥接部；
其中，所述第一方向与所述第二方向相交叉，所述驱动电极单元、所述连接部和所述感应电极单元均位于所述触控绝缘层远离所述基板的一侧且位于同一层，所述桥接部位于所述触控绝缘层与所述封装层之间。
在一些实施例中，所述触控信号线包括第一传输部和第二传输部，所述第一传输部位于所述触控绝缘层与所述封装层之间，所述第二传输部位于所述触控绝缘层远离所述封装层的一侧，所述第二传输部通过贯穿所述触控绝缘层的过孔与所述第一传输部电连接。
在一些实施例中，所述显示区包括多个像素单元，每个像素单元中设置有发光元件，所述显示面板还包括电源线，所述电源线与所述发光元件电连接，其中，所述电源线位于所述有机绝缘结构与所述基板之间，所述电源线在所述基板上的正投影与所述第一边界在所述基板上的正投影存在交叠。
在一些实施例中，所述阻挡物包括：
第一阻挡物，位于所述外围区中且环绕所述显示区；
第二阻挡物，位于所述外围区且环绕所述第一阻挡物；
其中，所述第一阻挡物的位于所述显示区与所述焊盘区之间的部分、所述第二阻挡物的位于所述显示区与所述焊盘区之间的部分构成所述单侧阻挡结构。
在一些实施例中，所述基板为柔性基板，其还包括位于所述外围区与所述焊盘区之间的弯曲区。
在一些实施例中，所述显示面板还包括：
第一缓冲层，设置在所述基板上；
半导体层，设置在所述第一缓冲层与所述第一平坦化层之间；
第一栅绝缘层，设置在所述半导体层与所述第一平坦化层之间；
第一栅电极层，设置在所述第一栅绝缘层与所述第一平坦化层之间；
第二栅绝缘层，设置在所述第一栅电极层与所述第一平坦化层之间；
第二栅电极层，设置在所述第二栅绝缘层与所述第一平坦化层之间；
层间绝缘层，设置在所述第二栅电极层与所述第一平坦化层之间；
第一源漏导电层，设置在所述层间绝缘层与所述第一平坦化层之间；
钝化层，设置在所述第一源漏导电层与所述第一平坦化层之间；
第二源漏导电层，设置在所述第一平坦化层与所述第二平坦化层之间；
第一电极层，设置在所述第二平坦化层与所述像素界定层之间，所述第一电极层包括多个第一电极，所述像素界定层包括与所述第一电极一一对应的像素开口；
发光层，设置在所述像素开口中；
第二电极层，设置在所述发光层远离所述基板的一侧；
封装层，设置在所述发光层远离所述基板的一侧；
第二缓冲层，设置在所述封装层远离所述基板的一侧。
根据本公开的第二方面，提供一种显示面板，包括：
基板，包括：显示区、外围区和焊盘区，所述外围区环绕所述显示区，所述焊盘区位于所述外围区远离所述显示区的一侧；
至少一个阻挡物，设置在所述基板上，所述阻挡物位于所述外围区中且环绕所述显示区，所述阻挡物包括位于所述显示区与所述焊盘区之间的单侧阻挡结构；
有机绝缘结构，设置在所述基板上，所述有机绝缘结构的一部分位于所述显示区，另一部分位于所述周边区，所述有机绝缘结构具 有朝向所述基板的底面、与所述底面相对的顶面、以及连接在所述底面与顶面之间且朝向所述单侧阻挡结构的第一侧面，所述第一侧面为斜坡面，所述斜坡面的坡度角在0～40°之间；
触控电极图形，设置在所述有机绝缘结构远离所述基板的一侧；
触控信号线，设置在所述有机绝缘结构远离所述基板的一侧，所述触控信号线的一端与所述触控电极图形电连接，另一端连接至所述焊盘区，所述触控信号线在所述外围区的部分在所述基板上的正投影穿过所述斜坡面在所述基板上的正投影。
在一些实施例中，所述斜坡面的坡度角在25°～35°之间。
在一些实施例中，所述有机绝缘结构的多个所述子绝缘结构包括：
第一平坦化层，设置在所述基板上；
第二平坦化层，位于所述第一平坦化层远离所述基板的一侧；
像素界定层，位于所述第二平坦化层远离所述基板的一侧。
在一些实施例中，所述第一侧面与所述单侧阻挡结构之间具有间隔。
在一些实施例中，所述显示面板还包括：封装层，设置在所述有机绝缘结构远离所述基板的一侧；
其中，所述触控电极图形和所述触控信号线均位于所述封装层远离所述基板的一侧。
在一些实施例中，所述封装层包括：
第一无机封装层；
第二无机封装层，位于所述第一无机封装层远离所述基板的一侧；
有机封装层，位于所述第一无机封装层和所述第二无机封装层之间。
在一些实施例中，所述有机绝缘结构与所述单侧阻挡结构之间形成凹槽，所述封装层在所述基板上的正投影同时覆盖所述有机绝缘结构在所述基板上的正投影、所述凹槽在所述基板上的正投影和所述单侧阻挡结构在所述基板上的正投影，所述单侧阻挡结构位于所述基 板与所述封装层之间。
在一些实施例中，所述显示面板还包括：触控绝缘层，设置在所述封装层远离所述基板的一侧；
所述触控电极图形包括多个触控驱动电极和多个触控感应电极，所述触控驱动电极与触控感应电极交叉设置，所述触控驱动电极与所述触控感应电极交叉处被所述触控绝缘层绝缘间隔开，每个所述触控驱动电极和每个所述触控感应电极均对应连接一条所述触控信号线。
在一些实施例中，所述触控驱动电极包括：沿第一方向排列的多个驱动电极单元、以及连接在每相邻两个所述驱动电极单元之间的连接部；
所述触控感应电极包括：沿第二方向排列的多个感应电极单元、以及连接在每相邻两个所述感应电极单元之间的桥接部；
其中，所述第一方向与所述第二方向相交叉，所述驱动电极单元、所述连接部和所述感应电极单元均位于所述触控绝缘层远离所述基板的一侧且位于同一层，所述桥接部位于所述触控绝缘层与所述封装层之间。
在一些实施例中，所述触控信号线包括第一传输部和第二传输部，所述第一传输部位于所述触控绝缘层与所述封装层之间，所述第二传输部位于所述触控绝缘层远离所述封装层的一侧，所述第二传输部通过贯穿所述触控绝缘层的过孔与所述第一传输部电连接。
在一些实施例中，所述显示区包括多个像素单元，每个像素单元中设置有发光元件，所述显示面板还包括电源线，所述电源线与所述发光元件电连接，其中，所述电源线位于所述有机绝缘结构与所述基板之间，所述电源线在所述基板上的正投影与所述第一侧面在所述基板上的正投影存在交叠。
在一些实施例中，所述阻挡物包括：
第一阻挡物，位于所述外围区中且环绕所述显示区；
第二阻挡物，位于所述外围区且环绕所述第一阻挡物；
其中，所述第一阻挡物的位于所述显示区与所述焊盘区之间的 部分、所述第二阻挡物的位于所述显示区与所述焊盘区之间的部分构成所述单侧阻挡结构。
在一些实施例中，所述基板为柔性基板，其还包括位于所述外围区与所述焊盘区之间的弯曲区。
在一些实施例中，所述显示面板还包括：
第一缓冲层，设置在所述基板上；
半导体层，设置在所述第一缓冲层与所述第一平坦化层之间；
第一栅绝缘层，设置在所述半导体层与所述第一平坦化层之间；
第一栅电极层，设置在所述第一栅绝缘层与所述第一平坦化层之间；
第二栅绝缘层，设置在所述第一栅电极层与所述第一平坦化层之间；
第二栅电极层，设置在所述第二栅绝缘层与所述第一平坦化层之间；
层间绝缘层，设置在所述第二栅电极层与所述第一平坦化层之间；
第一源漏导电层，设置在所述层间绝缘层与所述第一平坦化层之间；
钝化层，设置在所述第一源漏导电层与所述第一平坦化层之间；
第二源漏导电层，设置在所述第一平坦化层与所述第二平坦化层之间；
第一电极层，设置在所述第二平坦化层与所述像素界定层之间，所述第一电极层包括多个第一电极，所述像素界定层包括与所述第一电极一一对应的像素开口；
发光层，设置在所述像素开口中；
第二电极层，设置在所述发光层远离所述基板的一侧；
封装层，设置在所述发光层远离所述基板的一侧；
第二缓冲层，设置在所述封装层远离所述基板的一侧。
根据本公开的第三方面，提供一种显示面板，其包括：
基板，包括：显示区、外围区和焊盘区，所述外围区环绕所述 显示区，所述焊盘区位于所述外围区远离所述显示区的一侧；
至少一个阻挡物，设置在所述基板上，所述阻挡物位于所述外围区中且环绕所述显示区，所述阻挡物包括位于所述显示区与所述焊盘区之间的单侧阻挡结构；
有机绝缘结构，设置在所述基板上，所述有机绝缘结构包括层叠设置的多个子绝缘结构，所述多个子绝缘结构中的每个所述子绝缘结构的一部分位于所述显示区，每个所述子绝缘结构具有位于所述显示区与所述单侧阻挡结构之间的第一边界，除了最远离所述基板的所述子绝缘结构之外，其余每个所述子绝缘结构均包括伸出部；其中，对于任意相邻的两个所述子绝缘结构，靠近所述基板的所述子绝缘结构的伸出部位于远离所述基板的所述子绝缘结构的第一边界与所述单侧阻挡结构之间；
触控电极图形，设置在所述有机绝缘结构远离所述基板的一侧；
触控信号线，设置在所述有机绝缘结构远离所述基板的一侧，所述触控信号线的一端与所述触控电极图形电连接，另一端连接至所述焊盘区，所述触控信号线在所述外围区的部分在所述基板上的正投影与每个所述子绝缘结构的伸出部在所述基板上的正投影存在交叠；
其中，具有所述伸出部的所述子绝缘结构通过对有机材料层采用双色调掩膜板进行图案化工艺形成，其中，在进行所述图案化工艺时，待形成所述伸出部的区域对应于所述双色调掩膜板的半透光区。
在一些实施例中，所述有机绝缘结构的多个所述子绝缘结构包括：
第一平坦化层，设置所述基板上；
第二平坦化层，位于所述第一平坦化层远离所述基板的一侧；
像素界定层，位于所述第二平坦化层远离所述基板的一侧。
根据本公开的第四方面，提供一种显示装置，包括上述的显示面板。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一 部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1为本公开的一些实施例提供的显示面板的基板的区域划分示意图。
图2为本公开的一些实施例提供的显示面板的平面示意图。
图3为图2中Q1区域的放大图。
图4为沿图3中A-A'线的剖视图。
图5为本公开的一些实施例中有机绝缘结构与单侧阻挡结构之间的凹槽的示意图。
图6为本公开的一些实施例中的像素电路的等效示意图。
图7为沿图2中B-B'线的剖视图。
图8为沿图2中D-D’线的剖视图。
图9为本公开的另一些实施例中沿图3中A-A’线的剖视图。
图10为图9中有机绝缘结构的结构示意图之一。
图11为图9中的有机绝缘结构的结构示意图之二。
图12至图14为本公开的一些实施例提供的其中一个具有伸出部的子绝缘结构的制作过程示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
这里用于描述本公开的实施例的术语并非旨在限制和/或限定本公开的范围。例如，除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。应该理解的是，本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部 分。除非上下文另外清楚地指出，否则单数形式“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则所述相对位置关系也可能相应地改变。
在下面的描述中，当元件或层被称作“在”另一元件或层“上”或“连接到”另一元件或层时，该元件或层可以直接在所述另一元件或层上、直接连接到所述另一元件或层，或者可以存在中间元件或中间层。然而，当元件或层被称作“直接在”另一元件或层“上”、“直接连接到”另一元件或层时，不存在中间元件或中间层。术语“和/或”包括一个或更多个相关列出项的任意和全部组合。
本公开实施例提供一种显示面板，其包括基板，图1为本公开的一些实施例提供的显示面板的基板的区域划分示意图，如图1所示，基板SUB包括：显示区DA、外围区PA和焊盘区WA，外围区PA环绕显示区DA，焊盘区WA位于外围区PA远离显示区DA的一侧。其中，显示区DA中可以设置用于显示图像的元件，例如，像素电路、扫描线GL、数据线DL、发光元件等等。另外，显示区DA还可以设置触控电极图形，以实现触控功能。焊盘区WA位于外围区PA的远离显示区DA的其中一侧上，焊盘区WA包括多个接触垫PAD(或称焊盘)，每个接触垫PAD被配置为电连接从显示区DA或外围区PA延伸出来的信号线。例如，数据线DL可以通过数据连接线连接至接触垫。接触垫PAD可以是暴露在焊盘区WA表面的，即不被任何层覆盖，这样便于电连接到柔性印刷电路板FPCB(Flexible Print Circuit Board)。柔性印刷电路板FPCB与外部控制器电连接，被配置为传输来自外部控制器的信号。接触垫PAD与各个信号线电连接，从而实现信号线与柔性印刷电路板FPCB之间相互 通信。应当理解的是，图1中接触垫PAD的个数和布置方式仅为示意性说明，并不构成对接触垫PAD的限制。
图2为本公开的一些实施例提供的显示面板的平面示意图，图3为图2中Q1区域的放大图，图4为沿图3中A-A'线的剖视图，请一并参考图1至图4，该显示面板100还包括至少一个阻挡物10、有机绝缘结构20、触控电极图形和触控信号线TL。
其中，阻挡物10设置在基板SUB上，阻挡物10位于外围区PA中且环绕显示区DA。阻挡物10用于阻挡外界水汽或氧气进入显示区DA，从而防止对显示效果造成影响。阻挡物10包括位于显示区DA与外围区PA之间的单侧阻挡结构。作为一具体示例，如图2所示，阻挡部10包括第一阻挡物11和环绕第一阻挡物11的第二阻挡物12，第一阻挡物11包括位于显示区DA与外围区PA之间的第一阻挡部111，第二阻挡物12包括位于显示区DA与外围区PA之间的第四阻挡部121，此时，第一阻挡部111和第三阻挡部121构成了所述单侧阻挡结构。
有机绝缘结构20设置在基板SUB上，有机绝缘结构20包括层叠设置的多个子绝缘结构21，每个子绝缘结构21的一部分位于显示区DA，另一部分位于外围区PA，例如，子绝缘结构21在基板SUB上的正投影从显示区DA延伸至显示区DA与阻挡物10之间。每个子绝缘结构21具有第一边界E1，并且，对于任意相邻的两个子绝缘结构21，远离基板SUB一侧的子绝缘结构21的第一边界E1比靠近基板SUB一侧的子绝缘结构21的第一边界E1更靠近显示区DA，从而形成台阶状(参见图4中所示)。相邻两个子绝缘结构21的第一边界E1之间的距离d大于或等于20μm。需要说明的是，为了清楚示意各子绝缘结构21的第一边界E1之间的位置关系，图3仅对图2中的Q1区域进行放大，但应当理解的是，每个第一边界E1不仅仅是位于图2中的Q1区域，而是对应于图2中显示区DA的整个下边缘，即，第一边界E1从图2中Q区域的左端延伸至右端。相应地，有机绝缘结构20不仅在Q1区域形成图4中的台阶状形貌，在整个Q区域中也均形成台阶状形貌。
触控电极图形设置在有机绝缘结构20远离基板SUB的一侧。触控电极图形被配置为检测显示区DA中触控的发生。例如，触控电极图形包括图2中所示的触控驱动电极TX和触控感应电极TX。
触控信号线TL设置在有机绝缘结构20远离基板SUB的一侧，触控信号线TL的一端与触控电极图形电连接，另一端连接至焊盘区WA，从而与焊盘区WA中的接触垫PAD电连接。其中，触控信号线TL在外围区PA的部分在基板SUB上的正投影与每个子绝缘结构21的第一边界E1相交。
当相邻两个子绝缘结构21的第一边界E1之间的距离d较小(例如，d小于或等于5μm)时，触控信号线TL位于较陡的坡面上，这种情况下，在利用刻蚀工艺形成触控信号线TL时，容易在触控信号线TL之间产生导电物的残留，从而导致触控信号线TL之间发生短路。而在本公开实施例中，有机绝缘结构20的各子绝缘结构21中，相邻两个子绝缘结构21的第一边界E1之间的距离d较大，从而使触控信号线TL位于较平缓的坡面上，有利于减少导电物的残留，进而减少或防止触控信号线TL之间发生短路。
在一些实施例中，相邻两个子绝缘结构21的第一边界E1之间的距离d在25μm～60μm之间，从而在尽可能减小导电物残留的同时，减小显示面板100的边框。例如，d为30μm，或者为35μm，或者为40μm，或者为45μm，或者为50μm。
下面结合图1至图8对本公开的实施例中提供的显示面板进行具体介绍。
如图2所示，阻挡物10包括：第一阻挡物11和第二阻挡物12。第一阻挡物11位于外围区PA中且环绕显示区DA。第二阻挡物12位于外围区PA中且环绕第一阻挡物11，从而可以进一步防止外部水汽或氧气进入显示区DA中，为显示区DA提供双重保护。在一些实施例中，第一阻挡物11远离基板SUB的一端到基板SUB的垂直距离小于第二阻挡物12远离基板SUB的一端到基板SUB的垂直距离，从而延长外界水汽和氧气进入显示区DA的路径，进而提高阻挡物10的阻挡能力。第一阻挡物11包括第一阻挡部111和第二阻挡部 112，其中，第一阻挡部111位于显示区DA靠近弯曲区的一侧(即，图2中第一阻挡物11的位于显示区DA下方、横向延伸的部分)，第二阻挡部112为第一阻挡物11的除第一阻挡部111的其余部分，第二阻挡物12包括第三阻挡部121和第四阻挡部122，第三阻挡部121位于显示区DA靠近弯曲区的一侧(即，图2中第二阻挡物12的位于显示区DA下方、横向延伸的部分)，第四阻挡部122为第二阻挡物12中除第三阻挡部121之外的其余部分。第一阻挡部111和第三阻挡部113构成上述单侧阻挡结构。
在一些实施例中，基板SUB为柔性基板，其可以采用柔性的有机材料制成。例如，该有机材料为聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料。基板SUB还包括位于外围区PA与焊盘区WA之间的弯曲区BA。弯曲区BA被配置为沿弯曲轴BX弯曲。通过弯曲区BA的弯曲，可以使焊盘区WA处于显示面板100的背侧(其中，显示面板100的显示侧为前侧，与显示侧相反的一侧为后侧或背侧)，从而可以提高空间利用率，减小显示产品的边框宽度。
在一些实施例中，显示区DA包括多个像素单元P，像素单元P由扫描线GL和数据线DL交叉限定出。扫描线GL与外围区PA中的栅极驱动电路连接，数据线DL可以通过数据连接线与焊盘区WA的接触垫PAD连接。每个像素单元P中设置有发光元件50和像素电路。发光元件50可以为有机发光二极管OLED(Organic Light-Emitting Diode)，有机发光二极管OLED可以发射例如红光、绿光、蓝光或白光。图6为本公开的一些实施例中的像素电路的等效示意图，如图6所示，像素电路包括：驱动晶体管Td、开关晶体管Ts和存储电容Cs，开关晶体管Ts的栅极连接扫描线GL，第一极连接数据线DL，第二极连接驱动晶体管Td的栅极。存储电容Cs的两端分别与第一电源线VDD和驱动晶体管Td的栅极连接。驱动晶体管Td的第一极与第一电源线VDD连接，第二极与发光元件50的第一极连接，发光元件50的第二极与第二电源线VSS连接。其中，各晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。由于 采用的晶体管的源极和漏极是对称的，所以其源极、漏极是没有区别的。为区分晶体管的源极和漏极，这里将其中一极称为第一极，另一极称为第二极。
第一电源线VDD从焊盘区WA连接至显示区DA，从而将电压信号传输至各像素单元。第二电源线VSS包括第一部分和第二部分，其中第一部分位于外围区PA中，并以开环的方式环绕显示区DA。第二电源线VSS的第二部分连接在第一部分与焊盘区WA的接触垫PAD之间。如图2和图4所示，每个子绝缘结构21的第一边界E1在基板SUB上的正投影与第二电源线VSS在基板SUB上的正投影存在交叠。
在一些实施例中，触控电极图形可以采用互电容型结构，也可以采用自电容型结构。本公开实施例以互电容型结构为例进行说明。如图2所示，触控电极图形包括多个触控驱动电极TX和多个触控感应电极RX，触控驱动电极TX与触控感应电极RX交叉设置，触控驱动电极TX与触控感应电极RX交叉处被触控绝缘层TLD绝缘间隔开。图7为沿图2中B-B'线的剖视图，结合图2和图7所示，触控驱动电极TX包括：沿第一方向排列的多个驱动电极单元TX1和连接在驱动电极单元TX1之间的连接部TX2，触控感应电极RX包括多个感应电极单元RX1和连接在感应电极单元之间的桥接部RX2，其中，第一方向与第二方向相交叉，例如，第一方向为图2中的上下方向，第二方向为图2中的左右方向。驱动电极单元TX1、连接部TX2以及感应电极单元RX1均位于触控绝缘层TLD远离基板SUB的一侧，且驱动电极单元TX1、连接部TX2以及感应电极单元RX1可以同层设置，桥接部RX2位于触控绝缘层TLD靠近基板SUB的一侧。桥接部RX2与连接部TX2交叉设置并被触控绝缘层TLD间隔开。感应电极单元RX1通过触控绝缘层TLD上的过孔与桥接部RX2连接。需要说明的是，图2和图7中所示的触控驱动电极TX和触控感应电极RX仅为示例性说明，并不构成对本公开的限制。例如，还可以使桥接部RX2位于触控绝缘层TLD远离基板SUB的一侧，连接部位于触控绝缘层TLD靠近基板SUB的一侧。又例如， 将相邻的驱动电极单元TX1通过异层设置的桥接部连接，将相邻的感应电极单元RX1利用同层的连接部连接。
其中，每个触控驱动电极TX和触控感应电极RX均可以对应连接一条触控驱动线TL。触控信号线TL经过外围区PA时，触控信号线TL在外围区PA的部分在基板SUB上的正投影与每个子绝缘结构21的第一边界E1相交叉。在一个示例中，触控绝缘层TLD至少还覆盖显示区DA与焊盘区WA之间的外围区PA，显示区DA与焊盘区WA之间的外围区PA中的触控信号线TL位于触控绝缘层TLD上。在一个示例中，触控绝缘层TLD的厚度在0.2μm～0.5μm之间，例如为0.3μm或者0.33μm或者0.35μm。
在一些实施例中，如图4所示，触控信号线TL为双层结构，其包括第一传输部TL1和第二传输部TL2，第一传输部TL1位于触控绝缘层TLD靠近基板SUB的一侧，第二传输部TL2位于触控绝缘层TLD远离基板SUB的一侧。第二传输部TL2通过贯穿触控绝缘层TLD的过孔与第一传输部TL1电连接。需要说明的是，为了示意性地表示出第二传输部TL2和第一传输部TL1的连接方式，图4仅示意出了一个过孔，但实际上，在其他位置还可以设置多个过孔，从而使得第二传输部TL2通过多个过孔与第一传输部TL1并联。其中，第一传输部TL1可以与桥接部RX2同层设置，第二传输部TL2可以与驱动电极单元TX1、连接部TX2以及感应电极单元RX1同层设置。
如图7所示，第一缓冲层BFL1设置在基板SUB上，用于防止或减少金属原子和/或杂质从基板SUB扩散到晶体管的有源层中。本公开实施例中，第一缓冲层BFL1可以暴露基板SUB的位于弯曲区BA的一部分的上表面，以便于基板SUB进行弯曲。例如，第一缓冲层BFL1可以包括诸如氧化硅(SiOx)、氮化硅(SiNx)和/或氮氧化硅(SiON)的无机材料，并且可以形成为多层或单层。
半导体层设置在第一缓冲层BFL1上。半导体层的材料可以包括例如无机半导体材料(例如，多晶硅、非晶硅等)、有机半导体材料、氧化物半导体材料。半导体层包括各晶体管30的有源层31，有源层31包括沟道部和位于该沟道部两侧的源极连接部和漏极连接部，源 极连接部与晶体管30的源极33连接，漏极连接部与晶体管30的漏极34连接。源极连接部和漏极连接部均可以掺杂有比沟道部的杂质浓度高的杂质(例如，N型杂质或P型杂质)。沟道部与晶体管30的栅极32正对，当栅极32加载的电压信号达到一定值时，沟道部中形成载流子通路，形成使晶体管30的源极33和漏极34导通。
第一栅绝缘层GI1设置在半导体层上，其中，第一栅绝缘层GI1可以暴露基板SUB的位于弯曲区BA的一部分的上表面，以利于基板SUB进行弯曲。第一栅绝缘层GI1的材料可以包括硅化合物、金属氧化物。例如，第一栅绝缘层GI1的材料包括氮氧化硅(SiON)、氧化硅(SiOx)、氮化硅(SiNx)、碳氧化硅(SiOxCy)、氮碳化硅(SiCxNy)、氧化铝(AlOx)、氮化铝(AlNx)、氧化钽(TaOx)、氧化铪(HfOx)、氧化锆(ZrOx)、氧化钛(TiOx)等。另外，第一栅绝缘层GI1可以为单层或多层。
第一栅电极层G1设置在第一栅绝缘层GI1上。其中，第一栅电极层G1包括各晶体管30的栅极32、电容40的第一电极板41。第一栅电极层G1的材料可以包括例如金属、金属合金、金属氮化物、导电金属氧化物、透明导电材料等。例如，第一栅电极层G1可以包括金(Au)、金的合金、银(Ag)、银的合金、铝(Al)、铝的合金、氮化铝(AlNx)、钨(W)、氮化钨(WNx)、铜(Cu)、铜的合金、镍(Ni)、铬(Cr)、氮化铬(CrNx)、钼(Mo)、钼的合金、钛(Ti)、氮化钛(TiNx)、铂(Pt)、钽(Ta)、氮化钽(TaNx)、钕(Nd)、钪(Sc)、氧化锶钌(SRO)、氧化锌(ZnOx)、氧化锡(SnOx)、氧化铟(InOx)、氧化镓(GaOx)、氧化铟锡(ITO)、氧化铟锌(IZO)等。第一栅电极层G1可以具有单层或多层。
如图7所示，第二栅绝缘层GI2设置在第一栅电极层G1上，第二栅绝缘层GI2可以暴露基板SUB的位于弯曲区BA的一部分的上表面。第二栅绝缘层GI2的材料可以包括例如硅化合物、金属氧化物。例如，第二栅绝缘层GI2的材料可以包括氮氧化硅(SiON)、氧化硅(SiOx)、氮化硅(SiNx)、碳氧化硅(SiOxCy)、氮碳化硅(SiCxNy)、氧化铝(AlOx)、氮化铝(AlNx)、氧化钽(TaOx)、 氧化铪(HfOx)、氧化锆(ZrOx)、氧化钛(TiOx)等。第二栅绝缘层GI2可以形成为单层或多层。
如图7所示，第二栅电极层G2设置在第二栅绝缘层GI2上。第二栅电极层G2可以包括电容40的第二电极板42。第二栅电极层G2的材料可以包括例如金属、金属合金、金属氮化物、导电金属氧化物、透明导电材料等。例如，栅电极层可以包括金(Au)、金的合金、银(Ag)、银的合金、铝(Al)、铝的合金、氮化铝(AlNx)、钨(W)、氮化钨(WNx)、铜(Cu)、铜的合金、镍(Ni)、铬(Cr)、氮化铬(CrNx)、钼(Mo)、钼的合金、钛(Ti)、氮化钛(TiNx)、铂(Pt)、钽(Ta)、氮化钽(TaNx)、钕(Nd)、钪(Sc)、氧化锶钌(SRO)、氧化锌(ZnOx)、氧化锡(SnOx)、氧化铟(InOx)、氧化镓(GaOx)、氧化铟锡(ITO)、氧化铟锌(IZO)等。第二栅电极层G2可以具有单层或多层。
如图7所示，层间绝缘层ILD设置第二栅电极层G2上，层间绝缘层ILD可以暴露基板SUB的位于弯曲区BA的一部分的上表面。层间绝缘层ILD的材料可以包括例如硅化合物、金属氧化物等。具体可以选择上文所列举的硅化合物和金属氧化物，这里不再赘述。
第一源漏导电层SD1设置在层间绝缘层ILD上。第一源漏导电层SD1可以包括显示区DA中的各晶体管的源极33和漏极34，源极33与源极连接部电连接，漏极34与漏极连接部电连接。第一源漏导电层SD1可以包括金属、合金、金属氮化物、导电金属氧化物、透明导电材料等，例如，第一源漏导电层SD1可以为金属构成的单层或多层，例如为Mo/Al/Mo或Ti/Al/Ti。图7所示的晶体管30包括栅极32、源极33、漏极34和有源层31，图7所示的晶体管30可以为图6所示的像素电路的驱动晶体管Td，但需要说明的是，当像素电路采用其他电路结构时，与发光元件50直接连接的不一定是驱动晶体管Td，此时，图7中所示的晶体管对应的不一定是驱动晶体管Td。另外，第一源漏导电层SD1还可以包括第一电源线VDD和第二电源线VSS。
钝化层PVX设置在第一源漏导电层SD1上，钝化层PVX可以 暴露基板SUB的位于弯曲部BA的一部分的表面。钝化层PVX的材料可以包括硅的化合物，例如，氧化硅、氮化硅或氮氧化硅。
在一些实施例中，如图4所示，有机绝缘结构20的多个子绝缘结构21包括：第一平坦化层PLN1、第二平坦化层PLN2和像素界定层PDL。第一平坦化层PLN1、第二平坦化层PLN2和像素界定层PDL均包括位于显示区DA的部分和位于显示区DA与阻挡物10之间的部分。其中，第二平坦化层PLN2位于第一平坦化层PLN1远离基板SUB的一侧。像素界定层PDL位于第二平坦化层PLN2远离基板SUB的一侧。上述第一缓冲层BFL1、半导体层、第一栅绝缘层GI1、第一栅电极层G1、第二栅绝缘层GI2、第二栅电极层G2、层间绝缘层ILD、第一源漏导电层SD1、钝化层PVX均位于第一平坦化层PLN1与基板SUB之间。第一平坦化层PLN1的远离基板SUB的表面基本平坦。第一平坦化层PLN1采用有机绝缘材料制成，例如，该有机绝缘材料包括聚酰亚胺、环氧树脂、压克力、聚酯、光致抗蚀剂、聚丙烯酸酯、聚酰胺、硅氧烷等树脂类材料等。再例如，该有机绝缘材料包括弹性材料，例如、氨基甲酸乙酯、热塑性聚氨酯(TPU)等。
在一个示例中，第一平坦化层PLN1和第二平坦化层PLN2的厚度均在1μm～2μm之间，例如，第一平坦化层PLN1和第二平坦化层PLN2的厚度均为1.6μm。像素界定层PDL的厚度在1.5μm～3μm之间，例如为2μm。
如图7所示，第二源漏导电层SD2设置在第一平坦化层PLN1上。第二源漏导电层SD2可以包括位于显示区DA内的转接电极60。其中，转接电极60通过贯穿第一平坦化层PLN1和钝化层PVX的过孔与漏极34电连接，同时，转接电极60还通过贯穿第二平坦化层PLN2的过孔与发光元件50的第一电极51电连接。转接电极60可以避免直接在第一平坦化层PLN1和第二平坦化层PLN2中形成孔径比较大的过孔，从而改善过孔电连接的质量。第二源漏导电层SD2的材料可以包括金属、合金、金属氮化物、导电金属氧化物或透明导电材料等，例如，第二源漏导电层SD2可以为金属构成的单层或多层，例如为Mo/Al/Mo或Ti/Al/Ti。第二源漏导电层SD2的材料可以 与第一源漏导电层SD1的材料相同或不同。
如图7所示，第二平坦化层PLN2设置在第二源漏导电层SD2上，第二平坦化层PLN2覆盖转接电极，并且第二平坦化层PLN2的上表面基本平坦。可以具有基本平坦的上表面。第二平坦化层PLN2采用有机绝缘材料制成，例如，该有机绝缘材料包括聚酰亚胺、环氧树脂、压克力、聚酯、光致抗蚀剂、聚丙烯酸酯、聚酰胺、硅氧烷等树脂类材料等。再例如，该有机绝缘材料包括弹性材料，例如、氨基甲酸乙酯、热塑性聚氨酯(TPU)等。第二平坦化层PLN2的材料可以与第一平坦化层PLN1的材料相同或不同。
第一电极层设置在第二平坦化层PLN2上，其中，第一电极层包括多个第一电极，第一电极可以为发光元件50的阳极。如图7所示，发光元件50包括第一电极51、发光层53和第二电极52，第一电极51设置在第二平坦化层PLN2之上。第一电极51通过贯穿第二平坦化层PLN2的过孔与转接电极60电连接，进而与晶体管30的漏极34电连接。第一电极51可以采用例如金属、金属合金、金属氮化物、导电金属氧化物、透明导电材料等材料制成。第一电极51可以为单层或多层结构。
像素界定层PDL设置在第二平坦化层PLN2上。像素界定层PDL包括与像素单元一一对应的像素开口，像素开口将相应的第一电极51的一部分暴露出。发光层54一一对应地设置在像素开口中，发光层54可以包括小分子有机材料或聚合物分子有机材料，可以为荧光发光材料或磷光发光材料，可以发红光、绿光、蓝光，或可以发白光。像素界定层PDL的材料可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料。另外，像素界定层PDL上还可以设置隔垫物(图7中未示出)，隔垫物的材料与像素界定层PDL的材料可以相同。
第二电极52位于发光层53的远离基板SUB的一侧，第二电极52可以采用金属、金属合金、金属氮化物、导电金属氧化物、透明导电材料等制成。本公开实施例中，发光元件50可以采用顶发射型结构或底发射型结构。当采用顶发射型结构时，第一电极51包括具 有光反射性能的导电材料或者包括光反射膜，第二电极52包括透明或半透明的导电材料。当采用底发射型结构时，第二电极52包括光反射性能的导电材料制成或者包括光反射膜，第一电极51包括透明或半透明的导电材料。各个像素单元的发光元件50的第二电极52可以连接为一体，形成第二电极层。
需要说明的是，发光元件50还可以包括其他膜层，例如，还可以包括：位于第一电极51与发光层53之间的空穴注入层和空穴传输层，以及位于发光层53与第二电极52之间的电子传输层和电子注入层。
如图4和图7所示，显示面板100还包括封装层EPL，封装层EPL设置在像素界定层PDL上，封装层EPL覆盖像素界定层PDL和发光元件50，用于对发光元件50进行封装，以防止外界环境中的水汽和/或氧气侵蚀发光元件50。在一些实施例中，封装层EPL包括第一无机封装层CVD1、第二无机封装层CVD2和有机封装层IJP，第二无机封装层CVD2位于第一无机封装层CVD1的远离基板SUB的一侧，有机封装层IJP位于第一无机封装层CVD1和第二无机封装层CVD2之间。可选地，第一无机封装层CVD1和第二无机封装层CVD2延伸至外围区PA并覆盖阻挡物10；有机封装层IJP延伸至外围区PA，并位于阻挡物10所环绕的范围内。第一无机封装层CVD1和第二无机封装层CVD2均可以采用氮氧化硅(SiON)、氧化硅(SiOx)、氮化硅(SiNx)等致密性高的无机材料制成。有机封装层IJP可以采用含有干燥剂的高分子材料制成，或采用可阻挡水汽的高分子材料制成。例如，采用高分子树脂，从而可以缓解第一无机封装层CVD1和第二无机封装层CVD2的应力，还可以包括干燥剂等吸水性材料以吸收侵入内部的水、氧等物质。
在一个示例中，第一无机封装层CVD1和第二无机封装层CVD2的厚度均在0.5μm～1.5μm之间。例如，第一无机封装层CVD1的厚度为1.0μm，第二无机封装层CVD2的厚度为0.6μm。在显示区DA中的有机封装层IJP的厚度在5μm～10μm之间，例如为8μm，或者7μm，或者9μm。
第二缓冲层BFL2设置在封装层EPL上，第二缓冲层BFL2位于显示区DA并且延伸到外围区PA以覆盖封装层EPL。第二缓冲层BFL2可以采用与前述第一缓冲层BFL1相同的材料，此处不再赘述。触控电极图形位于封装层EPL远离基板SUB的一侧，触控电极图形的桥接部RX2设置在封装层EPL上，触控绝缘层TLD位于封装层EPL远离基板SUB的一侧，并覆盖桥接部RX2，触控驱动电极TX和触控感应电极RX的感应电极单元RX1位于触控绝缘层TLD上。其中，为了不影响显示，驱动电极单元TX1和感应电极单元RX1均采用透光性良好的结构。例如，采用透明导电材料(例如氧化铟锡)制成，或者，采用金属网格结构。
触控电极图形和触控绝缘层TLD均位于封装层EPL远离基板SUB的一侧，触控电极图形中的桥接部RX2位于触控绝缘层TLD与封装层EPL之间。其中，桥接部RX2和第一传输部TL1均位于触控绝缘层TLD与第二缓冲层BFL2之间。
如图4所示，每个子绝缘结构21的第一边界与单侧阻挡结构之间均具有间隔，即，每个子绝缘结构21与单侧阻挡结构均不接触。此时，有机绝缘结构20与单侧阻挡结构之间形成凹槽，图5为本公开的一些实施例中有机绝缘结构与单侧阻挡结构之间的凹槽的示意图，图5即为形成有机绝缘结构20和阻挡物10之后、且形成封装层EPL之前，沿图3中AA'线的剖视图。结合图4和图5所示，封装层EPL在基板SUB上的正投影同时覆盖有机绝缘结构20在基板SUB上的正投影、凹槽V1在基板SUB上的正投影和单侧阻挡结构在基板SUB上的正投影。
上覆层OC设置在触控电极图形远离基板SUB的一侧。上覆层OC从显示区DA延伸到外围区PA，上覆层OC可以保护外围区PA中的触控信号线TL。上覆层OC的材料可以包括无机绝缘材料或有机绝缘材料。
本公开实施例的柔性基板SUB上设置有第一栅绝缘层GI1、第二栅绝缘层GI2、第一缓冲层BFL1、第二缓冲层BFL2，然而，可以理解的是，在一些示例中，这些层可以根据实际需要进行删减或增加， 本公开对此不作具体限定。
图8为沿图2中D-D’线的剖视图，其中，为了简洁清楚地示意出阻挡物10的结构，图8仅示出了阻挡物10的剖面结构以及阻挡物10上的第一无机封装层和第二无机封装层。结合图2、图4和图8所示，第一阻挡部111、第二阻挡部112、第三阻挡部113和第四阻挡部114均包括第一阻挡层11a和位于该第一阻挡层11a上的第二阻挡层11b，其中，第一阻挡层11a与第二平坦化层PLN2同层设置且材料相同，第二阻挡层11b与像素界定层PDL同层设置且材料相同。另外，如图4所示，第三阻挡部121还包括第三阻挡层11c，第三阻挡层11c与第一平坦化层PLN1同层设置且材料相同。如图8所示，第二阻挡部112包括第一阻挡层11a、第二阻挡层11b，另外还包括第四阻挡层11d，该第四阻挡层11d与像素界定层PDL上的隔垫物同层设置且材料相同。第四阻挡部122包括第一阻挡层11a、第二阻挡层11b、第三阻挡层11c和第四阻挡层11d。
需要说明的是，本公开实施例中的“同层设置”是指两个结构是由同一个材料层经过构图工艺形成的，故二者在在层叠关系上是处于同一个层之中的；但这并不表示二者与基板SUB间的距离必定相同。另外，如图5和图8中所示，封装层EPL中的第一无机封装层CVD1和第二无机封装层CVD2均延伸至第一阻挡物11和第二阻挡物12上。
在一些实施例中，基板SUB的外围区PA包括第一扇出区FA1，第一扇出区FA1位于显示区DA与弯曲区BA之间，数据连接线与数据线DL连接后，经过第一扇出区FA1和弯曲区BA延伸到焊盘区WA。基板SUB还包括第二扇出区FA2，第二扇出区FA2位于弯曲区BA与焊盘区WA之间并与弯曲区BA邻接，即第二扇出区FA2与弯曲区BA相邻且彼此直接连接，两个区域之间没有其他区域。在基板SUB的第二扇出区和焊盘区WA之间还设置有测试区DTA、控制电路区CCA、第三扇出区FA3、集成电路区IC。至少一个示例中，测试区DTA被配置为连接外部测试装置以检测画面、弯曲区BA的断线等。至少一个示例中，控制电路区CCA包括选择器MUX，用于 在输入电路和输出电路之间切换。
本公开的另一些实施例还提供一种显示面板，包括：基板、阻挡物、有机绝缘结构、触控电极图形和触控信号线。其中，基板包括：显示区、外围区和焊盘区，所述外围区环绕所述显示区，所述焊盘区位于所述外围区远离所述显示区的一侧。阻挡物设置在所述基板上，所述阻挡物位于所述外围区中且环绕所述显示区，所述阻挡物包括位于所述显示区与所述焊盘区之间的单侧阻挡结构。有机绝缘结构设置在所述基板上，且所述有机绝缘结构的一部分位于所述显示区，另一部分位于所述周边区。
图9为本公开的另一些实施例中沿图3中A-A’线的剖视图，图10为图9中有机绝缘结构的结构示意图之一，图11为图9中的有机绝缘结构的结构示意图之二。结合图2、图9至图11所示，有机绝缘结构20具有朝向基板SUB的底面BS、与底面BS相对的顶面TS、以及连接在底面BS与顶面TS之间且朝向所述单侧阻挡结构的第一侧面LS，第一侧面LS为斜坡面，斜坡面的坡度角在0～40°之间。
需要说明的是，这里的“斜坡面”是指，沿远离基板SUB的方向，逐渐靠近显示区DA的表面。其中，斜坡面可以为倾斜的平面(如图10所示)，也可以为倾斜的弧面(如图11所示)。当斜坡面为平面时，其坡度角是指，斜坡面与有机绝缘结构20的底面BS之间的夹角θ1；当斜坡面为弧面时，其坡度角是指弧面的切线与有机绝缘结构20的底面BS之间的夹角的最大值θ2。还需要说明的是，斜坡面不仅位于Q1区域，而是从Q区域的左端延伸至右端。
结合图2和图9所示，触控电极图形(即图2中包括触控驱动电极TX和触控感应电极RX的图形)设置在有机绝缘结构20远离基板SUB的一侧。触控信号线TL设置在有机绝缘结构20远离基板SUB的一侧，触控信号线TL的一端与触控电极图形电连接，另一端连接至焊盘区WA。触控信号线TL在外围区PA的部分在基板SUB上的正投影穿过所述斜坡面在基板SUB上的正投影。
在一些实施例中，斜坡面的坡度角在25°～35°之间，从而在减少导电物残留的同时，防止显示产品的边框过宽。例如，该坡度角为 28°或者29°或者30°或者31°或者32°。
如图9所示，有机绝缘结构20包括层叠设置的多个子绝缘结构21，多个子绝缘结构21包括：第一平坦化层PLN1、第二平坦化层PLN2和像素界定层PDL。其中，第一平坦化层PLN1设置基板SUB上。第二平坦化层PLN2位于第一平坦化层PLN1远离基板SUB的一侧。像素界定层PDL位于第二平坦化层PLN2远离基板SUB的一侧。
有机绝缘结构20上还设置有封装层EPL、第二缓冲层BFL2、触控绝缘层TLD。其中，封装层EPL包括第一无机封装层CVD1、第二无机封装层CVD2和有机封装层IJP。第二无机封装层CVD2位于第一无机封装层CVD1远离基板SUB的一侧；有机封装层IJP位于第一无机封装层CVD1和第二无机封装层CVD2之间。
本实施例中，触控绝缘层TLD、触控信号线TL的设置方式参见上述实施例中的描述，如图2和图7中所示，所述触控电极图形包括触控驱动电极TX和触控感应电极RX，所述触控驱动电极TX与触控感应电极RX交叉设置，触控驱动电极TX与触控感应电极RX交叉处被所述触控绝缘层TLD绝缘间隔开。触控驱动电极TX和触控感应电极RX均与一条触控信号线TL电连接。触控信号线TL包括第一传输部TL1和第二传输部TL2，第一传输部TL1位于触控绝缘层TLD与封装层EPL之间，第二传输部TL2位于触控绝缘层TLD远离基板SUB的一侧，第二传输部TL2通过贯穿触控绝缘层TLD的过孔与第一传输部TL1电连接。触控电极图形和触控信号线TL均位于封装层EPL远离基板SUB的一侧。
第一侧面LS与所述单侧阻挡结构之间具有间隔，例如，第一侧面LS靠近基板SUB的一端以及远离基板SUB的一端与单侧阻挡结构之间均具有间隔。有机绝缘结构20与单侧阻挡结构之间形成凹槽，封装层EPL在基板SUB上的正投影同时覆盖有机绝缘结构20在基板SUB上的正投影、所述凹槽在基板SUB上的正投影和所述单侧阻挡结构在基板SUB上的正投影，所述单侧阻挡结构位于基板SUB与封装层EPL之间。
显示区DA包括多个像素单元，每个像素单元中设置有发光元件50，显示面板100还包括第二电源线VSS，第二电源线VSS与发光元件50电连接，其中，第二电源线VSS位于有机绝缘结构20与基板SUB之间，第一侧面LS在所述基板SUB上的正投影与第二电源线VSS在基板SUB上的正投影存在交叠。
阻挡物10包括第一阻挡物11和第二阻挡物12，第一阻挡物11位于外围区PA中且环绕显示区DA，第二阻挡物12位于外围区PA且环绕第一阻挡物11。第一阻挡物11和第二阻挡物12的具体结构参见上述实施例中的描述，这里不再赘述。基板SUB上还设置有第一缓冲层BFL1、半导体层、第一栅绝缘层GI1、第一栅电极层G1、第二栅绝缘层GI2、层间绝缘层ILD、第一源漏导电层SD1、钝化层PVX、第二源漏导电层SD2等结构，各膜层的结构和位置均参见上述实施例中的描述，这里不再赘述。本实施例中的基板SUB为柔性基板，其还包括外围区PA与焊盘区WA之间的弯曲区BA，另外，还包括测试区DTA、控制电路区CCA等其他区域，各区域之间的位置关系参见上述实施例中的描述，这里不再赘述。
本实施例中的显示面板，有机绝缘结构20的第一侧面为斜坡面，其坡度较小，因此，在后续通过刻蚀工艺来制作触控信号线时，可以减少导电物的残留，进而减少或防止触控信号线TL之间发生短路。
本公开实施例还提供一种显示面板，包括基板、阻挡物、有机绝缘结构、触控电极图形和触控信号线。其中，所述基板包括：显示区、外围区和焊盘区，所述外围区环绕所述显示区，所述焊盘区位于所述外围区远离所述显示区的一侧。所述阻挡物设置在所述基板上，所述阻挡物位于所述外围区中且环绕所述显示区，所述阻挡物包括位于所述显示区与所述焊盘区之间的单侧阻挡结构。有机绝缘结构设置在所述基板上，所述有机绝缘结构包括层叠设置的多个子绝缘结构，每个所述子绝缘结构的一部分位于所述显示区，另一部分位于周边区。每个所述子绝缘结构具有位于所述显示区与所述单侧阻挡结构之间的第一边界，除了最远离基板SUB的所述子绝缘结构之外，其余每个所述子绝缘结构均包括伸出部，其中，对于任意相邻的两个所述 子绝缘结构，靠近基板SUB的所述子绝缘结构的伸出部位于远离基板SUB的所述子绝缘结构的第一边界与所述单侧阻挡结构之间。触控电极图形设置在所述有机绝缘结构远离所述基板的一侧，并位于所述显示区。触控信号线设置在所述有机绝缘结构远离所述基板的一侧，所述触控信号线的一端与所述触控电极图形电连接，另一端连接至所述焊盘区，所述触控信号线在所述外围区的部分在所述基板上的正投影与每个所述子绝缘结构的伸出部在所述基板上的正投影存在交叠。
其中，具有所述伸出部的所述子绝缘结构通过对有机材料层采用双色调掩膜板进行图案化工艺形成，其中，在进行图案化工艺时，待形成所述伸出部的区域对应于所述双色调掩膜板的半透光区。
在一些实施例中，所述有机绝缘结构的多个所述子绝缘结构包括：第一平坦化层、第二平坦化层和像素界定层。所述第一平坦化层设置所述基板上；第二平坦化层位于所述第一平坦化层远离所述基板的一侧；所述像素界定层位于所述第二平坦化层远离所述基板的一侧。
图12至图14为本公开的一些实施例提供的其中一个具有伸出部的子绝缘结构的制作过程示意图，下面以其中一个具有伸出部的子绝缘结构为例，对其制作过程进行介绍。该子绝缘结构可以为第一平坦化层或第二平坦化层。
如图12所示，形成有机绝缘材料层210，其中，有机绝缘材料层210为对光敏感的有机材料层，例如正性光刻胶。
如图13所示，采用双色调掩膜板M对光刻胶层进行曝光。其中，双色调掩膜板M为灰色调掩膜板或半色调掩膜板。双色调掩膜板M包括全透光区M1、不透光区M3和半透光区M2，半透光区M2的透光率小于全透光区M1的透光率。以有机绝缘材料层210为正性光刻胶为例，在进行曝光时，将双色调掩膜板M的半透光区M2与待形成伸出部的区域对应，将双色调掩膜板M的全透光区M1与有机绝缘材料层210需要被完全去除的区域对应，将双色调掩膜板M的不透光区M3与其他区域对应。经过曝光后，有机绝缘材料层210 中与不透光区对应的部分未被曝光，有机绝缘材料层210中与全透光区对应的部分被完全曝光，有机绝缘材料层210中与半透光区对应的部分被部分曝光。
之后，有机绝缘材料层210进行显影，使得有机绝缘材料层210中与全透光区M1对应的部分被全部去除，与部分透光区M2对应的部分被去除掉一部分，与不透光区M3对应的部分被完全保留，形成的图案即为子绝缘结构21，如图14所示。其中，子绝缘结构21中与部分透光区M2对应的部分即为伸出部21a，伸出部21a的表面为平缓的斜坡面。
应当理解的是，在上述构图工艺中，也可以采用负性光刻胶，此时，采用的掩膜板的图案与上述双色调掩膜板M的图案互补。
本公开实施例中，具有伸出部21a的子绝缘结构21利用双色调掩膜板对有机材料层210进行构图工艺制成，在进行曝光时，待形成伸出部21a的区域与双色调掩膜板M的半透光区M2对应，从而可以使形成的伸出部21a具有斜坡面，因此，有机绝缘结构20的整体侧面较为平缓，在后续通过刻蚀工艺来制作触控信号线时，可以减少导电物的残留，进而减少或防止触控信号线之间发生短路。
在本实施例中，阻挡物20的结构、像素界定层PDL的结构和材料、第一平坦化层PLN1的结构和材料、第二平坦化层PLN2的结构和材料均可以参考上述实施例中的描述，这里不再赘述。
另外，在本实施例中，有机绝缘结构上还设置有封装层、触控绝缘层。基板的显示区还可以设置发光元件，发光元件与第二电源线连接。封装层的具体结构和材料、触控绝缘层的设置方式和材料、发光元件的结构和材料、第二电源线和触控信号线的设置方式均可以参考上述实施例中的描述，这里也不再赘述。
本公开实施例还提供一种显示装置，其包括上述任一实施例的显示面板。该显示装置可以为OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而 采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (31)

  1. 一种显示面板，包括：
    基板，包括显示区、外围区和焊盘区，所述外围区环绕所述显示区，所述焊盘区位于所述外围区远离所述显示区的一侧；
    至少一个阻挡物，设置在所述基板上，所述阻挡物位于所述外围区中且环绕所述显示区，所述阻挡物包括位于所述显示区与所述焊盘区之间的单侧阻挡结构；
    有机绝缘结构，设置在所述基板上，所述有机绝缘结构包括层叠设置的多个子绝缘结构，所述多个子绝缘结构中的每个子绝缘结构的一部分位于所述显示区，所述多个子绝缘结构中的每个子绝缘结构具有位于所述显示区与所述单侧阻挡结构之间的第一边界，其中，对于任意相邻的两个所述子绝缘结构，远离所述基板一侧的所述子绝缘结构的第一边界比靠近所述基板一侧的所述子绝缘结构的第一边界更靠近所述显示区；任意相邻两个所述子绝缘结构的第一边界之间的间距大于或等于20μm；
    触控电极图形，设置在所述有机绝缘结构远离所述基板的一侧；
    触控信号线，设置在所述有机绝缘结构远离所述基板的一侧，所述触控信号线的一端与所述触控电极图形电连接，另一端连接至所述焊盘区，所述触控信号线在所述外围区的部分在所述基板上的正投影与每个所述子绝缘结构的第一边界相交。
  2. 根据权利要求1所述的显示面板，其中，任意相邻两个所述子绝缘结构的第一边界之间的间距在25μm～60μm之间。
  3. 根据权利要求1所述的显示面板，其中，所述有机绝缘结构的多个所述子绝缘结构包括：
    第一平坦化层，设置在所述基板上；
    第二平坦化层，位于所述第一平坦化层远离所述基板的一侧；
    像素界定层，位于所述第二平坦化层远离所述基板的一侧。
  4. 根据权利要求1至3中任意一项所述的显示面板，其中，所述子绝缘结构的第一边界与所述单侧阻挡结构之间具有间隔。
  5. 根据权利要求1至3中任意一项所述的显示面板，其中，所述显示面板还包括：封装层，设置在所述有机绝缘结构远离所述基板的一侧；
    其中，所述触控电极图形和所述触控信号线均位于所述封装层远离所述基板的一侧。
  6. 根据权利要求5所述的显示面板，其中，所述封装层包括：
    第一无机封装层；
    第二无机封装层，位于所述第一无机封装层远离所述基板的一侧；
    有机封装层，位于所述第一无机封装层和所述第二无机封装层之间。
  7. 根据权利要求5所述的显示面板，其中，所述有机绝缘结构与所述单侧阻挡结构之间形成凹槽，所述封装层在所述基板上的正投影同时覆盖所述有机绝缘结构在所述基板上的正投影、所述凹槽在所述基板上的正投影和所述单侧阻挡结构在所述基板上的正投影，所述单侧阻挡结构位于所述基板与所述封装层之间。
  8. 根据权利要求5所述的显示面板，其中，所述显示面板还包括：触控绝缘层，设置在所述封装层远离所述基板的一侧；
    所述触控电极图形包括多个触控驱动电极和多个触控感应电极，所述触控驱动电极与触控感应电极交叉设置，所述触控驱动电极与所述触控感应电极交叉处被所述触控绝缘层绝缘间隔开，每个所述触控驱动电极和每个所述触控感应电极均对应连接一条所述触控信号线。
  9. 根据权利要求8所述的显示面板，其中，所述触控驱动电极包括：沿第一方向排列的多个驱动电极单元、以及连接在每相邻两个所述驱动电极单元之间的连接部；
    所述触控感应电极包括：沿第二方向排列的多个感应电极单元、以及连接在每相邻两个所述感应电极单元之间的桥接部；
    其中，所述第一方向与所述第二方向相交叉，所述驱动电极单元、所述连接部和所述感应电极单元均位于所述触控绝缘层远离所述基板的一侧且位于同一层，所述桥接部位于所述触控绝缘层与所述封装层之间。
  10. 根据权利要求8所述的显示面板，其中，所述触控信号线包括第一传输部和第二传输部，所述第一传输部位于所述触控绝缘层与所述封装层之间，所述第二传输部位于所述触控绝缘层远离所述封装层的一侧，所述第二传输部通过贯穿所述触控绝缘层的过孔与所述第一传输部电连接。
  11. 根据权利要求1至3中任意一项所述的显示面板，其中，所述显示区包括多个像素单元，每个像素单元中设置有发光元件，所述显示面板还包括电源线，所述电源线与所述发光元件电连接，其中，所述电源线位于所述有机绝缘结构与所述基板之间，所述电源线在所述基板上的正投影与所述第一边界在所述基板上的正投影存在交叠。
  12. 根据权利要求1至3中任意一项所述的显示面板，其中，所述阻挡物包括：
    第一阻挡物，位于所述外围区中且环绕所述显示区；
    第二阻挡物，位于所述外围区且环绕所述第一阻挡物；
    其中，所述第一阻挡物的位于所述显示区与所述焊盘区之间的部分、所述第二阻挡物的位于所述显示区与所述焊盘区之间的部分构成所述单侧阻挡结构。
  13. 根据权利要求1至3中任意一项所述的显示面板，其中，所述基板为柔性基板，其还包括位于所述外围区与所述焊盘区之间的弯曲区。
  14. 根据权利要求3所述的显示面板，其中，所述显示面板还包括：
    第一缓冲层，设置在所述基板上；
    半导体层，设置在所述第一缓冲层与所述第一平坦化层之间；
    第一栅绝缘层，设置在所述半导体层与所述第一平坦化层之间；
    第一栅电极层，设置在所述第一栅绝缘层与所述第一平坦化层之间；
    第二栅绝缘层，设置在所述第一栅电极层与所述第一平坦化层之间；
    第二栅电极层，设置在所述第二栅绝缘层与所述第一平坦化层之间；
    层间绝缘层，设置在所述第二栅电极层与所述第一平坦化层之间；
    第一源漏导电层，设置在所述层间绝缘层与所述第一平坦化层之间；
    钝化层，设置在所述第一源漏导电层与所述第一平坦化层之间；
    第二源漏导电层，设置在所述第一平坦化层与所述第二平坦化层之间；
    第一电极层，设置在所述第二平坦化层与所述像素界定层之间，所述第一电极层包括多个第一电极，所述像素界定层包括与所述第一电极一一对应的像素开口；
    发光层，设置在所述像素开口中；
    第二电极层，设置在所述发光层远离所述基板的一侧；
    封装层，设置在所述发光层远离所述基板的一侧；
    第二缓冲层，设置在所述封装层远离所述基板的一侧。
  15. 一种显示面板，包括：
    基板，包括：显示区、外围区和焊盘区，所述外围区环绕所述显示区，所述焊盘区位于所述外围区远离所述显示区的一侧；
    至少一个阻挡物，设置在所述基板上，所述阻挡物位于所述外围区中且环绕所述显示区，所述阻挡物包括位于所述显示区与所述焊盘区之间的单侧阻挡结构；
    有机绝缘结构，设置在所述基板上，所述有机绝缘结构的一部分位于所述显示区，另一部分位于所述周边区，所述有机绝缘结构具有朝向所述基板的底面、与所述底面相对的顶面、以及连接在所述底面与顶面之间且朝向所述单侧阻挡结构的第一侧面，所述第一侧面为斜坡面，所述斜坡面的坡度角在0～40°之间；
    触控电极图形，设置在所述有机绝缘结构远离所述基板的一侧；
    触控信号线，设置在所述有机绝缘结构远离所述基板的一侧，所述触控信号线的一端与所述触控电极图形电连接，另一端连接至所述焊盘区，所述触控信号线在所述外围区的部分在所述基板上的正投影穿过所述斜坡面在所述基板上的正投影。
  16. 根据权利要求15所述的显示面板，其中，所述斜坡面的坡度角在25°～35°之间。
  17. 根据权利要求15所述的显示面板，其中，所述有机绝缘结构的多个所述子绝缘结构包括：
    第一平坦化层，设置在所述基板上；
    第二平坦化层，位于所述第一平坦化层远离所述基板的一侧；
    像素界定层，位于所述第二平坦化层远离所述基板的一侧。
  18. 根据权利要求15至17中任意一项所述的显示面板，其中，所述第一侧面与所述单侧阻挡结构之间具有间隔。
  19. 根据权利要求15至17中任意一项所述的显示面板，其中，所述显示面板还包括：封装层，设置在所述有机绝缘结构远离所述基板的一侧；
    其中，所述触控电极图形和所述触控信号线均位于所述封装层远离所述基板的一侧。
  20. 根据权利要求19所述的显示面板，其中，所述封装层包括：
    第一无机封装层；
    第二无机封装层，位于所述第一无机封装层远离所述基板的一侧；
    有机封装层，位于所述第一无机封装层和所述第二无机封装层之间。
  21. 根据权利要求19所述的显示面板，其中，所述有机绝缘结构与所述单侧阻挡结构之间形成凹槽，所述封装层在所述基板上的正投影同时覆盖所述有机绝缘结构在所述基板上的正投影、所述凹槽在所述基板上的正投影和所述单侧阻挡结构在所述基板上的正投影，所述单侧阻挡结构位于所述基板与所述封装层之间。
  22. 根据权利要求19所述的显示面板，其中，所述显示面板还包括：触控绝缘层，设置在所述封装层远离所述基板的一侧；
    所述触控电极图形包括多个触控驱动电极和多个触控感应电极，所述触控驱动电极与触控感应电极交叉设置，所述触控驱动电极与所述触控感应电极交叉处被所述触控绝缘层绝缘间隔开，每个所述触控驱动电极和每个所述触控感应电极均对应连接一条所述触控信号线。
  23. 根据权利要求22所述的显示面板，其中，所述触控驱动电极包括：沿第一方向排列的多个驱动电极单元、以及连接在每相邻两个所述驱动电极单元之间的连接部；
    所述触控感应电极包括：沿第二方向排列的多个感应电极单元、以及连接在每相邻两个所述感应电极单元之间的桥接部；
    其中，所述第一方向与所述第二方向相交叉，所述驱动电极单元、所述连接部和所述感应电极单元均位于所述触控绝缘层远离所述基板的一侧且位于同一层，所述桥接部位于所述触控绝缘层与所述封装层之间。
  24. 根据权利要求22所述的显示面板，其中，所述触控信号线包括第一传输部和第二传输部，所述第一传输部位于所述触控绝缘层与所述封装层之间，所述第二传输部位于所述触控绝缘层远离所述封装层的一侧，所述第二传输部通过贯穿所述触控绝缘层的过孔与所述第一传输部电连接。
  25. 根据权利要求15至17中任意一项所述的显示面板，其中，所述显示区包括多个像素单元，每个像素单元中设置有发光元件，所述显示面板还包括电源线，所述电源线与所述发光元件电连接，其中，所述电源线位于所述有机绝缘结构与所述基板之间，所述电源线在所述基板上的正投影与所述第一侧面在所述基板上的正投影存在交叠。
  26. 根据权利要求15至17中任意一项所述的显示面板，其中，所述阻挡物包括：
    第一阻挡物，位于所述外围区中且环绕所述显示区；
    第二阻挡物，位于所述外围区且环绕所述第一阻挡物；
    其中，所述第一阻挡物的位于所述显示区与所述焊盘区之间的部分、所述第二阻挡物的位于所述显示区与所述焊盘区之间的部分构成所述单侧阻挡结构。
  27. 根据权利要求15至17中任意一项所述的显示面板，其中，所述基板为柔性基板，其还包括位于所述外围区与所述焊盘区之间的弯曲区。
  28. 根据权利要求17所述的显示面板，其中，所述显示面板还包括：
    第一缓冲层，设置在所述基板上；
    半导体层，设置在所述第一缓冲层与所述第一平坦化层之间；
    第一栅绝缘层，设置在所述半导体层与所述第一平坦化层之间；
    第一栅电极层，设置在所述第一栅绝缘层与所述第一平坦化层之间；
    第二栅绝缘层，设置在所述第一栅电极层与所述第一平坦化层之间；
    第二栅电极层，设置在所述第二栅绝缘层与所述第一平坦化层之间；
    层间绝缘层，设置在所述第二栅电极层与所述第一平坦化层之间；
    第一源漏导电层，设置在所述层间绝缘层与所述第一平坦化层之间；
    钝化层，设置在所述第一源漏导电层与所述第一平坦化层之间；
    第二源漏导电层，设置在所述第一平坦化层与所述第二平坦化层之间；
    第一电极层，设置在所述第二平坦化层与所述像素界定层之间，所述第一电极层包括多个第一电极，所述像素界定层包括与所述第一电极一一对应的像素开口；
    发光层，设置在所述像素开口中；
    第二电极层，设置在所述发光层远离所述基板的一侧；
    封装层，设置在所述发光层远离所述基板的一侧；
    第二缓冲层，设置在所述封装层远离所述基板的一侧。
  29. 一种显示面板，其包括：
    基板，包括：显示区、外围区和焊盘区，所述外围区环绕所述显示区，所述焊盘区位于所述外围区远离所述显示区的一侧；
    至少一个阻挡物，设置在所述基板上，所述阻挡物位于所述外围区中且环绕所述显示区，所述阻挡物包括位于所述显示区与所述焊盘区之间的单侧阻挡结构；
    有机绝缘结构，设置在所述基板上，所述有机绝缘结构包括层叠设置的多个子绝缘结构，所述多个子绝缘结构中的每个所述子绝缘结构的一部分位于所述显示区，每个所述子绝缘结构具有位于所述显示区与所述单侧阻挡结构之间的第一边界，除了最远离所述基板的所述子绝缘结构之外，其余每个所述子绝缘结构均包括伸出部；其中，对于任意相邻的两个所述子绝缘结构，靠近所述基板的所述子绝缘结构的伸出部位于远离所述基板的所述子绝缘结构的第一边界与所述单侧阻挡结构之间；
    触控电极图形，设置在所述有机绝缘结构远离所述基板的一侧；
    触控信号线，设置在所述有机绝缘结构远离所述基板的一侧，所述触控信号线的一端与所述触控电极图形电连接，另一端连接至所述焊盘区，所述触控信号线在所述外围区的部分在所述基板上的正投影与每个所述子绝缘结构的伸出部在所述基板上的正投影存在交叠；
    其中，具有所述伸出部的所述子绝缘结构通过对有机材料层采用双色调掩膜板进行图案化工艺形成，其中，在进行所述图案化工艺时，待形成所述伸出部的区域对应于所述双色调掩膜板的半透光区。
  30. 根据权利要求29所述的显示面板，其中，所述有机绝缘结构的多个所述子绝缘结构包括：
    第一平坦化层，设置所述基板上；
    第二平坦化层，位于所述第一平坦化层远离所述基板的一侧；
    像素界定层，位于所述第二平坦化层远离所述基板的一侧。
  31. 一种显示装置，包括权利要求1至30中任意一项所述的显示面板。
PCT/CN2020/083962 2020-04-09 2020-04-09 显示面板和显示装置 WO2021203360A1 (zh)

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