CN107154402A - 显示面板 - Google Patents

显示面板 Download PDF

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CN107154402A
CN107154402A CN201610837571.XA CN201610837571A CN107154402A CN 107154402 A CN107154402 A CN 107154402A CN 201610837571 A CN201610837571 A CN 201610837571A CN 107154402 A CN107154402 A CN 107154402A
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display panel
wire
substrate
channel width
semiconductor layer
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CN107154402B (zh
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王兆祥
陈奕静
李冠锋
林信宏
叶守圃
吴湲琳
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Innolux Corp
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Innolux Display Corp
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    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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Abstract

本发明公开一种显示面板，其包括相对设置的第一基板和第二基板，和设置于第一、第二基板之间的一显示层。第一基板包含一基材；一第一导线设置在基材上并沿第一方向延伸；一第二导线与一第三导线，沿第二方向延伸且互相间隔排列，第二与第三导线并与第一导线交错设置；一接触垫介于第二与第三导线之间；一半导体层与接触垫及第二导线连接且半导体层具有一厚度d(μm)；以及一像素电极连接接触垫。半导体层于第二方向具有通道宽度W(μm)，在第一方向上接触垫与第二导线具有通道长度L(μm)，在第一方向上第二与第三导线具有像素间距Px(μm)，且通道宽度W符合下列公式：

Description

显示面板
技术领域
本发明涉及一种显示面板，且特别是涉及显示面板的晶体管阵列基板的像素结构。
背景技术
不论在工作处理学习上或是个人休闲娱乐上，具显示面板的电子产品，包括智慧型手机(SmartPhone)、平板电脑(Pad)、笔记型电脑(Notebook)、显示器(Monitor)到电视(TV)等许多相关产品，已是现代人不可或缺的必需品。其中又以液晶显示面板最为普遍。液晶显示面板(LCD)是利用电压驱动液晶(LCs)转动进而调整亮度灰阶而可构成一种平面显示器、电子视觉显示器，及影像显示器。由于液晶显示面板在绝大多数应用上具有更简洁、更轻盈、可携带、更低价、更高可靠度以及让眼睛更舒适的功能，因此已经广泛地取代了阴极射线管显示器(CRT)，成为最广泛使用的显示器，同时提供多样性包括尺寸、形状、分辨率等多种选择。
随着应用产品的微型化和分辨率增加的需求，显示面板上的半导体装置尺寸也日益减小。然而，显示面板在制作时需考虑各元件如相关金属和半导体元件的图案和尺寸是否可使制得的显示装置具有稳定良好的电子特性，以符合应用产品要求的各项规格，例如符合高穿透率、高良率、良好的电性可靠度和显示品质稳定等要求。显示面板相关元件和各材料层的设计不良，可能造成电性表现降低，进而影响显示品质。以一背通道蚀刻型晶体管(BCE-type TFT)阵列基板上的晶体管为例，目前受限于晶体管的特性，其做为主动层的半导体层如氧化铟镓锌(indium gallium zinc oxide，IGZO)层在宽度和长度上缩减的幅度，已无法直接正比于像素尺寸缩减的幅度。
发明内容
本发明的目的在于提供一种显示面板，其晶体管阵列基板的像素结构的尺寸设计，可使像素结构缩小时仍可维持显示面板良好的电子特性。
根据本发明，其提出一种显示面板，包括一第一基板、与第一基板相对设置的一第二基板，和设置于第一基板与第二基板之间的一显示层。第一基板包含一基材；一第一导线，设置在基材上并沿第一方向延伸；一第二导线与一第三导线，沿第二方向延伸且互相间隔排列，第二导线与第三导线并与第一导线交错设置；一接触垫，介于第二导线与第三导线之间；一半导体层，与接触垫及第二导线连接，且半导体层具有一厚度d(μm)；以及一像素电极，连接接触垫。其中，半导体层具有一通道宽度W(μm)，在接触垫与第二导线间具有一通道长度L(μm)，在第一方向上第二导线与第三导线具有一像素间距Px(μm)，且通道宽度W符合下列公式：
根据本发明，是提出一种晶体管阵列基板，此基板包含多个阵列的像素区域，该些像素区域其中之一是包括上述第一基板的结构，且通道宽度W符合上方公式。
为了对本发明的上述及其他方面有更佳的了解，下文特举实施例，并配合所附附图，作详细说明如下：
附图说明
图1为本发明一显示面板实施例的背通道蚀刻型晶体管阵列基板的液晶显示面板的剖面示意图；
图2A为本发明该显示面板实施例的背通道蚀刻型晶体管阵列基板的局部上视图；
图2B为图2A中圈选处的局部放大图；
图3为半导体层的通道宽度W固定时，晶体管的临界电压随半导体层的通道长度L变化的曲线图；
图4A、图4B为温度条件25度C，半导体层的通道长度L为3.4μm到5.4μm，通道宽度W为10μm到1000μm的情况下，分别检视晶体管的临界电压以及磁滞现象的相关曲线图；
图5A、图5B为温度条件70度C，半导体层的通道长度L为3.4μm到5.4μm，通道宽度W为10μm到1000μm的情况下，分别检视晶体管的临界电压以及磁滞现象的相关曲线图；
图6A、图6B为温度条件70度C，半导体层的通道长度L为3.4μm到5.4μm，通道宽度W为10μm到1000μm的情况下，分别量测各通道宽度W的正栅极偏压偏移情况和负栅极偏压偏移情况的相关曲线图；
图7A-图7F为摄氏温度25度时，对模拟晶体管进行操作所得到的栅极电压(Vg)-源极电流(Id)的曲线图，其中通道宽度W固定为500μm，而通道长度L则由3.8μm变化至8.8μm；
图8A是根据图7A-图7F所得到的起始临界电压(initial Vth)相应于通道长度L做变化的关系图；
图8B是根据图7A-图7F所得到的偏压(bias，也代表磁滞)相应于通道长度L做变化的关系图；
图9A、图9B是显示在维持TFT充电能力的情况下，TFT与像素设计的相关模拟设计曲线；
图10A、图10B是显示实际制作产品的相关数值点(实验值)以及显示第9A、9B图所示的模拟设计曲线(虚线)。
符号说明
S1：第一基板
10：基材
12：栅极电极
13：第一绝缘层
14：半导体层
Ach：通道区
d：半导体层的厚度
15：源极电极
16：漏极电极
18：第二绝缘层
19：第三绝缘层
PE：像素电极
21：第一导线
22：第二导线
23：第三导线
PCONT：接触垫
Vcont：孔洞
L：通道长度
W：通道宽度
Px：像素间距
S2：第二基板
LC：液晶层
D1：第一方向
D2：第二方向
具体实施方式
本发明的实施例是提出一种显示面板，其关于晶体管阵列基板的特殊像素结构设计，如何在像素尺寸缩小时(例如高分辨率的应用产品)，相关元件的尺寸可以相应地缩减(例如是主动层的通道宽度和通道长度如何相应变化)，但又可维持显示面板的良好电子特性，包括使晶体管的充电能力和电容负载仍然符合一般应用产品的需求(如符合产品的操作规格)。
以下是参照所附附图详细叙述本发明的实施例。本发明的实施例例如是应用于背通道蚀刻型晶体管(BCE-type TFT)阵列基板的液晶显示面板。需注意的是，实施例所提出的实施态样的结构和内容仅为举例说明之用。本发明并非显示出所有可能的实施例，相关领域者可在不脱离本发明的精神和范围内对实施例的结构加以变化与修饰，以符合实际应用所需。因此，未于本发明提出的其他实施态样也可能可以应用。再者，附图是已简化以利清楚说明实施例的内容，附图上的尺寸比例并非按照实际产品等比例绘制。因此，说明书和图示内容仅作叙述实施例之用，而非作为限缩本发明保护范围之用。再者，实施例中相同或类似的标号是用以标示相同或类似的部分。
另外，说明书与请求项中所使用的序数例如”第一”、”第二”、”第三”等的用词，以修饰请求项的元件，其本身并不意含及代表该请求元件有任何之前的序数，也不代表某一请求元件与另一请求元件的顺序、或是制造方法上的顺序，该些序数的使用仅用来使具有某命名的一请求元件得以和另一具有相同命名的请求元件能作出清楚区分。以下是以背通道蚀刻型晶体管阵列基板的液晶显示面板做实施例的说明。
图1为本发明一显示面板实施例的背通道蚀刻型晶体管阵列基板的剖面示意图。图2A为该显示面板实施例的背通道蚀刻型晶体管阵列基板的局部上视图。图2B为图2A中圈选处的局部放大图。如图1所示，实施例的显示面板包括一第一基板S1、与第一基板S1相对设置一第二基板S2和设置于第一基板S1与第二基板S2之间的一显示层。实施例中，第一基板S1例如是一晶体管阵列基板，第二基板S2例如是一彩色滤光基板，显示层为液晶层LC。此实施例是以源极电极15和漏极电极16(i.e.第二金属层)直接形成于半导体层(i.e.主动层)上以位于通道区Ach的两侧为例作第一基板S1的结构说明。
如图1所示，设置在一基材10上的多个晶体管其中之一是包含一栅极电极12设置在基材10上，一第一绝缘层13设置在栅极电极12上，一半导体层14(做为主动层)设置在第一绝缘层13上且半导体层14包含一通道区Ach，一源极电极15和一漏极电极16(两者为第二金属层)设置在半导体层14上。于一背通道蚀刻型晶体管(BCE-type TFT)阵列基板中，半导体层14的材料例如是包含金属氧化物半导体，如氧化铟镓锌(indium gallium zincoxide，IGZO)。另外，晶体管还包括一第二绝缘层18覆盖源极电极15和漏极电极16，以及位于第二绝缘层18上的一第三绝缘层19。一实施例中，第一绝缘层13的厚度例如是(但不限制是)介于0.25μm至0.45μm之间。
在各像素区域中，还包括一像素电极PE(材料例如是ITO)通过第二绝缘层18的孔洞Vcont而电连接第二金属层，例如连接漏极电极16(漏极电极16亦即接触垫PCONT)，如图1所示。也请参照第2A、2B图的像素区域的局部上视图。其中图1为沿图2B的剖面线C1-C1的剖面示意图。在一个像素区域中，第一基板S1包括设置在基材10上并沿第一方向D1延伸的一第一导线21，第一导线21包含如图1的栅极电极12；沿第二方向D2延伸且互相间隔排列的一第二导线22(i.e对应于图1的源极电极15，即，数据线)与一第三导线23(即相邻的另一条数据线)，且第二导线22与第三导线23并与第一导线21交错设置；介于第二导线22与第三导线23之间的接触垫PCONT(即，图1的漏极电极16)，像素电极PE则与接触垫PCONT连接，且本实施例中第二导线22、第三导线23与接触垫PCONT是由同一金属层图案化所形成；以及连接接触垫PCONT及第二导线22的半导体层14(例如IGZO层)，且半导体层14具有一厚度d(μm，请参照图1)。因此，第一导线21、第二导线22与第三导线23对应一个像素区域。再者，于一实施例中，第一方向D1与第二方向D2垂直。当然，本发明并不非局限于图1所绘示的细部结构，例如第一方向D1也可与第二方向D2形成一夹角，其范围例如是在75度至90度之间。第二基板S2也省略了其他元件，以利清楚显示本发明。
本发明是针对像素尺寸和晶体管尺寸(i.e.通道尺寸)进行相关研究与设计。如图2B所示，半导体层14于第二方向D2具有一第一宽度(即标号W所指)(μm)，在第一方向D1上接触垫PCONT与第二导线22具有一第一间距(即标号L所指)(μm)。半导体层14包含一通道区Ach(大致位于第二导线22和接触垫PCONT之间)，且第一间距即为通道长度(channel length)L，一般是以第二导线22与接触垫PCONT间的最短距离为基准，第一宽度即为通道宽度(channelwidth)W，通道长度L与通道宽度W为本领域人士对于晶体管的通常知识，故不在此多加赘述。再者，在第一方向D1上第二导线22与第三导线23具有一像素间距Px(μm)。
实施例中，是根据上述如图2A、图2B的结构中的半导体层14尺寸进行多项模拟设计，以研究晶体管尺寸变化时，其元件特性的变化状况。以下提出其中几种模拟设计做说明。
图3为半导体层的通道宽度W固定时，晶体管的临界电压随半导体层的通道长度L变化的曲线图。图3中两条曲线分别代表通道宽度W为9.2μm和13.2μm时，晶体管的临界电压(threshold voltage)Vth是随通道长度L先上升而后稳定一区间后下降。其中X轴上所标记的通道长度L为对数尺度(Logarithmic Scale)。于此实验结果可知，当通道长度L介于4μm～10μm会有较佳的临界电压Vth一致性，且临界电压Vth较偏正(NMOS prefer)。当通道长度L小于4μm或大于10μm，临界电压Vth的一致性较差且朝负偏。
图4A、图4B为温度条件25度C，半导体层的通道长度L为3.4μm到5.4μm，通道宽度W为10μm到1000μm的情况下，分别检视晶体管的临界电压以及磁滞现象(Hysteresis)的相关曲线图。实验中，通道长度L为3.4μm，而通道宽度W为400μm及1000μm的情况下，通道区无法曝开，源极/漏极(S/D)直接导通而无数值。当通道长度L大于4.4μm，可以得到较一致且偏正的临界电压Vth(图4A)，且磁滞(Hys.，电压差，单位伏特(V))较不易随着通道宽度W的改变而剧烈变化(图4B)。图4B的结果也显示，当通道长度L大于4.4μm，磁滞是随通道宽度W的增加而变大，例如通道宽度W为1000μm时磁滞最大，大于通道宽度W为10μm、50μm时的磁滞。
图5A、图5B为温度条件70度C，半导体层的通道长度L为3.4μm到5.4μm，通道宽度W为10μm到1000μm的情况下，分别检视晶体管的临界电压以及磁滞现象(Hysteresis)的相关曲线图。类似图4A、图4B的结果，通道长度L为3.4μm，而通道宽度W400μm及1000μm的情况下，通道区无法曝开，源极/漏极(S/D)直接导通而无数值。当通道长度L大于4.4μm，可以得到较一致且偏正的临界电压Vth(图5A)，且磁滞现象较不易随着通道宽度W的改变而剧烈变化(图5B)。图5B的结果也显示，当通道长度L大于4.4μm，磁滞现象随通道宽度W的增加而变大。因此，比较图4A、图4B和图5A、图5B，实验结果显示当温度从25度C上升至70度C，晶体管的临界电压和磁滞现象的趋势是类似的。
图6A、图6B为温度条件70度C，半导体层的通道长度L为3.4μm到5.4μm，通道宽度W为10μm到1000μm的情况下，分别量测各通道宽度W的正栅极偏压偏移(positive gate-biostemperature stress，PBTS)情况和负栅极偏压偏移(negative gate-bios temperaturestress，NBTS)情况的相关曲线图。通道长度L为3.4μm，而通道宽度W为400μm及1000μm的情况下，通道区无法曝开，源极/漏极(S/D)直接导通而无数值。当通道长度L大于4.4μm，通道宽度W愈大，正栅极偏压偏移值PBTS愈小(图6A)(但需考虑磁滞现象)。当通道长度L大于4.4μm，通道宽度W小于50μm的负栅极偏压偏移值NBTS较小且较稳定(NMOS(IGZO做主动层)较佳)。
图7A-图7F为摄氏温度25度时，对模拟晶体管进行操作所得到的栅极电压(Vg)-源极电流(Id)的曲线图，其中通道宽度W固定为500μm，而通道长度L则分别为3.8μm、4.8μm、5.8μm、6.8μm、7.8μm和8.8μm。图7A-图7F中，各附图绘制出晶体管的V-I特性曲线，包括曲线HY01、曲线HY02和曲线HY03，首先是由负电压扫到正电压量测电流值得到曲线HY01，接着再由正电压扫到负电压量测电流值得到曲线HY02，最后再由负电压扫到正电压量测电流值得到曲线HY03，而在一预定电流值下，HY01与HY02的电压差即代表磁滞效应的大小。图8A是根据图7A-图7F所得到的起始临界电压(initial Vth)相应于通道长度L做变化的关系图。其中是根据图7A-图7F的源极电流(Id)值为1×10-8安培时于曲线HY01上相应的栅极电压(Vg)而得到图8A中该些数值点。图8B是根据图7A-图7F所得到的偏压(bias，也代表磁滞)相应于通道长度L做变化的关系图。其中是根据图7A-图7F的源极电流(Id)值为1×10-9安培时，在曲线HY01和HY02上相应的栅极电压差值而得到图8B中的该些偏压数值点。
根据图8A、图8B的实验结果，通道宽度W固定为500μm时，当通道长度L愈大，起始临界电压(Vth)数值愈往正值靠近(图8A)，且偏压愈小(图8B)代表磁滞愈小。如通道长度L为8.8μm时偏压为2.47717V。而磁滞愈小晶体管的电性表现越好。
由上述实验数据，通道宽度W及通道长度L分别有较佳的设计范围，通道宽度W及通道长度L的缩小幅度与像素电极PE的缩小幅度会具有差异(BCE IGZO TFT主动层需保持一定的尺寸而较难以压缩)。考虑TFT充电能力与对电容负载的关系，可表示为：
其中RIGZO为半导体层14(如IGZO)自身的电阻，(W/L)/RIGZO代表TFT充电能力，其正比于电容负载C。
其中RIGZO＝ρ(L/(W*dIGZO)，电容负载C可表示为mPx 2，因此上式可代换如下(其中m,n,a,b为常数参数)：
并做运算整理如下：
因此通道宽度W可整理为下列式(1)：
其中，b为寄生电容产生的常数参数。
因此，式(1)为和通道长度L、像素间距Px和半导体层厚度d相关的通道宽度W的模拟关系式。
而根据式(1)和运用一般产品的设计参数规格(例如电压常数，操作电压范围和像素电压等)，可获得如图9A、图9B所示的在维持TFT充电能力的情况下，TFT与像素设计的相关模拟设计曲线。之后，依照如式(1)和图9A、图9B的模拟设计曲线和一般产品现有的设计参数规格去进行阵列产品的制作。而后，并对制得的产品进行电性测试，发现该些产品的确都可以正常运作并具有良好的电子特性。
图10A、图10B是显示实际制作产品的相关数值点(实验值)，以及显示图9A、图9B所示的模拟设计曲线(图中虚线)。从图10A可看出实际制作产品的相关数值点的确接近而符合图9A的模拟设计曲线。而从图10B可看出实际制作产品的相关数值点是落在两条的模拟设计曲线的b值＝4.535和b值＝1.535的范围之间。其中a＝0.008。因此，考虑到制作工艺变异和材料选择的不同，一实施例中，是将通道宽度W表示为下式：
并进一步整理为下式(2)：
其中d为半导体层厚度(如图1中的半导体层14)，L为通道长度、Px为像素间距。而式(2)中，宽度、长度、厚度、间距等单位例如皆为μm。
因此，实施例中通道宽度W的设计可符合式(2)的关系式，且依实施例所设计的产品经检验的确仍符合产品的电性要求。
再者，于一实施例，通道宽度W例如是介于4μm至10μm之间、较佳是介于4μm至6μm之间，而通道长度L例如是介于3μm至8μm之间、较佳是介于3μm至5μm之间。于一实施例，通道宽度W与通道长度L的比值(W/L)例如是介于0.5至2之间。相关技术者当知，前述尺寸如通道宽度W、通道长度L等数值可因应用产品的规格不同(如电性要求和限制不同)而做适当选择，因此该些数值是做参考之用，而非限制本发明之用。
根据上述，本发明提出的晶体管阵列基板的像素结构设计，例如BCE-type TFT阵列基板上的晶体管，其半导体层(如IGZO层)于第二方向D2(i.e.垂直于通道长度方向)上的通道宽度W的设计可符合实施例所提出的关系式(2)。而实施例中进一步的检验依实施例所设计制得的产品，证明其的确仍符合产品的电性要求。因此，实施例提出的设计可使应用产品具有缩小的像素尺寸时(例如高分辨率的应用产品)，相关元件的尺寸可以相应地缩减，例如半导体层(如IGZO层)的通道宽度和通道长度可根据式(2)而做缩减调整，但又可符合产品的操作规格，维持显示面板的良好电子特性，例如晶体管的充电能力和电容负载仍然符合一般应用产品的需求。
综上所述，虽然结合以上实施例揭露了本发明，然而其并非用以限定本发明。本发明所属技术领域中熟悉此技术者，在不脱离本发明的精神和范围内，可作各种的更动与润饰。因此，本发明的保护范围应以附上的权利要求所界定的为准。

Claims (10)

1.一种显示面板，包含：
第一基板，包含：
基材，
第一导线，设置在该基材上并沿一第一方向延伸；
第二导线与一第三导线，沿一第二方向延伸且间隔排列，该第二导线与该第三导线并与该第一导线交错设置；
接触垫，介于该第二导线与该第三导线之间；
半导体层，与该接触垫及该第二导线连接，且该半导体层具有一厚度d(μm)；以及
像素电极，连接该接触垫；
第二基板，与该第一基板相对设置；以及
显示层，设置于该第一基板与该第二基板之间，
其中，该半导体层具有一通道宽度W(μm)，且在该接触垫与该第二导线间具有一通道长度L(μm)，在该第一方向上该第二导线与该第三导线具有一像素间距Px(μm)，且该通道宽度W符合下列公式：
<mrow> <mn>1.535</mn> <mo>&amp;le;</mo> <mi>W</mi> <mo>-</mo> <mn>0.008</mn> <mo>&amp;times;</mo> <mrow> <mo>(</mo> <mfrac> <mrow> <msub> <mi>P</mi> <mi>x</mi> </msub> <mo>&amp;times;</mo> <mi>L</mi> </mrow> <msqrt> <mi>d</mi> </msqrt> </mfrac> <mo>)</mo> </mrow> <mo>&amp;le;</mo> <mn>4.535.</mn> </mrow>
2.如权利要求1所述的显示面板，其中该半导体层包含金属氧化物半导体。
3.如权利要求1所述的显示面板，其中该通道宽度W介于4μm至10μm之间，该通道长度L介于3μm至8μm之间。
4.如权利要求3所述的显示面板，其中该通道宽度W介于4μm至6μm之间，该通道长度L介于3μm至5μm之间。
5.如权利要求1所述的显示面板，其中该通道宽度W与该通道长度L的比值介于0.5至2之间。
6.如权利要求1所述的显示面板，其中该半导体层包含通道区，该通道区具有该通道宽度W与该通道长度L，且该通道长度L平行于该第一方向。
7.如权利要求1所述的显示面板，其中该第一方向与该第二方向垂直。
8.如权利要求1所述的显示面板，其中该第一导线、该第二导线与该第三导线对应一像素区域。
9.如权利要求1所述的显示面板，还包含第一绝缘层，设置于该第一导线与该半导体层之间，以及第二绝缘层，设置于该接触垫与像素电极之间，且该第二绝缘层具有孔洞，该像素电极通过该孔洞电连接该接触垫。
10.如权利要求9所述的显示面板，其中该第一绝缘层厚度介于0.25μm至0.45μm之间。
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TWI608599B (zh) 2017-12-11
TW201733087A (zh) 2017-09-16
CN107154402B (zh) 2019-12-10
US20170256653A1 (en) 2017-09-07

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