TWI608599B - 顯示面板 - Google Patents

顯示面板 Download PDF

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TWI608599B
TWI608599B TW105106313A TW105106313A TWI608599B TW I608599 B TWI608599 B TW I608599B TW 105106313 A TW105106313 A TW 105106313A TW 105106313 A TW105106313 A TW 105106313A TW I608599 B TWI608599 B TW I608599B
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Taiwan
Prior art keywords
wire
channel
display panel
substrate
semiconductor layer
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TW105106313A
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TW201733087A (zh
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Chao Hsiang Wang
Yi Ching Chen
Kuan Feng Lee
Hsin Hung Lin
Shou Pu Yeh
yuan lin Wu
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Innolux Corp
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Priority to TW105106313A priority Critical patent/TWI608599B/zh
Priority to CN201610837571.XA priority patent/CN107154402B/zh
Priority to US15/436,752 priority patent/US10304965B2/en
Publication of TW201733087A publication Critical patent/TW201733087A/zh
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Publication of TWI608599B publication Critical patent/TWI608599B/zh

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    • H01L29/772—Field effect transistors
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    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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    • G02—OPTICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/136286—Wiring, e.g. gate line, drain line
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    • G02—OPTICS
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    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
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    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Description

顯示面板
本發明是有關於一種顯示面板，且特別是有關於顯示面板之電晶體陣列基板的畫素結構。
不論在工作處理學習上或是個人休閒娛樂上，具顯示面板的電子產品，包括智慧型手機(SmartPhone)、平板電腦(Pad)、筆記型電腦(Notebook)、顯示器(Monitor)到電視(TV)等許多相關產品，已是現代人不可或缺的必需品。其中又以液晶顯示面板最為普遍。液晶顯示面板(LCD)係利用電壓驅動液晶(LCs)轉動進而調整亮度灰階而可構成一種平面顯示器、電子視覺顯示器，及影像顯示器。由於液晶顯示面板在絕大多數應用上具有更簡潔、更輕盈、可攜帶、更低價、更高可靠度以及讓眼睛更舒適的功能，因此已經廣泛地取代了陰極射線管顯示器(CRT)，成為最廣泛使用的顯示器，同時提供多樣性包括尺寸、形狀、解析度等多種選擇。
隨著應用產品的微型化和解析度增加的需求，顯示面板上的半導體裝置尺寸也日益減小。然而，顯示面板在製作時需考量各元件如相關金屬和半導體元件的圖案和尺寸是否可使 製得之顯示裝置具有穩定良好的電子特性，以符合應用產品要求的各項規格，例如符合高穿透率、高良率、良好的電性可靠度和顯示品質穩定等要求。顯示面板相關元件和各材料層的設計不良，可能造成電性表現降低，進而影響顯示品質。以一背通道蝕刻型電晶體(BCE-type TFT)陣列基板上的電晶體為例，目前受限於電晶體的特性，其做為主動層的半導體層如氧化銦鎵鋅(indium gallium zinc oxide，IGZO)層在寬度和長度上縮減的幅度，已無法直接正比於畫素尺寸縮減的幅度。
本發明係有關於一種顯示面板，其電晶體陣列基板的畫素結構之尺寸設計，可使畫素結構縮小時仍可維持顯示面板良好的電子特性。
根據本發明，係提出一種顯示面板，包括一第一基板、與第一基板相對設置的一第二基板，和設置於第一基板與第二基板之間的一顯示層。第一基板包含一基材；一第一導線，設置在基材上並沿第一方向延伸；一第二導線與一第三導線，沿第二方向延伸且互相間隔排列，第二導線與第三導線並與第一導線交錯設置；一接觸墊，介於第二導線與第三導線之間；一半導體層，與接觸墊及第二導線連接，且半導體層具有一厚度d(μm)；以及一畫素電極，連接接觸墊。其中，半導體層具有一通道寬度W(μm)，在接觸墊與第二導線間具有一通道長度L(μm)，在第一方向上第二導線與第三導線具有一畫素間距Px(μm)，且通道寬 度W符合下列公式：
根據本發明，係提出一種電晶體陣列基板，此基板包含複數個陣列之畫素區域，該些畫素區域其中之一係包括上述第一基板之結構，且通道寬度W係符合上方公式。
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉實施例，並配合所附圖式，作詳細說明如下：
S1‧‧‧第一基板
10‧‧‧基材
12‧‧‧閘極電極
13‧‧‧第一絕緣層
14‧‧‧半導體層
Ach‧‧‧通道區
d‧‧‧半導體層之厚度
15‧‧‧源極電極
16‧‧‧汲極電極
18‧‧‧第二絕緣層
19‧‧‧第三絕緣層
PE‧‧‧畫素電極
21‧‧‧第一導線
22‧‧‧第二導線
23‧‧‧第三導線
PCONT‧‧‧接觸墊
Vcont‧‧‧孔洞
L‧‧‧通道長度
W‧‧‧通道寬度
Px‧‧‧畫素間距
S2‧‧‧第二基板
LC‧‧‧液晶層
D1‧‧‧第一方向
D2‧‧‧第二方向
第1圖為本揭露一顯示面板實施例之背通道蝕刻型電晶體陣列基板之液晶顯示面板的剖面示意圖。
第2A圖為本揭露該顯示面板實施例之背通道蝕刻型電晶體陣列基板的局部上視圖。
第2B圖為第2A圖中圈選處之局部放大圖。
第3圖為半導體層之通道寬度W固定時，電晶體的臨界電壓隨半導體層之通道長度L變化之曲線圖。
第4A、4B圖為溫度條件25度C，半導體層之通道長度L為3.4μm到5.4μm，通道寬度W為10μm到1000μm的情況下，分別檢視電晶體的臨界電壓以及磁滯現象之相關曲線圖。
第5A、5B圖為溫度條件70度C，半導體層之通道長度L為3.4μm到5.4μm，通道寬度W為10μm到1000μm的情況下， 分別檢視電晶體的臨界電壓以及磁滯現象之相關曲線圖。
第6A、6B圖為溫度條件70度C，半導體層之通道長度L為3.4μm到5.4μm，通道寬度W為10μm到1000μm的情況下，分別量測各通道寬度W的正閘極偏壓偏移情況和負閘極偏壓偏移情況之相關曲線圖。
第7A-7F圖為攝氏溫度25度時，對模擬電晶體進行操作所得到的閘極電壓(Vg)-源極電流(Id)之曲線圖，其中通道寬度W固定為500μm，而通道長度L則由3.8μm變化至8.8μm。
第8A圖係根據第7A-7F圖所得到之起始臨界電壓(initial Vth)相應於通道長度L做變化的關係圖。
第8B圖係根據第7A-7F圖所得到之偏壓(bias，也代表磁滯)相應於通道長度L做變化的關係圖。
第9A、9B圖係顯示在維持TFT充電能力的情況下，TFT與畫素設計之相關模擬設計曲線。
第10A、10B圖係顯示實際製作產品的相關數值點(實驗值)以及顯示第9A、9B圖所示之模擬設計曲線(虛線)。
本揭露之實施例係提出一種顯示面板，其關於電晶體陣列基板的特殊畫素結構設計，如何在畫素尺寸縮小時(例如高解析度之應用產品)，相關元件的尺寸可以相應地縮減(例如是主動層的通道寬度和通道長度如何相應變化)，但又可維持顯示面板的良好電子特性，包括使電晶體的充電能力和電容負載仍然符合 一般應用產品的需求(如符合產品的操作規格)。
以下係參照所附圖式詳細敘述本揭露之實施例。本揭露之實施例例如是應用於背通道蝕刻型電晶體(BCE-type TFT)陣列基板之液晶顯示面板。需注意的是，實施例所提出的實施態樣之結構和內容僅為舉例說明之用。本揭露並非顯示出所有可能的實施例，相關領域者可在不脫離本揭露之精神和範圍內對實施例之結構加以變化與修飾，以符合實際應用所需。因此，未於本揭露提出的其他實施態樣也可能可以應用。再者，圖式係已簡化以利清楚說明實施例之內容，圖式上的尺寸比例並非按照實際產品等比例繪製。因此，說明書和圖示內容僅作敘述實施例之用，而非作為限縮本揭露保護範圍之用。再者，實施例中相同或類似的標號係用以標示相同或類似之部分。
另外，說明書與請求項中所使用的序數例如”第一”、”第二”、”第三”等之用詞，以修飾請求項之元件，其本身並不意含及代表該請求元件有任何之前的序數，也不代表某一請求元件與另一請求元件的順序、或是製造方法上的順序，該些序數的使用僅用來使具有某命名的一請求元件得以和另一具有相同命名的請求元件能作出清楚區分。以下係以背通道蝕刻型電晶體陣列基板之液晶顯示面板做實施例之說明。
第1圖為本揭露一顯示面板實施例之背通道蝕刻型電晶體陣列基板的剖面示意圖。第2A圖為該顯示面板實施例之背通道蝕刻型電晶體陣列基板的局部上視圖。第2B圖為第2A圖 中圈選處之局部放大圖。如第1圖所示，實施例之顯示面板包括一第一基板S1、與第一基板S1相對設置一第二基板S2和設置於第一基板S1與第二基板S2之間之一顯示層。實施例中，第一基板S1例如是一電晶體陣列基板，第二基板S2例如是一彩色濾光基板，顯示層為液晶層LC。此實施例係以源極電極15和汲極電極16(i.e.第二金屬層)直接形成於半導體層(i.e.主動層)上以位於通道區Ach之兩側為例作第一基板S1之結構說明。
如第1圖所示，設置在一基材10上的多個電晶體其中之一係包含一閘極電極12設置在基材10上，一第一絕緣層13設置在閘極電極12上，一半導體層14(做為主動層)設置在第一絕緣層13上且半導體層14包含一通道區Ach，一源極電極15和一汲極電極16(兩者為第二金屬層)設置在半導體層14上。於一背通道蝕刻型電晶體(BCE-type TFT)陣列基板中，半導體層14的材料例如是包含金屬氧化物半導體，如氧化銦鎵鋅(indium gallium zinc oxide，IGZO)。另外，電晶體更包括一第二絕緣層18覆蓋源極電極15和汲極電極16，以及位於第二絕緣層18上的一第三絕緣層19。一實施例中，第一絕緣層13的厚度例如是(但不限制是)介於0.25μm至0.45μm之間。
於各畫素區域中，更包括一畫素電極PE(材料例如是ITO)透過第二絕緣層18的孔洞Vcont而電性連接第二金屬層，例如連接汲極電極16(汲極電極16亦即接觸墊PCONT)，如第1圖所示。亦請參照第2A、2B圖之畫素區域的局部上視圖。其 中第1圖為沿第2B圖之剖面線C1-C1之剖面示意圖。於一個畫素區域中，第一基板S1係包括設置在基材10上並沿第一方向D1延伸的一第一導線21，第一導線21包含如第1圖之閘極電極12；沿第二方向D2延伸且互相間隔排列的一第二導線22(i.e對應於第1圖之源極電極15，即，資料線)與一第三導線23(即相鄰之另一條資料線)，且第二導線22與第三導線23並與第一導線21交錯設置；介於第二導線22與第三導線23之間的接觸墊PCONT(即，第1圖之汲極電極16)，畫素電極PE則與接觸墊PCONT連接，且本實施例中第二導線22、第三導線23與接觸墊PCONT是由同一金屬層圖案化所形成；以及連接接觸墊PCONT及第二導線22的半導體層14(例如IGZO層)，且半導體層14具有一厚度d(μm，請參照第1圖)。因此，第一導線21、第二導線22與第三導線23係對應一個畫素區域。再者，於一實施例中，第一方向D1係與第二方向D2垂直。當然，本揭露並不非侷限於第1圖所繪示之細部結構，例如第一方向D1亦可與第二方向D2形成一夾角，其範圍例如是在75度至90度之間。第二基板S2亦省略了其他元件，以利清楚顯示本揭露。
本揭露係針對畫素尺寸和電晶體尺寸(i.e.通道尺寸)進行相關研究與設計。如第2B圖所示，半導體層14於第二方向D2係具有一第一寬度(即標號W所指)(μm)，在第一方向D1上接觸墊PCONT與第二導線22具有一第一間距(即標號L所指)(μm)。半導體層14包含一通道區Ach(大致位於第二導線22和接觸墊 PCONT之間)，且第一間距即為通道長度(channel length)L，一般是以第二導線22與接觸墊PCONT間的最短距離為基準，第一寬度即為通道寬度(channel width)W，通道長度L與通道寬度W為本領域人士對於電晶體的通常知識，故不在此多加贅述。再者，在第一方向D1上第二導線22與第三導線23具有一畫素間距Px(μm)。
實施例中，係根據上述如第2A圖、第2B圖之結構中的半導體層14尺寸進行多項模擬設計，以研究電晶體尺寸變化時，其元件特性的變化狀況。以下提出其中幾種模擬設計做說明。
第3圖為半導體層之通道寬度W固定時，電晶體的臨界電壓隨半導體層之通道長度L變化之曲線圖。第3圖中兩條曲線分別代表通道寬度W為9.2μm和13.2μm時，電晶體的臨界電壓(threshold voltage)Vth係隨通道長度L先上升而後穩定一區間後下降。其中X軸上所標記的通道長度L為對數尺度(Logarithmic Scale)。於此實驗結果可知，當通道長度L介於4μm~10μm會有較佳的臨界電壓Vth一致性，且臨界電壓Vth較偏正(NMOS prefer)。當通道長度L小於4μm或大於10μm，臨界電壓Vth的一致性較差且朝負偏。
第4A、4B圖為溫度條件25度C，半導體層之通道長度L為3.4μm到5.4μm，通道寬度W為10μm到1000μm的情況下，分別檢視電晶體的臨界電壓以及磁滯現象(Hysteresis)之相關曲線圖。實驗中，通道長度L為3.4μm，而通道寬度W為400μm 及1000μm的情況下，通道區無法曝開，源極/汲極(S/D)直接導通而無數值。當通道長度L大於4.4μm，可以得到較一致且偏正的臨界電壓Vth(第4A圖)，且磁滯(Hys.，電壓差，單位伏特(V))較不易隨著通道寬度W的改變而劇烈變化(第4B圖)。第4B圖的結果亦顯示，當通道長度L大於4.4μm，磁滯係隨通道寬度W的增加而變大，例如通道寬度W為1000μm時磁滯最大，大於通道寬度W為10μm、50μm時之磁滯。
第5A、5B圖為溫度條件70度C，半導體層之通道長度L為3.4μm到5.4μm，通道寬度W為10μm到1000μm的情況下，分別檢視電晶體的臨界電壓以及磁滯現象(Hysteresis)之相關曲線圖。類似第4A、4B圖之結果，通道長度L為3.4μm，而通道寬度W400μm及1000μm的情況下，通道區無法曝開，源極/汲極(S/D)直接導通而無數值。當通道長度L大於4.4μm，可以得到較一致且偏正的臨界電壓Vth(第5A圖)，且磁滯現象較不易隨著通道寬度W的改變而劇烈變化(第5B圖)。第5B圖的結果亦顯示，當通道長度L大於4.4μm，磁滯現象隨通道寬度W的增加而變大。因此，比較第4A、4B圖和第5A、5B圖，實驗結果顯示當溫度從25度C上升至70度C，電晶體的臨界電壓和磁滯現象的趨勢是類似的。
第6A、6B圖為溫度條件70度C，半導體層之通道長度L為3.4μm到5.4μm，通道寬度W為10μm到1000μm的情況下，分別量測各通道寬度W的正閘極偏壓偏移(positive gate- bios temperature stress，PBTS)情況和負閘極偏壓偏移(negative gate-bios temperature stress，NBTS)情況之相關曲線圖。通道長度L為3.4μm，而通道寬度W為400μm及1000μm的情況下，通道區無法曝開，源極/汲極(S/D)直接導通而無數值。當通道長度L大於4.4μm，通道寬度W愈大，正閘極偏壓偏移值PBTS愈小(第6A圖)(但需考量磁滯現象)。當通道長度L大於4.4μm，通道寬度W小於50μm的負閘極偏壓偏移值NBTS較小且較穩定(NMOS(IGZO做主動層)較佳)。
第7A-7F圖為攝氏溫度25度時，對模擬電晶體進行操作所得到的閘極電壓(Vg)-源極電流(Id)之曲線圖，其中通道寬度W固定為500μm，而通道長度L則分別為3.8μm、4.8μm、5.8μm、6.8μm、7.8μm和8.8μm。第7A-7F圖中，各圖式係繪製出電晶體的V-I特性曲線，包括曲線HY01、曲線HY02和曲線HY03，首先是由負電壓掃到正電壓量測電流值得到曲線HY01，接著再由正電壓掃到負電壓量測電流值得到曲線HY02，最後再由負電壓掃到正電壓量測電流值得到曲線HY03，而在一預定電流值下，HY01與HY02的電壓差即代表磁滯效應的大小。第8A圖係根據第7A-7F圖所得到之起始臨界電壓(initial Vth)相應於通道長度L做變化的關係圖。其中係根據第7A-7F圖之源極電流(Id)值為1×10-8安培時於曲線HY01上相應的閘極電壓(Vg)而得到第8A圖中該些數值點。第8B圖係根據第7A-7F圖所得到之偏壓(bias，也代表磁滯)相應於通道長度L做變化的關係圖。其中係根 據第7A-7F圖之源極電流(Id)值為1×10-9安培時，於曲線HY01和HY02上相應的閘極電壓差值而得到第8B圖中的該些偏壓數值點。
根據第8A、8B圖之實驗結果，通道寬度W固定為500μm時，當通道長度L愈大，起始臨界電壓(Vth)數值愈往正值靠近(第8A圖)，且偏壓愈小(第8B圖)代表磁滯愈小。如通道長度L為8.8μm時偏壓為2.47717V。而磁滯愈小電晶體的電性表現越好。
由上述實驗數據，通道寬度W及通道長度L分別有較佳的設計範圍，通道寬度W及通道長度L的縮小幅度與畫素電極PE的縮小幅度會具有差異(BCE IGZO TFT主動層需保持一定的尺寸而較難以壓縮)。考量TFT充電能力與對電容負載的關係，可表示為： 其中RIGZO為半導體層14(如IGZO)自身的電阻，(W/L)/RIGZO代表TFT充電能力，其正比於電容負載C。
其中RIGZO=ρ(L/(W*dIGZO)，電容負載C可表示為mPx 2，因此上式可代換如下(其中m,n,a,b為常數參數)：，並做運算整理如下： ，因此通道寬度W可整理為下列式(1)： 其中，b為寄生電容產生的常數參數。
因此，式(1)係為和通道長度L、畫素間距Px和半導體層厚度d相關的通道寬度W之模擬關係式。
而根據式(1)和運用一般產品的設計參數規格(例如電壓常數，操作電壓範圍和畫素電壓等)，可獲得如第9A、9B圖所示之在維持TFT充電能力的情況下，TFT與畫素設計之相關模擬設計曲線。之後，依照如式(1)和第9A、9B圖之模擬設計曲線和一般產品現有的設計參數規格去進行數組產品之製作。而後，並對製得之產品進行電性測試，發現該些產品的確都可以正常運作並具有良好的電子特性。
第10A、10B圖係顯示實際製作產品的相關數值點(實驗值)，以及顯示第9A、9B圖所示之模擬設計曲線(圖中虛線)。從第10A圖可看出實際製作產品的相關數值點的確接近而符合第9A圖之模擬設計曲線。而從第10B圖可看出實際製作產品的相關數值點係落在兩條之模擬設計曲線之b值=4.535和b值=1.535的範圍之間。其中a=0.008。因此，考量到製程變異和材 料選擇的不同，一實施例中，係將通道寬度W表示為下式：，並進一步整理為下式(2)： 其中d為半導體層厚度(如第1圖中之半導體層14)，L為通道長度、Px為畫素間距。而式(2)中，寬度、長度、厚度、間距等單位例如皆為μm。
因此，實施例中通道寬度W的設計可符合式(2)的關係式，且依實施例所設計的產品經檢驗的確仍符合產品的電性要求。
再者，於一實施例，通道寬度W例如是介於4μm至10μm之間、較佳是介於4μm至6μm之間，而通道長度L例如是介於3μm至8μm之間、較佳是介於3μm至5μm之間。於一實施例，通道寬度W與通道長度L的比值(W/L)例如是介於0.5至2之間。相關技藝者當知，前述尺寸如通道寬度W、通道長度L等數值可因應用產品的規格不同(如電性要求和限制不同)而做適當選擇，因此該些數值係做參考之用，而非限制本揭露之用。
根據上述，本揭露提出之電晶體陣列基板之畫素結構設計，例如BCE-type TFT陣列基板上的電晶體，其半導體層(如IGZO層)於第二方向D2(i.e.垂直於通道長度方向)上的通道寬度W之設計係可符合實施例所提出的關係式(2)。而實施例中進一步 的檢驗依實施例所設計製得的產品，證明其的確仍符合產品的電性要求。因此，實施例提出之設計可使應用產品具有縮小的畫素尺寸時(例如高解析度之應用產品)，相關元件的尺寸可以相應地縮減，例如半導體層(如IGZO層)的通道寬度和通道長度可根據式(2)而做縮減調整，但又可符合產品的操作規格，維持顯示面板的良好電子特性，例如電晶體的充電能力和電容負載仍然符合一般應用產品的需求。
綜上所述，雖然本發明已以實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。
12‧‧‧閘極電極
14‧‧‧半導體層
Ach‧‧‧通道區
PE‧‧‧畫素電極
21‧‧‧第一導線
22‧‧‧第二導線
23‧‧‧第三導線
PCONT‧‧‧接觸墊
VCONT‧‧‧孔洞
L‧‧‧通道長度
W‧‧‧通道寬度
Px‧‧‧畫素間距

Claims (9)

  1. 一種顯示面板，包含：一第一基板，包含：一基材，一第一導線，設置在該基材上並沿一第一方向延伸；一第二導線與一第三導線，沿一第二方向延伸且間隔排列，該第二導線與該第三導線並與該第一導線交錯設置，其中該第一導線與該第二導線之重疊部分具有一第一寬度平行該第二方向；一接觸墊，介於該第二導線與該第三導線之間；一半導體層，對應該第一導線設置，與該接觸墊及該第二導線連接，且該半導體層具有一厚度d(μm)，其中該半導體層與該第二導線之重疊部分具有一第二寬度平行該第二方向，該第二寬度小於該第一寬度，且該半導體層包含金屬氧化物半導體；以及一畫素電極，連接該接觸墊；一第二基板，與該第一基板相對設置；以及一顯示層，設置於該第一基板與該第二基板之間，其中，該半導體層具有一通道寬度W(μm)，且在該接觸墊與該第二導線間具有一通道長度L(μm)，在該第一方向上該第二導線與該第三導線具有一畫素間距Px(μm)，且該通道寬度W符合下列公式： 。
  2. 如申請專利範圍第1項所述之顯示面板，其中該通道寬度W介於4μm至10μm之間，該通道長度L介於3μm至8μm之間。
  3. 如申請專利範圍第2項所述之顯示面板，其中該通道寬度W介於4μm至6μm之間，該通道長度L介於3μm至5μm之間。
  4. 如申請專利範圍第1項所述之顯示面板，其中該通道寬度W與該通道長度L的比值介於0.5至2之間。
  5. 如申請專利範圍第1項所述之顯示面板，其中該半導體層包含一通道區，該通道區具有該通道寬度W與該通道長度L，且該通道長度L係平行於該第一方向。
  6. 如申請專利範圍第1項所述之顯示面板，其中該第一方向係與該第二方向垂直。
  7. 如申請專利範圍第1項所述之顯示面板，其中該第一導線、該第二導線與該第三導線係對應一畫素區域。
  8. 如申請專利範圍第1項所述之顯示面板，更包含一第一絕緣層設置於該第一導線與該半導體層之間，以及一第二絕緣層設置於該接觸墊與畫素電極之間，且該第二絕緣層具有一孔洞，該畫素電極透過該孔洞電性連接該接觸墊。
  9. 如申請專利範圍第8項所述之顯示面板，其中該第一絕緣層厚度介於0.25μm至0.45μm之間。
TW105106313A 2016-03-02 2016-03-02 顯示面板 TWI608599B (zh)

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