CN107154403B - 晶体管阵列基板及应用的显示面板 - Google Patents

晶体管阵列基板及应用的显示面板 Download PDF

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CN107154403B
CN107154403B CN201611108620.2A CN201611108620A CN107154403B CN 107154403 B CN107154403 B CN 107154403B CN 201611108620 A CN201611108620 A CN 201611108620A CN 107154403 B CN107154403 B CN 107154403B
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conductive layer
layer
substrate
disposed
protrusion
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CN107154403A (zh
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林峻良
崔博钦
陈宏昆
许乃方
陈奕静
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Innolux Corp
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Innolux Display Corp
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Abstract

本发明公开一种晶体管阵列基板及应用的显示面板。该晶体管阵列基板包含多个晶体管设置在一基材上，其中之一的晶体管包括设置在基材上的一栅极电极、设置在栅极电极上的一第一绝缘层、设置在第一绝缘层上且包含一通道区的一有源层、设置在有源层上的一源极电极和一漏极电极。其中源极电极和漏极电极中的至少一者包含：设置在有源层上的一第一导电层，和设置在第一导电层上并与第一导电层接触的一第二导电层。其中第二导电层暴露出第一导电层的部分上表面，以使第一导电层于第二导电层的边缘处具有一第一突出部朝向通道区延伸。

Description

晶体管阵列基板及应用的显示面板
技术领域
本发明涉及一种晶体管阵列基板及应用的显示面板，且特别是涉及具双层结构的第二金属层的一种晶体管阵列基板及应用的显示面板，可改善显示面板的电子特性和提高可靠度。
背景技术
具显示面板的电子产品已是现代人不论在工作处理学习上、或是个人休闲娱乐上，不可或缺的必需品，包括智慧型手机(SmartPhone)、平板电脑(Pad)、笔记型电脑(Notebook)、显示器(Monitor)到电视(TV)等许多相关产品。其中又以液晶显示面板最为普遍。液晶显示面板(LCD)是利用电压驱动液晶(LCs)转动进而调整亮度灰阶而可构成一种平面显示器、电子视觉显示器，及影像显示器。
显示装置在制作时需注意制作工艺上的细节，例如进行金属层和半导体层等各层图案化时需精确，而各层的相对位置与图案设计也需考虑到是否可使制得的显示装置具有稳定良好的电子特性，以符合产品要求的各项规格，例如符合高穿透率、高良率、良好可靠度和显示品质稳定等要求。显示装置相关元件和各材料层的设计不良，可能造成电性表现降低，进而影响显示品质。
发明内容
本发明的目的在于提供一种晶体管阵列基板及应用的显示面板，其具双层结构的第二金属层的设计可有效改善显示面板的电子特性和提高可靠度。
为达上述目的，本发明提出一种晶体管阵列基板，包含多个晶体管设置在一基材上，其中该些晶体管中的一晶体管包括设置在基材上的一栅极电极、设置在栅极电极上的一第一绝缘层、设置在第一绝缘层上且包含一通道区的一有源层、设置在有源层上的一源极电极和一漏极电极。其中源极电极和漏极电极中的至少一者包含：设置在有源层上的一第一导电层，和设置在第一导电层上并与第一导电层接触的一第二导电层。其中第二导电层暴露出第一导电层的部分上表面，以使第一导电层于第二导电层的边缘处具有一第一突出部朝向通道区延伸。
本发明还提出一种显示面板，包括一第一基板、与第一基板相对设置的一第二基板，和设置于第一基板与第二基板之间的一显示介质层。第一基板包括多个晶体管设置在一基材上，其中一晶体管包括上述的结构。
为了对本发明的上述及其他方面有更佳的了解，下文特举实施例，并配合所附附图，作详细说明如下：
附图说明
图1为本发明一实施例的具有晶体管阵列基板的液晶显示面板的剖面示意图；
图2A为一像素的电路图，图2B为图2A的栅极走线打开时的等效电路图，图2C为图2A的栅极走线关闭时的等效电路图；
图3为一应用例中，实施例的第一突出部长度与增加的寄生电容比值的曲线图；
图4为本发明另一实施例的晶体管阵列基板的剖面示意图；
图5，其为本发明又一实施例的晶体管阵列基板的剖面示意图；
图6A、图6B分别为本发明可应用的两种其他实施例的晶体管阵列基板的剖面示意图。
符号说明
S1：第一基板
10：基材
12：栅极电极
121：下导电层
122：上导电层
1211：第二突出部
L12：第二突出部的长度
13：第一绝缘层
14：有源层(主动层)
ACH：通道区
LCH：通道长度
14b：有源层的侧边
15：源极电极
16：漏极电极
151、161：第一导电层
152、162：第二导电层
1511、1611：第一突出部
1511a、1611a：第一底边
1511b、1611b：第一侧边
152a/162a：第二底边
152b/162b：第二侧边
152c、162c：第二导电层的上表面
θ1、θ2：夹角
L15、L16：第一突出部的长度
t15、t16：第二导电层的厚度
1513、1613：第三突出部
L15E、L16E：第三突出部的长度
18：第二绝缘层
19：第三绝缘层
S2：第二基板
D1：第一方向
D2：第二方向
Dis-1：第一距离
Dis-2：第二距离
3：显示介质层
P1、P2：线段
具体实施方式
本发明的实施例提出一种晶体管阵列基板及应用的显示面板，通过晶体管阵列基板的双层结构第二金属层的特殊设计，可防止金属氧化物渗入通道区的相关层，进而提升晶体管阵列基板的电子特性的稳定度，提高应用的显示面板的产品良率。再者，实施例的晶体管阵列基板仍然符合一般应用产品的需求，且与现有制作工艺相容性高，因此实施例所提出的设计不但可以使制得的阵列基板具有稳定优异的电子特性，也十分适合量产。
以下参照所附附图详细叙述本发明的其中几种实施态样。本发明的实施例例如是应用于背通道蚀刻型晶体管(BCE-type TFT)阵列基板的液晶显示面板。需注意的是，实施例所提出的多组实施态样的结构和内容仅为举例说明之用，本发明欲保护的范围并非仅限于所述的该些态样。需注意的是，本发明并非显示出所有可能的实施例，相关领域者可在不脱离本发明的精神和范围内对实施例的结构加以变化与修饰，以符合实际应用所需。因此，未在本发明提出的其他实施态样也可能可以应用。再者，附图已简化以利清楚说明实施例的内容，附图上的尺寸比例并非按照实际产品等比例绘制。因此，说明书和图示内容仅作叙述实施例之用，而非作为限缩本发明保护范围之用。再者，实施例中相同或类似的标号用以标示相同或类似的部分。
另外，说明书与权利要求中所使用的序数例如”第一”、”第二”、”第三”等的用词，以修饰权利要求的元件，其本身并不意含及代表该请求元件有任何之前的序数，也不代表某一请求元件与另一请求元件的顺序、或是制造方法上的顺序，该些序数的使用仅用来使具有某命名的一请求元件得以和另一具有相同命名的请求元件能作出清楚区分。
图1为本发明一实施例的具有晶体管阵列基板的液晶显示面板的剖面示意图。一显示面板包括一第一基板S1、与第一基板S1相对设置的一第二基板S2和设置于第一基板S1与第二基板S2之间的一显示介质层3。在一实施例中，第一基板S1例如是一晶体管阵列基板，第二基板S2例如是一彩色滤光基板，显示介质层3例如是液晶层。在另一实施例中，第一基板S1例如是一晶体管阵列基板，第二基板S2例如是一透明基板，显示介质层3例如是有机发光层。此实施例以源极电极和漏极电极(i.e.第二金属层)直接形成于有源层上以位于通道区的两侧为例作第一基板S1的结构说明，但本发明并不以此种形态及绘示的细部结构为限。第二基板S2省略了其他元件。
第一基板S1包含设置在一基材10上的多个晶体管。基材10可以是由硬性材料(例如玻璃)或是软性材料(例如塑胶)形成。如图1所示，多个晶体管其中之一包含一栅极电极12设置在基材10上，一第一绝缘层13设置在栅极电极12上，一有源层14设置在第一绝缘层13上且有源层14包含一通道区ACH，一源极电极15和一漏极电极16设置在有源层14上。根据实施例，源极电极15和漏极电极16中的至少一者包含至少两层导电层。本实施例中，源极电极15和漏极电极16可两者兼具实施例的两层导电层的设计，然而本实施例并不以此为限。
有源层14可由金属氧化物的材料形成，其金属可包含铟、镓、锌、锡、铝或上述的组合等，例如有源层14可以是氧化锌(indium zinc oxide，IZO)层、氧化铟镓锌(indiumgallium zinc oxide，IGZO)层或氧化锌锡(zinc tin oxide，ZSO)层等等。另外，晶体管还包括一第二绝缘层18覆盖源极电极15和漏极电极16，以及一第三绝缘层19形成于第二绝缘层18上。第一绝缘层13、第二绝缘层18和第三绝缘层19可以是单层或是多层结构。第一绝缘层13、第二绝缘层18和第三绝缘层19可使用有机或无机材料形成，有机材料可例如是全氟烷氧基树脂(perfluoroalkoxy，PFA)，无机材料可例如是氧化物(例如，氧化硅、氧化铝)、氮化物(例如，氮化硅)或氮氧化物(例如，氮氧化硅)等绝缘层材料制作。
如图1所示，源极电极15包括设置在有源层14上的一第一导电层151以及设置在第一导电层151上的一第二导电层152，且第二导电层152与第一导电层151接触，其中第二导电层152暴露出第一导电层151的部分上表面，以使第一导电层151于第二导电层152的边缘处具有第一突出部1511朝向通道区ACH延伸。
类似地，漏极电极16包括设置在有源层14上的一第一导电层161以及设置在第一导电层161上的一第二导电层162，且第二导电层162与第一导电层161接触，其中第二导电层162暴露出第一导电层161的部分上表面，以使第一导电层161于第二导电层162的边缘处具有第一突出部1611朝向通道区ACH延伸。
一实施例中，双层结构的源极电极15/漏极电极16例如是铜或铝/钛(Titanium)或钼(Molybdenum)结构，亦即下层的第一导电层151/161可包括金属钛或钼，上层的第二导电层152/162可包括金属铜或铝，下层金属钛或钼于上层金属铜或铝的边缘处具有第一突出部1511/1611。实施例可利用制作工艺条件的调节来达到应用产品所需的第一突出部1511/1611的状态，例如第一突出部的长度和/或侧边角度等相关参数。
一实施例中，在蚀刻(例如湿蚀刻)源极电极15/漏极电极16(i.e.第二金属层)的上层金属时，可通过过度蚀刻的方式，由此暴露出下层金层的部分上表面，而达到实施例的下层金属相较于上层金属具有第一突出部1511/1611的设计，如此可避免在蚀刻(例如湿蚀刻或干蚀刻)下层金属时造成底切(undercut)的情况发生。根据实验，湿蚀刻上层金属时比预计的蚀刻时间多20％～100％，使得上层金属(ex:Cu)在退后的距离至少为其厚度的20％～100％，用于定义出下层金属的突出部的长度。据此，一实施例中，第一突出部1511/1611的长度L15/L16可实质上大于等于第二导电层152/162的厚度(i.e.沿第二方向D2)t15/t16的20％。
再者，如上层的第二导电层152/162包括金属铜(Cu)，当沉积第二绝缘层18例如是二氧化硅(SiO2)于有源层(ex:IGZO)上方并覆盖源极电极15和漏极电极16时，SiO2会和铜形成氧化铜(CuO)，且氧化铜有可能溅到有源层(ex:IGZO)14的通道区ACH，而影响到有源层14的电子特性。因此实施例的下层金属相较于上层金属具有较长的第一突出部1511/1611可以防止上层金属与绝缘层形成的氧化物进入通道区ACH。
在此实施例中，通道区Ach于第一方向D1上具有一通道长度LCH，第一突出部1511/1611沿着第一方向D1朝向通道区ACH延伸，如图1所示。在本实施例中，第一方向D1指通道长度的方向，如图1中的X方向。第一突出部1511/1611的长度L15/L16定义为沿着通道长度LCH方向(i.e.第一方向D1)的长度。
另外，实施例的第一突出部1511/1611虽然可以防止氧化铜进入通道区Ach，但第一突出部太长会增加源极电极15/漏极电极与下方栅极电极12重叠的面积，进而增加寄生电容如栅极/漏极电容(以下简称Cgd)和栅极/源极电容(以下简称Cgs)。其中Cgd增加会增加像素的馈通电压(feed through voltage)，而Cgs增加会增加数据线的RC(电阻值与电容值的乘积)负载。因此第一突出部1511/1611较佳的长度上限值可根据应用产品规格如电性要求和限制而做适当选择。以下以一应用例做说明，但于该应用例中所提出的数值仅做参考之用，非限制本发明之用。
在一示例中，提出一边缘场切换(Fringe field switching，FFS)显示技术的应用产品，其像素尺寸为21纳米(nm)×63纳米，让TFT开启的正电压VGH为16V，让TFT关闭的负电压VGL为-12V，中间灰阶允许的馈通电压为-0.95V，漏极和栅极的寄生电容Cgd于关闭时(Cgd_off)为0.006皮法拉(picofarad，pF)于开启时(Cgd_on)为0.0066pF，存储电容CS为0.193pF，液晶电容CLC近似0pF。图2A为一像素的电路图，图2B为图2A的栅极走线打开时的等效电路图，图2C为图2A的栅极走线关闭时的等效电路图。根据图2A-图2C和电荷守恒：(Vd1-Vg1)*Cgd+(Vd1-VCOM)*(Cs+CLC)＝(Vd2-Vg2)*Cgd+(Vd2-VCOM)*(Cs+CLC)。
馈通电压(Vd2-Vd1)可表示为下式(1)：
(Vd2-Vd1)＝(Vg2-Vg1)*Cgd/(Cgd+Cs+CLC)…(1)。
根据上述FFS应用产品的示例条件，可利用式(1)经计算得到实际的馈通电压(Vd2-Vd1)，亦即(-12-16)*0.006/(0.006+0.193+0)＝-0.844221106(V)。
再利用式(1)和中间灰阶允许的馈通电压-0.95V(并带入Vg2＝-12,Vg1＝16,Cs＝0.193,CLC＝0)，来推得可允许的最大寄生电容值Cgd为0.006778189pF。
因此，在应用实施例的突出部设计于此示例的FFS应用产品时，可允许增加的寄生电容的比例为1.12969809(＝0.006778189/0.006)；即约113％。
图3为一应用例中，实施例的第一突出部长度与增加的寄生电容比值的曲线图。图3中，x轴代表第一突出部长度，0代表没有第一突出部形成。之后，将上述计算得到的可允许增加的寄生电容的比例约113％，对应图3的第一突出部长度对应增加的寄生电容比值的曲线，得到可允许的第一突出部长度值约0.36微米(μm)。因此，在一实施例中，第一突出部1511/1611的长度L15/L16(如图1所示的沿着通道长度LCH方向(i.e.第一方向D1)的长度)实质上小于等于0.36微米。
但相关技术者当知，上述仅以一应用例来说明如何进行第一突出部的相关设计，本发明并不仅限于上述提出的数值或数值范围。而是可根据应用产品规格如电性要求和限制做适当考虑(如上方计算方式)以定义出较适的第一突出部相关参数。
再者，在制作双层结构的源极电极15/漏极电极16时，可使上下两层的导电层具有不同倾斜角度的侧边。请参照图4，其为本发明另一实施例的晶体管阵列基板的剖面示意图。在一实施例中，制作双层结构的源极电极15/漏极电极16时，可先利用湿蚀刻对上层的第二导电层152/162进行图案化，再利用干蚀刻对下层的第一导电层151/161进行图案化，并使下层的第一导电层151/161于上层的第二导电层152/162的边缘处形成第一突出部1511/1611。其中，如图4所示，第一突出部1511/1611包含第一侧边1511b/1611b和第一底边1511a/1611a，第二导电层152/162包含第二底边152a/162a和第二侧边152b/162b，第二侧边152b/162b邻近于通道区ACH，其中第一侧边1511b/1611b和第一底边1511a/1611a具有夹角θ1，实质上大于第二侧边152b/162b和第二底边152a/162a的夹角θ2。
一实施例中，利用湿蚀刻对上层的第二导电层152/162进行图案化，可得到夹角θ2约30度至60度之间；利用干蚀刻对下层的第一导电层151/161进行图案化，可得到夹角θ1大于80度。
另外，在一实施例中，可制作双层结构的栅极电极12，且也具有类似的突出部设计，此可避免使栅极电极12的下层金属(例如钛，上层金属例如铜)在图案化时造成倒角的情况。请参照图5，其为本发明又一实施例的晶体管阵列基板的剖面示意图。如图5所示，栅极电极12包括一下导电层121和一上导电层122，下导电层121设置在基材10上，上导电层122设置在下导电层121上，其中下导电层121于上导电层122的边缘处具有一第二突出部1211突出于上导电层122。其余元件请参照图1及上述说明，在此不再赘述。
另外，在本实施例中，源极电极15和漏极电极16至少一者的下层金属161远离通道区ACH处也可以形成突出部。例如图5中源极电极15和漏极电极16在远离通道区ACH处各具有第三突出部1513和1613，其长度分别为L15E和L16E。类似地，第三突出部1513和1613的侧边和底边的夹角也可大于源极电极15和漏极电极16的上层金属162的侧边(远离通道区ACH)和底边的夹角，其具体内容可参照上述的实施方式，在此不再赘述。
再者，考虑到源极电极15/漏极电极16的下层金属除了产生倒角的情况外还要有效防止氧化铜溅到有源层(ex:IGZO)14的通道区ACH，实施例中可设计第一突出部1511/1611至少一者的长度L15/L16大于第二突出部1211的长度L12。例如图5所示，源极电极15和漏极电极16的第一突出部1511、1611的长度L15、L16皆大于栅极电极12的第二突出部1211的长度L12。
另外，图6A、图6B分别为本发明可应用的两种其他实施例的晶体管阵列基板的剖面示意图。在此实施例中，源极电极15和漏极电极16中至少一者覆盖有源层14的侧边14b。如图6A、图6B所示，源极电极15和漏极电极16所包括的第一导电层151和161覆盖有源层14的侧边14b。而图6A中，第一导电层151和161接近有源层14的侧边14b，上方的第二导电层152、162不会覆盖对应有源层14侧边14b的位置，即第二导电层152、162的上表面152c、162c的侧边(图6A的线段P1所指)尚未延伸至对应有源层14的侧边14b处。图6B中，第二导电层152、162则皆覆盖对应有源层14侧边14b的位置，即第二导电层152、162的上表面152c、162c的侧边(图6B的线段P2所指)延伸至对应有源层14的侧边14b处；因此，如于XZ平面朝第二导电层152、162的方向观看，则第二导电层152、162的边缘超过有源层14的侧边14b。
上述各个实施例中，有源层14的长度例如可超过栅极电极12的长度。以图1的实施例为例，有源层14于远离通道区ACH的边缘超过栅极电极12的边缘，且两者的边缘具有第一距离Dis-1。另外，位于有源层14上方的源极电极15和漏极电极16至少一者于远离通道区ACH的边缘也可超过栅极电极12的边缘，且两者的边缘具有第二距离Dis-2，其中第二距离Dis-2小于等于第一距离Dis-1。图1绘示第二距离Dis-2小于第一距离Dis-1，然本实施例并不以此为限。
由于实施例中，有源层14于远离通道区ACH的边缘超过栅极电极12的边缘，此超出的区域并未被栅极电极12遮住且会照射到背光。在本实施例有源层14可为金属氧化物的材料形成(例如IGZO)，其材料特性容易受到背光的影响使得半导体特性偏向导电性，因此有源层14于超过栅极电极12的边缘的区域(即第一距离Dis-1涵盖的区域)的阻抗会小于有源层14的通道区ACH的阻抗。另外，源极电极15和漏极电极16超出栅极电极12的边缘的区域(即第二距离Dis-2涵盖的区域)与有源层14其阻抗低的区域(即第一距离Dis-1涵盖的区域)直接接触，因此欧姆接触(ohmic contact)也可增加。
根据上述，本发明提出的晶体管阵列基板及应用的显示面板，其晶体管阵列基板上具有双层结构的第二金属层的设计，可有效防止金属氧化物渗入通道区的相关层，提升阵列基板的电子特性及其稳定度，进而提高应用产品的良率。而如上所述，可适当调整实施例的突出部的相关参数(例如第一突出部1511/1611的长度和/或侧边角度等相关参数)，以符合应用产品的电性需求，因此上述提出的各种数值仅为举例说明，非限制之用。再者，应用实施例所制得的晶体管阵列基板除了仍可达到稳定优异的电子特性，符合一般应用产品的需求，也与现有制作工艺相容性高，十分适合量产。
综上所述，虽然已结合以上实施例揭露了本发明，然而其并非用以限定本发明。本发明所属技术领域中熟悉此技术者，在不脱离本发明的精神和范围内，可作各种的更动与润饰。因此，本发明的保护范围应以附上的权利要求所界定的为准。

Claims (10)

1.一种晶体管阵列基板，包含多个晶体管设置在一基材上，其中该些晶体管中的一晶体管包括:
栅极电极，设置在该基材上；
第一绝缘层，设置在该栅极电极上；
有源层，设置在该第一绝缘层上，包含通道区；
源极电极和漏极电极，设置在该有源层上，其中该源极电极和该漏极电极中的至少一者包含:
第一导电层，设置在该有源层上；和
第二导电层，设置在该第一导电层上并与该第一导电层接触；
其中该第二导电层暴露出该第一导电层的部分上表面，以使该第一导电层于该第二导电层的边缘处具有一第一突出部朝向该通道区延伸，该第一导电层于该第二导电层的边缘处具有一第三突出部，该第三突出部远离该通道区延伸；和
第二绝缘层，覆盖该源极电极和该漏极电极，其中该第二绝缘层的部分上表面具有弧形边缘。
2.如权利要求1所述的晶体管阵列基板，其中该第一突出部的长度小于等于0.36微米。
3.如权利要求1所述的晶体管阵列基板，其中该第一突出部的长度大于等于该第二导电层的厚度的20％。
4.如权利要求1所述的晶体管阵列基板，其中该第一突出部包含第一侧边和第一底边，该第二导电层包含第二侧边和第二底边，该第二侧边邻近于该通道区，其中该第一侧边和该第一底边的夹角θ1大于该第二侧边和该第二底边的夹角θ2。
5.如权利要求1所述的晶体管阵列基板，其中该栅极电极包括下导电层和上导电层，该下导电层设置在该基材上，该上导电层设置在该下导电层上，其中该下导电层于该上导电层的边缘处具有第二突出部突出于该上导电层。
6.如权利要求5所述的晶体管阵列基板，其中该第一突出部的长度大于该第二突出部的长度。
7.如权利要求1所述的晶体管阵列基板，其中该有源层的边缘超过该栅极电极的边缘。
8.如权利要求1所述的晶体管阵列基板，其中该源极电极和该漏极电极中的该至少一者覆盖该有源层的侧边。
9.如权利要求1所述的晶体管阵列基板，其中该第一导电层覆盖该有源层的侧边。
10.一种显示面板，包括：
第一基板，包括多个晶体管设置在一基材上，其中该些晶体管中的一晶体管包含；
栅极电极，设置在该基材上；
第一绝缘层，设置在该栅极电极上；
有源层，设置在该第一绝缘层上，包含通道区；
源极电极和漏极电极，设置在该有源层上，其中该源极电极和该漏极电极中的至少一者包含:
第一导电层，设置在该有源层上；和
第二导电层，设置在该第一导电层上并与该第一导电层接触；
其中该第二导电层暴露出该第一导电层的部分上表面，以使该第一导电层于该第二导电层的边缘处具有一第一突出部朝向该通道区延伸，该第一导电层于该第二导电层的边缘处具有一第三突出部，该第三突出部远离该通道区延伸；和
第二绝缘层，覆盖该源极电极和该漏极电极，其中该第二绝缘层的部分上表面具有弧形边缘；和
第二基板，与该第一基板相对设置；和
显示介质层，设置于该第一基板与该第二基板之间。
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