TWI585954B - 電晶體陣列基板及應用之顯示面板 - Google Patents

電晶體陣列基板及應用之顯示面板 Download PDF

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TWI585954B
TWI585954B TW105106315A TW105106315A TWI585954B TW I585954 B TWI585954 B TW I585954B TW 105106315 A TW105106315 A TW 105106315A TW 105106315 A TW105106315 A TW 105106315A TW I585954 B TWI585954 B TW I585954B
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conductive layer
layer
substrate
disposed
protrusion
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TW201733088A (zh
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林峻良
崔博欽
陳宏昆
許乃方
陳奕靜
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群創光電股份有限公司
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Priority to TW105106315A priority Critical patent/TWI585954B/zh
Priority to CN201611108620.2A priority patent/CN107154403B/zh
Priority to US15/443,411 priority patent/US10615262B2/en
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Description

電晶體陣列基板及應用之顯示面板
本發明是有關於一種電晶體陣列基板及應用之顯示面板,且特別是有關於具雙層結構之第二金屬層的一種電晶體陣列基板及應用之顯示面板,可改善顯示面板的電子特性和提高可靠度。
具顯示面板的電子產品已是現代人不論在工作處理學習上、或是個人休閒娛樂上,不可或缺的必需品,包括智慧型手機(SmartPhone)、平板電腦(Pad)、筆記型電腦(Notebook)、顯示器(Monitor)到電視(TV)等許多相關產品。其中又以液晶顯示面板最為普遍。液晶顯示面板(LCD)係利用電壓驅動液晶(LCs)轉動進而調整亮度灰階而可構成一種平面顯示器、電子視覺顯示器,及影像顯示器。
顯示裝置在製作時需注意製程上的細節,例如進行金屬層和半導體層等各層圖案化時需精確,而各層之相對位置與圖案設計亦需考量到是否可使製得之顯示裝置具有穩定良好的電子特性,以符合產品要求的各項規格,例如符合高穿透率、高 良率、良好可靠度和顯示品質穩定等要求。顯示裝置相關元件和各材料層的設計不良,可能造成電性表現降低,進而影響顯示品質。
本發明係有關於一種電晶體陣列基板及應用之顯示面板,其具雙層結構之第二金屬層的設計可有效改善顯示面板的電子特性和提高可靠度。
根據本發明,係提出一種電晶體陣列基板,包含複數電晶體設置在一基材上,其中該些電晶體中的一電晶體包括設置在基材上的一閘極電極、設置在閘極電極上的一第一絕緣層、設置在第一絕緣層上且包含一通道區的一主動層、設置在主動層上的一源極電極和一汲極電極。其中源極電極和汲極電極中的至少一者包含:設置在主動層上的一第一導電層,和設置在第一導電層上並與第一導電層接觸的一第二導電層。其中第二導電層暴露出第一導電層的部分上表面,以使第一導電層於第二導電層之邊緣處具有一第一突出部朝向通道區延伸。
根據本發明,係提出一種顯示面板,包括一第一基板、與第一基板相對設置的一第二基板,和設置於第一基板與第二基板之間的一顯示介質層。第一基板包括複數電晶體設置在一基材上,其中一電晶體係包括上述之結構。
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉實施例,並配合所附圖式,作詳細說明如下:
S1‧‧‧第一基板
10‧‧‧基材
12‧‧‧閘極電極
121‧‧‧下導電層
122‧‧‧上導電層
1211‧‧‧第二突出部
L12‧‧‧第二突出部的長度
13‧‧‧第一絕緣層
14‧‧‧主動層
ACH‧‧‧通道區
LCH‧‧‧通道長度
14b‧‧‧主動層的側邊
15‧‧‧源極電極
16‧‧‧汲極電極
151、161‧‧‧第一導電層
152、162‧‧‧第二導電層
1511、1611‧‧‧第一突出部
1511a、1611a‧‧‧第一底邊
1511b、1611b‧‧‧第一側邊
152a/162a‧‧‧第二底邊
152b/162b‧‧‧第二側邊
152c、162c‧‧‧第二導電層之上表面
θ1θ2‧‧‧夾角
L15、L16‧‧‧第一突出部之長度
t15、t16‧‧‧第二導電層之厚度
1513、1613‧‧‧第三突出部
L15E、L16E‧‧‧第三突出部之長度
18‧‧‧第二絕緣層
19‧‧‧第三絕緣層
S2‧‧‧第二基板
D1‧‧‧第一方向
D2‧‧‧第二方向
Dis-1‧‧‧第一距離
Dis-2‧‧‧第二距離
3‧‧‧顯示介質層
P1、P2‧‧‧線段
第1圖為本揭露一實施例之具有電晶體陣列基板之液晶顯示面板的剖面示意圖。
第2A圖為一畫素之電路圖,第2B圖為第2A圖之閘極走線打開時之等效電路圖,第2C圖為第2A圖之閘極走線關閉時之等效電路圖。
第3圖為一應用例中,實施例之第一突出部長度與增加之寄生電容比值之曲線圖。
第4圖繪示本揭露另一實施例之電晶體陣列基板之剖面示意圖。
第5圖,其繪示本揭露又一實施例之電晶體陣列基板之剖面示意圖。
第6A、6B圖分別繪示本揭露可應用之兩種其他實施例之電晶體陣列基板之剖面示意圖。
本揭露之實施例係提出一種電晶體陣列基板及應用之顯示面板,透過電晶體陣列基板之雙層結構第二金屬層的特殊設計,可防止金屬氧化物滲入通道區的相關層,進而提升電晶體陣列基板之電子特性的穩定度,提高應用之顯示面板的產品良率。再者,實施例之電晶體陣列基板仍然符合一般應用產品的需求,且與現有製程相容性高,因此實施例所提出之設計不但可以 使製得之陣列基板具有穩定優異的電子特性,也十分適合量產。
以下係參照所附圖式詳細敘述本揭露之其中幾種實施態樣。本揭露之實施例例如是應用於背通道蝕刻型電晶體(BCE-type TFT)陣列基板之液晶顯示面板。需注意的是,實施例所提出的多組實施態樣之結構和內容僅為舉例說明之用,本揭露欲保護之範圍並非僅限於所述之該些態樣。需注意的是,本揭露並非顯示出所有可能的實施例,相關領域者可在不脫離本揭露之精神和範圍內對實施例之結構加以變化與修飾,以符合實際應用所需。因此,未於本揭露提出的其他實施態樣也可能可以應用。再者,圖式係已簡化以利清楚說明實施例之內容,圖式上的尺寸比例並非按照實際產品等比例繪製。因此,說明書和圖示內容僅作敘述實施例之用,而非作為限縮本揭露保護範圍之用。再者,實施例中相同或類似的標號係用以標示相同或類似之部分。
另外,說明書與請求項中所使用的序數例如”第一”、”第二”、”第三”等之用詞,以修飾請求項之元件,其本身並不意含及代表該請求元件有任何之前的序數,也不代表某一請求元件與另一請求元件的順序、或是製造方法上的順序,該些序數的使用僅用來使具有某命名的一請求元件得以和另一具有相同命名的請求元件能作出清楚區分。
第1圖為本揭露一實施例之具有電晶體陣列基板之液晶顯示面板的剖面示意圖。一顯示面板包括一第一基板S1、與第一基板S1相對設置之一第二基板S2和設置於第一基板S1與 第二基板S2之間之一顯示介質層3。於一實施例中,第一基板S1例如是一電晶體陣列基板,第二基板S2例如是一彩色濾光基板,顯示介質層3例如是液晶層。在另一實施例中,第一基板S1例如是一電晶體陣列基板,第二基板S2例如是一透明基板,顯示介質層3例如是有機發光層。此實施例係以源極電極和汲極電極(i.e.第二金屬層)直接形成於主動層上以位於通道區之兩側為例作第一基板S1之結構說明,但本揭露並不以此種形態及繪示之細部結構為限。第二基板S2省略了其他元件。
第一基板S1包含設置在一基材10上的多個電晶體。基材10可以是由硬性材料(例如玻璃)或是軟性材料(例如塑膠)形成。如第1圖所示,多個電晶體其中之一係包含一閘極電極12設置在基材10上,一第一絕緣層13設置在閘極電極12上,一主動層14設置在第一絕緣層13上且主動層14包含一通道區ACH,一源極電極15和一汲極電極16設置在主動層14上。根據實施例,源極電極15和汲極電極16中的至少一者包含至少兩層導電層。本實施例中,源極電極15和汲極電極16可兩者兼具實施例之兩層導電層之設計,然本實施例並不以此為限。
主動層14可由金屬氧化物之材料形成,其金屬可包含銦、鎵、鋅、錫、鋁或上述之組合等,例如主動層14可以是氧化鋅(indium zinc oxide,IZO)層、氧化銦鎵鋅(indium gallium zinc oxide,IGZO)層或氧化鋅錫(zinc tin oxide,ZSO)層等等。另外,電晶體更包括一第二絕緣層18覆蓋源極電極15和汲極電極 16,以及一第三絕緣層19形成於第二絕緣層18上。第一絕緣層13、第二絕緣層18和第三絕緣層19可以是單層或是多層結構。第一絕緣層13、第二絕緣層18和第三絕緣層19可使用有機或無機材料形成,有機材料可例如是全氟烷氧基樹脂(perfluoroalkoxy,PFA),無機材料可例如是氧化物(例如,氧化矽、氧化鋁)、氮化物(例如,氮化矽)或氮氧化物(例如,氮氧化矽)等絕緣層材料製作。
如第1圖所示,源極電極15包括設置在主動層14上之一第一導電層151以及設置在第一導電層151上之一第二導電層152,且第二導電層152與第一導電層151接觸,其中第二導電層152暴露出第一導電層151的部分上表面,以使第一導電層151於第二導電層152之邊緣處具有第一突出部1511朝向通道區ACH延伸。
類似地,汲極電極16包括設置在主動層14上之一第一導電層161以及設置在第一導電層161上之一第二導電層162,且第二導電層162與第一導電層161接觸,其中第二導電層162暴露出第一導電層161的部分上表面,以使第一導電層161於第二導電層162之邊緣處具有第一突出部1611朝向通道區ACH延伸。
一實施例中,雙層結構的源極電極15/汲極電極16例如是銅或鋁/鈦(Titanium)或鉬(Molybdenum)結構,亦即下層的第一導電層151/161可包括金屬鈦或鉬,上層的第二導電層 152/162可包括金屬銅或鋁,下層金屬鈦或鉬於上層金屬銅或鋁之邊緣處具有第一突出部1511/1611。實施例係可利用製程條件的調節來達到應用產品所需之第一突出部1511/1611的狀態,例如第一突出部的長度和/或側邊角度等相關參數。
一實施例中,在蝕刻(例如濕蝕刻)源極電極15/汲極電極16(i.e.第二金屬層)的上層金屬時,可透過過度蝕刻的方式,藉此暴露出下層金層的部分上表面,而達到實施例之下層金屬相較於上層金屬具有第一突出部1511/1611的設計,如此可避免在蝕刻(例如濕蝕刻或乾蝕刻)下層金屬時造成底切(undercut)的情況發生。根據實驗,濕蝕刻上層金屬時比預計的蝕刻時間多20%~100%,使得上層金屬(ex:Cu)在退後的距離至少為其厚度的20%~100%,藉以定義出下層金屬之突出部的長度。據此,一實施例中,第一突出部1511/1611的長度L15/L16可實質上大於等於第二導電層152/162之厚度(i.e.沿第二方向D2)t15/t16的20%。
再者,如上層的第二導電層152/162包括金屬銅(Cu),當沉積第二絕緣層18例如是二氧化矽(SiO2)於主動層(ex:IGZO)上方並覆蓋源極電極15和汲極電極16時,SiO2會和銅形成氧化銅(CuO),且氧化銅有可能濺到主動層(ex:IGZO)14的通道區ACH,而影響到主動層14之電子特性。因此實施例之下層金屬相較於上層金屬具有較長的第一突出部1511/1611可以防止上層金屬與絕緣層形成之氧化物進入通道區ACH
於此實施例中,通道區Ach於第一方向D1上具有一 通道長度LCH,第一突出部1511/1611係沿著第一方向D1朝向通道區ACH延伸,如第1圖所示。於本實施例中,第一方向D1係指通道長度之方向,如第1圖中的X方向。第一突出部1511/1611之長度L15/L16係定義為沿著通道長度LCH方向(i.e.第一方向D1)的長度。
另外,實施例之第一突出部1511/1611雖然可以防止氧化銅進入通道區Ach,但第一突出部太長會增加源極電極15/汲極電極與下方閘極電極12重疊的面積,進而增加寄生電容如閘極/汲極電容(以下簡稱Cgd)和閘極/源極電容(以下簡稱Cgs)。其中Cgd增加會增加畫素的饋通電壓(feed through voltage),而Cgs增加會增加資料線的RC(電阻值與電容值之乘積)負載。因此第一突出部1511/1611較佳的長度上限值可根據應用產品規格如電性要求和限制而做適當選擇。以下係以一應用例做說明,但於該應用例中所提出之數值僅做參考之用,非限制本揭露之用。
於一示例中,係提出一邊緣場切換(Fringe field switching,FFS)顯示技術之應用產品,其畫素尺寸為21奈米(nm)×63奈米,讓TFT開啟之正電壓VGH為16V,讓TFT關閉之負電壓VGL為-12V,中間灰階允許的饋通電壓為-0.95V,汲極和閘極的寄生電容Cgd於關閉時(Cgd_off)為0.006皮法拉(picofarad,pF)於開啟時(Cgd_on)為0.0066pF,儲存電容CS為0.193pF,液晶電容CLC近似0pF。第2A圖為一畫素之電路圖,第2B圖為第2A圖之閘極走線打開時之等效電路圖,第2C圖為第2A圖之閘極走 線關閉時之等效電路圖。根據第2A-2C圖和電荷守恆:(Vd1-Vg1)*Cgd+(Vd1-VCOM)*(Cs+CLC)=(Vd2-Vg2)*Cgd+(Vd2-VCOM)*(Cs+CLC)。
饋通電壓(Vd2-Vd1)可表示為下式(1):(Vd2-Vd1)=(Vg2-Vg1)*Cgd/(Cgd+Cs+CLC)...(1)。
根據上述FFS應用產品之示例條件,可利用式(1)經計算得到實際的饋通電壓(Vd2-Vd1),亦即(-12-16)*0.006/(0.006+0.193+0)=-0.844221106(V)。
再利用式(1)和中間灰階允許的饋通電壓-0.95V(並帶入Vg2=-12,Vg1=16,Cs=0.193,CLC=0),來推得可允許的最大寄生電容值Cgd為0.006778189pF。
因此,在應用實施例之突出部設計於此示例之FFS應用產品時,可允許增加之寄生電容的比例為1.12969809(=0.006778189/0.006);即約113%。
第3圖為一應用例中,實施例之第一突出部長度與增加之寄生電容比值之曲線圖。第3圖中,x軸代表第一突出部長度,0代表沒有第一突出部形成。之後,將上述計算得到的可允許增加之寄生電容的比例約113%,對應第3圖之第一突出部長度對應增加之寄生電容比值之曲線,得到可允許的第一突出部長度值約0.36微米(μm)。因此,於一實施例中,第一突出部1511/1611之長度L15/L16(如第1圖所示之沿著通道長度LCH方向(i.e.第一方向D1)的長度)實質上小於等於0.36微米。
但相關技藝者當知,上述僅以一應用例來說明如何進行第一突出部之相關設計,本揭露並不僅限於上述提出之數值或數值範圍。而是可根據應用產品規格如電性要求和限制做適當考量(如上方計算方式)以定義出較適的第一突出部相關參數。
再者,於製作雙層結構的源極電極15/汲極電極16時,可使上下兩層的導電層具有不同傾斜角度之側邊。請參照第4圖,其繪示本揭露另一實施例之電晶體陣列基板之剖面示意圖。於一實施例中,製作雙層結構的源極電極15/汲極電極16時,可先利用濕蝕刻對上層的第二導電層152/162進行圖案化,再利用乾蝕刻對下層的第一導電層151/161進行圖案化,並使下層的第一導電層151/161於上層的第二導電層152/162之邊緣處形成第一突出部1511/1611。其中,如第4圖所示,第一突出部1511/1611包含第一側邊1511b/1611b和第一底邊1511a/1611a,第二導電層152/162包含第二底邊152a/162a和第二側邊152b/162b,第二側邊152b/162b鄰近於通道區ACH,其中第一側邊1511b/1611b和第一底邊1511a/1611a具有夾角θ1,實質上大於第二側邊152b/162b和第二底邊152a/162a之夾角θ2
一實施例中,利用濕蝕刻對上層的第二導電層152/162進行圖案化,可得到夾角θ2約30度至60度之間;利用乾蝕刻對下層的第一導電層151/161進行圖案化,可得到夾角θ1大於80度。
另外,於一實施例中,可製作雙層結構的閘極電極 12,且亦具有類似的突出部設計,此可避免使閘極電極12之下層金屬(例如鈦,上層金屬例如銅)在圖案化時造成倒角的情況。請參照第5圖,其繪示本揭露又一實施例之電晶體陣列基板之剖面示意圖。如第5圖所示,閘極電極12包括一下導電層121和一上導電層122,下導電層121設置在基材10上,上導電層122設置在下導電層121上,其中下導電層121於上導電層122之邊緣處係具有一第二突出部1211突出於上導電層122。其餘元件請參照第1圖及上述說明,在此不再贅述。
另外,於本實施例中,源極電極15和汲極電極16至少一者之下層金屬161遠離通道區ACH處亦可以形成突出部。例如第5圖中源極電極15和汲極電極16在遠離通道區ACH處各具有第三突出部1513和1613,其長度分別為L15E和L16E。類似地,第三突出部1513和1613的側邊和底邊之夾角亦可大於源極電極15和汲極電極16之上層金屬162的側邊(遠離通道區ACH)和底邊之夾角,其具體內容可參照上述之實施方式,於此不再贅述。
再者,考量到源極電極15/汲極電極16的下層金屬除了產生倒角的情況外還要有效防止氧化銅濺到主動層(ex:IGZO)14的通道區ACH,實施例中可設計第一突出部1511/1611至少一者的長度L15/L16大於第二突出部1211的長度L12。例如第5圖所示,源極電極15和汲極電極16之第一突出部1511、1611的長度L15、L16皆大於閘極電極12的第二突出部1211的長度L12
另外,第6A、6B圖分別繪示本揭露可應用之兩種其他實施例之電晶體陣列基板之剖面示意圖。於此實施例中,源極電極15和汲極電極16中至少一者係覆蓋主動層14的側邊14b。如第6A、6B圖所示,源極電極15和汲極電極16所包括的第一導電層151和161係覆蓋主動層14的側邊14b。而第6A圖中,第一導電層151和161接近主動層14的側邊14b,上方的第二導電層152、162不會覆蓋對應主動層14側邊14b的位置,即第二導電層152、162的上表面152c、162c之側邊(第6A圖之線段P1所指)尚未延伸至對應主動層14之側邊14b處。第6B圖中,第二導電層152、162則皆覆蓋對應主動層14側邊14b的位置,即第二導電層152、162的上表面152c、162c之側邊(第6B圖之線段P2所指)延伸至對應主動層14之側邊14b處;因此,如於XZ平面朝第二導電層152、162的方向觀看,則第二導電層152、162的邊緣係超過主動層14之側邊14b。
上述各個實施例中,主動層14的長度例如可超過閘極電極12的長度。以第1圖之實施例為例,主動層14於遠離通道區ACH之邊緣係超過閘極電極12的邊緣,且兩者之邊緣具有第一距離Dis-1。另外,位於主動層14上方的源極電極15和汲極電極16至少一者於遠離通道區ACH之邊緣亦可超過閘極電極12的邊緣,且兩者之邊緣具有第二距離Dis-2,其中第二距離Dis-2小於等於第一距離Dis-1。第1圖係繪示第二距離Dis-2小於第一距離Dis-1,然本實施例並不以此為限。
由於實施例中,主動層14於遠離通道區ACH之邊緣係超過閘極電極12的邊緣,此超出的區域並未被閘極電極12遮住且會照射到背光。在本實施例主動層14可為金屬氧化物之材料形成(例如IGZO),其材料特性容易受到背光的影響使得半導體特性偏向導電性,因此主動層14於超過閘極電極12的邊緣的區域(即第一距離Dis-1涵蓋之區域)之阻抗會小於主動層14之通道區ACH之阻抗。另外,源極電極15和汲極電極16超出閘極電極12之邊緣的區域(即第二距離Dis-2涵蓋之區域)係與主動層14其阻抗低的區域(即第一距離Dis-1涵蓋之區域)直接接觸,因此歐姆接觸(ohmic contact)亦可增加。
根據上述,本揭露提出之電晶體陣列基板及應用之顯示面板,其電晶體陣列基板上具有雙層結構的第二金屬層之設計,可有效防止金屬氧化物滲入通道區的相關層,提升陣列基板之電子特性及其穩定度,進而提高應用產品的良率。而如上所述,可適當調整實施例之突出部的相關參數(例如第一突出部1511/1611的長度和/或側邊角度等相關參數),以符合應用產品的電性需求,因此上述提出之各種數值僅為舉例說明,非限制之用。再者,應用實施例所製得之電晶體陣列基板除了仍可達到穩定優異的電子特性,符合一般應用產品的需求,也與現有製程相容性高,十分適合量產。
綜上所述,雖然本發明已以實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者, 在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。
S1‧‧‧第一基板
10‧‧‧基材
12‧‧‧閘極電極
13‧‧‧第一絕緣層
14‧‧‧主動層
ACH‧‧‧通道區
LCH‧‧‧通道長度
15‧‧‧源極電極
16‧‧‧汲極電極
151、161‧‧‧第一導電層
152、162‧‧‧第二導電層
1511、1611‧‧‧第一突出部
L15、L16‧‧‧第一突出部的長度
t15、t16‧‧‧第二導電層之厚度
18‧‧‧第二絕緣層
19‧‧‧第三絕緣層
S2‧‧‧第二基板
D1‧‧‧第一方向
D2‧‧‧第二方向
Dis-1‧‧‧第一距離
Dis-2‧‧‧第二距離
3‧‧‧顯示介質層

Claims (9)

  1. 一種電晶體陣列基板,包含複數電晶體設置在一基材上,其中該些電晶體中的一電晶體包括:一閘極電極,設置在該基材上;一第一絕緣層,設置在該閘極電極上;一主動層,設置在該第一絕緣層上,包含一通道區;及一源極電極和一汲極電極設置在該主動層上,其中該源極電極和該汲極電極中的至少一者包含:一第一導電層,設置在該主動層上;及一第二導電層,設置在該第一導電層上並與該第一導電層接觸;其中該第二導電層暴露出該第一導電層的部分上表面,以使該第一導電層於該第二導電層之邊緣處具有一第一突出部朝向該通道區延伸,該第一突出部包含一第一側邊和一第一底邊,該第二導電層包含一第二側邊和一第二底邊,該第二側邊鄰近於該通道區,且該第一側邊和該第一底邊的夾角θ1大於該第二側邊和該第二底邊的夾角θ2
  2. 如請求項1所述的電晶體陣列基板,其中該第一突出部的長度小於等於0.36微米。
  3. 如請求項1所述的電晶體陣列基板,其中該第一突出部的長度大於等於該第二導電層之厚度的20%。
  4. 如請求項1所述的電晶體陣列基板,其中該閘極電極包括一下導電層和一上導電層,該下導電層設置在該基材上,該上導電層設置在該下導電層上,其中該下導電層於該上導電層之邊 緣處係具有一第二突出部突出於該上導電層。
  5. 如請求項4所述的電晶體陣列基板,其中該第一突出部的長度大於該第二突出部的長度。
  6. 如請求項1所述的電晶體陣列基板,其中該主動層之邊緣係超過該閘極電極之邊緣。
  7. 如請求項1所述的電晶體陣列基板,其中該源極電極和該汲極電極中的該至少一者係覆蓋該主動層的側邊。
  8. 如請求項1所述的電晶體陣列基板,其中該第一導電層係覆蓋該主動層的側邊。
  9. 一種顯示面板,包括:一第一基板,包括複數電晶體設置在一基材上,其中該些電晶體中的一電晶體包含:一閘極電極,設置在該基材上;一第一絕緣層,設置在該閘極電極上;一主動層,設置在該第一絕緣層上,包含一通道區;及一源極電極和一汲極電極設置在該主動層上,其中該源極電極和該汲極電極中的至少一者包含:一第一導電層,設置在該主動層上;及一第二導電層,設置在該第一導電層上並與該第一導電層接觸;其中該第二導電層暴露出該第一導電層的部分上表面,以使該第一導電層於該第二導電層之邊緣處具有一第一突出部朝向該通道區延伸,該第一突出部包含一第一側邊和一第一底邊,該第二導電層包含一第二側邊和一第二底邊,該第二側邊 鄰近於該通道區,且該第一側邊和該第一底邊的夾角θ1大於該第二側邊和該第二底邊的夾角θ2;一第二基板,與該第一基板相對設置;和一顯示介質層,設置於該第一基板與該第二基板之間。
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