WO2021031166A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2021031166A1
WO2021031166A1 PCT/CN2019/101834 CN2019101834W WO2021031166A1 WO 2021031166 A1 WO2021031166 A1 WO 2021031166A1 CN 2019101834 W CN2019101834 W CN 2019101834W WO 2021031166 A1 WO2021031166 A1 WO 2021031166A1
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WO
WIPO (PCT)
Prior art keywords
signal line
transistor
base substrate
driving circuit
scan driving
Prior art date
Application number
PCT/CN2019/101834
Other languages
English (en)
French (fr)
Inventor
曾超
黄炜赟
龙跃
黄耀
李孟
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to MX2019015381A priority Critical patent/MX2019015381A/es
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to AU2019275624A priority patent/AU2019275624B2/en
Priority to PCT/CN2019/101834 priority patent/WO2021031166A1/zh
Priority to CN202211333476.8A priority patent/CN116027600A/zh
Priority to JP2019569423A priority patent/JP7550516B2/ja
Priority to BR112019026794A priority patent/BR112019026794A2/pt
Priority to CN201980001412.8A priority patent/CN112771599B/zh
Priority to RU2019141643A priority patent/RU2720735C1/ru
Priority to US16/771,446 priority patent/US11404007B2/en
Priority to EP19933237.0A priority patent/EP4020443A4/en
Publication of WO2021031166A1 publication Critical patent/WO2021031166A1/zh
Priority to US17/854,556 priority patent/US11900884B2/en
Priority to US18/394,000 priority patent/US20240127759A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the embodiments of the present disclosure relate to a display substrate, a manufacturing method thereof, and a display device.
  • a pixel array of a liquid crystal display panel or an Organic Light Emitting Diode (OLED) display panel usually includes multiple rows of gate lines and multiple columns of data lines interlaced with the gate lines.
  • the gate line can be driven by a bonded integrated drive circuit.
  • GOA Gate Driver On Array
  • a GOA including multiple cascaded shift register units can be used to provide switching state voltage signals (scanning signals) for multiple rows of gate lines of the pixel array, so as to control the multiple rows of gate lines to be turned on sequentially, and the data lines simultaneously
  • a data signal is provided to the pixel units of the corresponding row in the pixel array, so as to form a gray level voltage required for each gray scale of the displayed image in each pixel unit, and then display a frame of image.
  • At least one embodiment of the present disclosure provides a display substrate, which includes: a base substrate including a pixel array area and a peripheral area; a first scan driving circuit, a plurality of power lines, a first signal line group, and a second signal line group; In the peripheral area and located on the first side of the base substrate.
  • the first scan driving circuit includes a plurality of cascaded first shift registers; the plurality of power supply lines are configured to provide a plurality of cascaded first shift registers included in the first scan driving circuit Power supply voltage; the first signal line group includes at least one timing signal line, configured to provide at least one timing signal to a plurality of cascaded first shift registers included in the first scan driving circuit; the second signal The line group includes a first trigger signal line, which is configured to be connected to the first shift register of the first stage among the plurality of cascaded first shift registers included in the first scan driving circuit, so as to communicate to the first stage
  • the first shift register provides a first trigger signal, and the first trigger signal line is located between the plurality of power supply lines and the pixel array area.
  • the second signal line group is located on the side of the first scan driving circuit close to the pixel array area, and the first signal line group is located on the The other side of the first scan driving circuit opposite to the side where the second signal line group is located.
  • the pixel array region includes a first display area and a second display area that are parallel to each other and do not overlap, and the first scan driving circuit and the first display The area is connected to drive the display of the first display area;
  • the display substrate further includes a second scan driving circuit disposed in the peripheral area and located on the first side of the base substrate, and scans along the pixel array The direction is arranged in sequence with the first scan driving circuit, and is connected to the second display area to drive the second display area to display.
  • the second scan driving circuit includes a plurality of cascaded second shift registers, the second signal line group further includes a second trigger signal line, and the second scan driving circuit includes a plurality of cascaded first shift registers.
  • the first-stage second shift register of the two shift registers is connected to provide a second trigger signal to the first-stage second shift register included in the second scan driving circuit.
  • the extension lengths of the first trigger signal line and the second trigger signal line are different from those of the first scan driving circuit and the second scan driving circuit.
  • the arrangement length is the same.
  • the first trigger signal line and the second trigger signal line are arranged side by side.
  • the multiple power lines include a first power line and a second power line; the first power line and the second power line are configured to provide the same The first power supply voltage.
  • the orthographic projection of the first power line on the base substrate overlaps with the orthographic projection of the first scan driving circuit on the base substrate
  • the orthographic projection of the second power line on the base substrate is located between the orthographic projection of the first power line on the base substrate and the orthographic projection of the second signal line group on the base substrate. between.
  • the display substrate provided by at least one embodiment of the present disclosure further includes at least one first resistor; the first resistor is located on the side of the first scan driving circuit away from the first shift register of the first stage, so The first trigger signal line is connected to the first stage first shift register of the first scan driving circuit through the at least one first resistor.
  • the display substrate provided by at least one embodiment of the present disclosure further includes at least one second resistor, and the second resistor is located at the last stage of the first scan driving circuit, the first shift register and the second scan driver. Between the first stage and the second shift register of the circuit, the second trigger signal line is connected to the first stage and second shift register of the second scan driving circuit through the at least one second resistor.
  • the first resistor and the second resistor have different sizes.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a folding line located between the first display area and the second display area; the second resistor is located in the extending direction of the folding line, The extension direction of the folding line is perpendicular to the extension direction of the first signal line group and the second signal line group.
  • the orthographic projection of the at least one second resistor on the base substrate is located at the last stage of the first scan driving circuit.
  • the orthographic projection of the base substrate and the first-stage second shift register of the second scan driving circuit are between the orthographic projection of the base substrate.
  • the at least one first resistor is located between the base substrate and the second signal line group in a direction perpendicular to the base substrate, And the orthographic projection of the at least one first resistor on the base substrate is located on the side of the orthographic projection of the second signal line group on the base substrate away from the pixel array area.
  • the material of the first resistor is a semiconductor material.
  • the display substrate provided by at least one embodiment of the present disclosure further includes at least one first connection line and at least one second connection line; the first connection line connects one end of the at least one first resistor to the first The first-stage first shift register of the scan driving circuit is connected, and the second connection line connects the other end of the at least one first resistor with the first trigger signal line.
  • the first connection line and the second connection line are located on a side of the at least one first resistor away from the base substrate.
  • the display substrate provided by at least one embodiment of the present disclosure further includes: a first conductive connecting portion, a second conductive connecting portion, a first insulating layer, and a second insulating layer; the first conductive connecting portion and the second
  • the conductive connection part is located on the side of the first connection line and the second connection line away from the base substrate, and is connected to the plurality of power lines, the first signal line group, and the second signal line
  • the first insulating layer is located between the at least one first resistor and the first connecting line and the second connecting line in a direction perpendicular to the base substrate.
  • the two insulating layers are located between the first connection line and the second connection line and the first conductive connection portion and the second conductive connection portion in a direction perpendicular to the base substrate.
  • One end of the first conductive connection portion is connected to one end of the first connection line through a via hole penetrating the second insulating layer, and the other end of the first conductive connection portion is connected to one end of the first connection line by penetrating the first insulating layer and
  • the via hole of the second insulating layer is connected to one end of the at least one first resistor, and the other end of the first connection line is connected to the first shift register of the first stage of the first scan driving circuit;
  • One end of the second conductive connection portion is connected to one end of the second connection line through a via hole penetrating the second insulating layer, and the other end of the second conductive connection portion is connected to one end of the second connection line by penetrating the first insulating layer and the The via hole of the second insulating layer is connected to the other
  • each of the first shift registers of the first scan driving circuit includes a first constituent transistor connected to the first power line and a The second constituent transistor and the third constituent transistor connected to the two power lines;
  • the orthographic projection of the first constituent transistor on the base substrate is located on the orthographic projection of the first signal line group on the base substrate and the The first power line is between the orthographic projection of the base substrate and is close to the orthographic projection of the first power line on the base substrate, and the second and third constituent transistors are on the base substrate
  • the orthographic projection of the first power line is located between the orthographic projection of the first power line on the base substrate and the orthographic projection of the second power line on the base substrate, and is close to the second power line on the substrate Orthographic projection of the base substrate.
  • the multiple power lines include a third power line and a fourth power line; the third power line and the fourth power line are configured to provide the same The second power supply voltage; the orthographic projection of the fourth power line on the base substrate coincides with the orthographic projection of the first scan drive circuit on the base substrate, and the third power line is on the substrate
  • the orthographic projection of the base substrate is located between the orthographic projection of the fourth power line on the base substrate and the orthographic projection of the first signal line group on the base substrate.
  • the first shift register of the first scan driving circuit each further includes a fourth constituent transistor connected to the third power line and The fifth constituent transistor connected by four power lines;
  • the orthographic projection of the fourth constituent transistor on the base substrate is located at the orthographic projection of the third power line on the base substrate away from the first signal line group One side of the orthographic projection of the base substrate and close to the orthographic projection of the third power line on the base substrate, and the orthographic projection of the fifth constituent transistor on the base substrate is located on the fourth
  • the orthographic projection of the power line on the base substrate and the orthographic projection of the second signal line group on the base substrate are close to the orthographic projection of the fourth power line on the base substrate.
  • At least one embodiment of the present disclosure provides a display substrate, including: a base substrate, including a pixel array area and a peripheral area, a first scan driving circuit, a plurality of power lines, a first signal line group, and a second signal line group;
  • the first scan driving circuit includes a plurality of cascaded first shift registers; the plurality of power lines are configured to The plurality of cascaded first shift registers included in the scan driving circuit provide a plurality of power supply voltages;
  • the first signal line group includes at least one timing signal line configured to provide multiple stages of the first scan driving circuit
  • the connected first shift register provides at least one timing signal;
  • the second signal line group includes a first trigger signal line, which is configured to be connected to a plurality of cascaded first shift registers included in the first scan driving circuit
  • the first shift register of the first stage is connected to provide a first trigger signal to the first shift register of the first stage.
  • the first scan driving circuit includes a first transistor, a second transistor, and a third transistor.
  • the first transistor, the second transistor, and the third transistor are respectively connected to the first signal line group, and the extension direction of the channels of the first transistor, the second transistor, and the third transistor It is parallel to the extending direction of the first signal line group and the second signal line group.
  • the first scan driving circuit further includes a sixth transistor and a seventh transistor, and the sixth transistor and the seventh transistor are respectively connected to the first signal The line group is connected, and the extension direction of the channel of the sixth transistor and the seventh transistor is parallel to the extension direction of the first signal line group and the second signal line group.
  • At least one embodiment of the present disclosure further provides a display device including the display substrate provided by any embodiment of the present disclosure.
  • At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate, including: providing a base substrate; and sequentially forming a semiconductor layer, a first insulating layer, a first conductive layer, and a first insulating layer in a direction perpendicular to the base substrate.
  • the second insulating layer, the second conductive layer, the third insulating layer, and the third conductive layer; the power line, the first signal line group, and the second signal line group are located on the third conductive layer;
  • a scan driving circuit is formed on the semiconductor layer, the first conductive layer and the second conductive layer; the first scan driving circuit penetrates the first insulating layer, the second insulating layer and the The via holes of the third insulating layer are respectively connected to the power line, the first signal line group, and the second signal line group.
  • Figure 1 is a circuit diagram of a light-emitting control shift register
  • FIG. 2 is a signal timing diagram of the light-emitting control shift register shown in FIG. 1 during operation;
  • FIG. 3 is a schematic diagram of a first resistor and a second resistor provided by at least one embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • 5A is a schematic diagram of the layout of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 5B shows a schematic diagram of the layout of the display substrate including the first stage shift register of the second scan driving circuit
  • FIG. 7A, FIG. 8 and FIG. 9A respectively show plan views of each layer wiring of the display substrate shown in FIG. 5A;
  • FIG. 6B, FIG. 7B, FIG. 8 and FIG. 9B respectively show plan views of each layer wiring of the first-stage shift register included in the display substrate shown in FIG. 5B;
  • FIG. 10 is a cross-sectional view of the display substrate shown in FIG. 5B along the A-A' direction;
  • FIG. 11 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • FIG. 12 is a flowchart of a manufacturing method of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 1 is a circuit diagram of a light-emitting control shift register.
  • FIG. 2 is a signal timing diagram of the light-emitting control shift register shown in FIG. 1 during operation. The working process of the light-emitting control shift register will be briefly introduced below in conjunction with FIG. 1 and FIG. 2.
  • the light emission control shift register 100 includes 10 transistors (first transistor T1, second transistor T2, ..., tenth transistor T10) and 3 capacitors (first capacitor C1, second capacitor C2, The third capacitor C3).
  • the first pole of the first transistor T1 in the first stage shift register 100 is configured to be connected to the first trigger signal line ESTV1 to receive the first trigger signal ESTV1
  • the first pole of the first transistor T1 in the light-emission control shift register 100 at other levels is connected to the light-emission control shift register 100 at the previous level to receive the first output signal output by the light-emission control shift register 100 at the previous level EM.
  • CK in FIGS. 1 and 2 represents the first clock signal terminal
  • ECK represents the first clock signal line and the first clock signal
  • the first clock signal terminal CK is connected to the first clock signal line ECK to receive the first clock.
  • CB represents the second clock signal terminal
  • ECB represents the second clock signal line and the second clock signal
  • the second clock signal terminal CB and the second clock signal line ECB are connected to receive the second clock signal, for example, the first clock
  • the signal ECK and the second clock signal ECB can use pulse signals with a duty cycle greater than 50%
  • VGH1 represents the first power supply voltage provided by the first power supply line and the first power supply line, for example, the first power supply voltage is a DC high level
  • VGL1 represents the third power supply line and the second power supply voltage provided by the third power supply line.
  • the second power supply voltage is a DC low level
  • the first power supply voltage is greater than the second power supply voltage
  • N1, N2, N3, and N4 represent respectively The first node, the second node
  • the gate of the first transistor T1 is connected to the first clock signal terminal CK (ie, the first clock signal line ECK) to receive the first clock signal, and the first electrode of the first transistor T1 and the input terminal IN Connected, the second electrode of the first transistor T1 is connected to the first node N1.
  • the input terminal IN is connected to the first trigger signal line ESTV1 to receive the first trigger signal
  • the light emission control shift register is the first stage shift register
  • the input terminal IN is connected to the output terminal OUT of the upper stage light-emitting control shift register.
  • the gate of the second transistor T2 is connected to the first node N1
  • the first electrode of the second transistor T2 is connected to the first clock signal line ECK to receive the first clock signal
  • the second electrode of the second transistor T2 is connected to the second node N2 connection.
  • the gate of the third transistor T3 is connected to the first clock signal line ECK to receive the first clock signal, the first pole of the third transistor is connected to the third power line VGL1 to receive the second power supply voltage, and the second of the third transistor T3 The pole is connected to the second node N2.
  • the gate of the fourth transistor T4 is connected to the second clock signal terminal CB (ie, the second clock signal line ECB) to receive the second clock signal, the first pole of the fourth transistor T4 is connected to the first node N1, and the fourth transistor The second pole of T4 is connected to the first pole of the fifth transistor T5.
  • the gate of the fifth transistor T5 is connected to the second node N2, and the second electrode of the fifth transistor T5 is connected to the first power line VGH to receive the first power voltage.
  • the gate of the sixth transistor T6 is connected to the second node N2, the first electrode of the sixth transistor T6 is connected to the second clock signal line ECB to receive the second clock signal, and the second electrode of the sixth transistor T6 is connected to the third node N3 connection.
  • the first end of the first capacitor C1 is connected to the second node N2, and the second end of the first capacitor C2 is connected to the third node N3.
  • the gate of the seventh transistor T7 is connected to the second clock signal line ECB to receive the second clock signal, the first electrode of the seventh transistor T7 is connected to the third node N3, and the second electrode of the seventh transistor T7 is connected to the fourth node N4 connection.
  • the gate of the eighth transistor T8 is connected to the first node N1, the first electrode of the eighth transistor T8 is connected to the first power supply line VGH1 to receive the first power supply voltage, and the second electrode of the eighth transistor T8 is connected to the fourth node N4 .
  • the gate of the ninth transistor T9 is connected to the fourth node N4, the first electrode of the ninth transistor T9 is connected to the first power line VGH1 to receive the first power voltage, and the second electrode of the ninth transistor T9 is connected to the output terminal OUT.
  • the first terminal of the third capacitor C3 is connected to the fourth node N4, and the second terminal of the third capacitor C3 is connected to the first power line VGH1 to receive the first power voltage.
  • the gate of the tenth transistor T10 is connected to the first node N1, the first electrode of the tenth transistor T10 is connected to the third power line VGL1 to receive the second power voltage, and the second electrode of the tenth transistor T10 is connected to the output terminal OUT.
  • the first end of the second capacitor C2 is connected to the second clock signal line ECB to receive the second clock signal, and the second end of the second capacitor C2 is connected to the first node N1.
  • the transistors in the light emission control shift register 100 shown in FIG. 1 are all described using P-type transistors as an example, that is, each transistor is turned on when the gate is connected to a low level, and is turned off when the gate is connected to a high level.
  • the first electrode may be a source electrode
  • the second electrode may be a drain electrode.
  • each transistor in the light-emitting control shift register 100 can also adopt N-type transistors or a mixture of P-type transistors and N-type transistors.
  • the port polarity of the type of transistor can be connected according to the port polarity of the corresponding transistor in the embodiment of the present disclosure.
  • FIG. 2 is a signal timing diagram of the light-emitting control shift register shown in FIG. 1 during operation.
  • the working process of the light-emitting control shift register will be described in detail below in conjunction with FIG. 1 and FIG. 2.
  • the working principle of the first-stage light-emitting control shift register 100 is described, and the working principles of the other stages of the light-emitting control shift register 100 are similar to this, and will not be repeated.
  • the working process of the light emission control shift register includes six stages, namely the first stage P1, the second stage P2, the third stage P3, the fourth stage P4, the fifth stage P5 and the sixth stage.
  • P6, Figure 2 shows the timing waveforms of each signal in each phase.
  • the first clock signal ECK is low, so the first transistor T1 and the third transistor T3 are turned on, and the turned-on first transistor T1 will be high.
  • the trigger signal ESTV1 is transmitted to the first node N1, so that the level of the first node N1 becomes a high level, so the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned off.
  • the turned-on third transistor T3 transmits the low-level second power supply voltage VGL1 to the second node N2, so that the level of the second node N2 becomes low, so the fifth transistor T5 and the sixth transistor T6 is turned on. Since the second clock signal ECB is at a high level, the seventh transistor T7 is turned off.
  • the level of the fourth node N4 can be maintained at a high level, so that the ninth transistor T9 is turned off.
  • the first output signal output by the output terminal OUT_1 of the light emission control shift register 100 maintains the previous low level.
  • the second clock signal ECB is low, so the fourth transistor T4 and the seventh transistor T7 are turned on. Since the first clock signal ECK is at a high level, the first transistor T1 and the third transistor T3 are turned off. Due to the storage effect of the first capacitor C1, the second node N2 can continue to maintain the low level of the previous stage, so the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the high-level first power supply voltage VGH1 is transmitted to the first node N1 through the turned-on fifth transistor T5 and the fourth transistor T4, so that the level of the first node N1 continues to maintain the high level of the previous stage, so the first The second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned off.
  • the low-level second clock signal ECB is transmitted to the fourth node N4 through the turned-on sixth transistor T6 and the seventh transistor T7, so that the level of the fourth node N4 becomes low, so the ninth The transistor T9 is turned on, and the turned-on ninth transistor T9 outputs the high-level first power supply voltage VGH1, so the first output signal output by the output terminal OUT_1 of the light-emitting control shift register 100 in the second stage P2 is high Level.
  • the first clock signal ECK is low, so the first transistor T1 and the third transistor T3 are turned on.
  • the second clock signal ECB is at a high level, so the fourth transistor T4 and the seventh transistor T7 are turned off. Due to the storage effect of the third capacitor C3, the level of the fourth node N4 can maintain the low level of the previous stage, so that the ninth transistor T9 remains in the on state, and the turned-on ninth transistor T9 will be high.
  • the first power supply voltage VGH1 is output, so the output signal output by the output terminal OUT_1 of the light emission control shift register 100 in the third stage P3 is still at a high level.
  • the output terminal OUT_2 of the second stage light-emitting control shift register 100 outputs a high level (for detailed description, please refer to the working process of the first stage light-emitting control shift register in the second stage P2).
  • the first clock signal ECK is at a high level, so the first transistor T1 and the third transistor T3 are turned off.
  • the second clock signal ECB is low, so the fourth transistor T4 and the seventh transistor T7 are turned on. Due to the storage effect of the second capacitor C2, the level of the first node N1 maintains the high level of the previous stage, so that the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned off. Due to the storage effect of the first capacitor C1, the second node N2 continues to maintain the low level of the previous stage, so that the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the low-level second clock signal ECB is transmitted to the fourth node N4 through the turned-on sixth transistor T6 and the seventh transistor T7, so that the level of the fourth node N4 becomes low, so the ninth The transistor T9 is turned on, and the turned-on ninth transistor T9 outputs the high-level first power supply voltage VGH1, so the first output signal output by the output terminal OUT_1 of the light emission control shift register 100 in the second stage P2 is still High level.
  • the output terminal OUT_2 of the second stage light emission control shift register 100 outputs a high level (for detailed description, please refer to the working process of the first stage light emission control shift register in the third stage P3).
  • the first clock signal ECK is low, so the first transistor T1 and the third transistor T3 are turned on.
  • the second clock signal ECB is at a high level, so the fourth transistor T4 and the seventh transistor T7 are turned off.
  • the turned-on first transistor T1 transmits the low-level first trigger signal ESTV to the first node N1, so that the level of the first node N1 becomes low.
  • the low level voltage of the first clock signal ECK is -6V
  • the low level voltage of the first trigger signal ESTV1 is -6V
  • the threshold voltage Vth of the first transistor T1 is -1.5V . Since the first transistor T1 is a P-type transistor, in order to turn on the first transistor T1, the voltage Vgs of the gate and source of the first transistor T1 needs to be smaller than the threshold voltage Vth of the first transistor T1. Therefore, when the first node N1 When the first transistor T1 is charged to -4.5V, the first transistor T1 is turned off. At this time, the charging of the first node N1 is stopped.
  • the low-level voltage of the first node N1 is -4.5V, so the second transistor T2, the second transistor The eight transistor T8 and the tenth transistor T10 are turned on.
  • the turned-on second transistor T2 transmits the low-level first clock signal ECK to the second node N2, thereby further lowering the level of the second node N2, so the second node N2 continues to maintain the low power level of the previous stage Level, so that the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the turned-on eighth transistor T8 transmits the high-level first power supply voltage VGH1 to the fourth node N4, so that the level of the fourth node N4 becomes a high level, so the ninth transistor T9 is turned off.
  • the turned-on tenth transistor T10 responds to the low level (for example, -4.5V) of the first node N1 and outputs the low level second power supply voltage VGL (for example, -6V). Similarly, the tenth transistor T10 The threshold voltage Vth of the tenth transistor T10 is -1.5V. In order to turn on the tenth transistor T10, the voltage Vgs of the gate and source of the tenth transistor T10 needs to be smaller than the threshold voltage Vth of the tenth transistor T10.
  • the output terminal OUT outputs The tenth transistor T10 is turned off when the voltage is -3V, that is, the voltage of the low level of the output terminal OUT at this stage is -3V, so the output signal of the output terminal OUT_1 of the light emission control shift register 100 in the fifth stage P5 It becomes the first low level (for example, -3V).
  • the output terminal OUT_2 of the second-stage light-emitting control shift register 100 outputs a high level (for detailed description, please refer to the working process of the first-stage light-emitting control shift register in the fourth stage P4).
  • the first clock signal ECK is at a high level and the second clock signal ECB is at a low level, so the fourth transistor T4 and the seventh transistor T7 are turned on.
  • the second clock signal ECB changes from the high level of the fifth stage P5 to the low level, for example, the amount of change is ⁇ t (for example, greater than 6V), according to the bootstrap effect of the second capacitor C2, the power of the first node N1
  • the level changes from the low level (for example, -4.5V) of P5 in the fifth stage to a lower low level (for example, -4.5V- ⁇ t), so that the second transistor T2 and the tenth transistor T10 are in the first
  • the node N1 is turned on under the control of the low level (for example, -4.5V- ⁇ t).
  • the low level second power supply voltage VGL (for example, -6V) Can be completely output to the output terminal OUT.
  • the voltage output by the output terminal OUT is the second low level (for example, -6V).
  • the output terminal OUT_2 of the second stage first shift register 100 outputs a low level (for example, -3V, for specific description, please refer to the working process of the first stage first shift register in the fourth stage P4. ).
  • the space left for the first trigger signal line ESTV1 is small, which makes it inconvenient to introduce multiple trigger signal lines.
  • the eighth transistor T8, and the ninth transistor T9 are wound in order to be connected to the first power supply voltage line VGH1, thereby increasing
  • the space occupied by the display substrate in the vertical direction is not conducive to the layout design of the display substrate.
  • At least one embodiment of the present disclosure provides a display substrate, including: a base substrate including a pixel array area and a peripheral area; a first scan driving circuit, a plurality of power lines, a first signal line group, and a second signal line group; In the peripheral area and located on the first side of the base substrate.
  • the first scan driving circuit includes a plurality of cascaded first shift registers; the plurality of power supply lines are configured to provide a plurality of power supply voltages to the plurality of cascaded first shift registers included in the first scan driving circuit; a first signal The line group includes at least one timing signal line, configured to provide at least one timing signal to a plurality of cascaded first shift registers included in the first scan driving circuit; the second signal line group includes a first trigger signal line, configured to The first-stage first shift register of the plurality of cascaded first shift registers included in the first scan driving circuit is connected to provide a first trigger signal to the first-stage first shift register, and the first trigger signal line Located between the multiple power supply voltage lines and the pixel array area.
  • At least one embodiment of the present disclosure also provides a display device and a manufacturing method corresponding to the above-mentioned display substrate.
  • the first trigger signal line is arranged between the plurality of power lines and the pixel array area, which facilitates the introduction of signal lines and facilitates the realization of the display of a large-size display panel.
  • the display substrate may be suitable for a single-row single-drive scan driving circuit, that is, the output signal output by the first-stage shift register drives only one row of pixel units. Since the single-row single-drive scan driving circuit requires half of the driving load compared to the single-row dual-drive scan driving circuit, it has stronger driving capability and is more suitable for large-size display panels.
  • the display substrate can also be applied to a single-row dual-drive scan driving circuit, that is, the output signal output by the one-stage shift register can drive two rows of pixel units, which is not limited in the embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • the display substrate 1 includes a base substrate 10, a first scan driving circuit 130, a plurality of power lines 140, a first signal line group 150, and a second signal line group 160.
  • the base substrate 100 may be made of, for example, glass, plastic, quartz, or other suitable materials, which are not limited in the embodiments of the present disclosure.
  • the base substrate 10 includes a pixel array area 110 and a peripheral area 120.
  • a first scan driving circuit 130, a plurality of power supply lines 140, a first signal line group 150, and a second signal line group 160 are arranged in the peripheral area 120 and located
  • the first side of the base substrate 10 is, for example, located on the left side of the base substrate 10.
  • the pixel array area 110 includes a plurality of pixel units P arranged in an array.
  • each of the plurality of pixel units P includes a pixel circuit, for example, may further include a light-emitting element (not shown in the figure).
  • the first scan driving circuit 130 includes a plurality of cascaded first shift registers 100, for example, includes a plurality of shift registers 100 as shown in FIG. 1.
  • the first shift register 100 is referred to as the shift register 100 for short below.
  • the output terminals of the plurality of shift registers 100 are respectively connected to the light emission control terminals of each row of pixel circuits located in the pixel array area to provide output signals (for example, light emission control signals) to the pixel circuits of each row, so as to drive the light emitting elements to emit light.
  • the pixel circuit may be a pixel circuit including circuit structures such as 2T1C, 4T2C, 8T2C, etc. in the art, which will not be repeated here.
  • the first scan driving circuit 130 includes at least one transistor, and the extension direction of the channel of the at least one transistor is parallel to the extension direction of the first signal line group 150 and the second signal line group 160, so that the first scan driving can be reduced.
  • the circuit 130 has an area in the direction perpendicular to the channel length direction, which improves the process matching degree and forms a better channel effect.
  • the first scan driving circuit 130 includes a first transistor T1, a second transistor T2, and a third transistor T3.
  • the first transistor T1, the second transistor T2, and the third transistor T3 are respectively connected to the first signal line group 150, for example, It is connected to the first clock signal ECK in the first signal line group 150.
  • the extension directions of the channels of the first transistor T1, the second transistor T2, and the third transistor T3 are parallel to the extension directions of the first signal line group 150 and the second signal line group 160.
  • the extension direction of the channel is the extension direction from the first pole to the second pole of the transistor, for example, the extension direction from the first pole to the second pole of the first transistor T1.
  • the first scan driving circuit 130 further includes a sixth transistor T6 and a seventh transistor T7, the sixth transistor T6 and the seventh transistor T7 are respectively connected to the first signal line group 150, and the sixth transistor T6 and the seventh transistor T7 are connected to each other.
  • the extension direction of the track is parallel to the extension direction of the first signal line group 150 and the second signal line group 160.
  • the plurality of power supply lines 140 are configured to provide a plurality of power supply voltages to the plurality of cascaded shift registers 100 included in the first scan driving circuit 130.
  • a first power supply voltage for example, with a high DC level
  • a second power supply voltage for example, with a low DC level
  • the first signal line group 150 includes at least one timing signal line, for example, including a first clock signal line ECK and a second clock signal line ECB, and is configured to add multiple cascaded shift registers 100 included in the first scan driving circuit 130 At least one timing signal is provided, for example, the first clock signal ECK and the second clock signal ECB described above.
  • the second signal line group 160 includes a first trigger signal line ESTV1, which is configured to be a first-stage shift register in a plurality of cascaded shift registers 100 included in the first scan driving circuit 150 Connected to provide the first trigger signal to the first stage shift register.
  • the first trigger signal line ESTV1 is located between the plurality of power supply lines 140 and the pixel array area 110.
  • the first trigger signal line ESTV1 may be located on the right side of the first scan drive circuit 130, that is, the orthographic projection of the first trigger signal line ESTV1 on the base substrate 10 is located on the first scan drive circuit.
  • the orthographic projection of the base substrate 10 and the orthographic projection of the first scan driving circuit 130 on the base substrate 10 at least partially overlap, as long as it can be installed in an area where the wiring is not dense to facilitate the introduction of trigger signal lines.
  • the embodiment does not limit this.
  • the display substrate may also include a plurality of scan driving circuits, and a plurality of trigger signal lines respectively connected to the first-stage shift registers of the plurality of scan driving circuits, which is not limited in the embodiment of the present disclosure. .
  • the display substrate when the display substrate further includes a plurality of scan driving circuits such as a second scan driving circuit, a third scan driving circuit, etc., the display substrate further includes a first-stage shift with the second scan driving circuit.
  • There are multiple trigger signal lines such as the second trigger signal line ESTV2 connected to the bit register and the third trigger signal line connected to the first stage shift register of the third scan driving circuit.
  • multiple scan driving circuits such as the second scan driving circuit and the third scan driving circuit have the same structure as the first scan driving circuit and are arranged in sequence with the first scan driving circuit to jointly drive the pixel array area of the display substrate.
  • the pixel array area includes a plurality of display areas that do not overlap each other (for example, arranged side by side), and a plurality of scan driving circuits such as a first scan driving circuit, a second scan driving circuit, and a third scan driving circuit respectively drive the corresponding displays. area.
  • a plurality of scan driving circuits such as a first scan driving circuit, a second scan driving circuit, and a third scan driving circuit respectively drive the corresponding displays. area.
  • the second signal line group 160 also includes the plurality of trigger signal lines.
  • the plurality of trigger signal lines may be located between the plurality of power supply lines 140 and the pixel array area 110, for example, located on the right side of each scan driving circuit, or at least overlap with each scan driving circuit, as long as it can be set in The area where the wiring is not dense is sufficient to facilitate the introduction of the trigger signal line, which is not limited in the embodiment of the present disclosure.
  • the display substrate provided by the above-mentioned embodiments of the present disclosure by adjusting the position of the first trigger signal line, avoids problems such as the inability to introduce more signal lines and winding connections due to dense wiring, and is more conducive to the realization of the display panel
  • the narrow frame design is conducive to the realization of large-size display panels.
  • FIG. 5A is a schematic diagram of a layout of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 5B shows a schematic diagram of the layout of the display substrate of the first stage shift register including the second scan driving circuit.
  • Fig. 10 is a cross-sectional view of the display substrate shown in Fig. 5B along the A-A' direction.
  • FIG. 10 can also be used to explain the laminated structure shown in FIG. 5A.
  • the stacked structure of the first-stage shift register shown in FIG. 5B can be applied to the first-stage shift register of each scan driving circuit, and only needs to change the connection with the corresponding trigger signal.
  • the first-stage shift register of a scan driving circuit is connected to the first trigger signal line ESTV1
  • the first-stage shift register of the second scan driving circuit is connected to the second trigger signal line ESTV2..., and so on.
  • FIG. 6A, FIG. 7A, FIG. 8 and FIG. 9A respectively show plan views of each layer wiring of the display substrate shown in FIG. 5A.
  • 6A is a plan view of a semiconductor layer of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 7A is a plan view of a first conductive layer of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 8 is a display provided by at least one embodiment of the present disclosure
  • FIG. 9A is a plan view of the third conductive layer of the display substrate provided by at least one embodiment of the present disclosure.
  • an interlayer insulating layer (for example, including a first insulating layer, a second insulating layer, a third insulating layer, etc.) may be located between the layer structures shown in FIGS. 6A to 9A.
  • the first insulating layer 350 (shown in FIG. 10) is located between the semiconductor layer 310 shown in FIG. 6A and the first conductive layer 320 shown in FIG. 7A
  • the second insulating layer 360 (shown in FIG. 10) is located Between the first conductive layer 320 shown in FIG. 7A and the second conductive layer 330 shown in FIG. 8, the third insulating layer 370 (shown in FIG. 10) is located between the second conductive layer 330 shown in FIG. 8 and FIG. 9A Between the third conductive layer 340 shown.
  • the display substrate further includes a fourth insulating layer 380, and the fourth insulating layer 380 is located on the third conductive layer 340 for protecting the third conductive layer 340.
  • the materials of the first insulating layer 350, the second insulating layer 360, the third insulating layer 370, and the fourth insulating layer 380 may include inorganic insulating materials such as SiNx, SiOx, SiNxOy, and organic insulating materials such as organic resins, or other materials. Suitable materials are not limited in the embodiments of the present disclosure.
  • the display substrate shown in FIG. 5A takes the layout design of a shift register in the first scan driving circuit and the signal line connected to it as an example for description, and the layout implementation of the shift registers at other levels can be referred to The layout shown in FIG. 5A will not be repeated here.
  • other layouts may also be adopted, which is not limited in the embodiment of the present disclosure.
  • the shift registers of each level of the remaining scan driving circuits can also refer to the layout shown in FIG. 5A, and other layout implementations can also be adopted, which is not limited in the embodiments of the present disclosure.
  • the display substrate provided by at least one embodiment of the present disclosure will be described in detail below with reference to FIGS. 5A to 9A.
  • the first transistor T1 to the tenth transistor T10 of the shift register 100 shown in FIG. 5A may be formed on the semiconductor layer 310 shown in FIG. 6A.
  • the semiconductor layer 310 may be formed by patterning a semiconductor material.
  • the semiconductor layer 310 may have a short rod shape or a curved or bent shape as required, and may be used to fabricate the active layers of the first transistor T1 to the tenth transistor T10.
  • Each active layer may include a source region, a drain region, and a channel region between the source region and the drain region.
  • the channel region may be doped with impurities, thereby having semiconductor characteristics; the source region and the drain region are on both sides of the channel region, and may be doped with impurities, and thus have conductivity.
  • the source region corresponds to the source (or called the first electrode) of the transistor
  • the drain region corresponds to the drain (or called the second electrode) of the transistor.
  • the active layer of the first transistor T1 includes a source region S1, a drain region D1 (shown by the dotted line in FIG. 10), and a channel region P1.
  • the first transistor T1 also includes a gate G1, where the gate G1 is located on the first conductive layer 320, which will be introduced below, and will not be repeated here. It should be noted that the drain region D1 of the first transistor is not in the cross-sectional view along the A-A′ direction in FIG. 5B. To ensure a clear description, the drain region D1 of the first transistor T1 is added with a dotted line in FIG. 10.
  • the material of the semiconductor layer 310 may include oxide semiconductors, organic semiconductors, or amorphous silicon, polysilicon, etc.
  • the oxide semiconductors include metal oxide semiconductors (such as indium gallium zinc oxide (IGZO)), and the polysilicon includes low-temperature polysilicon or high-temperature polysilicon.
  • IGZO indium gallium zinc oxide
  • Polysilicon and the like are not limited in the embodiments of the present disclosure.
  • the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities, which is not limited in the embodiments of the present disclosure.
  • first electrode and the second electrode of each transistor can also be located on other conductive layers, and are connected to their corresponding active layers through vias in the insulating layer between them and the semiconductor layer.
  • the embodiment of the present disclosure does not limit this.
  • FIG. 7A shows the first conductive layer 320 of the display substrate.
  • the first conductive layer 320 is disposed on the first insulating layer so as to be insulated from the semiconductor layer 310.
  • the first conductive layer 320 may include the first electrodes CE11, CE12, and CE13 of the first capacitor C1 to the third capacitor C3 and the gates of the first transistor T1 to the tenth transistor T10.
  • the first insulating layer also serves as a gate. Extremely insulating layer.
  • the gates of the first transistor T1 to the tenth transistor T10 are the parts where the semiconductor layer structure of each transistor overlaps the wiring on the first conductive layer 320.
  • FIG. 8 shows the second conductive layer 330 of the display substrate.
  • the second conductive layer 330 includes the second electrodes CE21, CE22, CE23 of the first capacitor C1 to the third capacitor C3.
  • the second electrode CE21 and the first electrode CE11 at least partially overlap to form a first capacitor C1
  • the second electrode CE22 and the first electrode CE12 at least partially overlap to form a second capacitor C2
  • the second electrode CE23 and the first electrode CE13 at least Partially overlap to form a third capacitor C3.
  • the third conductive layer 340 includes a first signal line group 150, a plurality of power lines 140, and a second signal line group 160. It should be noted that the third conductive layer also includes conductive connections between transistors, capacitors, and signal lines. As shown in FIGS. 5A and 9A, the first signal line group 150, the plurality of power lines 140, and the second signal line group 160 are connected to the transistors in the remaining layers that need to be connected to them through at least one via hole, and each transistor also passes through At least one via is connected or bridged by a conductive connection part, which will not be repeated here.
  • the material of the third conductive layer 340 may include aluminum, aluminum alloy, copper, copper alloy, or any other suitable material, which is not limited in the embodiment of the present disclosure.
  • the material of the first conductive layer 320 and the second conductive layer 330 may be the same as the material of the third conductive layer 340, which will not be repeated here.
  • FIG. 5A shows the relationship between the stacked position of the semiconductor layer 310 shown in FIG. 6A, the first conductive layer 320 shown in FIG. 7A, the second conductive layer 330 shown in FIG. 8 and the third conductive layer 340 shown in FIG. 9A Schematic.
  • the display substrate includes a first signal line group 150 (for example, including a first clock signal line ECK and a second clock signal line ECB) and multiple One power supply line 140 (for example, includes a third power supply line VGL1, a first power supply line VGH1, and a fourth power supply line VGL2) and a second signal line group 160 (for example, includes a first trigger signal line ESTV1).
  • first signal line group 150 for example, including a first clock signal line ECK and a second clock signal line ECB
  • multiple One power supply line 140 for example, includes a third power supply line VGL1, a first power supply line VGH1, and a fourth power supply line VGL2
  • a second signal line group 160 for example, includes a first trigger signal line ESTV1.
  • the second signal line group 160 also includes a second start signal line ESTV2.
  • the second signal line group 160 is located on the side of the first scan driving circuit 130 close to the pixel array area 110, and the first signal line group 150 is located on the first scan driving circuit 130.
  • the other side opposite to the side where the second signal line group 160 is located.
  • the second signal line group 160 is located on the right side of the shift register 100, and the first signal line group 150 is located on the left side of the shift register 100.
  • the second signal line group 160 such as the first trigger signal line ESTV1 and the second trigger signal line ESTV2 are arranged on the right side of the shift register, that is, it is connected to the first signal group 150 and multiple power lines 140.
  • Separate arrangement can avoid the dense wiring caused by too many signal lines on the left side, thereby avoiding the problem that the space left for the trigger signal line is too small due to the dense wiring, which affects the introduction of other signal lines.
  • the plurality of power supply lines 140 include a first power supply line VGH1, a second power supply line VGH2, a third power supply line VGL1, and a fourth power supply line VGL2.
  • the first power supply line VGH1 and the second power supply line VGH2 provide the same first power supply voltage, for example, a DC high voltage.
  • the orthographic projection of the first power line VGH1 on the base substrate 10 overlaps with the orthographic projection of the first scan driving circuit on the base substrate 10, and the orthographic projection of the second power line VGH2 on the base substrate 10 is located on the first power line. Between the orthographic projection of VGH1 on the base substrate 10 and the orthographic projection of the second signal line group 160 on the base substrate.
  • the orthographic projection of the first scan driving circuit on the base substrate 10 is not a continuous area. Therefore, the orthographic projection of the first power line VGH1 on the base substrate 10 only needs to be the same as that of the first scan driving circuit.
  • the transistors or capacitors can be overlapped on the orthographic projection portion of the base substrate 10. The embodiment of the present disclosure does not limit this.
  • the orthographic projection of the first power line VGH1 on the base substrate 10 overlaps the trace on the first conductive layer 320, for example, and the gate of the third transistor T3 and the first transistor T1.
  • the wiring between the gates, the wiring connecting the gate of the fourth transistor T4, the wiring connecting the gate of the fifth transistor T5, and the wiring connecting the gate of the second transistor T2 partially overlap.
  • each shift register of the first scan driving circuit includes a first constituent transistor connected to the first power supply line VGH1, and a second constituent transistor and a third constituent transistor connected to the second power supply line VGH2.
  • the fifth transistor T5 is an example of the first constituent transistor
  • the eighth transistor T8 is an example of the second constituent transistor
  • the ninth transistor T9 is an example of the third constituent transistor.
  • the first constituent transistor is the fifth transistor T5, the second constituent transistor is the eighth transistor T8, and the third constituent transistor is the ninth transistor T9 as an example for description, which is not limited in the embodiment of the present disclosure. The following embodiments are the same as this and will not be repeated here.
  • the orthographic projection of the fifth transistor T5 on the base substrate 10 is located between the orthographic projection of the first signal line group 150 on the base substrate 10 and the orthographic projection of the first power line VGH1 on the base substrate and is close to the first power line.
  • the orthographic projection of VGH1 on the base substrate 10 the orthographic projection of the eighth transistor T8 and the ninth transistor T9 on the base substrate 10 are located on the orthographic projection of the first power line VGH1 on the base substrate 10 and the second power line VGH2 on the substrate between the orthographic projections of the substrate 10 and close to the orthographic projection of the second power line VGH2 on the base substrate 10.
  • the first power line VGH1 is arranged at a position close to the fifth transistor T5, and the eighth transistor T8 and the ninth transistor T9 are arranged at a position close to the second power line VGH2, so that the fifth transistor T5, the eighth transistor T8, and the The ninth transistor T9 is wired in order to be connected to one power line (for example, the first power line VGH1), thereby avoiding the space occupied by the winding in the vertical direction of the display substrate.
  • one power line for example, the first power line VGH1
  • the third power supply line VGL1 and the fourth power supply line VGL2 are configured to provide the same second power supply voltage, for example, a DC low voltage.
  • the first power supply voltage is higher than the second power supply voltage.
  • the orthographic projection of the fourth power line VGL2 on the base substrate 10 overlaps with the orthographic projection of the first scan driving circuit on the base substrate 10, and the orthographic projection of the third power line VGL1 on the base substrate 10 is located on the third power line. Between the orthographic projection of VGL1 on the base substrate 10 and the orthographic projection of the first signal line group 150 on the base substrate 10.
  • the orthographic projection of the first scan driver circuit on the base substrate 10 is not a continuous area. Therefore, the orthographic projection of the fourth power line VGL2 on the base substrate 10 only needs to be in line with some transistors of the first scan driver circuit. Or the capacitors can be overlapped on the orthographic projection part of the base substrate 10. The embodiment of the present disclosure does not limit this.
  • the orthographic projection of the fourth power line VGL2 on the base substrate 10 overlaps the trace on the first conductive layer 320, for example, and the trace connected to the gate of the eighth transistor T8 and connected to the first conductive layer.
  • the wiring of the gate of the ten transistor T10 and the first electrode CE12 of the second capacitor C2 partially overlap.
  • each shift register of the first scan driving circuit further includes a fourth constituent transistor connected to the third power supply line VGL1, and a fifth constituent transistor connected to the fourth power supply line VGL2.
  • the third transistor T3 is an example of the fourth constituent transistor
  • the tenth transistor T10 is an example of the fifth constituent transistor.
  • the third transistor T3 is the fourth constituent transistor and the tenth transistor T10 is the fifth constituent transistor as an example for description, which is not limited in the embodiment of the present disclosure. The following embodiments are the same as this and will not be repeated here.
  • the orthographic projection of the third transistor T3 on the base substrate 10 is located on the orthographic projection of the third power line VGL1 on the base substrate 10 away from the first signal line group 150 on the side of the orthographic projection of the base substrate 10, and close to the first The orthographic projection of the three power supply lines VGL1 on the base substrate 10.
  • the orthographic projection of the tenth transistor T10 on the base substrate 10 is located between the orthographic projection of the fourth power line VGL2 on the base substrate 10 and the orthographic projection of the second signal line group 160 on the base substrate 10, and is close to the tenth.
  • the third power line VGL1 is disposed at a position close to the third transistor T3, and the tenth transistor T10 is disposed at a position close to the fourth power line VGL2, so as to prevent the third transistor T3 and the tenth transistor T10 from being connected to the same power line.
  • the third power line VGL1 or are respectively connected to the third power line VGL1 and the fourth power line VGL2 located on the left side of the display substrate to be wound, thereby avoiding the space occupied by the winding in the vertical direction of the display substrate .
  • the first power line VGH1, the second power line VGH2, the third power line VGL1, and the fourth power line VGL2 respectively beside the transistors connected to it, it is possible to prevent each transistor from being balanced. It is connected to a power cord and wound, thereby avoiding the space occupied by the winding in the vertical direction of the display substrate, which is beneficial to realize the design of a narrow frame.
  • the pixel array area 110 includes a first display area and a second display area (not shown in the figure) that are parallel to each other and do not overlap, and the first scan driving circuit 130 is connected to the first display area to drive the second display area. A display area is displayed.
  • the display substrate further includes a second scan driving circuit arranged in the peripheral area and located on one side of the base substrate.
  • the second scan driving circuit is arranged in sequence with the first scan driving circuit along the scanning direction (for example, the column direction) of the pixel array, and is connected to the second display area to drive the second display area to display.
  • the second scan driving circuit includes a plurality of cascaded second shift registers (for example, includes the first stage shift register 132 shown in FIG. 5B).
  • the structure of the second shift register is the same as the circuit structure of the first shift register, and both adopt the circuit structure of the shift register shown in FIG. 1.
  • the structure of the second shift register is the same as that of the first shift register.
  • the circuit structure may also be different, which is not limited in the embodiments of the present disclosure.
  • the second shift register is also referred to as a shift register for short below. The following embodiments are the same as this and will not be repeated here.
  • the display substrate is a folding display substrate, and further includes a folding line, which is located between the first display area and the second display area.
  • the second resistor R2 is located in the extension direction of the fold line, and the extension direction of the fold line is perpendicular to the extension direction of the first signal line group 150 and the second signal line group 160, so that the signal line can penetrate the entire display substrate.
  • the extension direction of the one signal line group 150 and the second signal line group 160 is the vertical direction described in FIG. 4, and the extension direction of the folding line is the horizontal direction.
  • the second signal line group 160 further includes a second trigger signal line ESTV2, which is connected to the first-stage shift register 132 of the plurality of cascaded shift registers included in the second scan driving circuit,
  • the second trigger signal is provided to the first stage shift register 132 included in the second scan driving circuit.
  • the first trigger signal line ESTV1 and the second trigger signal line ESTN2 are adjacent and arranged side by side.
  • the first trigger signal line ESTV1 and the second trigger signal line ESTV2 extend side by side, and their extension lengths are the same as the arrangement length of the first scan driving circuit and the second scan driving circuit.
  • the remaining trigger signal lines can also be adjacent to and arranged side by side with the first trigger signal line ESTV1 and the second trigger signal line ESTV2, and their extension lengths can all be the same as those of the first trigger signal line ESTV1 and the second trigger signal line ESTV2.
  • the extension length of one trigger signal line ESTV1 and the second trigger signal line ESTV2 are the same.
  • FIG. 5B only schematically shows the last stage shift register 131 of the first scan driver circuit and the first stage shift register 132 of the second scan driver circuit.
  • the layout of the other stages of shift registers The manner can refer to the layout manner shown in FIG. 5A, and details are not described again.
  • FIG. 6B, FIG. 7B, FIG. 8 and FIG. 9B respectively show plan views of each layer wiring of the first-stage shift register included in the display substrate shown in FIG. 5B.
  • the display substrate provided by at least one embodiment of the present disclosure will be described in detail below with reference to FIGS. 5B to 9B.
  • the semiconductor layer shown in FIG. 6B is similar to the semiconductor layer shown in FIG. 6A, except that it also includes at least one resistor (for example, a second resistor R2); the first conductive layer 320 shown in FIG.
  • the first conductive layer 320 shown in 7A is similar, except that it also includes a first connection line L1 and a second connection line L2;
  • the third conductive layer 340 shown in FIG. 9B is similar to the third conductive layer 340 shown in FIG. 9A, The difference lies in that it also includes a first conductive connection portion 341 and a second conductive connection portion 342, and the specific connection relationship will be described in detail below.
  • the second trigger signal line ESTV2 provides a second trigger signal to the first-stage shift register 132 of the second scan driving circuit to drive the A plurality of cascaded shift registers output the output signal line by line.
  • the first trigger signal line ESTV1 provides the first trigger signal to the first scan driver circuit
  • the second trigger signal line ESTV2 provides the second trigger signal to the second scan driver circuit, so that it can be simultaneously
  • the first scan driving circuit and the second scan driving circuit are driven to work, as long as the pixel units in the pixel array area of the display substrate can be driven to display a normal image, which is not limited in the embodiment of the present disclosure.
  • the display substrate further includes at least one first resistor R1 (as shown in FIG. 3).
  • the first resistor R1 is located on the side of the first scan driving circuit 130 far away from the first shift register of the first stage.
  • the first trigger signal line ESTV1 is connected to the first stage shift register of the first scan driving circuit 130 (for example, the first transistor T1 of the first stage shift register) through the first resistor R1.
  • the display substrate may further include at least one second resistor R2.
  • the second resistor R2 is located between the last stage first shift register of the first scan driving circuit 130 and the first stage second shift register of the second scan driving circuit 230.
  • the second trigger signal line ESTV2 is connected to the first stage second shift register of the second scan driving circuit 230 through the second resistor R2, for example, to the first stage shift register 132 of the second scan driving circuit 230 A transistor T1 is connected.
  • the resistance of the first resistor R1 and the resistance of the second resistor R2 are different.
  • the first trigger signal line ESTV1 is connected to the controller 20 from the upper side of the display substrate to receive the first trigger signal, and the second trigger signal line ESTV2 passes through the middle of the display substrate to communicate with the controller 20.
  • the wiring resistance (load) of the first trigger signal line ESTV1 and the second trigger signal line ESTV2 are different, so, for example, the load on the first trigger signal line ESTV1 is greater than the second trigger signal line
  • the first resistor R1 is smaller than the second resistor R2, so that the resistance of the wiring resistance on the first trigger signal line ESTV1 plus the resistance of the first resistor and the wiring on the second trigger signal line ESTV1
  • the resistance of the resistor plus the resistance of the second resistor is approximately equal.
  • the resistance of the first resistor R1 is 5000 ohms
  • the resistance of the second resistor R2 is 5500 ohms
  • the resistance of the trace resistance on the first trigger signal line ESTV1 is 1000 ohms
  • the resistance of the second trigger The resistance value of the trace resistance on the signal line ESTV1 is 500 ohms.
  • the display substrate may also include a plurality of resistors to respectively connect the first-stage shift registers of the plurality of scan driving circuits and the corresponding trigger signal lines.
  • the display substrate when the display substrate includes a plurality of scan driving circuits such as a third scan driving circuit and a fourth scan driving circuit, correspondingly, the display substrate further includes a first transistor T1 connected to the first transistor T1 of the first stage shift register.
  • the settings of the remaining multiple resistors can refer to the settings of the first resistor and the second resistor R2, and will not be repeated.
  • the first resistance and the second resistance may be the same or different, and the specifics may be determined according to actual conditions, which are not limited in the embodiments of the present disclosure.
  • the material of the first resistor and the second resistor may be a semiconductor material, which may be provided in the same layer as the active layer of the transistor.
  • the first resistor and the second resistor are located in the semiconductor layer shown in Fig. 6B.
  • FIG. 5B shows the connection mode of the second resistor
  • the second resistor R2 shown in FIG. 5B is taken as an example for description.
  • Fig. 10 is a cross-sectional view of the display substrate shown in Fig. 5B along the A-A' direction. The connection manner of each resistor using the second resistor as an example will be described in detail below in conjunction with FIG. 5B and FIG. 10.
  • the second resistor R2 is located between the base substrate 10 and the second signal line group 160 in a direction perpendicular to the base substrate 10 (ie, located on the semiconductor layer 310), and the second resistor R2
  • the orthographic projection on the base substrate 10 is located on the side of the orthographic projection of the second signal line group 160 on the base substrate 10 away from the pixel array area.
  • the first resistor is located between the base substrate 10 and the second signal line group 160 in a direction perpendicular to the base substrate 10 (ie, located in the semiconductor layer 310), and the first resistor is in the orthographic projection of the base substrate 10 It is located on the side of the orthographic projection of the second signal line group 160 on the base substrate 10 away from the pixel array area.
  • the first resistor and the second resistor R2 can also be arranged at other suitable positions, which are not limited to the position shown in FIG. 5B, as long as they are located at a position convenient to connect the trigger signal line and the first transistor T1. The embodiment does not limit this.
  • the display substrate further includes at least one first connection line L1 and at least one second connection line L2.
  • the first connection line L1 connects one end of the second resistor R2 to the first stage shift register (for example, the first transistor T1) of the second scan driving circuit, and the second connection line L2 connects the other end of the second resistor R2 to the Second, the trigger signal line ESTV2 is connected.
  • the display substrate also includes a plurality of first connecting lines and second connecting lines corresponding to the resistors of other scan driving circuits in a one-to-one correspondence, and the first resistors or other resistors pass through the corresponding first connecting lines.
  • the first connection line connects one end of the first resistor to the first stage shift register of the first scan drive circuit
  • the second connection line connects the The other end of the first resistor is connected to the first trigger signal line, which will not be repeated here.
  • the first connection line L1 and the second connection line L2 are located on the side of the second resistor R2 away from the base substrate 10, that is, the first connection line L1 and the second connection line L2 are located on the first conductive layer 320 shown in FIG. 7B Therefore, it is possible to avoid the phenomenon of signal disorder caused by crossing the fourth power line VGL2 when it is disposed on the third conductive layer 340.
  • the display substrate further includes at least one first conductive connection portion L3 and a second conductive connection portion L4, so that each resistor is connected to the first connection line and the second connection line in a bridging manner.
  • the first conductive connection portion L3 and the second conductive connection portion L4 are located on the side of the first connection line L1 and the second connection line L2 away from the base substrate 10, and are connected to the multiple power lines 140 and the first signal line group 150. It is arranged in the same layer as the second signal line 160 group, that is, the first conductive connection portion L3 and the second conductive connection portion L4 are located on the third conductive layer 340 as shown in FIG. 9B.
  • the display substrate 1 further includes a first insulating layer 350, a second insulating layer 360, and a third insulating layer 370.
  • the first insulating layer 350 is located between the second resistor R2 (ie the semiconductor layer 310) and the first connection line L1 and the second connection line L2 (first conductive layer 320) in a direction perpendicular to the base substrate 10.
  • the second insulating layer 360 is located on the first connection line L1 and the second connection line L2 (i.e., the first conductive layer 320) and the first conductive connection portion L3 and the second conductive connection portion L4 in the direction perpendicular to the base substrate 10. That is, between the third conductive layer 340).
  • the second insulating layer 360 and the third conductive layer 340 also includes the second conductive layer 330 shown in FIG. 8 and the third insulating layer located between the second conductive layer 330 and the third conductive layer 340.
  • the layer 370 please refer to the above description for specific introduction, which will not be repeated here.
  • one end of the first conductive connection portion L3 is connected to one end of the first connection line L1 through a via 133 that penetrates the second insulating layer 360 (and the third insulating layer 370), and the first The other end of the conductive connecting portion L3 is connected to one end of the second resistor R2 through a via 134 penetrating the first insulating layer 350 and the second insulating layer 360 (and the third insulating layer 370).
  • the other end of the first connection line L1 passes through the via hole 135 that penetrates the second insulating layer 360 and the third insulating layer 360, and passes through the via hole that penetrates the first insulating layer 350, the second insulating layer 360, and the third insulating layer 360.
  • 139 is connected to the first-stage shift register of the first scan driving circuit (for example, the source S1 of the first transistor T1).
  • the first connecting line L1 may also be connected to the source S1 of the first transistor T1 through a via hole (not shown in the figure) penetrating the first insulating layer 350, which is not limited in the embodiment of the present disclosure.
  • One end of the second conductive connection portion L4 is connected to one end of the second connection line L2 through a via 136 penetrating through the second insulating layer 350 (and the third insulating layer 360), and the other end of the second conductive connection portion L4 penetrates through the first
  • the insulating layer 350 and the via 137 of the second insulating layer 360 (and the third insulating layer 370) are connected to the other end of the second resistor R2.
  • the other end of the second connecting line L2 is connected to the second trigger signal line ESTV2 through a via 138 penetrating through the second insulating layer 360 and the third insulating layer 370.
  • the display substrate also includes a plurality of first conductive connecting portions and second conductive connecting portions corresponding to the resistors of other scan driving circuits in a one-to-one correspondence.
  • the conductive connecting portion and the second conductive connecting portion are connected to the corresponding first connecting wire and the second connecting wire, which will not be repeated here.
  • one end of the first conductive connection part is connected to one end of the first connection line through a via hole penetrating the second insulating layer, and the other end of the first conductive connection part is connected to one end of the first connection line through a via hole penetrating the first insulating layer and the second insulating layer.
  • One end of the first resistor is connected, and the other end of the first connection line is connected to the first stage shift register of the first scan driving circuit; one end of the second conductive connection part is connected to the second connection line through a via hole penetrating the second insulating layer One end of the second conductive connection part is connected to the other end of the first resistor through a via hole penetrating the first insulating layer and the second insulating layer, and the other end of the second connecting line is connected to the other end of the first resistor through the second insulating layer.
  • the hole is connected with the first trigger signal line.
  • the first-stage shift register of each scan driving circuit is connected to the corresponding trigger signal through each resistor, which can prevent the static electricity generated at the moment of energizing the device from affecting each signal (for example, trigger signal, clock Signal, etc.), which can make the output signal output by the scan driving circuit more accurate and improve the display quality of the display panel.
  • FIG. 11 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • the display device 2 includes a display substrate 1 provided in any embodiment of the present disclosure, for example, the display substrate 1 shown in FIG. 4, FIG. 5A or FIG. 5B.
  • the display device 2 can be any product or component with a display function, such as an OLED panel, an OLED TV, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc.
  • the display device 2 may also include other components, which are not limited in the embodiment of the present disclosure.
  • FIG. 12 is a flowchart of a manufacturing method of a display substrate provided by at least one embodiment of the present disclosure.
  • the manufacturing method can be used to manufacture the display substrate provided by any embodiment of the present disclosure.
  • it can be used to make the display substrate shown in FIG. 5A or FIG. 5B.
  • the manufacturing method of the display substrate includes step S110 to step S120.
  • Step S110 Provide a base substrate.
  • Step S120 forming a first scan driving circuit, a plurality of power lines, a first signal line group, and a second signal line group on the peripheral area of the base substrate and the first side of the base substrate.
  • the base substrate 10 may be made of glass, plastic, quartz, or other suitable materials, which is not limited in the embodiment of the present disclosure.
  • the base substrate 10 includes a pixel array area 110 and a peripheral area 120.
  • the first scan driving circuit 130, the plurality of power lines 140, the first signal line group 150, and the second signal line group 160 are arranged in the peripheral area 120 and located on the first side of the base substrate 10, for example , Located on the left side of the base substrate 10.
  • the first scan driving circuit 130 includes a plurality of cascaded shift registers 100, for example, includes a plurality of shift registers as shown in FIG. 1.
  • the first transistor T1 to the tenth transistor T10 of the shift register may be formed on the semiconductor layer 310 shown in FIG. 6A.
  • the material of the semiconductor layer 310 may include oxide semiconductors, organic semiconductors, or amorphous silicon, polysilicon, etc.
  • the oxide semiconductors include metal oxide semiconductors (such as indium gallium zinc oxide (IGZO)), and the polysilicon includes low-temperature polysilicon or high-temperature polysilicon.
  • IGZO indium gallium zinc oxide
  • Polysilicon and the like are not limited in the embodiments of the present disclosure.
  • the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities, which is not limited in the embodiments of the present disclosure.
  • the first electrodes CE11, CE12, CE13 of the first capacitor C1 to the third capacitor C3 and the gates of the first transistor T1 to the tenth transistor T10 may be formed on the first conductive layer 320 shown in FIG. 7A.
  • the gates of the first transistor T1 to the tenth transistor T10 are the parts where the semiconductor layer structure of each transistor overlaps the wiring on the first conductive layer 320.
  • the second electrodes CE21, CE22, and CE23 of the first capacitor C1 to the third capacitor C3 may be formed on the second conductive layer 330 shown in FIG. 8.
  • the second electrode CE21 and the first electrode CE11 at least partially overlap to form a first capacitor C1
  • the second electrode CE22 and the first electrode CE12 at least partially overlap to form a second capacitor C2
  • the second electrode CE23 and the first electrode CE13 at least Partially overlap to form a third capacitor C3.
  • the plurality of power lines 140, the first signal line group 150, and the second signal line group may be formed on the third conductive layer 340 shown in FIG. 9A.
  • the third conductive layer also includes conductive connections between transistors, capacitors, and signal lines.
  • the first signal line group 150, the plurality of power lines 140, and the second signal line group 160 are connected to the transistors in the remaining layers that need to be connected to them through at least one via hole, and each transistor also passes through At least one via is connected or bridged by a conductive connection part, which will not be repeated here.
  • the material of the third conductive layer 340 may include aluminum, aluminum alloy, copper, copper alloy, or any other suitable material, which is not limited in the embodiment of the present disclosure.
  • the material of the first conductive layer 320 and the second conductive layer 330 may be the same as the material of the third conductive layer 340, which will not be repeated here.
  • the plurality of power supply lines 140 are configured to provide a power supply voltage to the plurality of cascaded shift registers 100 included in the first scan driving circuit 130.
  • a first power supply voltage for example, with a high DC level
  • a second power supply voltage for example, with a low DC level
  • the first signal line group 150 includes at least one timing signal line, for example, including a first clock signal line ECK and a second clock signal line ECB, and is configured to shift to a plurality of cascades included in the first scan driving circuit 130
  • the register 100 provides timing signals, for example, the first clock signal ECK and the second clock signal ECB described above.
  • the second signal line group 160 includes a first trigger signal line ESTV1, which is configured to be a first-stage shift register in a plurality of cascaded shift registers 100 included in the first scan driving circuit 150 Connected to provide the first trigger signal to the first stage shift register.
  • the first trigger signal line ESTV1 is located between the plurality of power supply lines 140 and the pixel array area 110.
  • the second signal line group 160 is formed on the side of the first scan driving circuit 130 close to the pixel array area 110, and the first signal line group 150 is formed in the first scan driving circuit.
  • the second signal line group 160 is located on the right side of the shift register 100
  • the first signal line group 150 is located on the left side of the shift register 100.
  • the first trigger signal line ESTV1 on the right side of the shift register, that is, separately from the first signal group 150 and the multiple power lines 140, it is possible to avoid the occurrence of too many signal lines on the left side.
  • the wiring is dense, which can avoid the problem that the space left for the trigger signal line is too small due to the dense wiring, which affects the introduction of other signal lines.
  • step S120 further includes forming a first power line VGH1, a second power line VGH2, a third power line VGL1, and a third power line VGL1 on the base substrate 10, and forming a connection with the first power line VGH1 on the base substrate 10.
  • the first power supply line VGH1 and the second power supply line VGH2 provide the same first power supply voltage, for example, a DC high voltage.
  • the orthographic projection of the first power line VGH1 on the base substrate 10 overlaps with the orthographic projection of the first scan driving circuit on the base substrate 10, and the orthographic projection of the second power line VGH2 on the base substrate 10 is located on the first power line. Between the orthographic projection of VGH1 on the base substrate 10 and the orthographic projection of the second signal line group 160 on the base substrate.
  • the first power line VGH1 is formed at a position close to the fifth transistor T5, and the second power line VGH2 is formed at a position close to the eighth transistor T8 and the ninth transistor T9, so that the fifth transistor T5, the eighth transistor T8, and the The ninth transistor T9 is wired in order to be connected to one power line (for example, the first power line VGH1), thereby avoiding the space occupied by the winding in the vertical direction of the display substrate.
  • one power line for example, the first power line VGH1
  • the third power line VGL1 and the fourth power line VGL2 provide the same second power supply voltage, for example, a DC low voltage.
  • the first power supply voltage is higher than the second power supply voltage.
  • the orthographic projection of the fourth power line VGL2 on the base substrate 10 overlaps with the orthographic projection of the first scan driving circuit on the base substrate 10, and the orthographic projection of the third power line VGL1 on the base substrate 10 is located on the third power line. Between the orthographic projection of VGL1 on the base substrate 10 and the orthographic projection of the first signal line group 150 on the base substrate 10.
  • the third power line VGL1 is formed at a position close to the third transistor T3, and the fourth power line VGL2 is formed at a position close to the tenth transistor T10, so as to prevent the third transistor T3 and the tenth transistor T10 from being connected to the same power line.
  • the third power line VGL1 or are respectively connected to the third power line VGL1 and the fourth power line VGL2 located on the left side of the display substrate to be wound, thereby avoiding the space occupied by the winding in the vertical direction of the display substrate .
  • the manufacturing method of the display substrate further includes: forming a second scan driving circuit in the peripheral area and the first side of the base substrate 10.
  • the second scan driving circuit includes a plurality of cascaded shift registers (for example, includes the first stage shift register 132 shown in FIG. 5B).
  • the second signal line group 160 further includes a second trigger signal line ESTV2, which is connected to the first-stage shift register 132 of the plurality of cascaded shift registers included in the second scan driving circuit, The second trigger signal is provided to the first stage shift register 132 included in the second scan driving circuit.
  • the extension lengths of the first trigger signal line ESTV1 and the second trigger signal line ESTV2 are the same as the arrangement lengths of the first scan driver circuit and the second scan driver circuit, so that the first trigger signal line ESTV1 and the second trigger signal
  • the different extension lengths of the signal line ESTV2 lead to different wiring resistances to affect the trigger signals transmitted respectively.
  • the extension lengths of the remaining trigger signal lines may be the same as the extension lengths of the first trigger signal line ESTV1 and the second trigger signal line ESTV2.
  • the manufacturing method of the display substrate further includes: forming at least one first resistor and at least one resistor in a direction perpendicular to the base substrate 10 and between the base substrate 10 and the second signal line group 160 The second resistance.
  • the manufacturing method of the display substrate further includes: In the direction of the substrate 10 and between the base substrate 10 and the second signal line group, resistors corresponding to a plurality of scan driving circuits are formed, which is not limited in the embodiment of the present disclosure.
  • the second resistor R2 is located between the base substrate 10 and the second signal line group 160 in a direction perpendicular to the base substrate 10 (ie, located on the semiconductor layer 310), and the second resistor R2
  • the orthographic projection on the base substrate 10 is located on the side of the orthographic projection of the second signal line group 160 on the base substrate 10 away from the pixel array area.
  • the first resistor is located between the base substrate 10 and the second signal line group 160 in a direction perpendicular to the base substrate 10, and the orthographic projection of the first resistor on the base substrate 10 is located in the second signal line group 160.
  • the orthographic projection of the base substrate 10 is away from the side of the pixel array area.
  • the first resistor and the second resistor R2 can also be arranged at other suitable positions, which are not limited to the positions shown in FIG. 5B.
  • the manufacturing method of the display substrate further includes: forming at least one first connecting line on the side of the first resistor R1 and the second resistor R2 away from the base substrate 10, that is, on the first conductive layer 320 And at least one second connection line. Therefore, it is possible to avoid the phenomenon of signal disorder caused by crossing the fourth power line VGL2 when it is disposed on the third conductive layer 340.
  • the first connecting line connects one end of the first resistor with the first-stage shift register of the first scan driving circuit, and the second connecting line connects the other end of the first resistor with the first trigger signal line;
  • the connecting line L1 connects one end of the second resistor R2 with the first stage shift register (for example, the first transistor T1) of the second scan driving circuit, and the second connecting line L2 connects the other end of the second resistor R2 with the second trigger
  • the signal line ESTV2 is connected.
  • the manufacturing method of the display substrate further includes: forming a first conductive layer on the base substrate 10 and the plurality of power lines 140, the first signal line group 150, and the second signal line group 160 on the same layer.
  • the connecting portion L3 and the second conductive connecting portion L4; in the direction perpendicular to the base substrate 10 and in the first resistor R1 (ie the semiconductor layer 310) and the first connecting line L1 and the second connecting line L2 (first conductive layer 320) is formed between the first insulating layer 350; in the direction perpendicular to the base substrate 10 and on the first connection line L1 and the second connection line L2 (first conductive layer 320) and the first conductive connection portion L3 and the first
  • a second insulating layer 360 is formed between the two conductive connecting portions L4 (ie, the third conductive layer 340).
  • the manufacturing method of the display substrate further includes forming a second conductive layer 330 as shown in FIG. 8 between the second insulating layer 360 and the third conductive layer 340 and the second conductive layer 330 and the third conductive layer 330
  • a second conductive layer 330 as shown in FIG. 8 between the second insulating layer 360 and the third conductive layer 340 and the second conductive layer 330 and the third conductive layer 330
  • the third insulating layer 370 between the layers 340 reference may be made to the above description for specific introduction, which will not be repeated here.
  • one end of the first conductive connection portion L3 is connected to one end of the first connection line L1 through a via 133 that penetrates the second insulating layer 360 (and the third insulating layer 370), and the first The other end of the conductive connecting portion L3 is connected to one end of the second resistor R2 through a via 134 penetrating the first insulating layer 350 and the second insulating layer 360 (and the third insulating layer 370).
  • the other end of the first connection line L1 passes through the via hole 135 that penetrates the second insulating layer 360 and the third insulating layer 360, and passes through the via hole that penetrates the first insulating layer 350, the second insulating layer 360, and the third insulating layer 360.
  • 139 is connected to the first-stage shift register of the first scan driving circuit (for example, the source S1 of the first transistor T1).
  • the first connecting line L1 may also be connected to the source S1 of the first transistor T1 through a via hole (not shown in the figure) penetrating the first insulating layer 350, which is not limited in the embodiment of the present disclosure.
  • One end of the second conductive connection portion L4 is connected to one end of the second connection line L2 through a via 136 penetrating through the second insulating layer 350 (and the third insulating layer 360), and the other end of the second conductive connection portion L4 penetrates through the first
  • the insulating layer 350 and the via 137 of the second insulating layer 360 (and the third insulating layer 370) are connected to the other end of the second resistor R2.
  • the other end of the second connecting line L2 is connected to the second trigger signal line ESTV2 through a via 138 penetrating through the second insulating layer 360 and the third insulating layer 370.
  • the first-stage shift register of each scan driving circuit is connected to the corresponding trigger signal through each resistor, which can prevent the static electricity generated at the moment of energizing the device from affecting each signal (for example, trigger signal, clock Signal, etc.), which can make the output signal output by the scan driving circuit more accurate and improve the display quality of the display panel.
  • the flow of the method for manufacturing the display substrate may include more or fewer operations, and these operations may be performed sequentially or in parallel.
  • the flow of the production method described above includes multiple operations appearing in a specific order, it should be clearly understood that the order of the multiple operations is not limited.
  • the above-described production method can be executed once or multiple times according to predetermined conditions.

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Abstract

一种显示基板及其制作方法、显示装置。该显示基板，包括：衬底基板，包括像素阵列区和周边区域；第一扫描驱动电路、多条电源线、第一信号线组以及第二信号线组，设置在周边区域内且位于衬底基板的第一侧。第一扫描驱动电路包括多个级联的第一移位寄存器；多条电源线配置为向第一扫描驱动电路包括的多个级联的移位寄存器提供多个电源电压；第一信号线组包括至少一条时序信号线；第二信号线组包括第一触发信号线，配置为向第一级第一移位寄存器提供第一触发信号，第一触发信号线位于多条电源线和像素阵列区之间。该显示基板便于信号线的引入，有利于实现大尺寸显示面板的显示。

Description

显示基板及其制作方法、显示装置 技术领域
本公开的实施例涉及一种显示基板及其制作方法、显示装置。
背景技术
在显示技术领域，例如液晶显示面板或有机发光二极管(Organic Light Emitting Diode,OLED)显示面板的像素阵列通常包括多行栅线和与栅线交错的多列数据线。对栅线的驱动可以通过绑定的集成驱动电路实现。近几年随着非晶硅薄膜晶体管或氧化物薄膜晶体管制备工艺的不断提高，也可以将栅线驱动电路直接集成在薄膜晶体管阵列基板上形成GOA(Gate driver On Array)来对栅线进行驱动。例如，可以采用包括多个级联的移位寄存器单元的GOA为像素阵列的多行栅线提供开关态电压信号(扫描信号)，从而例如控制多行栅线依序打开，并且同时由数据线向像素阵列中对应行的像素单元提供数据信号，以在各像素单元形成显示图像的各灰阶所需要的灰度电压，进而显示一帧图像。
发明内容
本公开至少一实施例提供一种显示基板，包括：衬底基板，包括像素阵列区和周边区域；第一扫描驱动电路、多条电源线、第一信号线组以及第二信号线组，设置在所述周边区域内且位于所述衬底基板的第一侧。所述第一扫描驱动电路包括多个级联的第一移位寄存器；所述多条电源线配置为向所述第一扫描驱动电路包括的多个级联的第一移位寄存器提供多个电源电压；所述第一信号线组包括至少一条时序信号线，配置为向所述第一扫描驱动电路包括的多个级联的第一移位寄存器提供至少一个时序信号；所述第二信号线组包括第一触发信号线，配置为与所述第一扫描驱动电路包括的多个级联的第一移位寄存器中的第一级第一移位寄存器连接，以向所述第一级第一移位寄存器提供第一触发信号，所述第一触发信号线位于所述多条电源线和所述像素阵列区之间。
例如，在本公开至少一实施例提供的显示基板中，所述第二信号线组位 于所述第一扫描驱动电路靠近所述像素阵列区的一侧，所述第一信号线组位于所述第一扫描驱动电路的与所述第二信号线组所在侧相对的另一侧。
例如，在本公开至少一实施例提供的显示基板中，所述像素阵列区包括彼此并列且不重叠的第一显示区域和第二显示区域，所述第一扫描驱动电路与所述第一显示区域连接以驱动所述第一显示区域显示；所述显示基板还包括设置在所述周边区域内且位于所述衬底基板的第一侧的第二扫描驱动电路，沿所述像素阵列的扫描方向与所述第一扫描驱动电路依次排列，且与所述第二显示区域连接以驱动所述第二显示区域显示。所述第二扫描驱动电路包括多个级联的第二移位寄存器，所述第二信号线组还包括第二触发信号线，与所述第二扫描驱动电路包括的多个级联的第二移位寄存器中的第一级第二移位寄存器连接，以向所述第二扫描驱动电路包括的第一级第二移位寄存器提供第二触发信号。
例如，在本公开至少一实施例提供的显示基板中，所述第一触发信号线和所述第二触发信号线的延伸长度与所述第一扫描驱动电路和所述第二扫描驱动电路的排列长度相同。
例如，在本公开至少一实施例提供的显示基板中，所述第一触发信号线和所述第二触发信号线并排设置。
例如，在本公开至少一实施例提供的显示基板中，所述多条电源线包括第一电源线和第二电源线；所述第一电源线和所述第二电源线配置为提供相同的第一电源电压。
例如，在本公开至少一实施例提供的显示基板中，所述第一电源线在所述衬底基板的正投影与所述第一扫描驱动电路在所述衬底基板的正投影部分重合，所述第二电源线在所述衬底基板的正投影位于所述第一电源线在所述衬底基板的正投影与和所述第二信号线组在所述衬底基板的正投影之间。
例如，本公开至少一实施例提供的显示基板，还包括至少一个第一电阻；所述第一电阻位于所述第一扫描驱动电路远离所述第一级第一移位寄存器的一侧，所述第一触发信号线通过所述至少一个第一电阻与所述第一扫描驱动电路的第一级第一移位寄存器连接。
例如，本公开至少一实施例提供的显示基板，还包括至少一个第二电阻，所述第二电阻位于所述第一扫描驱动电路的最后一级第一移位寄存器和所述 第二扫描驱动电路第一级第二移位寄存器之间，所述第二触发信号线通过所述至少一个第二电阻与所述第二扫描驱动电路的第一级第二移位寄存器连接。
例如，在本公开至少一实施例提供的显示基板中，所述第一电阻和所述第二电阻的大小不同。
例如，本公开至少一实施例提供的显示基板，还包括折叠线，位于所述第一显示区域和所述第二显示区域之间；所述第二电阻位于所述折叠线的延伸方向上，所述折叠线的延伸方向与所述第一信号线组和所述第二信号线组的延伸方向垂直。
例如，在本公开至少一实施例提供的显示基板中，所述至少一个第二电阻在所述衬底基板的正投影位于所述第一扫描驱动电路的最后一级第一移位寄存器在所述衬底基板的正投影和所述第二扫描驱动电路的第一级第二移位寄存器在所述衬底基板的正投影之间。
例如，在本公开至少一实施例提供的显示基板中，所述至少一个第一电阻在垂直于所述衬底基板的方向上位于所述衬底基板和所述第二信号线组之间，且所述至少一个第一电阻在所述衬底基板的正投影位于所述第二信号线组在所述衬底基板的正投影远离所述像素阵列区的一侧。
例如，在本公开至少一实施例提供的显示基板中，所述第一电阻的材料为半导体材料。
例如，本公开至少一实施例提供的显示基板，还包括至少一条第一连接线和至少一条第二连接线；所述第一连接线将所述至少一个第一电阻的一端与所述第一扫描驱动电路的第一级第一移位寄存器连接，所述第二连接线将所述至少一个第一电阻的另一端与所述第一触发信号线连接。
例如，在本公开至少一实施例提供的显示基板中，所述第一连接线和所述第二连接线位于所述至少一个第一电阻远离所述衬底基板的一侧。
例如，本公开至少一实施例提供的显示基板，还包括：第一导电连接部、第二导电连接部、第一绝缘层和第二绝缘层；所述第一导电连接部和所述第二导电连接部位于所述第一连接线和所述第二连接线远离所述衬底基板的一侧，且与所述多条电源线、所述第一信号线组和所述第二信号线组同层设置，所述第一绝缘层在垂直于所述衬底基板的方向上位于所述至少一个第一电阻 和所述第一连接线以及所述第二连接线之间，所述第二绝缘层在垂直于所述衬底基板的方向上位于所述第一连接线以及所述第二连接线和所述第一导电连接部以及所述第二导电连接部之间。所述第一导电连接部的一端通过贯穿所述第二绝缘层的过孔与所述第一连接线的一端连接，所述第一导电连接部的另一端通过贯穿所述第一绝缘层以及所述第二绝缘层的过孔与所述至少一个第一电阻的一端连接，所述第一连接线的另一端与所述第一扫描驱动电路的第一级第一移位寄存器连接；所述第二导电连接部的一端通过贯穿所述第二绝缘层的过孔与所述第二连接线的一端连接，所述第二导电连接部的另一端通过贯穿所述第一绝缘层以及所述第二绝缘层的过孔与所述至少一个第一电阻的另一端连接，所述第二连接线的另一端通过贯穿所述第二绝缘层的过孔与所述第一触发信号线连接。
例如，在本公开至少一实施例提供的显示基板中，所述第一扫描驱动电路的第一移位寄存器的每个包括与所述第一电源线连接的第一构成晶体管以及与所述第二电源线连接的第二构成晶体管和第三构成晶体管；所述第一构成晶体管在所述衬底基板的正投影位于所述第一信号线组在所述衬底基板的正投影和所述第一电源线在所述衬底基板的正投影之间且靠近所述第一电源线在所述衬底基板的正投影，所述第二构成晶体管和第三构成晶体管在所述衬底基板的正投影位于所述第一电源线在所述衬底基板的正投影和所述第二电源线在所述衬底基板的正投影之间，且靠近所述第二电源线在所述衬底基板的正投影。
例如，在本公开至少一实施例提供的显示基板中，所述多条电源线包括第三电源线和第四电源线；所述第三电源线和所述第四电源线配置为提供相同的第二电源电压；所述第四电源线在所述衬底基板的正投影与所述第一扫描驱动电路在所述衬底基板的正投影部分重合，所述第三电源线在所述衬底基板的正投影位于所述第四电源线在所述衬底基板的正投影与和所述第一信号线组在所述衬底基板的正投影之间。
例如，在本公开至少一实施例提供的显示基板中，所述第一扫描驱动电路的第一移位寄存器每个还包括与所述第三电源线连接的第四构成晶体管以及与所述第四电源线连接的第五构成晶体管；所述第四构成晶体管在所述衬底基板的正投影位于所述第三电源线在所述衬底基板的正投影远离所述第一 信号线组在所述衬底基板的正投影的一侧，且靠近所述第三电源线在所述衬底基板的正投影，所述第五构成晶体管在所述衬底基板的正投影位于所述第四电源线在所述衬底基板的正投影和所述第二信号线组在所述衬底基板的正投影之间，且靠近所述第四电源线在所述衬底基板的正投影。
本公开至少一实施例提供一种显示基板，包括：衬底基板，包括像素阵列区和周边区域，第一扫描驱动电路、多条电源线、第一信号线组以及第二信号线组，设置在所述周边区域内且位于所述衬底基板的第一侧；所述第一扫描驱动电路包括多个级联的第一移位寄存器；所述多条电源线配置为向所述第一扫描驱动电路包括的多个级联的第一移位寄存器提供多个电源电压；所述第一信号线组包括至少一条时序信号线，配置为向所述第一扫描驱动电路包括的多个级联的第一移位寄存器提供至少一个时序信号；所述第二信号线组包括第一触发信号线，配置为与所述第一扫描驱动电路包括的多个级联的第一移位寄存器中的第一级第一移位寄存器连接，以向所述第一级第一移位寄存器提供第一触发信号，所述第一扫描驱动电路包括第一晶体管、第二晶体管和第三晶体管，所述第一晶体管、所述第二晶体管和所述第三晶体管分别与所述第一信号线组连接，所述第一晶体管、所述第二晶体管和所述第三晶体管的沟道的延伸方向与所述第一信号线组和所述第二信号线组的延伸方向平行。
例如，在本公开至少一实施例提供的显示基板中，所述第一扫描驱动电路还包括第六晶体管和第七晶体管，所述第六晶体管和所述第七晶体管分别与所述第一信号线组连接，所述第六晶体管和所述第七晶体管的沟道的延伸方向与所述第一信号线组和所述第二信号线组的延伸方向平行。
本公开至少一实施例还提供一种显示装置，包括本公开任一实施例提供的显示基板。
本公开至少一实施例还提供一种显示基板的制作方法，包括：提供衬底基板；在垂直于所述衬底基板的方向上依次形成半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层以及第三导电层；所述电源线、所述第一信号线组以及所述第二信号线组位于所述第三导电层；所述第一扫描驱动电路形成在所述半导体层、所述第一导电层以及所述第二导电层；所述第一扫描驱动电路通过贯穿所述第一绝缘层、所述第二绝缘层以及 所述第三绝缘层的过孔分别与所述电源线、所述第一信号线组以及所述第二信号线组连接。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为一种发光控制移位寄存器的电路图；
图2为图1所示的发光控制移位寄存器工作时的信号时序图；
图3为本公开至少一实施例提供的一种第一电阻和第二电阻的示意图；
图4为本公开至少一实施例提供的一种显示基板的示意图；
图5A为本公开至少一实施例提供的一种显示基板的布局示意图；
图5B示出了包括第二扫描驱动电路的第一级移位寄存器的显示基板的布局示意图；
图6A、图7A、图8和图9A分别示出了图5A中所示显示基板的各层布线的平面图；
图6B、图7B、图8和图9B分别示出了图5B中所示显示基板包括的第一级移位寄存器的各层布线的平面图；
图10为图5B所示的显示基板沿A-A`方向的剖面图；
图11为本公开至少一实施例提供的一种显示装置的示意图；以及
图12为本公开至少一实施例提供的一种显示基板的制作方法的流程图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第 二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面通过几个具体的实施例对本公开进行说明。为了保持本发明实施例的以下说明清楚且简明，可省略已知功能和已知部件的详细说明。当本发明实施例的任一部件在一个以上的附图中出现时，该部件在每个附图中由相同的参考标号表示。
图1为一种发光控制移位寄存器的电路图。图2为图1所示的发光控制移位寄存器工作时的信号时序图。下面结合图1和图2对该发光控制移位寄存器的工作过程进行简要地介绍。
如图1所示，该发光控制移位寄存器100包括10个晶体管(第一晶体管T1、第二晶体管T2、…、第十晶体管T10)以及3个电容(第一电容C1、第二电容C2、第三电容C3)。例如，当多个发光控制移位寄存器100级联时，第一级移位寄存器100中的第一晶体管T1的第一极被配置为与第一触发信号线ESTV1连接以接收第一触发信号ESTV1，而其它各级发光控制移位寄存器100中的第一晶体管T1的第一极和上一级发光控制移位寄存器100连接，以接收上一级发光控制移位寄存器100输出的第一输出信号EM。
另外，图1和图2中的CK表示第一时钟信号端，ECK表示第一时钟信号线和第一时钟信号，且第一时钟信号端CK和第一时钟信号线ECK连接以接收第一时钟信号，CB表示第二时钟信号端，ECB表示第二时钟信号线和第二时钟信号，且第二时钟信号端CB和第二时钟信号线ECB连接以接收第二时钟信号，例如，第一时钟信号ECK以及第二时钟信号ECB可以采用占空比大于50％的脉冲信号；VGH1表示第一电源线以及第一电源线提供的第一电源电压，例如，第一电源电压为直流高电平，VGL1表示第三电源线以及第三电源线提供的第二电源电压，例如，第二电源电压为直流低电平，且 第一电源电压大于第二电源电压；N1、N2、N3以及N4分别表示第一节点、第二节点、第三节点以及第四节点。
如图1所示，第一晶体管T1的栅极和第一时钟信号端CK(即，第一时钟信号线ECK)连接以接收第一时钟信号，第一晶体管T1的第一极和输入端IN连接，第一晶体管T1的第二极和第一节点N1连接。例如，当该发光控制移位寄存器为第一级移位寄存器时，输入端IN与第一触发信号线ESTV1连接以接收第一触发信号，当该发光控制移位寄存器为除第一级移位寄存器以外的其他各级移位寄存器时，输入端IN与其上级发光控制移位寄存器的输出端OUT连接。
第二晶体管T2的栅极和第一节点N1连接，第二晶体管T2的第一极和第一时钟信号线ECK连接以接收第一时钟信号，第二晶体管T2的第二极和第二节点N2连接。
第三晶体管T3的栅极和第一时钟信号线ECK连接以接收第一时钟信号，第三晶体管的第一极和第三电源线VGL1连接以接收第二电源电压，第三晶体管T3的第二极和第二节点N2连接。
第四晶体管T4的栅极和第二时钟信号端CB(即，第二时钟信号线ECB)连接以接收第二时钟信号，第四晶体管T4的第一极和第一节点N1连接，第四晶体管T4的第二极和第五晶体管T5的第一极连接。
第五晶体管T5的栅极和第二节点N2连接，第五晶体管T5的第二极和第一电源线VGH连接以接收第一电源电压。
第六晶体管T6的栅极和第二节点N2连接，第六晶体管T6的第一极和第二时钟信号线ECB连接以接收第二时钟信号，第六晶体管T6的第二极和第三节点N3连接。
第一电容C1的第一端和第二节点N2连接，第一电容C2的第二端和第三节点N3连接。
第七晶体管T7的栅极和第二时钟信号线ECB连接以接收第二时钟信号，第七晶体管T7的第一极和第三节点N3连接，第七晶体管T7的第二极和第四节点N4连接。
第八晶体管T8的栅极和第一节点N1连接，第八晶体管T8的第一极和第一电源线VGH1连接以接收第一电源电压，第八晶体管T8的第二极和第 四节点N4连接。
第九晶体管T9的栅极和第四节点N4连接，第九晶体管T9的第一极和第一电源线VGH1连接以接收第一电源电压，第九晶体管T9的第二极和输出端OUT连接。
第三电容C3的第一端和第四节点N4连接，第三电容C3的第二端和第一电源线VGH1连接以接收第一电源电压。
第十晶体管T10的栅极和第一节点N1连接，第十晶体管T10的第一极和第三电源线VGL1连接以接收第二电源电压，第十晶体管T10的第二极和输出端OUT连接。
第二电容C2的第一端和第二时钟信号线ECB连接以接收第二时钟信号，第二电容C2的第二端和第一节点N1连接。
图1中所示的发光控制移位寄存器100中的晶体管均是以P型晶体管为例进行说明的，即各个晶体管在栅极接入低电平时导通，而在接入高电平时截止。此时，第一极可以是源极，第二极可以是漏极。
本公开的实施例包括但不限于图1的配置方式，例如，发光控制移位寄存器100中的各个晶体管也可以采用N型晶体管或混合采用P型晶体管和N型晶体管，只需同时将选定类型的晶体管的端口极性按照本公开的实施例中的相应晶体管的端口极性相应连接即可。
图2为图1所示的发光控制移位寄存器工作时的信号时序图。下面结合图1和图2对该发光控制移位寄存器的工作过程进行详细地介绍。例如，以第一级发光控制移位寄存器100的工作原理进行说明，其余各级发光控制移位寄存器100的工作原理与其类似，不再赘述。如图2所示，该发光控制移位寄存器的工作过程包括六个阶段，分别为第一阶段P1、第二阶段P2、第三阶段P3、第四阶段P4、第五阶段P5以及第六阶段P6，图2示出了每个阶段中各个信号的时序波形。
在第一阶段P1，如图2所示，第一时钟信号ECK为低电平，所以第一晶体管T1和第三晶体管T3被导通，导通的第一晶体管T1将高电平的第一触发信号ESTV1传输至第一节点N1，从而使得第一节点N1的电平变为高电平，所以第二晶体管T2、第八晶体管T8以及第十晶体管T10被截止。另外，导通的第三晶体管T3将低电平的第二电源电压VGL1传输至第二节点 N2，从而使得第二节点N2的电平变为低电平，所以第五晶体管T5和第六晶体管T6被导通。由于第二时钟信号ECB为高电平，所以第七晶体管T7被截止。另外，由于第三电容C3的存储作用，第四节点N4的电平可以保持高电平，从而使得第九晶体管T9被截止。在第一阶段P1中，由于第九晶体管T9以及第十晶体管T10均被截止，该发光控制移位寄存器100的输出端OUT_1输出的第一输出信号保持之前的低电平。
在第二阶段P2，如图4所示，第二时钟信号ECB为低电平，所以第四晶体管T4、第七晶体管T7被导通。由于第一时钟信号ECK为高电平，所以第一晶体管T1和第三晶体管T3被截止。由于第一电容C1的存储作用，所以第二节点N2可以继续保持上一阶段的低电平，所以第五晶体管T5以及第六晶体管T6被导通。高电平的第一电源电压VGH1通过导通的第五晶体管T5以及第四晶体管T4传输至第一节点N1，从而使得第一节点N1的电平继续保持上一阶段的高电平，所以第二晶体管T2、第八晶体管T8以及第十晶体管T10被截止。另外，低电平的第二时钟信号ECB通过导通的第六晶体管T6以及第七晶体管T7被传输至第四节点N4，从而使得第四节点N4的电平变为低电平，所以第九晶体管T9被导通，导通的第九晶体管T9将高电平的第一电源电压VGH1输出，所以该发光控制移位寄存器100的输出端OUT_1在第二阶段P2输出的第一输出信号为高电平。
在第三阶段P3，如图4所示，第一时钟信号ECK为低电平，所以第一晶体管T1以及第三晶体管T3被导通。第二时钟信号ECB为高电平，所以第四晶体管T4以及第七晶体管T7被截止。由于第三电容C3的存储作用，所以第四节点N4的电平可以保持上一阶段的低电平，从而使得第九晶体管T9保持导通状态，导通的第九晶体管T9将高电平的第一电源电压VGH1输出，所以该发光控制移位寄存器100的输出端OUT_1在第三阶段P3输出的输出信号仍然为高电平。同时，在此阶段，第二级发光控制移位寄存器100的输出端OUT_2输出高电平(具体描述可参考上述第二阶段P2中第一级发光控制移位寄存器的工作过程)。
在第四阶段P4，如图4所示，第一时钟信号ECK为高电平，所以第一晶体管T1以及第三晶体管T3被截止。第二时钟信号ECB为低电平，所以第四晶体管T4以及第七晶体管T7被导通。由于第二电容C2的存储作用， 所以第一节点N1的电平保持上一阶段的高电平，从而使得第二晶体管T2、第八晶体管T8以及第十晶体管T10被截止。由于第一电容C1的存储作用，第二节点N2继续保持上一阶段的低电平，从而使得第五晶体管T5以及第六晶体管T6被导通。另外，低电平的第二时钟信号ECB通过导通的第六晶体管T6以及第七晶体管T7被传输至第四节点N4，从而使得第四节点N4的电平变为低电平，所以第九晶体管T9被导通，导通的第九晶体管T9将高电平的第一电源电压VGH1输出，所以该发光控制移位寄存器100的输出端OUT_1在第二阶段P2输出的第一输出信号仍然为高电平。同时，在此阶段，第二级发光控制移位寄存器100的输出端OUT_2输出高电平(具体描述可参考上述第三阶段P3中第一级发光控制移位寄存器的工作过程)。
在第五阶段P5，如图4所示，第一时钟信号ECK为低电平，所以第一晶体管T1以及第三晶体管T3被导通。第二时钟信号ECB为高电平，所以第四晶体管T4以及第七晶体管T7被截止。导通的第一晶体管T1将低电平的第一触发信号ESTV传输至第一节点N1，从而使得第一节点N1的电平变为低电平。
例如，在第五阶段P5，第一时钟信号ECK的低电平的电压为-6V，第一触发信号ESTV1的低电平的电压为-6V，第一晶体管T1的阈值电压Vth为-1.5V。由于第一晶体管T1为P型晶体管，为了使得第一晶体管T1导通，需要使得第一晶体管T1栅极和源极的电压Vgs小于第一晶体管T1的阈值电压Vth，因此，当第一节点N1被充电至-4.5V时第一晶体管T1截止，此时停止对第一节点N1充电，即，在此阶段第一节点N1的低电平的电压为-4.5V，所以第二晶体管T2、第八晶体管T8以及第十晶体管T10被导通。导通的第二晶体管T2将低电平的第一时钟信号ECK传输至第二节点N2，从而可以进一步拉低第二节点N2的电平，所以第二节点N2继续保持上一阶段的低电平，从而使得第五晶体管T5以及第六晶体管T6被导通。另外，导通的第八晶体管T8将高电平的第一电源电压VGH1传输至第四节点N4，从而使得第四节点N4的电平变为高电平，所以第九晶体管T9被截止。导通的第十晶体管T10响应于第一节点N1的低电平(例如，-4.5V)，将低电平的第二电源电压VGL(例如，-6V)输出，同理，第十晶体管T10的阈值电压Vth为-1.5V，为了使得第十晶体管T10导通，需要使得第十晶体管T10栅极和源极的电压 Vgs小于第十晶体管T10的阈值电压Vth，因此，当输出端OUT输出的电压为-3V时第十晶体管T10截止，即，在此阶段输出端OUT的低电平的电压为-3V，所以该发光控制移位寄存器100的输出端OUT_1在第五阶段P5输出的输出信号变为第一低电平(例如，-3V)。同时，在此阶段，第二级发光控制移位寄存器100的输出端OUT_2输出高电平(具体描述可参考上述第四阶段P4中第一级发光控制移位寄存器的工作过程)。
在第六阶段P6，如图4所示，第一时钟信号ECK为高电平，第二时钟信号ECB为低电平，所以第四晶体管T4以及第七晶体管T7被导通。由于第二时钟信号ECB由第五阶段P5的高电平变为低电平，例如，变化量为Δt(例如，大于6V)，根据第二电容C2的自举效应，第一节点N1的电平由第五阶段P5的低电平(例如，-4.5V)变为一个更低的低电平(例如，-4.5V-Δt)，从而，第二晶体管T2和第十晶体管T10在第一节点N1的低电平(例如，-4.5V-Δt)的控制下导通，根据上面所述的第十晶体管T10的导通特性，低电平的第二电源电压VGL(例如，-6V)可完全输出至输出端OUT。例如，在该第六阶段P6，该输出端OUT输出的电压为第二低电平(例如，-6V)。同时，在此阶段，第二级第一移位寄存器100的输出端OUT_2输出低电平(例如，-3V，具体描述可参考上述第四阶段P4中第一级第一移位寄存器的工作过程)。
例如，如图1所示，在该显示基板的左侧，由于走线密集，留给第一触发信号线ESTV1的空间较小，从而不方便多个触发信号线的引入。另外，如图1所示，由于第一电源线VGH1仅有一条，且第五晶体管T5、第八晶体管T8和第九晶体管T9为了与该第一电源电压线VGH1连接而绕线，从而增加了显示基板在竖直方向上占据的空间，不利于显示基板的布局设计。
本公开至少一实施例提供一种显示基板，包括：衬底基板，包括像素阵列区和周边区；第一扫描驱动电路、多条电源线、第一信号线组以及第二信号线组，设置在周边区域内且位于衬底基板的第一侧。第一扫描驱动电路包括多个级联的第一移位寄存器；多条电源线配置为向第一扫描驱动电路包括的多个级联的第一移位寄存器提供多个电源电压；第一信号线组包括至少一条时序信号线，配置为向第一扫描驱动电路包括的多个级联的第一移位寄存器提供至少一个时序信号；第二信号线组包括第一触发信号线，配置为与第 一扫描驱动电路包括的多个级联的第一移位寄存器中的第一级第一移位寄存器连接，以向第一级第一移位寄存器提供第一触发信号，第一触发信号线位于多条电源电压线和像素阵列区之间。
本公开至少一实施例还提供一种对应于上述显示基板的显示装置和制作方法。
本公开上述实施例提供的显示基板，将第一触发信号线设置于多条电源线和像素阵列区之间，便于信号线的引入，有利于实现大尺寸显示面板的显示。
下面结合附图对本公开的实施例及其一些示例进行详细说明。
本公开至少一实施例提供一种显示基板。例如，该显示基板可以适用于单行单驱的扫描驱动电路，即一级移位寄存器输出的输出信号仅驱动一行像素单元。由于单行单驱的扫描驱动电路相比于单行双驱的扫描驱动电路需要驱动的负载少了一半，因此具有更强的驱动能力，更适合大尺寸显示面板的显示。
需要注意的是，该显示基板同样也可以适用于单行双驱的扫描驱动电路，即一级移位寄存器输出的输出信号可以驱动两行像素单元，本公开的实施例对此不作限制。
图4为本公开至少一实施例提供的一种显示基板的示意图。例如，如图4所示，该显示基板1包括：衬底基板10、第一扫描驱动电路130、多条电源线140、第一信号线组150以及第二信号线组160。
例如，该衬底基板100可以采用例如玻璃、塑料、石英，或其他适合的材料，本公开的实施例对此不作限制。例如，衬底基板10包括像素阵列区110和周边区120，第一扫描驱动电路130、多条电源线140、第一信号线组150以及第二信号线组160设置在周边区域120内且位于衬底基板10的第一侧，例如，位于衬底基板10的左侧。
例如，像素阵列区110包括阵列排布的多个像素单元P。例如，多个像素单元P的每个包括像素电路，例如还可以进一步包括发光元件(图中未示出)。
例如，第一扫描驱动电路130包括多个级联的第一移位寄存器100，例如，包括多个如图1所示的移位寄存器100。为了描述清楚、简洁，下面将 第一移位寄存器100简称为移位寄存器100。以下实施例与此相同，不再赘述。例如，该多个移位寄存器100的输出端分别与位于像素阵列区的各行像素电路的发光控制端连接以向该各行像素电路提供输出信号(例如，发光控制信号)，从而实现驱动发光元件发光。例如，该像素电路可以是本领域内的例如包括2T1C、4T2C、8T2C等电路结构的像素电路，在此不再赘述。
例如，第一扫描驱动电路130包括至少一个晶体管，该至少一个晶体管的沟道的延伸方向与第一信号线组150和第二信号线组160的延伸方向平行，从而可以减小第一扫描驱动电路130在于沟道长度方向垂直的方向上的面积，提高工艺匹配度，形成较好的沟道效应。
例如，第一扫描驱动电路130包括第一晶体管T1、第二晶体管T2和第三晶体管T3，第一晶体管T1、第二晶体管T2和第三晶体管T3分别与第一信号线组150连接，例如，与第一信号线组150中的第一时钟信号ECK连接。例如，第一晶体管T1、第二晶体管T2和第三晶体管T3的沟道的延伸方向与第一信号线组150和第二信号线组160的延伸方向平行。例如，沟道的延伸方向为晶体管的第一极至第二极的延伸方向，例如，为第一晶体管T1的第一极至第二极的延伸方向。
例如，第一扫描驱动电路130还包括第六晶体管T6和第七晶体管T7，第六晶体管T6和第七晶体管T7分别与第一信号线组150连接，第六晶体管T6和第七晶体管T7的沟道的延伸方向与第一信号线组150和第二信号线组160的延伸方向平行。
例如，多条电源线140配置为向第一扫描驱动电路130包括的多个级联的移位寄存器100提供多个电源电压。例如，提供第一电源电压(例如，具有直流高电平)和第二电源电压(例如，具有直流低电平)等。
第一信号线组150包括至少一条时序信号线，例如，包括第一时钟信号线ECK和第二时钟信号线ECB，配置为向第一扫描驱动电路130包括的多个级联的移位寄存器100提供至少一个时序信号，例如，上面所述的第一时钟信号ECK和第二时钟信号ECB。
例如，在至少一个示例中，第二信号线组160包括第一触发信号线ESTV1，配置为与第一扫描驱动电路150包括的多个级联的移位寄存器100中的第一级移位寄存器连接，以向第一级移位寄存器提供第一触发信号。例 如，第一触发信号线ESTV1位于多条电源线140和像素阵列区110之间。例如，如图4所示，该第一触发信号线ESTV1可以位于该第一扫描驱动电路130的右侧，即，第一触发信号线ESTV1在衬底基板10的正投影位于第一扫描驱动电路130在衬底基板10的正投影和像素阵列区110在衬底基板10的正投影之间；当然，也可以位于第一扫描驱动电路130的晶体管之间，即第一触发信号线ESTV1在衬底基板10的正投影与第一扫描驱动电路130在衬底基板10的正投影至少部分重叠，只要能满足将其设置在走线不密集的区域以便于触发信号线的引入即可，本公开的实施例对此不作限制。
需要注意的是，该显示基板还可以包括多个扫描驱动电路，以及分别与该多个扫描驱动电路的第一级移位寄存器连接的多条触发信号线，本公开的实施例对此不作限制。
例如，在一些示例中，当该显示基板还进一步包括第二扫描驱动电路、第三扫描驱动电路等多个扫描驱动电路时，该显示基板还包括与该第二扫描驱动电路的第一级移位寄存器连接的第二触发信号线ESTV2，与第三扫描驱动电路的第一级移位寄存器连接的第三触发信号线等多条触发信号线。例如，该第二扫描驱动电路、第三扫描驱动电路等多个扫描驱动电路与第一扫描驱动电路的结构相同，且与第一扫描驱动电路依次排列，共同驱动该显示基板的像素阵列区。例如，该像素阵列区包括多个互不重叠(例如并排设置)的显示区域，第一扫描驱动电路、第二扫描驱动电路以及第三扫描驱动电路等多个扫描驱动电路分别驱动与其对应的显示区域。
例如，当包括多个扫描驱动电路时，该第二信号线组160还包括该多条触发信号线。例如，该多条触发信号线可以位于多条电源线140和像素阵列区110之间，例如，位于各个扫描驱动电路的右侧，或与各个扫描驱动电路至少重叠，只要能满足将其设置在走线不密集的区域以便于触发信号线的引入即可，本公开的实施例对此不作限制。
本公开上述实施例提供的显示基板，通过调整第一触发信号线的位置，避免了由于走线密集而造成的无法引入更多的信号线以及绕线连接等问题，更有利于实现显示面板的窄边框设计，从而有利于实现大尺寸显示面板的显示。
图5A为本公开至少一实施例提供的一种显示基板的布局示意图。图5B 示出了包括第二扫描驱动电路的第一级移位寄存器的显示基板的布局示意图。图10为图5B所示的显示基板沿A-A`方向的剖面图。当然，图10也可以用于解释图5A中所示的层叠结构。
需要注意的是，图5B中所示的第一级移位寄存器的层叠结构可以适用于各个扫描驱动电路的第一级移位寄存器，只需改变与相应的触发信号的连接即可，即第一扫描驱动电路的第一级移位寄存器连接第一触发信号线ESTV1，第二扫描驱动电路的第一级移位寄存器连接第二触发信号线ESTV2……，以此类推。
图6A、图7A、图8和图9A分别示出了图5A中所示显示基板的各层布线的平面图。图6A为本公开至少一实施例提供显示基板的半导体层的平面图，图7A为本公开至少一实施例提供显示基板的第一导电层的平面图，图8为本公开至少一实施例提供的显示基板的第二导电层的平面图，图9A为本公开至少一实施例提供的显示基板的第三导电层的平面图。
例如，层间绝缘层(例如，包括第一绝缘层、第二绝缘层、第三绝缘层等)可以位于图6A至图9A所示的层结构之间。例如，第一绝缘层350(如图10所示)位于图6A所示的半导体层310和图7A所示的第一导电层320之间，第二绝缘层360(如图10所示)位于图7A所示的第一导电层320和图8所示的第二导电层330之间，第三绝缘层370(如图10所示)位于图8所示的第二导电层330和图9A所示的第三导电层340之间。
例如，如图10所示，该显示基板还包括第四绝缘层380，该第四绝缘层380位于第三导电层340上，用于保护第三导电层340。
例如，第一绝缘层350、第二绝缘层360、第三绝缘层370以及第四绝缘层380的材料可以包括例如SiNx、SiOx、SiNxOy等无机绝缘材料、例如有机树脂等有机绝缘材料，或其它适合的材料，本公开的实施例对此不作限定。
需要注意的是，图5A所示的显示基板以第一扫描驱动电路中的一个移位寄存器和与其连接的信号线的布局设计为例进行说明，其余各级移位寄存器的布局实施方式可以参考图5A中所示的布局方式，在此不再赘述，当然也可以采用其他的布局方式，本公开的实施例对此不作限制。当然，其余各个扫描驱动电路的各级移位寄存器也可以参考图5A中所示的布局方式，也可以采用其他的布局实式，本公开的实施例对此不作限制。
下面结合图5A-图9A对本公开至少一实施例提供的显示基板进行详细地介绍。
例如，图5A中所示的移位寄存器100的第一晶体管T1至第十晶体管T10可以形成在图6A所示的半导体层310上。半导体层310可采用半导体材料图案化形成。例如，如图6A所示，根据需要，该半导体层310可以短棒状或具有弯曲或弯折的形状，可用于制作上述第一晶体管T1至第十晶体管T10的有源层。各有源层可包括源极区域、漏极区域以及位于源极区域和漏极区域之间的沟道区。例如，沟道区可掺杂有杂质，从而具有半导体特性；源极区域和漏极区域在沟道区的两侧，并且可掺杂有杂质，并因此具有导电性。例如，该源极区域即对应于晶体管的源极(或叫做第一极)，漏极区域即对应于晶体管的漏极(或叫做第二极)。例如，如图10所示，以第一晶体管T1为例，该第一晶体管T1的有源层包括源极区域S1、漏极区域D1(如图10中的虚线所示)和沟道区P1，该第一晶体管T1还包括栅极G1，其中，栅极G1位于第一导电层320，将在下面进行介绍，在此不再赘述。需要注意的是，第一晶体管的漏极区域D1并不在图5B沿A-A`方向的剖面图内，为了保证描述清楚，在图10中将第一晶体管T1的漏极区域D1用虚线添加上。
例如，半导体层310的材料可以包括氧化物半导体、有机半导体或非晶硅、多晶硅等，例如，氧化物半导体包括金属氧化物半导体(例如氧化铟镓锌(IGZO))，多晶硅包括低温多晶硅或者高温多晶硅等，本公开的实施例对此不作限定。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域，本公开的实施例对此不作限制。
需要注意的是，在另一些示例中，各个晶体管的第一极和第二极也可以位于其他导电层，通过位于其和半导体层中间的绝缘层中的过孔与其对应的有源层连接，本公开的实施例对此不作限制。
图7A示出了该显示基板的第一导电层320，第一导电层320设置在第一绝缘层上，从而与半导体层310绝缘。例如，第一导电层320可包括第一电容C1至第三电容C3的第一电极CE11、CE12、CE13以及第一晶体管T1至第十晶体管T10的栅极，相应地第一绝缘层也作为栅极绝缘层。如图7A所示，第一晶体管T1至第十晶体管T10的栅极为各个晶体管的半导体层结构与第一导电层320上的走线交叠的部分。
图8示出了该显示基板的第二导电层330，第二导电层330包括第一电容C1至第三电容C3的第二电极CE21、CE22、CE23。例如，第二电极CE21与第一电极CE11至少部分重叠以形成第一电容C1，第二电极CE22与第一电极CE12至少部分重叠以形成第二电容C2，第二电极CE23与第一电极CE13至少部分重叠以形成第三电容C3。
图9A示出了该显示基板的第三导电层340，第三导电层340包括第一信号线组150、多条电源线140以及第二信号线组160。需要注意的是，该第三导电层还包括连接各个晶体管、电容以及信号线之间的导电连接部。如图5A和9A所示，第一信号线组150、多条电源线140以及第二信号线组160通过至少一个过孔与其余各层中需要与其连接的晶体管连接，各个晶体管之间也通过至少一个过孔连接，或通过导电连接部桥接，在此不再赘述。
例如，上述第三导电层340的材料可以包括铝、铝合金、铜、铜合金或其他任意适合的材料，本公开的实施例对此不作限定。例如，第一导电层320和第二导电层330的材料可以与第三导电层340的材料相同，在此不再赘述。
图5A为上述图6A所示的半导体层310、图7A所示的第一导电层320、图8所示的第二导电层330和图9A所示的第三导电层340的层叠位置关系的示意图。
如图5A和9A所示，在至少一个示例中，该显示基板包括沿行方向依次设置的第一信号线组150(例如，包括第一时钟信号线ECK和第二时钟信号线ECB)和多条电源线140(例如，包括第三电源线VGL1、第一电源线VGH1和第四电源线VGL2)和第二信号线组160(例如，包括第一触发信号线ESTV1)。需要注意的是，在包括第二扫描驱动电路时，例如，第二信号线组160还包括第二出发信号线ESTV2。
在一些实施例中，如图4或图5A所示，第二信号线组160位于第一扫描驱动电路130靠近像素阵列区110的一侧，第一信号线组150位于第一扫描驱动电路130的与第二信号线组160所在侧相对的另一侧。例如，如图4或图5A所示，第二信号线组160位于移位寄存器100的右侧，第一信号线组150位于移位寄存器100的左侧。
在该实施例中，通过将第一触发信号线ESTV1和第二触发信号线ESTV2等第二信号线组160设置在移位寄存器的右侧，即与第一信号组150和多条 电源线140分开设置，可以避免由于左侧信号线太多而造成走线密集，从而可以避免由于走线密集使得留给触发信号线的空间太小而影响其他信号线的引入的问题。
在另一些示例中，如图5A所示，多条电源线140包括第一电源线VGH1、第二电源线VGH2、第三电源线VGL1和第四电源线VGL2。例如，第一电源线VGH1和第二电源线VGH2提供相同的第一电源电压，例如，直流高电压。
例如，第一电源线VGH1在衬底基板10的正投影与第一扫描驱动电路在衬底基板10的正投影部分重合，第二电源线VGH2在衬底基板10的正投影位于第一电源线VGH1在衬底基板10的正投影与和第二信号线组160在衬底基板的正投影之间。
需要注意的是，第一扫描驱动电路在衬底基板10上的正投影并非是一个连续的区域，因此，第一电源线VGH1在衬底基板10的正投影只要与第一扫描驱动电路的部分晶体管或电容在衬底基板10的正投影部分重合即可。本公开的实施例对此不作限制。例如，如图5A所示，第一电源线VGH1在衬底基板10的正投影与第一导电层320上的走线重叠，例如，和连接第三晶体管T3的栅极和第一晶体管T1的栅极之间的走线、连接第四晶体管T4的栅极的走线、连接第五晶体管T5的栅极的走线以及连接第二晶体管T2的栅极的走线部分重叠。
例如，如图5A所示，第一扫描驱动电路的各个移位寄存器包括与第一电源线VGH1连接的第一构成晶体管以及与第二电源线VGH2连接的第二构成晶体管和第三构成晶体管。例如，第五晶体管T5为第一构成晶体管的一个示例，第八晶体管T8为第二构成晶体管的一个示例，第九晶体管T9为第三构成晶体管的一个示例。下面以第一构成晶体管为第五晶体管T5、第二构成晶体管为第八晶体管T8以及第三构成晶体管为第九晶体管T9为例进行说明，本公开的实施例对此不作限制。以下实施例与此相同，不再赘述。
例如，第五晶体管T5在衬底基板10的正投影位于第一信号线组150在衬底基板10的正投影和第一电源线VGH1在衬底基板的正投影之间且靠近第一电源线VGH1在衬底基板10的正投影，第八晶体管T8和第九晶体管T9在衬底基板10的正投影位于第一电源线VGH1在衬底基板10的正投影 和第二电源线VGH2在衬底基板10的正投影之间，且靠近第二电源线VGH2在衬底基板10的正投影。即，第一电源线VGH1设置在靠近第五晶体管T5的位置，第八晶体管T8和第九晶体管T9设置在靠近第二电源线VGH2的位置，从而可以避免第五晶体管T5、第八晶体管T8和第九晶体管T9为了均与一条电源线(例如，第一电源线VGH1)连接而绕线，从而避免了显示基板在竖直方向上由于绕线占据的空间。
例如，第三电源线VGL1和第四电源线VGL2配置为提供相同的第二电源电压，例如，直流低电压。例如，第一电源电压高于第二电源电压。例如，第四电源线VGL2在衬底基板10的正投影与第一扫描驱动电路在衬底基板10的正投影部分重合，第三电源线VGL1在衬底基板10的正投影位于第三电源线VGL1在衬底基板10的正投影与和第一信号线组150在衬底基板10的正投影之间。
如上所述，第一扫描驱动电路在衬底基板10上的正投影并非是一个连续的区域，因此，第四电源线VGL2在衬底基板10的正投影只要与第一扫描驱动电路的部分晶体管或电容在衬底基板10的正投影部分重合即可。本公开的实施例对此不作限制。例如，如图5A所示，第四电源线VGL2在衬底基板10的正投影与第一导电层320上的走线重叠，例如，和连接第八晶体管T8的栅极的走线、连接第十晶体管T10的栅极的走线以及第二电容C2的第一极CE12部分重叠。
例如，第一扫描驱动电路的各个移位寄存器还包括与第三电源线VGL1连接的第四构成晶体管，以及包括与第四电源线VGL2连接的第五构成晶体管。例如，第三晶体管T3是第四构成晶体管的一个示例，第十晶体管T10是第五构成晶体管的一个示例。下面以第三晶体管T3为第四构成晶体管以及第十晶体管T10为第五构成晶体管为例进行说明，本公开的实施例对此不作限制。以下实施例与此相同，不再赘述。
例如，第三晶体管T3在衬底基板10的正投影位于第三电源线VGL1在衬底基板10的正投影远离第一信号线组150在衬底基板10的正投影的一侧，且靠近第三电源线VGL1在衬底基板10的正投影。例如，第十晶体管T10在衬底基板10的正投影位于第四电源线VGL2在衬底基板10的正投影和第二信号线组160在衬底基板10的正投影之间，且靠近第十晶体管T10在衬 底基板10的正投影。即，第三电源线VGL1设置在靠近第三晶体管T3的位置，第十晶体管T10设置在靠近第四电源线VGL2的位置，从而可以避免第三晶体管T3和第十晶体管T10为了均与一条电源线(例如，第三电源线VGL1)或分别与位于显示基板左侧的第三电源线VGL1和第四电源线VGL2连接而绕线，从而避免了显示基板在竖直方向上由于绕线占据的空间。
在本公开的至少一实施例中，通过将第一电源线VGH1、第二电源线VGH2、第三电源线VGL1和第四电源线VGL2分别设置在与其连接的晶体管旁边，可以避免各个晶体管为了均与一条电源线连接而绕线，从而避免了显示基板在竖直方向上由于绕线占据的空间，有利于实现窄边框的设计。
在另一些实施例中，像素阵列区110包括彼此并列且不重叠的第一显示区域和第二显示区域(图中未示出)，第一扫描驱动电路130与第一显示区域连接以驱动第一显示区域显示。
该显示基板还包括设置在周边区域内且位于衬底基板的一侧的第二扫描驱动电路。例如，该第二扫描驱动电路沿像素阵列的扫描方向(例如，列方向)与第一扫描驱动电路依次排列，且与第二显示区域连接以驱动第二显示区域显示。例如，第二扫描驱动电路包括多个级联的第二移位寄存器(例如，包括图5B中所示的第一级移位寄存器132)。例如，第二移位寄存器的结构和第一移位寄存器的电路结构相同，均采用图1所示的移位寄存器的电路结构，当然，第二移位寄存器的结构和第一移位寄存器的电路结构也可以不相同，本公开的实施例对此不作限制。为了表示清楚、简洁，下面将第二移位寄存器也简称为移位寄存器。以下实施例与此相同，不再赘述。
例如，该显示基板为折叠显示基板，还包括折叠线，位于第一显示区域和第二显示区域之间。例如，第二电阻R2位于折叠线的延伸方向上，折叠线的延伸方向与第一信号线组150和第二信号线组160的延伸方向垂直，从而信号线可以贯穿整个显示基板，例如，第一信号线组150和第二信号线组160的延伸方向为图4所述的竖直方向，折叠线的延伸方向为水平方向。
例如，如图5B所示，第二信号线组160还包括第二触发信号线ESTV2，与第二扫描驱动电路包括的多个级联的移位寄存器中的第一级移位寄存器132连接，以向第二扫描驱动电路包括的第一级移位寄存器132提供第二触发信号。例如，第一触发信号线ESTV1和第二触发信号线ESTN2相邻且并 排设置。第一触发信号线ESTV1和第二触发信号线ESTV2并列延伸，二者的延伸长度均与第一扫描驱动电路和第二扫描驱动电路的排列长度相同，例如，可贯穿整个显示面板，从而可以避免由于第一触发信号线ESTV1和第二触发信号线ESTV2的长度不同而导致走线电阻不同，以影响其分别传输的触发信号。相应地，例如，当包括多个扫描驱动电路时，其余各条触发信号线也可以与第一触发信号线ESTV1和第二触发信号线ESTV2相邻且并排设置，且其延伸长度均可以与第一触发信号线ESTV1和第二触发信号线ESTV2的延伸长度相同。
需要注意的是，图5B仅示意性地示出了第一扫描驱动电路的最后一级移位寄存器131和第二扫描驱动电路的第一级移位寄存器132，其他各级移位寄存器的布局方式可以参考图5A所示的布局方式，不再赘述。
图6B、图7B、图8和图9B分别示出了图5B中所示显示基板包括的第一级移位寄存器的各层布线的平面图。下面结合图5B-图9B对本公开至少一实施例提供的显示基板进行详细地介绍。
需要注意的是，图6B所示的半导体层与图6A所示的半导体层类似，区别在于还包括至少一个电阻(例如，第二电阻R2)；图7B所示的第一导电层320与图7A所示的第一导电层320类似，区别在于还包括第一连接线L1和第二连接线L2；图9B所示的第三导电层340和图9A所示的第三导电层340类似，区别在于还包括第一导电连接部341和第二导电连接部342，具体的连接关系将在下面进行详细地介绍。
例如，在第一扫描驱动电路的最后一级移位寄存器131输出输出信号时，第二触发信号线ESTV2提供第二触发信号至第二扫描驱动电路第一级移位寄存器132，以驱动其包括的多个级联的移位寄存器逐行输出所述输出信号。需要注意的是，也可以在在第一触发信号线ESTV1提供第一触发信号至第一扫描驱动电路的同时，第二触发信号线ESTV2提供第二触发信号至第二扫描驱动电路，从而可以同时驱动第一扫描驱动电路和第二扫描驱动电路工作，只要可以驱动显示基板的像素阵列区的像素单元显示正常的图像即可，本公开的实施例对此不作限制。
例如，在一些示例中，如图3所示，该显示基板还包括至少一个第一电阻R1(如图3所示)。例如，该第一电阻R1位于第一扫描驱动电路130远 离第一级第一移位寄存器的一侧。例如，第一触发信号线ESTV1通过第一电阻R1与第一扫描驱动电路130的第一级移位寄存器(例如，第一级移位寄存器的第一晶体管T1)连接。例如，如图5B所示，在显示基板包括第二扫描驱动电路230时，该显示基板还可以包括至少一个第二电阻R2。例如，第二电阻R2位于第一扫描驱动电路130的最后一级第一移位寄存器和第二扫描驱动电路230第一级第二移位寄存器之间。例如，第二触发信号线ESTV2通过第二电阻R2与第二扫描驱动电路230的第一级第二移位寄存器连接，例如，与第二扫描驱动电路230的第一级移位寄存器132的第一晶体管T1连接。
例如，第一电阻R1的阻值和第二电阻R2的阻值不同。例如，在一些示例中，第一触发信号线ESTV1从显示基板的上侧与控制器20连接，以接收第一触发信号，第二触发信号线ESTV2从该显示基板的中间穿过，与控制器连接以接收第二触发信号，从而第一触发信号线ESTV1和第二触发信号线ESTV2的走线电阻(负载)不同，因此，例如，在第一触发信号线ESTV1的负载大于第二触发信号线ESTV2的负载时，第一电阻R1小于第二电阻R2，以使得第一触发信号线ESTV1上的走线电阻的阻值加上第一电阻的阻值与第二触发信号线ESTV1上的走线电阻的阻值加上第二电阻的阻值近似相等。例如，在一些示例中，第一电阻R1的阻值为5000欧姆，第二电阻R2的阻值为5500欧姆，第一触发信号线ESTV1上的走线电阻的阻值为1000欧姆，第二触发信号线ESTV1上的走线电阻的阻值为500欧姆。
需要注意的是，当该显示基板包括多个扫描驱动电路时，该显示基板还可以包括多个电阻，以分别连接该多个扫描驱动电路的第一级移位寄存器和相应的触发信号线，例如，当该显示基板包括第三扫描驱动电路、第四扫描驱动电路等多个扫描驱动电路时，相应地，该显示基板还包括分别与其第一级移位寄存器的第一晶体管T1连接的第三电阻、第四电阻等，本公开的实施例对此不作限制。例如，其余多个电阻的设置均可参考该第一电阻和第二电阻R2的设置，不再赘述。
例如，该第一电阻和第二电阻可以相同，也可以不同，具体可视实际情况而定，本公开的实施例对此不作限制。例如，该第一电阻和第二电阻的材料可以为半导体材料，其可以和晶体管的有源层同层设置。例如，该第一电 阻和第二电阻位于图6B所示的半导体层。
由于图5B中示出了第二电阻的连接方式，下面以图5B中所示的第二电阻R2为例进行说明。图10为图5B中所示的显示基板沿A-A`方向的剖面图。下面结合图5B和图10详细地描述以第二电阻为例的各个电阻的连接方式。
如图5B和图10所示，第二电阻R2在垂直于衬底基板10的方向上位于衬底基板10和第二信号线组160之间(即位于半导体层310)，且第二电阻R2在衬底基板10的正投影位于第二信号线组160在衬底基板10的正投影远离像素阵列区的一侧。相应地，第一电阻在垂直于衬底基板10的方向上位于衬底基板10和第二信号线组160之间(即位于半导体层310)，且第一电阻在衬底基板10的正投影位于第二信号线组160在衬底基板10的正投影远离像素阵列区的一侧。需要注意的是，第一电阻和第二电阻R2还可以设置在其他合适的位置，不限于图5B所示的位置，只要位于便于连接触发信号线和第一晶体管T1的位置即可，本公开的实施例对此不作限制。
如图5B所示，该显示基板还包括至少一条第一连接线L1和至少一条第二连接线L2。第一连接线L1将第二电阻R2的一端与第二扫描驱动电路的第一级移位寄存器(例如，第一晶体管T1)连接，第二连接线L2将第二电阻R2的另一端与第二触发信号线ESTV2连接。
需要注意的是，该显示基板还包括多条与其他扫描驱动电路对应的电阻一一对应的第一连接线和第二连接线，第一电阻或其他的电阻均通过与其对应的第一连接线和第二连接线连接相应的扫描驱动电路和触发信号线，例如，第一连接线将第一电阻的一端与第一扫描驱动电路的第一级移位寄存器连接，第二连接线将所述第一电阻的另一端与第一触发信号线连接，在此不再赘述。
例如，第一连接线L1和第二连接线L2位于第二电阻R2远离衬底基板10的一侧，即第一连接线L1和第二连接线L2位于图7B所示的第一导电层320，因此，可以避免在将其设置在第三导电层340时由于与第四电源线VGL2交叉而导致信号错乱的现象。
例如，显示基板还包括至少一个第一导电连接部L3和第二导电连接部L4，使得各个电阻与第一连接线和第二连接线采用桥接的方式连接。例如，第一导电连接部L3和第二导电连接部L4位于第一连接线L1和第二连接线 L2远离衬底基板10的一侧，且与多条电源线140、第一信号线组150和第二信号线160组同层设置，即，第一导电连接部L3和第二导电连接部L4位于如图9B所示的第三导电层340。
例如，如上所述，显示基板1还包括第一绝缘层350、第二绝缘层360和第三绝缘层370。例如，第一绝缘层350在垂直于衬底基板10的方向上位于第二电阻R2(即半导体层310)和第一连接线L1以及第二连接线L2(第一导电层320)之间，第二绝缘层360在垂直于衬底基板10的方向上位于第一连接线L1以及第二连接线L2(即第一导电层320)和第一导电连接部L3以及第二导电连接部L4(即第三导电层340)之间。需要注意的是，在第二绝缘层360和第三导电层之间340还包括图8所示的第二导电层330和位于第二导电层330和第三导电层340之间的第三绝缘层370，具体介绍可参考上面的描述，在此不再赘述。
例如，如图5B和图10所示，第一导电连接部L3的一端通过贯穿第二绝缘层360(以及第三绝缘层370)的过孔133与第一连接线L1的一端连接，第一导电连接部L3的另一端通过贯穿第一绝缘层350以及第二绝缘层360(以及第三绝缘层370)的过孔134与第二电阻R2的一端连接。例如，第一连接线L1的另一端通过贯穿第二绝缘层360以及第三绝缘层360的过孔135以及通过贯穿第一绝缘层350、第二绝缘层360以及第三绝缘层360的过孔139与第一扫描驱动电路的第一级移位寄存器(例如，第一晶体管T1的源极S1)连接。例如，当该第一连接线L1的另一端在衬底基板10上的正投影与第一晶体管T1的源极S1在衬底基板10上的正投影至少部分重叠时，第一连接线L1的另一端也可以通过贯穿第一绝缘层350的过孔(图中未示出)与第一晶体管T1的源极S1连接，本公开的实施例对此不作限制。
第二导电连接部L4的一端通过贯穿第二绝缘层350(和第三绝缘层360)的过孔136与第二连接线L2的一端连接，第二导电连接部L4的另一端通过贯穿第一绝缘层350以及第二绝缘层360(以及第三绝缘层370)的过孔137与第二电阻R2的另一端连接。第二连接线L2的另一端通过贯穿第二绝缘层360和第三绝缘层370的过孔138与第二触发信号线ESTV2连接。
需要注意的是，该显示基板还包括多个与其他扫描驱动电路对应的电阻一一对应的第一导电连接部和第二导电连接部，第一电阻或其他的电阻均通 相应的过第一导电连接部和第二导电连接部和与其对应的第一连接线和第二连接线连接，在此不再赘述。
例如，第一导电连接部的一端通过贯穿第二绝缘层的过孔与第一连接线的一端连接，第一导电连接部的另一端通过贯穿第一绝缘层以及第二绝缘层的过孔与第一电阻的一端连接，第一连接线的另一端与第一扫描驱动电路的第一级移位寄存器连接；第二导电连接部的一端通过贯穿第二绝缘层的过孔与第二连接线的一端连接，第二导电连接部的另一端通过贯穿第一绝缘层以及第二绝缘层的过孔与第一电阻的另一端连接，第二连接线的另一端通过贯穿第二绝缘层的过孔与第一触发信号线连接。
在本公开的实施例中，各个扫描驱动电路的第一级移位寄存器通过各个电阻与对应的触发信号连接，可以避免在对设备通电的瞬间产生的静电对各个信号(例如，触发信号、时钟信号等)的影响，从而可以使得扫描驱动电路输出的输出信号更加精确，提高显示面板的显示质量。
本公开至少一实施例还提供一种显示装置。图11为本公开至少一实施例提供的一种显示装置的示意图。如图11所示，该显示装置2包括本公开任一实施例提供显示基板1，例如，图4、图5A或图5B中所示的显示基板1。
需要说明的是，该显示装置2可以为OLED面板、OLED电视、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置2还可以包括其他部件，本公开的实施例对此不作限定。
需要说明的是，为表示清楚、简洁，本公开的实施例并没有给出该显示装置的全部组成单元。为实现该显示装置的基板功能，本领域技术人员可以根据具体需要提供、设置其他未示出的结构，本公开的实施例对此不作限制。
关于上述实施例提供的显示装置2的技术效果可以参考本公开的实施例中提供的显示基板1的技术效果，这里不再赘述。
本公开至少一实施例还提供了一种显示基板的制作方法。图12为本公开至少一实施例提供的一种显示基板的制作方法的流程图。例如，该制作方法可以用于制作本公开任一实施例提供的显示基板。例如，可以用于制作图5A或图5B中所示的显示基板。
如图12所示，该显示基板的制作方法包括步骤S110至步骤S120。
步骤S110：提供衬底基板。
步骤S120：在衬底基板的周边区域以及衬底基板的第一侧形成第一扫描驱动电路、多条电源线、第一信号线组以及第二信号线组。
对于步骤S110，例如，该衬底基板10可以采用例如玻璃、塑料、石英，或其他适合的材料，本公开的实施例对此不作限制。例如，衬底基板10包括像素阵列区110和周边区120。
对于步骤S120，例如，第一扫描驱动电路130、多条电源线140、第一信号线组150以及第二信号线组160设置在周边区域120内且位于衬底基板10的第一侧，例如，位于衬底基板10的左侧。
例如，第一扫描驱动电路130包括多个级联的移位寄存器100，例如，包括多个如图1所示的移位寄存器。例如，该移位寄存器的第一晶体管T1至第十晶体管T10可以形成在图6A所示的半导体层310上。例如，半导体层310的材料可以包括氧化物半导体、有机半导体或非晶硅、多晶硅等，例如，氧化物半导体包括金属氧化物半导体(例如氧化铟镓锌(IGZO))，多晶硅包括低温多晶硅或者高温多晶硅等，本公开的实施例对此不作限定。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域，本公开的实施例对此不作限制。
例如，第一电容C1至第三电容C3的第一电极CE11、CE12、CE13以及第一晶体管T1至第十晶体管T10的栅极可以形成在图7A所示的第一导电层320。如图7A所示，第一晶体管T1至第十晶体管T10的栅极为各个晶体管的半导体层结构与第一导电层320上的走线交叠的部分。
例如，第一电容C1至第三电容C3的第二电极CE21、CE22、CE23可以形成在图8所示的第二导电层330。例如，第二电极CE21与第一电极CE11至少部分重叠以形成第一电容C1，第二电极CE22与第一电极CE12至少部分重叠以形成第二电容C2，第二电极CE23与第一电极CE13至少部分重叠以形成第三电容C3。
例如，该多条电源线140、第一信号线组150以及第二信号线组可以形成在图9A所示的第三导电层340。需要注意的是，该第三导电层还包括连接各个晶体管、电容以及信号线之间的导电连接部。如图5A和9A所示，第一信号线组150、多条电源线140以及第二信号线组160通过至少一个过孔与其余各层中需要与其连接的晶体管连接，各个晶体管之间也通过至少一个过 孔连接，或通过导电连接部桥接，在此不再赘述。
例如，上述第三导电层340的材料可以包括铝、铝合金、铜、铜合金或其他任意适合的材料，本公开的实施例对此不作限定。例如，第一导电层320和第二导电层330的材料可以与第三导电层340的材料相同，在此不再赘述。
例如，多条电源线140配置为向第一扫描驱动电路130包括的多个级联的移位寄存器100提供电源电压。例如，提供第一电源电压(例如，具有直流高电平)和第二电源电压(例如，具有直流低电平)等。
例如，第一信号线组150包括至少一条时序信号线，例如，包括第一时钟信号线ECK和第二时钟信号线ECB，配置为向第一扫描驱动电路130包括的多个级联的移位寄存器100提供时序信号，例如，上面所述的第一时钟信号ECK和第二时钟信号ECB。
例如，在至少一个示例中，第二信号线组160包括第一触发信号线ESTV1，配置为与第一扫描驱动电路150包括的多个级联的移位寄存器100中的第一级移位寄存器连接，以向第一级移位寄存器提供第一触发信号。例如，第一触发信号线ESTV1位于多条电源线140和像素阵列区110之间。
在一些实施例中，如图4或图5A所示，第二信号线组160形成于第一扫描驱动电路130靠近像素阵列区110的一侧，第一信号线组150形成于第一扫描驱动电路130的与第二信号线组160所在侧相对的另一侧。例如，如图4或图5A所示，第二信号线组160位于移位寄存器100的右侧，第一信号线组150位于移位寄存器100的左侧。
在该实施例中，通过将第一触发信号线ESTV1设置在移位寄存器的右侧，即与第一信号组150和多条电源线140分开设置，可以避免由于左侧信号线太多而造成走线密集，从而可以避免由于走线密集使得留给触发信号线的空间太小而影响其他信号线的引入的问题。
例如，步骤S120还包括在衬底基板10上形成第一电源线VGH1、第二电源线VGH2、第三电源线VGL1第三电源线VGL1，以及在衬底基板10上形成与第一电源线VGH1连接的第五晶体管T5、与第二电源线VGH2连接的第八晶体管T8和第九晶体管T9、与第三电源线VGHL1连接的第三晶体管T3以及与第四电源线VGL2连接的第十晶体管T10。例如，第一电源线VGH1和第二电源线VGH2提供相同的第一电源电压，例如，直流高电压。
例如，第一电源线VGH1在衬底基板10的正投影与第一扫描驱动电路在衬底基板10的正投影部分重合，第二电源线VGH2在衬底基板10的正投影位于第一电源线VGH1在衬底基板10的正投影与和第二信号线组160在衬底基板的正投影之间。
例如，第一电源线VGH1形成在靠近第五晶体管T5的位置，第二电源线VGH2形成在靠近第八晶体管T8和第九晶体管T9的位置，从而可以避免第五晶体管T5、第八晶体管T8和第九晶体管T9为了均与一条电源线(例如，第一电源线VGH1)连接而绕线，从而避免了显示基板在竖直方向上由于绕线占据的空间。
例如，第三电源线VGL1和第四电源线VGL2提供相同的第二电源电压，例如，直流低电压。例如，第一电源电压高于第二电源电压。例如，第四电源线VGL2在衬底基板10的正投影与第一扫描驱动电路在衬底基板10的正投影部分重合，第三电源线VGL1在衬底基板10的正投影位于第三电源线VGL1在衬底基板10的正投影与和第一信号线组150在衬底基板10的正投影之间。
例如，第三电源线VGL1形成在靠近第三晶体管T3的位置，第四电源线VGL2形成在靠近第十晶体管T10的位置，从而可以避免第三晶体管T3和第十晶体管T10为了均与一条电源线(例如，第三电源线VGL1)或分别与位于显示基板左侧的第三电源线VGL1和第四电源线VGL2连接而绕线，从而避免了显示基板在竖直方向上由于绕线占据的空间。
例如，在一些示例中，该显示基板的制作方法还包括：在周边区域内以及衬底基板10的第一侧形成第二扫描驱动电路。例如，第二扫描驱动电路包括多个级联的移位寄存器(例如，包括图5B中所示的第一级移位寄存器132)。例如，如图5B所示，第二信号线组160还包括第二触发信号线ESTV2，与第二扫描驱动电路包括的多个级联的移位寄存器中的第一级移位寄存器132连接，以向第二扫描驱动电路包括的第一级移位寄存器132提供第二触发信号。
例如，第一触发信号线ESTV1和第二触发信号线ESTV2的延伸长度均与第一扫描驱动电路和第二扫描驱动电路的排列长度相同，从而可以避免由于第一触发信号线ESTV1和第二触发信号线ESTV2的延伸长度不同而导致 走线电阻不同，以影响其分别传输的触发信号。相应地，例如，当包括多个扫描驱动电路时，其余各条触发信号线的延伸长度均可以与第一触发信号线ESTV1和第二触发信号线ESTV2的延伸长度相同。
例如，在一些示例中，该显示基板的制作方法还包括：在垂直于衬底基板10的方向上且在衬底基板10和第二信号线组160之间形成至少一个第一电阻和至少一个第二电阻。
需要注意的是，当该显示基板包括多个扫描驱动电路(例如，还包括第三扫描驱动电路、第四扫描驱动电路等)时，该显示基板的制作方法，还包括：在垂直于衬底基板10的方向上且在衬底基板10和第二信号线组之间形成与多个扫描驱动电路对应的电阻，本公开的实施例对此不作限制。
如图5B和图10所示，第二电阻R2在垂直于衬底基板10的方向上位于衬底基板10和第二信号线组160之间(即位于半导体层310)，且第二电阻R2在衬底基板10的正投影位于第二信号线组160在衬底基板10的正投影远离像素阵列区的一侧。相应地，第一电阻在垂直于衬底基板10的方向上位于衬底基板10和第二信号线组160之间，且第一电阻在衬底基板10的正投影位于第二信号线组160在衬底基板10的正投影远离像素阵列区的一侧。需要注意的是，第一电阻和第二电阻R2还可以设置在其他合适的位置，不限于图5B所示的位置。
例如，在一些示例中，该显示基板的制作方法还包括：在第一电阻R1和第二电阻R2远离衬底基板10的一侧，即在第一导电层320，形成至少一条第一连接线和至少一条第二连接线。因此，可以避免在将其设置在第三导电层340时由于与第四电源线VGL2交叉而导致信号错乱的现象。
例如，第一连接线将第一电阻的一端与第一扫描驱动电路的第一级移位寄存器连接，第二连接线将所述第一电阻的另一端与第一触发信号线连接；第一连接线L1将第二电阻R2的一端与第二扫描驱动电路的第一级移位寄存器(例如，第一晶体管T1)连接，第二连接线L2将第二电阻R2的另一端与第二触发信号线ESTV2连接。
例如，在一些示例中，该显示基板的制作方法还包括：在衬底基板10上形成与多条电源线140、第一信号线组150和第二信号线组160同层设置的第一导电连接部L3和第二导电连接部L4；在垂直于衬底基板10的方向上 且在第一电阻R1(即半导体层310)和第一连接线L1以及第二连接线L2(第一导电层320)之间形成第一绝缘层350；在垂直于衬底基板10的方向上且在第一连接线L1以及第二连接线L2(第一导电层320)和第一导电连接部L3以及第二导电连接部L4(即第三导电层340)之间形成第二绝缘层360。需要注意的是，该显示基板的制作方法还包括在第二绝缘层360和第三导电层之间340形成如图8所示的第二导电层330和位于第二导电层330和第三导电层340之间的第三绝缘层370，具体介绍可参考上面的描述，在此不再赘述。
例如，如图5B和图10所示，第一导电连接部L3的一端通过贯穿第二绝缘层360(以及第三绝缘层370)的过孔133与第一连接线L1的一端连接，第一导电连接部L3的另一端通过贯穿第一绝缘层350以及第二绝缘层360(以及第三绝缘层370)的过孔134与第二电阻R2的一端连接。例如，第一连接线L1的另一端通过贯穿第二绝缘层360以及第三绝缘层360的过孔135以及通过贯穿第一绝缘层350、第二绝缘层360以及第三绝缘层360的过孔139与第一扫描驱动电路的第一级移位寄存器(例如，第一晶体管T1的源极S1)连接。例如，当该第一连接线L1的另一端在衬底基板10上的正投影与第一晶体管T1的源极S1在衬底基板10上的正投影至少部分重叠时，第一连接线L1的另一端也可以通过贯穿第一绝缘层350的过孔(图中未示出)与第一晶体管T1的源极S1连接，本公开的实施例对此不作限制。
第二导电连接部L4的一端通过贯穿第二绝缘层350(和第三绝缘层360)的过孔136与第二连接线L2的一端连接，第二导电连接部L4的另一端通过贯穿第一绝缘层350以及第二绝缘层360(以及第三绝缘层370)的过孔137与第二电阻R2的另一端连接。第二连接线L2的另一端通过贯穿第二绝缘层360和第三绝缘层370的过孔138与第二触发信号线ESTV2连接。
在本公开的实施例中，各个扫描驱动电路的第一级移位寄存器通过各个电阻与对应的触发信号连接，可以避免在对设备通电的瞬间产生的静电对各个信号(例如，触发信号、时钟信号等)的影响，从而可以使得扫描驱动电路输出的输出信号更加精确，提高显示面板的显示质量。
需要说明的是，本公开的多个实施例中，该显示基板的制作方法的流程可以包括更多或更少的操作，这些操作可以顺序执行或并行执行。虽然上文 描述的制作方法的流程包括特定顺序出现的多个操作，但是应该清楚地了解，多个操作的顺序并不受限制。上文描述的制作方法可以执行一次，也可以按照预定条件执行多次。
关于上述实施例提供的显示基板的制作方法的技术效果可以参考本公开的实施例中提供的显示基板的技术效果，这里不再赘述。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (24)

  1. 一种显示基板，包括：
    衬底基板，包括像素阵列区和周边区域，
    第一扫描驱动电路、多条电源线、第一信号线组以及第二信号线组，设置在所述周边区域内且位于所述衬底基板的第一侧；
    其中，所述第一扫描驱动电路包括多个级联的第一移位寄存器；
    所述多条电源线配置为向所述第一扫描驱动电路包括的多个级联的第一移位寄存器提供多个电源电压；
    所述第一信号线组包括至少一条时序信号线，配置为向所述第一扫描驱动电路包括的多个级联的第一移位寄存器提供至少一个时序信号；
    所述第二信号线组包括第一触发信号线，配置为与所述第一扫描驱动电路包括的多个级联的第一移位寄存器中的第一级第一移位寄存器连接，以向所述第一级第一移位寄存器提供第一触发信号，
    所述第一触发信号线位于所述多条电源线和所述像素阵列区之间。
  2. 根据权利要求1所述的显示基板，其中，所述第二信号线组位于所述第一扫描驱动电路靠近所述像素阵列区的一侧，
    所述第一信号线组位于所述第一扫描驱动电路的与所述第二信号线组所在侧相对的另一侧。
  3. 根据权利要求1或2所述的显示基板，其中，所述像素阵列区包括彼此并列且不重叠的第一显示区域和第二显示区域，所述第一扫描驱动电路与所述第一显示区域连接以驱动所述第一显示区域显示，
    所述显示基板还包括设置在所述周边区域内且位于所述衬底基板的第一侧的第二扫描驱动电路，沿所述像素阵列的扫描方向与所述第一扫描驱动电路依次排列，且与所述第二显示区域连接以驱动所述第二显示区域显示；其中，
    所述第二扫描驱动电路包括多个级联的第二移位寄存器，
    所述第二信号线组还包括第二触发信号线，配置为与所述第二扫描驱动电路包括的多个级联的第二移位寄存器中的第一级第二移位寄存器连接，以向所述第二扫描驱动电路包括的第一级第二移位寄存器提供第二触发信号。
  4. 根据权利要求3所述的显示基板，其中，所述第一触发信号线和所述第二触发信号线的延伸长度与所述第一扫描驱动电路和所述第二扫描驱动电路的排列长度相同。
  5. 根据权利要求3或4所述的显示基板，其中，所述第一触发信号线和所述第二触发信号线并排设置。
  6. 根据权利要求1-5任一所述的显示基板，其中，所述多条电源线包括第一电源线和第二电源线；其中，
    所述第一电源线和所述第二电源线配置为提供相同的第一电源电压。
  7. 根据权利要求6所述的显示基板，其中，所述第一电源线在所述衬底基板的正投影与所述第一扫描驱动电路在所述衬底基板的正投影部分重合，
    所述第二电源线在所述衬底基板的正投影位于所述第一电源线在所述衬底基板的正投影与和所述第二信号线组在所述衬底基板的正投影之间。
  8. 根据权利要求3所述的显示基板，还包括至少一个第一电阻；其中，
    所述第一电阻位于所述第一扫描驱动电路远离所述第一级第一移位寄存器的一侧，所述第一触发信号线通过所述至少一个第一电阻与所述第一扫描驱动电路的第一级第一移位寄存器连接。
  9. 根据权利要求8所述的显示基板，还包括至少一个第二电阻，其中，
    所述第二电阻位于所述第一扫描驱动电路的最后一级第一移位寄存器和所述第二扫描驱动电路第一级第二移位寄存器之间，所述第二触发信号线通过所述至少一个第二电阻与所述第二扫描驱动电路的第一级第二移位寄存器连接。
  10. 根据权利要求9所述的显示基板，其中，所述第一电阻的阻值和所述第二电阻的阻值不同。
  11. 根据权利要求9所述的显示基板，还包括折叠线，位于所述第一显示区域和所述第二显示区域之间，
    其中，所述第二电阻位于所述折叠线的延伸方向上，所述折叠线的延伸方向与所述第一信号线组和所述第二信号线组的延伸方向垂直。
  12. 根据权利要求9-11任一所述的显示基板，其中，所述至少一个第二电阻在所述衬底基板的正投影位于所述第一扫描驱动电路的最后一级第一移位寄存器在所述衬底基板的正投影和所述第二扫描驱动电路的第一级第二移 位寄存器在所述衬底基板的正投影之间。
  13. 根据权利要求8-12任一所述的显示基板，其中，所述至少一个第一电阻在垂直于所述衬底基板的方向上位于所述衬底基板和所述第二信号线组之间，且所述至少一个第一电阻在所述衬底基板的正投影位于所述第二信号线组在所述衬底基板的正投影远离所述像素阵列区的一侧。
  14. 根据权利要求8-13任一所述的显示基板，其中，所述第一电阻的材料为半导体材料。
  15. 根据权利要求8-14任一所述的显示基板，还包括至少一条第一连接线和至少一条第二连接线，
    其中，所述第一连接线将所述至少一个第一电阻的一端与所述第一扫描驱动电路的第一级第一移位寄存器连接，
    所述第二连接线将所述至少一个第一电阻的另一端与所述第一触发信号线连接。
  16. 根据权利要求15所述的显示基板，其中，所述第一连接线和所述第二连接线位于所述至少一个第一电阻远离所述衬底基板的一侧。
  17. 根据权利要求15或16所述的显示基板，还包括：第一导电连接部、第二导电连接部、第一绝缘层和第二绝缘层，
    其中，所述第一导电连接部和所述第二导电连接部位于所述第一连接线和所述第二连接线远离所述衬底基板的一侧，且与所述多条电源线、所述第一信号线组和所述第二信号线组同层设置，
    所述第一绝缘层在垂直于所述衬底基板的方向上位于所述至少一个第一电阻和所述第一连接线以及所述第二连接线之间，所述第二绝缘层在垂直于所述衬底基板的方向上位于所述第一连接线以及所述第二连接线和所述第一导电连接部以及所述第二导电连接部之间；
    所述第一导电连接部的一端通过贯穿所述第二绝缘层的过孔与所述第一连接线的一端连接，所述第一导电连接部的另一端通过贯穿所述第一绝缘层以及所述第二绝缘层的过孔与所述至少一个第一电阻的一端连接，
    所述第一连接线的另一端与所述第一扫描驱动电路的第一级第一移位寄存器连接；
    所述第二导电连接部的一端通过贯穿所述第二绝缘层的过孔与所述第二 连接线的一端连接，所述第二导电连接部的另一端通过贯穿所述第一绝缘层以及所述第二绝缘层的过孔与所述至少一个第一电阻的另一端连接，
    所述第二连接线的另一端通过贯穿所述第二绝缘层的过孔与所述第一触发信号线连接。
  18. 根据权利要求3所述的显示基板，其中，所述第一扫描驱动电路的第一移位寄存器每个包括与所述第一电源线连接的第一构成晶体管以及与所述第二电源线连接的第二构成晶体管和第三构成晶体管；其中，
    所述第一构成晶体管在所述衬底基板的正投影位于所述第一信号线组在所述衬底基板的正投影和所述第一电源线在所述衬底基板的正投影之间且靠近所述第一电源线在所述衬底基板的正投影，
    所述第二构成晶体管和第三构成晶体管在所述衬底基板的正投影位于所述第一电源线在所述衬底基板的正投影和所述第二电源线在所述衬底基板的正投影之间，且靠近所述第二电源线在所述衬底基板的正投影。
  19. 根据权利要求1-18任一所述的显示基板，其中，所述多条电源线包括第三电源线和第四电源线；其中，
    所述第三电源线和所述第四电源线配置为提供相同的第二电源电压；
    所述第四电源线在所述衬底基板的正投影与所述第一扫描驱动电路在所述衬底基板的正投影部分重合，
    所述第三电源线在所述衬底基板的正投影位于所述第四电源线在所述衬底基板的正投影与和所述第一信号线组在所述衬底基板的正投影之间。
  20. 根据权利要求19所述的显示基板，其中，所述第一扫描驱动电路的第一移位寄存器每个还包括与所述第三电源线连接的第四构成晶体管以及与所述第四电源线连接的第五构成晶体管；其中，
    所述第四构成晶体管在所述衬底基板的正投影位于所述第三电源线在所述衬底基板的正投影远离所述第一信号线组在所述衬底基板的正投影的一侧，且靠近所述第三电源线在所述衬底基板的正投影，
    所述第五构成晶体管在所述衬底基板的正投影位于所述第四电源线在所述衬底基板的正投影和所述第二信号线组在所述衬底基板的正投影之间，且靠近所述第四电源线在所述衬底基板的正投影。
  21. 一种显示基板，包括：
    衬底基板，包括像素阵列区和周边区域，
    第一扫描驱动电路、多条电源线、第一信号线组以及第二信号线组，设置在所述周边区域内且位于所述衬底基板的第一侧；
    其中，所述第一扫描驱动电路包括多个级联的第一移位寄存器；
    所述多条电源线配置为向所述第一扫描驱动电路包括的多个级联的第一移位寄存器提供多个电源电压；
    所述第一信号线组包括至少一条时序信号线，配置为向所述第一扫描驱动电路包括的多个级联的第一移位寄存器提供至少一个时序信号；
    所述第二信号线组包括第一触发信号线，配置为与所述第一扫描驱动电路包括的多个级联的第一移位寄存器中的第一级第一移位寄存器连接，以向所述第一级第一移位寄存器提供第一触发信号，
    其中，所述第一扫描驱动电路包括第一晶体管、第二晶体管和第三晶体管，所述第一晶体管、所述第二晶体管和所述第三晶体管分别与所述第一信号线组连接，
    所述第一晶体管、所述第二晶体管和所述第三晶体管的沟道的延伸方向与所述第一信号线组和所述第二信号线组的延伸方向平行。
  22. 根据权利要求21所述的显示基板，其中，所述第一扫描驱动电路还包括第六晶体管和第七晶体管，所述第六晶体管和所述第七晶体管分别与所述第一信号线组连接，
    所述第六晶体管和所述第七晶体管的沟道的延伸方向与所述第一信号线组和所述第二信号线组的延伸方向平行。
  23. 一种显示装置，包括如权利要求1-22任一所述的显示基板。
  24. 一种如权利要求1-22任一所述的显示基板的制作方法，包括：
    提供所述衬底基板；
    在垂直于所述衬底基板的方向上依次形成半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层以及第三导电层；
    其中，所述电源线、所述第一信号线组以及所述第二信号线组位于所述第三导电层；
    所述第一扫描驱动电路形成在所述半导体层、所述第一导电层以及所述第二导电层；
    所述第一扫描驱动电路通过贯穿所述第一绝缘层、所述第二绝缘层以及所述第三绝缘层的过孔分别与所述电源线、所述第一信号线组以及所述第二信号线组连接。
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