WO2020024664A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2020024664A1
WO2020024664A1 PCT/CN2019/087656 CN2019087656W WO2020024664A1 WO 2020024664 A1 WO2020024664 A1 WO 2020024664A1 CN 2019087656 W CN2019087656 W CN 2019087656W WO 2020024664 A1 WO2020024664 A1 WO 2020024664A1
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Prior art keywords
display panel
compensation
conductive layer
load
unit
Prior art date
Application number
PCT/CN2019/087656
Other languages
English (en)
French (fr)
Inventor
童振霄
黄炜赟
董向丹
刘庭良
肖云升
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/621,763 priority Critical patent/US10997905B2/en
Priority to EP19845449.8A priority patent/EP3832633A4/en
Priority to JP2020557985A priority patent/JP7438972B2/ja
Publication of WO2020024664A1 publication Critical patent/WO2020024664A1/zh

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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • the OLED display panel may include a display area AA, a pixel unit PX located in the display area AA, a high-level voltage supply line 110 electrically connected to a pixel circuit in each pixel unit PX, and The high-level voltage power supply trace 110 is electrically connected to a high-level voltage power supply terminal 120.
  • the high-level voltage power supply terminal 120 is used to be electrically connected to an external power management chip to input a power signal ELVDD into the display area AA.
  • the high-level voltage power supply trace 110 has a resistance, so that the voltage of the power signal ELVDD decreases in order from the high-level voltage power supply terminal 120 to the direction of the high-level voltage power supply trace 110, that is, the IR drop phenomenon. In this way, the brightness of the display area AA is gradually reduced from the direction from the high-level voltage power supply terminal 120 to the high-level voltage power supply line 110, resulting in poor brightness uniformity, which further affects the display effect.
  • An embodiment of the present disclosure provides a display panel and a display device.
  • the specific solutions are as follows:
  • an embodiment of the present disclosure provides a display panel including:
  • a gate driving circuit including a plurality of output terminals, at least one of the plurality of output terminals being electrically connected to at least one of the plurality of gate lines;
  • At least one load compensation unit between the at least one output terminal and the at least one gate line, and the at least one gate line and the at least one output terminal are electrically connected;
  • the display substrate includes a display area and a non-display area surrounding the display area, the plurality of gate lines are located in the display area, the gate driving circuit and the at least one load compensation unit are located in a non-display area;
  • the at least one load compensation unit is used to adjust the charging time of the pixels by controlling the grid lines, so that the brightness of each area of the display screen is uniform.
  • each of the output terminals of the gate driving circuit is respectively connected to one of the gate lines, and different output terminals are connected to different gate lines.
  • it further includes a first voltage power supply trace and a first voltage power supply terminal;
  • the first voltage supply line is located in a display area, and the first voltage supply terminal is located in a non-display area and is electrically connected to the first voltage supply line;
  • the first voltage power supply trace is intersected with the plurality of gate lines, and all the load compensation units are sequentially divided in a direction away from the first voltage power supply terminal along the first voltage power supply trace.
  • All the load compensation units are sequentially divided in a direction away from the first voltage power supply terminal along the first voltage power supply trace.
  • each of the unit groups includes at least two adjacent load compensation units.
  • the compensation load value of each of the load compensation units in the same unit group is the same, and the compensation load value in different unit groups is different.
  • the number of load compensation units in each of the unit groups is the same.
  • each of the unit groups includes a load compensation unit.
  • the load compensation unit includes at least one of a compensation resistor and a compensation capacitor; wherein an output terminal of the gate driving circuit is electrically connected to a corresponding gate line through the compensation resistor.
  • One end of the compensation capacitor is electrically connected to an output end of the gate driving circuit, and the other end is electrically connected to a ground end;
  • the load compensation unit includes a compensation resistor
  • a resistance value of the compensation resistor is used as a compensation load value of the load compensation unit
  • the load compensation unit includes a compensation capacitor
  • a capacitance value of the compensation capacitor is used as a compensation load value of the load compensation unit
  • the load compensation unit includes a compensation resistor and a compensation capacitor
  • a product of a resistance value of the compensation resistor and a capacitance value of the compensation capacitor is used as a compensation load value of the load compensation unit.
  • the compensation resistor includes: a polygonal-shaped resistance trace; wherein one end of the resistance trace is electrically connected to an output end of the gate driving circuit, and the other end is electrically connected to the gate drive circuit.
  • the gate line is electrically connected.
  • the resistance trace includes: a plurality of first resistance traces extending in a first direction and a plurality of second resistance traces extending in a second direction, and the first A resistance trace is electrically connected to the second resistance trace in sequence; the first direction intersects the second direction.
  • a cross-sectional area of at least one of the first resistance trace and the second resistance trace is smaller than the cross-sectional area of the gate line.
  • the display panel further includes: a first conductive layer corresponding to each of the resistance traces and provided with different layers of insulation; wherein the first conductive layer is on the display panel
  • the orthographic projection and the corresponding resistance trace have overlapping areas on the orthographic projection of the display panel;
  • the compensation capacitor includes a first capacitor formed by the first conductive layer and the resistance trace in the overlapping region.
  • the orthographic projection of the first conductive layer on the display panel covers the orthographic projection of the corresponding resistive trace on the display panel.
  • the display panel further includes: a second conductive layer connected between the first resistance trace and the second resistance trace; wherein the first conductive layer The orthographic projection of the layer on the display panel covers the orthographic projection of the second conductive layer on the display panel;
  • the compensation capacitor further includes a second capacitor formed by the first conductive layer and the second conductive layer.
  • the display panel further includes: a third conductive layer corresponding to the output terminal provided with the load compensation unit, and a shift register unit provided with the load compensation unit.
  • a fourth conductive layer that is electrically connected to the output end; wherein the third conductive layer is insulated from the fourth conductive layer in a different layer;
  • the orthographic projection of the third conductive layer on the display panel and the orthographic projection of the corresponding fourth conductive layer on the display panel have overlapping areas;
  • the compensation capacitor includes a third capacitor formed by the fourth conductive layer and the third conductive layer in the overlapping region.
  • the orthographic projection of the third conductive layer on the display panel covers the orthographic projection of the fourth conductive layer on the display panel.
  • an embodiment of the present disclosure further provides a display device including a display panel provided by an embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a display panel in the prior art
  • FIG. 2 is a schematic structural diagram of a pixel circuit in the related art
  • FIG. 3 is a driving timing diagram of the pixel circuit shown in FIG. 2;
  • 4a is one of the structural schematic diagrams of a display panel provided by an embodiment of the present disclosure.
  • 4b is a second schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a gate-on signal provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a partial structure of a display panel according to an embodiment of the present disclosure.
  • FIG. 7 is a second schematic diagram of a partial structure of a display panel according to an embodiment of the present disclosure.
  • FIG. 8 is a third schematic diagram of a partial structure of a display panel according to an embodiment of the present disclosure.
  • 9a is a fourth partial structural schematic view of a display panel according to an embodiment of the present disclosure.
  • FIG. 9b is a schematic cross-sectional structure view along the BB 'direction in FIG. 9a;
  • FIG. 10 is a fifth schematic diagram of a partial structure of a display panel according to an embodiment of the present disclosure.
  • FIG. 11 is a sixth schematic diagram of a partial structure of a display panel according to an embodiment of the present disclosure.
  • the pixel circuit may include: a driving transistor DTFT, a switching transistor M1, and a storage capacitor Cst; wherein the gate of the switching transistor M1 is connected to the gate line G_m, the source of the switching transistor M1 is connected to the data line data, and the switch
  • the drain of the transistor M1 is connected to the gate of the driving transistor DTFT, the source of the driving transistor DTFT is connected to the first voltage power supply trace 110, the drain of the driving transistor DTFT is connected to the anode of the OLED, and the cathode of the OLED is connected to the low voltage power supply.
  • Line ELVSS is connected.
  • the driving timing diagram of the pixel circuit shown in FIG. 2 is shown in FIG. 3.
  • the switching transistor M1 is controlled to turn on.
  • the data signal on the data line Data is provided to the gate of the driving transistor DTFT, and the gate voltage of the driving transistor DTFT is the voltage V data of the data signal, and is stored by the storage capacitor Cst.
  • the switching transistor M1 is controlled to be turned off.
  • the gate voltage of the driving transistor DTFT is V data
  • an embodiment of the present disclosure provides a display panel that sequentially reduces the gate-on signal in a direction in which the first row of pixel units is directed to the last row of pixel units, thereby enabling V data to be charged into the gate of the driving transistor DTFT. It is lowered so that the corresponding ⁇ V data in the pixel unit can be consistent with the corresponding ⁇ V dd , thereby maintaining the stability of I and improving the uniformity of brightness.
  • a gate driving circuit includes a plurality of output terminals O_m, and at least one of the plurality of output terminals O_m is electrically connected to at least one gate line G_m of the plurality of gate lines G_m;
  • At least one load compensation unit 130 located between at least one output terminal O_m and at least one gate line G_m, and electrically connected to at least one gate line G_m and at least one output terminal O_m;
  • the display substrate includes a display area AA and a non-display area BB surrounding the display area, a plurality of gate lines G_m are located in the display area AA, a gate driving circuit and at least one load compensation unit 130 are located in the non-display area BB;
  • the at least one load compensation unit 130 is configured to adjust the charging time of the pixels by controlling the gate line G_m to make the brightness of each area of the display screen uniform.
  • At least one load compensation unit is provided in the non-display area, and the charging time of the pixels is adjusted by controlling the grid lines using the load compensation unit, so that the brightness of each area of the display screen is uniform.
  • each output terminal O_m of the gate driving circuit is respectively connected to one gate line G_m of a plurality of gate lines, and different output terminals O_m Connect different gate lines G_m.
  • the display panel provided by the embodiment of the present invention further includes a first voltage power supply wiring 110 and a first voltage power supply terminal 120;
  • the first voltage supply line 110 is located in the display area AA, and the first voltage supply terminal 120 is located in the non-display area BB, and is electrically connected to the first voltage supply line 110;
  • the first voltage power supply trace 110 is intersected with a plurality of gate lines G_m.
  • all load compensation units are sequentially divided into at least two unit groups along the first voltage power supply wiring away from the first voltage power supply terminal, and are away from the first voltage power supply terminal.
  • the first voltage generally refers to a high-level power supply voltage for outputting a power supply signal ELVDD.
  • the gate driving circuit generally includes a cascaded shift register unit SR_m, and each shift register unit SR_m corresponds to one output terminal O_m of the gate driving circuit for connecting with one gate line G_m Corresponding electrical connection.
  • the gate lines have RC load loading, and because the process preparation conditions are generally the same, the RC load loading of each gate line in the display panel is basically the same.
  • the load compensation unit responds to the output.
  • the load compensation of the signal output from the terminal O_m is actually to compensate the RC load loading of the gate line, so as to improve the RC load loading of the gate line, thereby reducing the sustaining time of the gate turn-on signal.
  • the output end of the gate driving circuit can be electrically connected to a load compensation unit, or the output end of the gate driving circuit can be electrically connected to two, three, etc. load compensation units, which needs to be based on the actual application.
  • the environment is determined by design and is not limited herein.
  • the shape of a general display panel can be rectangular, which has four sides, namely, an upper side, a lower side, a left side, and a right side.
  • the gate driving circuits are disposed on the left and / or the right.
  • the first voltage supply terminal 120 is disposed on the upper side and / or the lower side, so that the side where the gate driving circuit is located is adjacent to the side where the first voltage supply terminal 120 is located.
  • the display panel further includes a plurality of pixel units PX disposed in the display area AA, and one grid line corresponds to one row of pixel units.
  • the gate driving circuit and the load compensation unit may be disposed in a non-display area.
  • each shift register unit SR_m is disposed at the same end of the gate line G_m, so that unilateral driving can be achieved.
  • each shift register unit may include a left shift register unit and a right shift register unit, and the left shift register unit and the right shift register unit are respectively connected to two ends of a gate line, so that bilateral driving can be achieved. .
  • OLEDs Organic Light Emitting Diodes
  • QLEDs Quantum Dot Light Emitting Diodes
  • the display panel may include an OLED display panel or a QLED display panel, which is not limited herein.
  • each output terminal O_m of the gate driving circuit may be respectively corresponding to one load compensation unit 130.
  • each output terminal O_m of the gate driving circuit may also correspond to multiple load compensation units 130, and the multiple load compensation units 130 may be connected in series or parallel.
  • each output terminal O_m may be made to correspond to two load compensation units 130.
  • each output terminal O_m may be corresponding to three, four, etc. load compensation units. This can be designed and determined according to the actual application environment, which is not limited here.
  • the area where the display panel is relatively close to the first voltage power supply terminal 120 may be less affected by IR and Drop, so it can be ignored.
  • only a part of the output terminals of the gate driving circuit may be provided with a load compensation unit in a one-to-one correspondence.
  • the partial output terminal may include an output terminal remote from the first voltage power supply terminal and at least one output terminal adjacent to the output terminal remote from the first voltage power supply terminal, that is, it may include a first-stage shift register unit to a K-th stage shift Register output corresponding to the unit; where K ⁇ M and integer. This can reduce the setting of the load compensation unit and reduce power consumption.
  • the compensation load value of each load compensation unit 130 in the same unit group 10_n is the same, and the compensation load value in different unit groups is different.
  • the compensation load value in the cell group 10_2 shown in FIG. 4a is greater than the compensation load value in the cell group 10_1, and the gate-on signals output by the first-stage shift register unit and the fourth-stage shift register unit are taken as examples for illustration. .
  • the signal g_1 and the fourth-stage shift register unit g_4 output by the first-stage shift register unit are shown in FIG. 5, where the abscissa represents time and the ordinate represents voltage. Affected by the output load, the waveforms of the signals g_1 and g_4 will change.
  • the switching transistor in the pixel circuit When the voltages of the signals g_1 and g_4 drop to Vref, the switching transistor in the pixel circuit is turned on, and the voltage of the data signal V data starts to be written.
  • the voltages of the signals g_1 and g_4 rise to Vref the The switching transistor is loaded, and the writing of the voltage V data of the data signal ends, that is, the equivalent writing time (ie, equivalent charging time) of the data voltage is a time period in which the voltage is less than Vref. Since the compensation load value in the unit group 10_1 is smaller than the compensation load value in the unit group 10_2, the charging time t2 of the signal g_4 is greater than the charging time t1 of the signal g_1.
  • the compensation load values in the cell group 10_1 and the cell group 10_2 are set according to the ⁇ V dd corresponding to the cell group 10_1 and the cell group 10_2 respectively, so that the corresponding ⁇ V data in the pixel unit corresponding to the cell group 10_1 and the cell group 10_2 can be related to
  • the corresponding ⁇ V dd is kept consistent, so that the ⁇ V data corresponding to the same pixel unit and the corresponding ⁇ V dd cancel each other out, so as to maintain the stability of I, and then improve the brightness uniformity of the display panel and the display effect.
  • each unit group may include at least two adjacent load compensations. unit.
  • the cell group may include two adjacent load compensation units, that is, the compensation load values of two rows of gate lines are the same.
  • the cell group may also include three adjacent load compensation units 130, that is, the compensation load values of the three rows of gate lines are the same.
  • the unit group may include four, five, six, etc. load compensation units adjacent to each other. The rest can be deduced by analogy, and will not be repeated here.
  • each unit group may also include a load compensation unit. In practical applications, the number of load compensation units included in the unit group can be designed and determined according to the actual application environment, which is not limited herein.
  • the number of load compensation units 130 in each unit group 130_n is the same. This allows uniform brightness changes and simplifies the process.
  • the load compensation unit 130 may include: a compensation resistor R0 and a compensation capacitor C0; wherein the output terminal O_m of the gate driving circuit is electrically connected to the corresponding gate line G_m through the compensation resistor R0; compensation One end of the capacitor C0 is electrically connected to the output terminal O_m of the gate driving circuit, and the other end is electrically connected to the ground terminal GND.
  • the product of the resistance value r 0 of the compensation resistor R0 and the capacitance value c 0 of the compensation capacitor C0 that is, r 0 * c 0 is used as the compensation load value of the load compensation unit 130.
  • the specific values of r 0 , c 0 and r 0 * c 0 need to be determined by design according to ⁇ V dd , which is not limited herein.
  • the compensation resistor R0 may include: a polygonal-shaped resistance trace s0; wherein one end of the resistance trace s0 is electrically connected to the output terminal O_m of the gate driving circuit. The other end is electrically connected to the gate line G_m.
  • R ⁇ L / S.
  • ⁇ is the resistivity
  • L is the length of the resistance trace
  • S is the cross-sectional area of the resistance trace
  • R is the resistance value of the resistance trace. It can be known that by increasing L, R can be increased, and the gate can be improved. The load at the output of the drive circuit.
  • the resistance trace s0 may include: a plurality of first resistance traces s01 extending along the first direction F1 and a plurality of traces along the second direction F2 extends the second resistance trace s02, and the first resistance trace s01 and the second resistance trace s02 are electrically connected in sequence; and the first direction F1 and the second direction F2 cross.
  • the first direction F1 may be perpendicular to the second direction F2; wherein the first direction F1 may be a row direction of the pixel unit, and the second direction F2 may be a column direction of the pixel unit; or the first direction F1 may also be made It is the column direction of the pixel unit, and the second direction F2 is the row direction of the pixel unit, which is not limited herein.
  • the lengths of the first resistance traces s01 can be made the same.
  • the lengths of the at least two first resistance traces can also be different, which is not limited herein.
  • the lengths of the second resistance traces s02 can be made the same.
  • the lengths of the at least two second resistance traces can also be different, which is not limited herein.
  • each of the first resistance traces s01 and each of the second resistance traces s02 may be the same.
  • the cross-sectional area of at least one first resistance trace s01 can be made smaller than the cross-sectional area of the gate line G_m to increase the resistance of the compensation resistor. value. Because the resistance value of the compensation resistor connected to a gate line is determined, by reducing the cross-sectional area of the first resistance trace to reduce the resistance value, the length of the first resistance trace can be correspondingly reduced, thereby reducing occupation. space.
  • the cross-sectional area of one first resistance trace s01 may be smaller than the cross-sectional area of the gate line G_m; or, the cross-sectional area of two first resistance traces s01 may be smaller than the cross-sectional area of the gate line G_m Or, as shown in FIG. 8, the cross-sectional area of each first resistance trace s01 may be smaller than the cross-sectional area of the gate line G_m. The rest can be deduced by analogy, and will not be repeated here.
  • the cross-sectional area of at least one second resistance trace s02 can be made smaller than the cross-sectional area of the gate line G_m to increase the resistance of the compensation resistor. value. Because the resistance value of the compensation resistor connected to a gate line is determined, by reducing the cross-sectional area of the second resistance trace to reduce the resistance value, the length of the second resistance trace can be correspondingly reduced, thereby reducing occupation. space.
  • the cross-sectional area of one second resistance trace s02 may be smaller than the cross-sectional area of the gate line G_m; or, the cross-sectional area of two second resistance traces s02 may be smaller than the cross-sectional area of the gate line G_m. Or, as shown in FIG. 8, the cross-sectional area of each second resistance trace s02 may be smaller than the cross-sectional area of the gate line. The rest can be deduced by analogy, and will not be repeated here.
  • the display panel may further include: a first conductive layer 140 corresponding to each resistance trace s0 and provided with different layers of insulation; wherein, the first The orthographic projection of the conductive layer 140 on the display panel and the orthographic projection of the corresponding resistance trace s0 on the display panel have overlapping areas. Since the first conductive layer 140 and the resistance trace s0 located in the overlapped region have opposite areas, so that a capacitor can be formed, the compensation capacitor may include: the first conductive layer 140 and the resistance trace s0 formed in the overlapped region First capacitor. Further, the first conductive layer 140 can be electrically connected to the ground terminal. Alternatively, the first conductive layer 140 may be floated, which is not limited herein. In addition, an insulating layer is provided between the first conductive layer and each resistance trace.
  • the front projection of the first conductive layer 140 on the display panel covers the corresponding projection of the corresponding resistance trace s0 on the display panel.
  • the display panel may further include: a second conductive layer 150 connected between the first resistance trace s01 and the second resistance trace s02.
  • the orthographic projection of the first conductive layer 140 on the display panel covers the orthographic projection of the second conductive layer 150 on the display panel. Since the first conductive layer 140 and the second conductive layer 150 have opposite areas, so that a capacitor can be formed, the compensation capacitor may further include a second capacitor formed by the first conductive layer 140 and the second conductive layer 150.
  • the resistance trace, the second conductive layer, and the gate line can be made of the same layer and the same material.
  • the pattern of the resistance trace, the second conductive layer, and the gate line can be formed through a single patterning process, which can simplify the preparation process, save production costs, and improve production efficiency.
  • the display panel may further include: a plurality of data lines; and each of the first conductive layers may be insulated from each data line with the same layer and the same material.
  • the pattern of the first conductive layer and each data line can be formed through a single patterning process, which can simplify the preparation process, save production costs, and improve production efficiency.
  • the load compensation unit 130 may also include: a compensation resistor R0; wherein the output terminal O_m of the gate driving circuit is electrically connected to the corresponding gate line G_m through the compensation resistor 130.
  • the resistance value r 0 of the compensation resistor is used as a compensation load value of the load compensation unit.
  • the load compensation unit 130 may also include: a compensation capacitor C0; wherein one end of the compensation capacitor C0 is electrically connected to the output terminal O_m of the gate driving circuit, The other end is electrically connected to the ground terminal GND.
  • the capacitance value c 0 of the compensation capacitor C0 can be used as a compensation load value of the load compensation unit 130.
  • the display panel may further include a third conductive layer 160 corresponding to the output terminal O_m provided with the load compensation unit 130 and a load compensation unit provided.
  • the fourth conductive layer 170 which is electrically connected to the output terminal O_m of the gate driving circuit of 130; wherein the third conductive layer 160 and the fourth conductive layer 170 are provided with different layers of insulation, and the third conductive layer 160 corresponds to the orthographic projection of the display panel.
  • the fourth conductive layer 170 has an overlapping area in the orthographic projection of the display panel; the compensation capacitor may include a third capacitor formed by the third conductive layer 160 and the fourth conductive layer 170 located in the overlapping area.
  • the third conductive layer may be electrically connected to the ground terminal; or the third conductive layer may be floated, which is not limited herein.
  • the orthographic projection of the third conductive layer 160 on the display panel may cover the orthographic projection of the fourth conductive layer 170 on the display panel.
  • an embodiment of the present disclosure further provides a display device including the above display panel provided by the embodiment of the present disclosure.
  • the principle of the display device for solving the problem is similar to that of the foregoing display panel. Therefore, for implementation of the display device, reference may be made to the implementation of the foregoing display panel, and duplicates are not repeated here.
  • the display device provided in the embodiments of the present disclosure may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • Other essential components of the display device are understood by those of ordinary skill in the art, and are not repeated here, and should not be used as a limitation on the present disclosure.
  • At least one load compensation unit is provided in a non-display area, and the load compensation unit is used to adjust the charging time of the pixels by controlling the grid lines, so that the brightness of each area of the display screen is uniform.

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Abstract

本公开公开了一种显示面板及显示装置，通过在非显示区设置至少一个负载补偿单元，利用负载补偿单元通过控制栅线来调节像素的充电时间，从而使显示屏幕各个区域亮度均一。

Description

显示面板及显示装置
本申请要求在2018年07月30日提交中国专利局、申请号为201810852874.8、发明名称为“一种显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，特别涉及一种显示面板及显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)具有自发光、广色域、高对比度、轻薄等优点，已广泛应用于显示装置中。如图1所示，OLED显示面板可以包括：显示区域AA，位于显示区域AA中的像素单元PX、与每个像素单元PX中的像素电路电连接的高电平电压供电走线110，以及与高电平电压供电走线110电连接的高电平电压供电端子120。该高电平电压供电端子120用于与外部电源管理芯片电连接，以将电源信号ELVDD输入到显示区域AA中。由于高电平电压供电走线110具有电阻，这样使得由高电平电压供电端子120指向高电平电压供电走线110的方向上，电源信号ELVDD的电压依次减小，即IR Drop现象。这样使得显示区域AA的亮度从由高电平电压供电端子120指向高电平电压供电走线110的方向上逐渐减小，导致亮度均一性变差，进而影响显示效果。
发明内容
本公开实施例提供一种显示面板及显示装置，具体方案如下：
因此，本公开实施例提供了一种显示面板，包括：
栅极驱动电路，所述栅极驱动电路包括多个输出端，所述多个输出端中的至少一个与所述多条栅线中的至少一条栅线电连接；
至少一个负载补偿单元，位于所述至少一个输出端与所述至少一条栅线 之间，并且所述至少一条栅线和所述至少一个输出端电连接；
其中，所述显示基板包括显示区和围绕显示区的非显示区，所述多条栅线位于所述显示区，所述栅极驱动电路和所述至少一个负载补偿单元位于非显示区；
所述至少一个负载补偿单元用于通过控制栅线来调节像素的充电时间，以使显示屏幕各个区域亮度均一。
可选地，在本公开实施例中，所述栅极驱动电路的每一所述输出端分别连接所述多条栅线中的一条栅线，且不同的所述输出端连接不同的栅线。
可选地，在本公开实施例中，还包括第一电压供电走线和第一电压供电端子；
所述第一电压供电走线位于显示区，所述第一电压供电端子位于非显示区，且与所述第一电压供电走线电连接；
所述第一电压供电走线与所述多条栅线交叉设置，沿所述第一电压供电走线远离所述第一电压供电端子的方向上，将所有的所述负载补偿单元顺次分为至少两个单元组，每一所述单元组内具有至少一个负载补偿单元；
距离所述第一电压供电端子越远的所述单元组，所述单元组内的所述负载补偿单元的补偿负载值越大。
可选地，在本公开实施例中，各所述单元组包括相邻的至少两个所述负载补偿单元。
可选地，在本公开实施例中，同一所述单元组中各所述负载补偿单元的补偿负载值相同，不同所述单元组中的补偿负载值不同。
可选地，在本公开实施例中，各所述单元组中的负载补偿单元的数量相同。
可选地，在本公开实施例中，各所述单元组包括一个负载补偿单元。
可选地，在本公开实施例中，所述负载补偿单元至少包括补偿电阻和补偿电容中之一；其中，所述栅极驱动电路的输出端通过所述补偿电阻与对应的栅线电连接；所述补偿电容的一端与所述栅极驱动电路的输出端电连接， 另一端与接地端电连接；
在所述负载补偿单元包括补偿电阻时，所述补偿电阻的电阻值作为所述负载补偿单元的补偿负载值；
在所述负载补偿单元包括补偿电容时，所述补偿电容的电容值作为所述负载补偿单元的补偿负载值；
在所述负载补偿单元包括补偿电阻和补偿电容时，所述补偿电阻的电阻值与所述补偿电容的电容值的乘积作为所述负载补偿单元的补偿负载值。
可选地，在本公开实施例中，所述补偿电阻包括：折线形的电阻走线；其中，所述电阻走线的一端与所述栅极驱动电路的输出端电连接，另一端与所述栅线电连接。
可选地，在本公开实施例中，所述电阻走线包括：多条沿第一方向延伸的第一电阻走线和多条沿第二方向延伸的第二电阻走线，且所述第一电阻走线与所述第二电阻走线依次电连接；所述第一方向与所述第二方向交叉。
可选地，在本公开实施例中，所述第一电阻走线和所述第二电阻走线中至少有一条走线的横截面积小于所述栅线的横截面积。
可选地，在本公开实施例中，所述显示面板还包括：与各所述电阻走线对应且异层绝缘设置的第一导电层；其中，所述第一导电层在所述显示面板的正投影与对应的所述电阻走线在所述显示面板的正投影具有交叠区域；
所述补偿电容包括：位于所述交叠区域中的所述第一导电层与所述电阻走线形成的第一电容。
可选地，在本公开实施例中，所述第一导电层在所述显示面板的正投影覆盖对应的所述电阻走线在所述显示面板的正投影。
可选地，在本公开实施例中，所述显示面板还包括：连接于所述第一电阻走线与所述第二电阻走线之间的第二导电层；其中，所述第一导电层在所述显示面板的正投影覆盖所述第二导电层在所述显示面板的正投影；
所述补偿电容还包括：所述第一导电层与所述第二导电层形成的第二电容。
可选地，在本公开实施例中，所述显示面板还包括：与设置有所述负载补偿单元的输出端对应的第三导电层、以及与设置有所述负载补偿单元的移位寄存器单元的输出端电连接的第四导电层；其中，所述第三导电层与所述第四导电层异层绝缘设置；
所述第三导电层在所述显示面板的正投影与对应的所述第四导电层在所述显示面板的正投影具有交叠区域；
所述补偿电容包括：位于所述交叠区域中的所述第四导电层和所述第三导电层形成的第三电容。
可选地，在本公开实施例中，所述第三导电层在所述显示面板的正投影覆盖所述第四导电层在所述显示面板的正投影。
相应地，本公开实施例还提供了一种显示装置，包括本公开实施例提供的显示面板。
附图说明
图1为现有技术中的显示面板的结构示意图；
图2为相关技术中的像素电路的结构示意图；
图3为图2所示的像素电路的驱动时序图；
图4a为本公开实施例提供的显示面板的结构示意图之一；
图4b为本公开实施例提供的显示面板的结构示意图之二；
图5为本公开实施例提供的栅极开启信号的示意图；
图6为本公开实施例提供的显示面板的局部结构示意图之一；
图7为本公开实施例提供的显示面板的局部结构示意图之二；
图8为本公开实施例提供的显示面板的局部结构示意图之三；
图9a为本公开实施例提供的显示面板的局部结构示意图之四；
图9b为图9a中沿BB’方向的剖视结构示意图；
图10为本公开实施例提供的显示面板的局部结构示意图之五；
图11为本公开实施例提供的显示面板的局部结构示意图之六。
具体实施方式
为了使本公开的目的，技术方案和优点更加清楚，下面结合附图，对本公开实施例提供的显示面板及显示装置的具体实施方式进行详细地说明。应当理解，下面所描述的优选实施例仅用于说明和解释本公开，并不用于限定本公开。并且在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。并且，附图中各层薄膜厚度和形状不反映显示面板及显示装置的真实比例，目的只是示意说明本公开内容。
一般像素单元中设置有OLED以及用于驱动OLED发光的像素电路。如图2所示，像素电路可以包括：驱动晶体管DTFT、开关晶体管M1、存储电容Cst；其中，开关晶体管M1的栅极与栅线G_m连接，开关晶体管M1的源极与数据线data连接，开关晶体管M1的漏极与驱动晶体管DTFT的栅极连接，驱动晶体管DTFT的源极与第一电压供电走线110连接，驱动晶体管DTFT的漏极与OLED的阳极连接，OLED的阴极与低电压供电走线ELVSS连接。图2所示的像素电路的驱动时序图如图3所示，在T1阶段中，在栅线G_m上的信号g_m为栅极开启信号(即低电平信号)时，控制开关晶体管M1开启，以将数据线Data上的数据信号提供给驱动晶体管DTFT的栅极，驱动晶体管DTFT的栅极电压为数据信号的电压V data，并通过存储电容Cst进行存储。在T2阶段中，在栅线G_m上信号g_m为栅极截止信号(即高电平信号)时，控制开关晶体管M1截止，由于驱动晶体管DTFT的栅极电压为V data，驱动晶体管DTFT的源极电压为电源信号ELVDD的电压V dd，使得驱动晶体管DTFT产生工作电流I：I＝K(V dd-V data-|V th|) 2；其中，|V th|代表驱动晶体管DTFT的阈值电压，K为结构参数，相同结构中此数值相对稳定，可以算作常量。由于IR Drop的影响，在V dd降低ΔV dd时，ΔV dd代表V dd的变化量，则I降低，造成亮度降低，导致显示均一性减低。为了改善显示均一性，可以通过调整V data，以使V data降低ΔV data，通过使ΔV data＝ΔV dd，从而使V dd-V data的电压差保 持稳定，进而避免I降低，以改善亮度均一性。
一般栅极开启信号的维持时长降低，则使充入驱动晶体管DTFT的栅极的V data会降低。基于此，本公开实施例提供一种显示面板，通过在第一行像素单元指向最后一行像素单元的方向上，依次使栅极开启信号降低，从而使充入驱动晶体管DTFT的栅极的V data降低，以使像素单元中对应的ΔV data可以与相应的ΔV dd保持一致，从而保持I的稳定，提高亮度均一性。
如图4a所示，本公开实施例提供一种显示面板可以包括：多条栅线G_m(1≤m≤M且为整数，M为栅线的总数，图2以M＝6为例)、
栅极驱动电路，栅极驱动电路包括多个输出端O_m，多个输出端O_m中的至少一个与多条栅线G_m中的至少一条栅线G_m电连接；
至少一个负载补偿单元130，位于至少一个输出端O_m与至少一条栅线G_m之间，并且和至少一条栅线G_m和至少一个输出端O_m电连接；
其中，显示基板包括显示区AA和围绕显示区的非显示区BB，多条栅线G_m位于显示区AA，栅极驱动电路和至少一个负载补偿单元130位于非显示区BB；
至少一个负载补偿单元130用于通过控制栅线G_m来调节像素的充电时间，以使显示屏幕各个区域亮度均一。
本公开实施例提供的显示面板，通过在非显示区设置至少一个负载补偿单元，利用负载补偿单元通过控制栅线来调节像素的充电时间，从而使显示屏幕各个区域亮度均一。
可选地，在本发明实施例提供的显示面板中，如图4a所示，栅极驱动电路的每一输出端O_m分别连接多条栅线中的一条栅线G_m，且不同的输出端O_m连接不同的栅线G_m。
可选地，在本发明实施例提供的显示面板中，如图4a所示，还包括第一电压供电走线110和第一电压供电端子120；
第一电压供电走线110位于显示区AA，第一电压供电端子120位于非显示区BB，且与第一电压供电走线110电连接；
第一电压供电走线110与改多条栅线G_m交叉设置，
沿第一电压供电走线110远离第一电压供电端子110的方向上，将所有的负载补偿单元130顺次分为至少两个单元组10_n(1≤n≤N且为整数，N为单元组的总数，图2以N＝2为例)，每一所述单元组10_n内具有至少一个负载补偿单元130；
距离第一电压供电端子120越远的单元组10_n，该单元组10_n内的负载补偿单元130的补偿负载值越大。
在本公开实施例提供的显示面板中，沿第一电压供电走线远离第一电压供电端子的方向上，将所有的负载补偿单元顺次分为至少两个单元组，距离第一电压供电端子越远的单元组，其内的负载补偿单元的补偿负载值越大，可以使栅极驱动电路的输出端输出的栅极开启信号的时长逐渐减少，从而将IR Drop导致的亮度递减进行抵消，进而提高显示均一性。
在具体实施时，在本公开实施例提供的显示面板中，第一电压一般是指高电平的电源电压，用于输出电源信号ELVDD。
在具体实施时，如图4a所示，栅极驱动电路一般包括级联的移位寄存器单元SR_m，每一移位寄存器单元SR_m对应栅极驱动电路的一个输出端O_m用于与一条栅线G_m对应电连接。
一般栅线具有RC负载loading，并且，由于工艺制备条件一般相同，则显示面板中的各条栅线的RC负载loading基本相同，在具体实施时，在本公开实施例中，负载补偿单元对输出端O_m输出的信号进行负载补偿实际是通过对栅线的RC负载loading进行补偿，以提高栅线的RC负载loading，进而使栅极开启信号的维持时长降低。
进一步地，可以使栅极驱动电路的输出端电连接一个负载补偿单元，或者也可以使栅极驱动电路的输出端电连接两个、三个…等多个负载补偿单元，这需要根据实际应用环境来设计确定，在此不作限定。
一般显示面板的形状可以为矩形，其具有上侧、下侧、左侧、右侧共四个侧边。在具体实施时，如图4a所示，栅极驱动电路设置在左侧和/右侧。第 一电压供电端子120设置在上侧和/或下侧，使得栅极驱动电路所在的侧边与第一电压供电端子120所在的侧边相邻。并且，显示面板中还包括设置于显示区AA中的多个像素单元PX，一条栅线对应一行像素单元。栅极驱动电路和负载补偿单元可以设置于非显示区中。
一般可以采用单边驱动或双边驱动的方式对显示面板进行驱动。如图4a所示，各移位寄存器单元SR_m设置于栅线G_m的同一端，这样可以实现单边驱动。或者，各移位寄存器单元可以包括左侧移位寄存器单元和右侧移位寄存器单元，左侧移位寄存器单元和右侧移位寄存器单元分别连接于栅线的两端，从而可以实现双边驱动。
有机发光二极管(Organic Light Emitting Diode，OLED)和量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点，在具体实施时，显示面板可以包括OLED显示面板或QLED显示面板，在此不作限定。
下面结合具体实施例，对本公开进行详细说明。需要说明的是，本实施例是为了更好的解释本公开，但不限制本公开。
实施例一、
在具体实施时，在本公开实施例中，如图4a所示，可以使栅极驱动电路的各输出端O_m分别对应一个负载补偿单元130。这样可以对各输出端O_m的负载进行补偿，进一步提高亮度均一性。或者，如图4b所示，也可以使栅极驱动电路的各输出端O_m对应多个负载补偿单元130，所述多个负载补偿单元130可以采用串联或并联方式连接。例如，可以使每一输出端O_m对应两个负载补偿单元130。或者，也可以使每一输出端O_m对应三个、四个…等数量的负载补偿单元。这可以根据实际应用环境来设计确定，在此不作限定。
一般在实际应用中，显示面板在距离第一电压供电端子120较近的区域受IR Drop影响可能较小，从而可以忽略不计。在具体实施时，在本公开实施例中，可以仅使栅极驱动电路的部分输出端一一对应设置负载补偿单元。该 部分输出端可以包括远离第一电压供电端子的输出端以及与远离第一电压供电端子的输出端相邻的至少一个输出端，即可以包括第一级移位寄存器单元至第K级移位寄存器单元对应的输出端；其中K<M且为整数。这样可以减少负载补偿单元的设置，降低功耗。
在具体实施时，如图4a所示，同一单元组10_n中各负载补偿单元130的补偿负载值相同，不同单元组中的补偿负载值不同。以图4a所示的单元组10_2中的补偿负载值大于单元组10_1中的补偿负载值，以及第一级移位寄存器单元和第四级移位寄存器单元输出的栅极开启信号为例进行说明。第一级移位寄存器单元输出的信号g_1和第四级移位寄存器单元g_4如图5所示，其中，横坐标代表时间，纵坐标代表电压。受输出负载的影响，信号g_1和g_4的波形会产生变化。当信号g_1和g_4的电压下降到Vref时，则使得像素电路中的开关晶体管开启，数据信号的电压V data开始写入；当信号g_1和g_4的电压上升到Vref时，则使得像素电路中的开关晶体管加载，数据信号的电压V data写入结束，即数据电压的等效写入时间(即等效充电时间)为电压小于Vref所处的时间段。由于单元组10_1中的补偿负载值小于单元组10_2中的补偿负载值，则信号g_4的充电时间t2大于信号g_1的充电时间t1，由于等效充电时间越少，则V data写入越不充分，使得充入到驱动晶体管DTFT的栅极上的电压会减小。这样通过根据单元组10_1和单元组10_2分别对应的ΔV dd设置单元组10_1和单元组10_2中的补偿负载值，以使单元组10_1和单元组10_2对应的像素单元中所对应的ΔV data可以与相应的ΔV dd保持一致，从而使同一像素单元对应的ΔV data与相应的ΔV dd互相抵消，以保持I的稳定，继而提高了显示面板的亮度均一性，提升显示效果。
一般相邻几行像素单元所在区域中的IR Drop的变化较小，因此可以看作相同，在具体实施时，在本公开实施例中，可以使各单元组包括相邻的至少两个负载补偿单元。具体地，可以使单元组包括相邻的两个负载补偿单元，即两行栅线的补偿负载值相同。或者，如图4a所示，也可以使单元组包括相邻的三个负载补偿单元130，即三行栅线的补偿负载值相同。或者，也可以使 单元组包括相邻的四个、五个、六个…等数量的负载补偿单元。其余以此类推，在此不作赘述。当然，各单元组也可以包括一个负载补偿单元。在实际应用中，单元组中包括的负载补偿单元的数量可以根据实际应用环境来设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图4a所示，各单元组130_n中的负载补偿单元130的数量相同。这样可以使亮度均匀变化，以及简化工艺。
在具体实施时，如图6所示，负载补偿单元130可以包括：补偿电阻R0和补偿电容C0；其中，栅极驱动电路的输出端O_m通过补偿电阻R0与对应的栅线G_m电连接；补偿电容C0的一端与栅极驱动电路的输出端O_m电连接，另一端与接地端GND电连接。并且，补偿电阻R0的电阻值r 0与补偿电容C0的电容值c 0的乘积，即r 0*c 0作为负载补偿单元130的补偿负载值。进一步地，r 0、c 0以及r 0*c 0的具体数值需要根据ΔV dd进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图7所示，补偿电阻R0可以包括：折线形的电阻走线s0；其中，电阻走线s0的一端与栅极驱动电路的输出端O_m电连接，另一端与栅线G_m电连接。这样根据电阻定律公式：R＝ρL/S。其中，ρ代表电阻率，L代表电阻走线的长度，S代表电阻走线的横截面积，R代表电阻走线的电阻值；可知，通过使L增加从而可以使R增加，进而提高栅极驱动电路输出端的负载。
进一步地，在具体实施时，在本公开实施例中，如图7所示，电阻走线s0可以包括：多条沿第一方向F1延伸的第一电阻走线s01和多条沿第二方向F2延伸的第二电阻走线s02，且第一电阻走线s01与第二电阻走线s02依次电连接；并且第一方向F1与第二方向F2交叉。具体地，第一方向F1可以与第二方向F2垂直；其中，可以使第一方向F1为像素单元的行方向，第二方向F2为像素单元的列方向；或者，也可以使第一方向F1为像素单元的列方向，第二方向F2为像素单元的行方向，在此不作限定。
进一步地，在具体实施时，在本公开实施例中，如图7所示，可以使各 第一电阻走线s01的长度相同。当然，也可以使至少两条第一电阻走线的长度不同，在此不作限定。
进一步地，在具体实施时，在本公开实施例中，如图7所示，可以使各第二电阻走线s02的长度相同。当然，也可以使至少两条第二电阻走线的长度不同，在此不作限定。
进一步地，在具体实施时，在本公开实施例中，如图7所示，可以使各第一电阻走线s01与各第二电阻走线s02的横截面积相同。
进一步地，在具体实施时，在本公开实施例中，如图8所示，可以使至少一条第一电阻走线s01的横截面积小于栅线G_m的横截面积，以提高补偿电阻的电阻值。由于与一条栅线连接的补偿电阻的电阻值是确定的，因此通过降低第一电阻走线的横截面积来降低电阻值，可以对应的减小第一电阻走线的长度，从而减小占用空间。具体地，可以使一条第一电阻走线s01的横截面积小于栅线G_m的横截面积；或者，也可以使两条第一电阻走线s01的横截面积小于栅线G_m的横截面积；或者，如图8所示，也可以使各条第一电阻走线s01的横截面积小于栅线G_m的横截面积。其余以此类推，在此不作赘述。
进一步地，在具体实施时，在本公开实施例中，如图8所示，可以使至少一条第二电阻走线s02的横截面积小于栅线G_m的横截面积，以提高补偿电阻的电阻值。由于与一条栅线连接的补偿电阻的电阻值是确定的，因此通过降低第二电阻走线的横截面积来降低电阻值，可以对应的减小第二电阻走线的长度，从而减小占用空间。具体地，可以使一条第二电阻走线s02的横截面积小于栅线G_m的横截面积；或者，也可以使两条第二电阻走线s02的横截面积小于栅线G_m的横截面积；或者，如图8所示，也可以使各条第二电阻走线s02的横截面积小于栅线的横截面积。其余以此类推，在此不作赘述。
进一步地，在具体实施时，在本公开实施例中，如图7所示，显示面板还可以包括：与各电阻走线s0对应且异层绝缘设置的第一导电层140；其中，第一导电层140在显示面板的正投影与对应的电阻走线s0在显示面板的正投 影具有交叠区域。由于位于交叠区域中的第一导电层140与电阻走线s0具有正对面积，从而可以形成电容，因此补偿电容可以包括：位于交叠区域中的第一导电层140与电阻走线s0形成的第一电容。进一步地，可以使第一导电层140与接地端电连接。或者也可以使第一导电层140浮接，在此不作限定。并且，第一导电层与各电阻走线之间设置有绝缘层。
在具体实施时，在本公开实施例中，如图7所示，第一导电层140在显示面板的正投影覆盖对应的电阻走线s0在显示面板的正投影。
在具体实施时，在本公开实施例中，如图9a与图9b所示，显示面板还可以包括：连接于第一电阻走线s01与第二电阻走线s02之间的第二导电层150；其中，第一导电层140在显示面板的正投影覆盖第二导电层150在显示面板的正投影。由于第一导电层140与第二导电层150具有正对面积，从而可以形成电容，因此补偿电容还可以包括：第一导电层140与第二导电层150形成的第二电容。
进一步地，在具体实施时，在本公开实施例中，可以使电阻走线、第二导电层以及栅线同层同材质。这样可以通过一次构图工艺形成电阻走线、第二导电层以及栅线的图形，能够简化制备工艺，节省生产成本，提高生产效率。
进一步地，在具体实施时，在本公开实施例中，显示面板还可以包括：多条数据线；并且，可以使各第一导电层与各数据线绝缘且同层同材质。这样可以通过一次构图工艺形成第一导电层与各数据线的图形，能够简化制备工艺，节省生产成本，提高生产效率。
实施例二、
在具体实施时，如图6所示，也可以使负载补偿单元130包括：补偿电阻R0；其中，栅极驱动电路的输出端O_m通过补偿电阻130与对应的栅线G_m电连接。并且，补偿电阻的电阻值r 0作为负载补偿单元的补偿负载值。其具体实施时，可以参见实施例一中的补偿电阻R0的实施方式，在此不作赘述。
实施例三、
在具体实施时，在本公开实施例中，如图10所示，也可以使负载补偿单元130包括：补偿电容C0；其中，补偿电容C0的一端与栅极驱动电路的输出端O_m电连接，另一端与接地端GND电连接。并且，补偿电容C0的电容值c 0可以作为负载补偿单元130的补偿负载值。
在具体实施时，在本公开实施例中，如图11所示，显示面板还可以包括：与设置有负载补偿单元130的输出端O_m对应的第三导电层160、以及与设置有负载补偿单元130的栅极驱动电路的输出端O_m电连接的第四导电层170；其中，第三导电层160与第四导电层170异层绝缘设置，第三导电层160在显示面板的正投影与对应的第四导电层170在显示面板的正投影具有交叠区域；补偿电容可以包括：位于交叠区域中的第三导电层160与第四导电层170形成的第三电容。其中，可以使第三导电层与接地端电连接；或者，也可以使第三导电层浮接，在此不作限定。
在具体实施时，在本公开实施例中，如图11所示，可以使第三导电层160在显示面板的正投影覆盖第四导电层170在显示面板的正投影。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板。该显示装置解决问题的原理与前述显示面板相似，因此该显示装置的实施可以参见前述显示面板的实施，重复之处在此不再赘述。
在具体实施时，本公开实施例提供的显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例提供的显示面板及显示装置，通过在非显示区设置至少一个负载补偿单元，利用负载补偿单元通过控制栅线来调节像素的充电时间，从而使显示屏幕各个区域亮度均一。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本 公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (16)

  1. 一种显示面板，包括：
    多条栅线；
    栅极驱动电路，所述栅极驱动电路包括多个输出端，所述多个输出端中的至少一个与所述多条栅线中的至少一条栅线电连接；
    至少一个负载补偿单元，位于所述至少一个输出端与所述至少一条栅线之间，并且所述至少一条栅线和所述至少一个输出端电连接；
    其中，所述显示基板包括显示区和围绕显示区的非显示区，所述多条栅线位于所述显示区，所述栅极驱动电路和所述至少一个负载补偿单元位于非显示区；
    所述至少一个负载补偿单元用于通过控制栅线来调节像素的充电时间，以使显示屏幕各个区域亮度均一。
  2. 如权利要求1所述的显示面板，其中，所述栅极驱动电路的每一所述输出端分别连接所述多条栅线中的一条栅线，且不同的所述输出端连接不同的栅线。
  3. 如权利要求2所述的显示基板，其中，还包括第一电压供电走线和第一电压供电端子；
    所述第一电压供电走线位于显示区，所述第一电压供电端子位于非显示区，且与所述第一电压供电走线电连接；
    所述第一电压供电走线与所述多条栅线交叉设置，沿所述第一电压供电走线远离所述第一电压供电端子的方向上，将所有的所述负载补偿单元顺次分为至少两个单元组，每一所述单元组内具有至少一个负载补偿单元；
    距离所述第一电压供电端子越远的所述单元组，所述单元组内的所述负载补偿单元的补偿负载值越大。
  4. 如权利要求3所述的显示面板，其中，各所述单元组包括相邻的至少两个所述负载补偿单元。
  5. 如权利要求4所述的显示面板，其中，同一所述单元组中各所述负载补偿单元的补偿负载值相同，不同所述单元组中的补偿负载值不同。
  6. 如权利要求3所述的显示面板，其中，各所述单元组中的负载补偿单元的数量相同。
  7. 如权利要求1所述的显示面板，其中，所述负载补偿单元至少包括补偿电阻和补偿电容中之一；其中，所述栅极驱动电路的输出端通过所述补偿电阻与对应的栅线电连接；所述补偿电容的一端与所述栅极驱动电路的输出端电连接，另一端与接地端电连接；
    在所述负载补偿单元包括补偿电阻时，所述补偿电阻的电阻值作为所述负载补偿单元的补偿负载值；
    在所述负载补偿单元包括补偿电容时，所述补偿电容的电容值作为所述负载补偿单元的补偿负载值；
    在所述负载补偿单元包括补偿电阻和补偿电容时，所述补偿电阻的电阻值与所述补偿电容的电容值的乘积作为所述负载补偿单元的补偿负载值。
  8. 如权利要求7所述的显示面板，其中，所述补偿电阻包括：折线形的电阻走线；其中，所述电阻走线的一端与所述栅极驱动电路的输出端电连接，另一端与所述栅线电连接。
  9. 如权利要求8所述的显示面板，其中，所述电阻走线包括：多条沿第一方向延伸的第一电阻走线和多条沿第二方向延伸的第二电阻走线，且所述第一电阻走线与所述第二电阻走线依次电连接；所述第一方向与所述第二方向交叉。
  10. 如权利要求9所述的显示面板，其中，所述第一电阻走线和所述第二电阻走线中至少有一条走线的横截面积小于所述栅线的横截面积。
  11. 如权利要求8-10任一项所述的显示面板，其中，所述显示面板还包括：与各所述电阻走线对应且异层绝缘设置的第一导电层；其中，所述第一导电层在所述显示面板的正投影与对应的所述电阻走线在所述显示面板的正投影具有交叠区域；
    所述补偿电容包括：位于所述交叠区域中的所述第一导电层与所述电阻走线形成的第一电容。
  12. 如权利要求11所述的显示面板，其中，所述第一导电层在所述显示面板的正投影覆盖对应的所述电阻走线在所述显示面板的正投影。
  13. 如权利要求11所述的显示面板，其中，所述显示面板还包括：连接于所述第一电阻走线与所述第二电阻走线之间的第二导电层；其中，所述第一导电层在所述显示面板的正投影覆盖所述第二导电层在所述显示面板的正投影；
    所述补偿电容还包括：所述第一导电层与所述第二导电层形成的第二电容。
  14. 如权利要求7所述的显示面板，其中，所述显示面板还包括：与设置有所述负载补偿单元的输出端对应的第三导电层、以及与设置有所述负载补偿单元的输出端电连接的第四导电层；其中，所述第三导电层与所述第四导电层异层绝缘设置；
    所述第三导电层在所述显示面板的正投影与对应的所述第四导电层在所述显示面板的正投影具有交叠区域；
    所述补偿电容包括：位于所述交叠区域中的所述第四导电层和所述第三导电层形成的第三电容。
  15. 如权利要求14所述的显示面板，其中，所述第三导电层在所述显示面板的正投影覆盖所述第四导电层在所述显示面板的正投影。
  16. 一种显示装置，其中，包括如权利要求1-15任一项所述的显示面板。
PCT/CN2019/087656 2018-07-30 2019-05-20 显示面板及显示装置 WO2020024664A1 (zh)

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