WO2014176834A1 - 像素电路及其驱动方法、显示装置 - Google Patents

像素电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2014176834A1
WO2014176834A1 PCT/CN2013/080456 CN2013080456W WO2014176834A1 WO 2014176834 A1 WO2014176834 A1 WO 2014176834A1 CN 2013080456 W CN2013080456 W CN 2013080456W WO 2014176834 A1 WO2014176834 A1 WO 2014176834A1
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Prior art keywords
tube
control signal
switch
driving
gate
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PCT/CN2013/080456
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English (en)
French (fr)
Inventor
王颖
Original Assignee
京东方科技集团股份有限公司
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Priority to US14/342,053 priority Critical patent/US9424780B2/en
Publication of WO2014176834A1 publication Critical patent/WO2014176834A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a pixel circuit, a driving method thereof, and a display device. Background technique
  • AMOLED Active Matrix/Organic Light Emitting Diode
  • TFT Thin Film Transistor
  • LCD Liquid Crystal Display
  • the active light emitting diode display shows that because of its brightness and the magnitude of the driving current supplied to the OLED device, a large driving current is required for achieving an optimum display effect, and low temperature poly-silicon (LTPS) is used.
  • LTPS low temperature poly-silicon
  • Backplane technology is the best choice for AMOLED display backplane technology because it can provide high mobility.
  • the inherent threshold voltage drift problem of low-temperature polysilicon technology causes the non-uniformity of the drive current generated by the pixel circuit.
  • the uniformity of brightness presents a challenge. Different drive voltages produce different drive currents, resulting in poor current consistency and consistent brightness uniformity.
  • the circuit contains only two TFTs, and T1 is a switching transistor.
  • the DTFT is a pixel-driven driving tube
  • the scanning line Scan turns on the switching tube T1
  • the data voltage Data charges the storage capacitor C
  • the switching tube T1 is turned off during the light-emitting period
  • the stored voltage on the capacitor keeps the driving tube DTFT turned on, and the conduction current is made.
  • OLED illumination To achieve a stable display, it is necessary to provide a stable current for the OLED.
  • the advantage of the voltage control circuit is that the structure is simple and the charging speed of the capacitor is fast, but the disadvantage is that the linear control of the driving current is difficult because the uniformity of the ⁇ ⁇ (threshold voltage) of the DTFT is very poor on the low-temperature polysilicon process, and V th ( The threshold voltage) also drifts, even if the ⁇ ⁇ (threshold voltage) of different TFTs fabricated by the same process parameters is greatly different, causing poor illumination uniformity and brightness degradation of the driving light-emitting circuit.
  • the technical solution of the present invention provides a pixel circuit, a driving method thereof, and a display device.
  • the pixel circuit for compensating driving tubes are hook v th degree, light emitting diode solving the problem of poor brightness uniformity.
  • the embodiment of the invention provides a pixel circuit, and the pixel circuit includes:
  • the first end of the light emitting device is connected to the first voltage signal end;
  • a driving tube for driving the light emitting device
  • a source of the first switching transistor is connected to a data signal end, and a gate of the first switching transistor is connected to a first control signal end;
  • a first capacitor a first end of the first capacitor is connected to a drain of the first switch; a second capacitor, a first end of the second capacitor is connected to a second voltage signal end, and the second a second end of the capacitor is coupled to the second end of the first capacitor;
  • a third capacitor a first end of the third capacitor is connected to the first control signal end, and a second end of the third capacitor is connected to a gate of the driving tube;
  • a source of the second switching transistor is connected to a gate of the driving tube, a drain of the second switching transistor is connected to a drain of the driving tube, and a second switching transistor is a gate is connected to the first control signal end;
  • a source of the third switching transistor is respectively connected to a gate of the driving tube and a second end of the first capacitor, and a drain of the third switching transistor and a second control signal end Connecting, the gate of the third switch tube is connected to the third control signal end;
  • a source of the fourth switching transistor is connected to a drain of the driving tube, a drain of the fourth switching transistor is connected to a second end of the light emitting device, and the fourth switching tube
  • the gate is connected to the fourth control signal end;
  • a source of the fifth switch tube is connected to the second voltage signal end, a drain of the fifth switch tube is connected to a source of the drive tube, and the fifth switch tube is a gate is connected to the fourth control signal end;
  • a gate of the sixth switch is connected to the first control signal end, a source of the sixth switch is connected to a second end of the second capacitor, and the sixth switch The drain of the tube is connected to the drain of the fifth switching transistor.
  • the driving tube, the first switching tube, the second switching tube, the third switching tube, the fourth switching tube, the fifth switching tube, and the The sixth switch tube is a P-type thin film field effect transistor.
  • the second control signal terminal is grounded.
  • the light emitting device is an organic light emitting diode, and may be other light emitting elements.
  • the embodiment of the invention further provides a display device, comprising the pixel circuit according to any one of the preceding claims.
  • An embodiment of the present invention further provides a driving method of a pixel circuit as described above, where the driving method includes:
  • the third switch tube is turned on, the first switch tube, the second switch tube, and the sixth switch tube are turned off, and the gate of the drive tube is the second control signal The output voltage of the terminal;
  • the third switch tube, the fourth switch tube, and the fifth switch tube are turned off, and the first switch tube, the second switch tube, and the sixth switch tube are turned on.
  • the output voltage of the data signal end is transmitted to the gate of the driving tube, and the gate and the drain of the driving tube are turned on, and the driving tube forms a diode connection state;
  • the first switch tube, the second switch tube, the third switch tube, and the sixth switch tube are turned off, and the fourth switch tube and the fifth switch tube are turned on.
  • the voltage at the gate of the driving tube is held by the second capacitor, the driving tube is in a saturated state and turned on, and the light emitting device emits light.
  • the driving tube, the first switching tube, the second switching tube, the third switching tube, the fourth switching tube, the fifth switching tube, and the The sixth switch tube is a P-type thin film field effect transistor.
  • the first control signal end and the data signal end respectively output a high level, the third control signal end and the fourth control signal end Outputting a low level respectively; in the second phase, the third control signal end and the fourth control signal end respectively output a high level, and the first control signal end and the data signal end output low power
  • the third control signal end, the third control signal end and the data signal end output a high level, and the fourth control signal end outputs a low level.
  • the second control signal end is grounded in the first phase, the second phase, and the third phase.
  • the pixel circuit and the driving method are used to make the voltage value of the driving tube and the voltage of the data writing signal during the data writing process in the second stage,
  • the voltage of the second control signal terminal, the voltage of the first control signal terminal and the threshold voltage of the driving tube are related to each other and are maintained by the second capacitor;
  • the driving tube operates in the saturation region, and since the voltage at the gate of the driving tube is held by the second capacitor, the drain current of the driving tube is independent of the threshold value ⁇ ⁇ of the driving tube, thereby effectively solving the threshold voltage of the low temperature polysilicon film tube
  • the unevenness of the pixel drive current caused by drift ensures uniformity of display brightness.
  • FIG. 1 is a schematic diagram showing the circuit structure of a prior art pixel circuit
  • FIG. 2 is a schematic diagram showing a connection structure of a pixel circuit according to an embodiment of the present invention
  • FIG. 3 is a timing chart showing control signals of a pixel circuit according to an embodiment of the present invention.
  • FIG. 4 is an equivalent circuit diagram of the pixel circuit of the present invention in a first stage tl;
  • Fig. 5 is an equivalent circuit diagram showing the pixel circuit of the present invention in the second stage t2; and Fig. 6 is an equivalent circuit diagram showing the pixel circuit of the present invention in the third stage t3.
  • the first end of the light emitting device is connected to the first voltage signal end;
  • a driving tube for driving the light emitting device
  • a source of the first switching transistor is connected to a data signal end, and a gate of the first switching transistor is connected to a first control signal end;
  • a first capacitor a first end of the first capacitor is connected to a drain of the first switch; a second capacitor, a first end of the second capacitor is connected to a second voltage signal end, and the second a second end of the capacitor is coupled to the second end of the first capacitor;
  • a third capacitor a first end of the third capacitor is connected to the first control signal end, and a second end of the third capacitor is connected to a gate of the driving tube;
  • a source of the second switching transistor is connected to a gate of the driving tube, a drain of the second switching transistor is connected to a drain of the driving tube, and a second switching transistor is a gate is connected to the first control signal end;
  • a third switching transistor a source of the third switching transistor and a gate of the driving tube and the first a second end of the capacitor is connected, a drain of the third switch is connected to a second control signal end, and a gate of the third switch is connected to a third control signal end;
  • a source of the fourth switching transistor is connected to a drain of the driving tube, a drain of the fourth switching transistor is connected to a second end of the light emitting device, and the fourth switching tube
  • the gate is connected to the fourth control signal end;
  • a source of the fifth switch tube is connected to the second voltage signal end, a drain of the fifth switch tube is connected to a source of the drive tube, and the fifth switch tube is a gate is connected to the fourth control signal end;
  • a gate of the sixth switch is connected to the first control signal end, a source of the sixth switch is connected to a second end of the second capacitor, and the sixth switch The drain of the tube is connected to the drain of the fifth switching transistor.
  • the driving method using the above pixel circuit includes:
  • the third switch tube is turned on, the first switch tube, the second switch tube, and the sixth switch tube are turned off, and the gate of the drive tube is the second control signal The output voltage of the terminal;
  • the third switch tube, the fourth switch tube, and the fifth switch tube are turned off, and the first switch tube, the second switch tube, and the sixth switch tube are turned on.
  • the output voltage of the data signal end is transmitted to the gate of the driving tube, and the gate and the drain of the driving tube are turned on, and the driving tube forms a diode connection state;
  • the first switch tube, the second switch tube, the third switch tube, and the sixth switch tube are turned off, and the fourth switch tube and the fifth switch tube are turned on.
  • the voltage at the gate of the driving tube is held by the second capacitor, the driving tube is in a saturated state and turned on, and the light emitting device emits light.
  • the driving tube, the first switching tube, the second switching tube, the third switching tube, the fourth switching tube, and the The fifth switch tube and the sixth switch tube are respectively P-type thin film field effect transistors.
  • the second control signal end is grounded in the first phase, the second phase, and the third phase.
  • the first control signal end and the data signal end respectively output a high level
  • the third control signal end and the fourth control signal end respectively output a low level
  • the third control signal end and the fourth control signal end respectively output a high level
  • the first control signal end and the data signal end output a low level
  • the fourth control signal end outputs a low level.
  • the pixel circuit and the driving method are used to make the voltage value of the driving tube and the voltage of the data writing signal, the voltage of the second control signal end, the voltage of the first control signal end, and the driving tube in the data writing process of the second stage.
  • the threshold voltage is related to and maintained by the second capacitor; in the third phase, the driving transistor operates in the saturation region, and since the voltage at the gate of the driving transistor is held by the second capacitor, the drain current of the driving transistor is threshold ⁇ ⁇ independent drive tube, so as to effectively solve the problem of uneven pixel threshold voltage drift tube temperature polysilicon thin film caused by the driving current, the brightness of the display ensure homogeneity.
  • FIG. 2 is a schematic structural diagram of a pixel circuit according to the present invention.
  • the pixel circuit structure of this embodiment includes seven TFTs and three capacitors C, wherein all of the seven TFTs are P-channel tubes, wherein T1 ⁇ T6 are switching tubes, and DTFT is a driving tube.
  • the first control signal terminal S Gate the second control signal terminal 8 ⁇ , the third control signal terminal S Reset , the fourth control signal terminal S EM , the data signal terminal S Data , and the first voltage are used in this embodiment.
  • a fifth switching transistor T5, a driving transistor DTFT, a fourth switching transistor T4, and a light emitting device OLED are sequentially connected in series between the first voltage signal terminal and the second voltage signal terminal, wherein the fifth switching transistor T5
  • the gate is connected to the fourth control signal terminal S EM for responding to the voltage outputted by the fourth control signal terminal S EM to open or turn on the connection between the second voltage signal terminal and the source of the driving transistor DTFT
  • gate of the fourth switching transistor T4 is also connected to the fourth control signal terminal S EM, a voltage in response to the fourth control signal output terminal S EM, is turned OFF or the drain of the drive tube DTFT of the light emitting device OLED The connection between the two.
  • the method further includes:
  • the sixth switch tube T6, the first capacitor C1 and the first switch tube T1 are disposed in series between the source of the drive tube DTFT and the data signal terminal S Data , wherein the sixth switch tube ⁇ 6 and the gate of the first switch tube T1 The poles are respectively connected to the first control signal terminal S Cate and are respectively turned off or turned on in response to the voltage of the first control signal terminal S Cat .
  • the source of the sixth switch tube T6 is connected to the source of the driving tube DTFT, and the drain of the sixth switch tube T6 is connected to the second end of the first capacitor C1, as shown in FIG. 2, and the sixth switch tube T6.
  • the source is also connected to the second end of the second capacitor C2, and the sixth switch tube T6
  • the drain is also connected to the drain of the fifth switch T5; the drain of the first switch T1 is connected to the first end of the first capacitor C1, and the source of the first switch T1 is connected to the data signal terminal S Data ;
  • the first end is connected to the second voltage signal end, and the second end is connected to the second end of the first capacitor C1;
  • a third capacitor C3 the first end is connected to the first control signal end S Gate , and the second end is connected to the gate of the driving tube DTFT;
  • a source of the second switching transistor T2 is connected to a gate of the driving transistor DTFT, a drain of the second switching transistor T2 is connected to a drain of the driving transistor DTFT, and a gate of the second switching transistor T2
  • the first control signal terminal S Cate is connected to the voltage of the output of the first control signal terminal S Cate to disconnect or turn on the gate and the drain of the driving transistor DTFT;
  • the third switch tube T3, the source of the third switch tube T3 is respectively connected to the gate of the driving tube DTFT and the second end of the first capacitor C1, the drain of the third switch tube T3 and the second control signal S Ref terminal connected to a gate of the third switch T3 of the third control signal terminal S Reset connection.
  • the second control signal terminal S Ref may be grounded, that is, the output voltage V Ref is zero; and the first control signal terminal S Gate outputs a row scan signal of the display panel.
  • FIG. 3 is a timing diagram of control signals of the pixel circuit shown in FIG. 2;
  • FIG. 4 to FIG. 6 are equivalent circuit diagrams of the pixel circuit in the first stage 11, the second stage t2, and the third stage 13, respectively.
  • the first stage t1 shown in Figure 3 is the initialization phase of the pixel circuit.
  • the third control signal terminal S Reset inputs a low level, so that the third switch transistor T3 is turned on in response to the low voltage outputted by the third control signal terminal S Reset , and writes the voltage output from the second control signal terminal S Ref to the A.
  • a point that is, at the gate of the driving tube
  • a connection end between the third switching tube T3 and the second end of the third capacitor C3 at this time, the voltages of the second end of the first capacitor C1 and the second end of the third capacitor C3 are also respectively
  • the voltage value outputted by the second control signal terminal S Ref is completed, and the initialization of the pixel state is completed.
  • the first control signal terminal S Gate the fourth control signal terminal S EM and the data signal terminal S Date output a high level, the first switching transistor T1, the second switching transistor 2, and the fifth switching transistor Disconnected from the sixth switch tube ⁇ 6.
  • the second stage 12 shown in Figure 3 is the write phase of pixel data.
  • the voltage outputted by the third control signal terminal S Reset changes from a low level to a high level
  • the third switching transistor T3 is turned off
  • the voltage value V Ref outputted by the second control signal terminal S Ref is The second capacitor C2 is maintained.
  • the voltage of the data signal terminal S Data is at Low level
  • the first control signal end S Cate of the output line scan signal is also at a low level to make the control signal valid
  • the first switch tube T1 is turned on
  • the voltage output from the data signal end S Data is written into the pixel circuit
  • the voltage at the point A of the gate of the driving transistor DTFT is (V Data + V Ref + V Gate ).
  • the second switching transistor T2 is turned on in response to the voltage outputted by the control signal terminal S Gate , then the gate and the drain of the driving transistor DTFT are connected to form a diode connection state.
  • the threshold voltage ⁇ ⁇ of the drive tube is recorded and held by the second capacitor C2.
  • the voltage at point A that is, the voltage of the gate of the driving transistor DTFT is (V Data + V Ref + V Gate - ⁇ ⁇ ), and the voltage is stored by the second capacitor C2.
  • the signal outputted by the fourth control signal terminal S EM is at a high level to ensure that the fourth switching transistor T4 is turned off, and the operation of writing data into the pixel does not generate a light-emitting state of the light-emitting device OLED. Affects, avoids the flicker of the display.
  • the signal outputted by the fourth control signal terminal S EM is high level, which also ensures that the fifth switching transistor T5 is turned off, ensuring that the source of the driving transistor DTFT and the second voltage signal terminal are disconnected at this time, thereby avoiding the driving tube
  • the leakage of the DTFT indirectly affects the adverse effect of the gate voltage of the driving transistor DTFT.
  • the diode diode state of the driving transistor is present at this time, so that the leakage between the source and the drain of the driving transistor DTFT is directly introduced to the gate terminal, thereby The drain current of the driving transistor DTFT, that is, the driving current of the light emitting device OLED, is affected.
  • the sixth switching transistor T6 is turned on, and the voltage of the point A is led to the source of the driving transistor DTFT. In the second case, even if there is a leakage phenomenon of the driving transistor DTFT, the gate voltage of the driving transistor DTFT is not affected, thereby affecting the leakage current of the driving transistor DTFT.
  • the third phase t3 shown in FIG. 3 is the illumination phase of the light-emitting device OLED.
  • the third control signal terminal S Reset output remains at a high level, the third switching transistor T3 off; s data while the data signal stops writing the data terminal, is high; a first control signal
  • the terminal S Gate jumps to a high level, and the first switching transistor T1, the second switching transistor T2, and the sixth switching transistor T6 are turned off, and the voltage at the point A of the driving transistor DTFT gate (V Data +V Ref +V Gate - V Th ) is held by the second capacitor C2 which ensures that the drive transistor DTFT operates in the saturation region.
  • the signal outputted by the fourth control signal terminal S EM is at a low level, so that the fourth switching transistor T4 and the fifth switching transistor T5 are turned on to ensure that the light emitting device OLED emits light.
  • the voltage between the source and the source of the DTFT gate; the mobility of the drive tube, C. x (W / L) is the capacitance of the gate insulating layer, the channel width of the W thin film tube, and the channel length of the L thin film tube.
  • the drain current of the drive tube DTFT "and independent of the threshold voltage ⁇ ⁇ , the threshold voltage of the drive tube ⁇ ⁇ the DTFT drift, will not, i.e., drive current for driving the drain pipe of the pixel circuit DTFT The current has an effect.
  • V Ref is grounded to reset the potential of point A, and if there is a voltage drop caused by wire resistance or parasitic resistance at the second voltage signal end, that is, IR drop, the value of V Ref may be The adjustment is made such that it can cancel out the voltage drop caused by the IR drop.
  • the pixel circuit structure can also compensate for the problem of pixel current fluctuation caused by the IR drop of the power supply.
  • the pixel circuit introduces the third capacitor C3, so that the potential of the A point, that is, the gate potential of the driving transistor DTFT can be raised, thereby providing a larger driving current, and the driving transistor DTFT is increased due to the increase of the gate voltage.
  • the response speed is also correspondingly faster.
  • the capacitance of the third capacitor C3 is very small, on the order of 10E-2pF, occupying a small layout area, and does not affect the overall pixel layout area.
  • the pixel circuit and the driving method thereof can not only compensate the Vth uniformity of the driving tube, but also solve the problem that the luminous brightness of the LED is poor, and can solve the IR drop of the compensation power supply.
  • the resulting pixel fluctuation problem also makes the response speed of the drive tube DTFT faster.
  • All of the switching transistors and transistors in the pixel circuit provided in the embodiments of the present invention are P-type thin film field effect transistors.
  • all of the switching transistors and transistors may also be N-type thin film field effect transistors, but the first voltage signal terminal The output voltage is VDD, the output voltage of the second voltage signal terminal is VSS, and the position of the organic light emitting diode is also changed.
  • the first end of the organic light emitting diode is connected to the second voltage signal end, and the second end of the organic light emitting diode is connected to the fifth end.
  • the source of the switch tube, all the switch tubes are turned on at a high level, and the voltage signals output by all the control signal terminals can be adjusted accordingly.
  • the specific working principle is similar to the above, and will not be described again.
  • the switch tube mentioned in the present invention is not limited to a thin film field effect transistor having a gate, a source and a drain, as long as it can function as a switching element having the same function as the thin film field effect transistor, and In the field of liquid crystal display, there is no clear difference between the drain and the source.
  • the source of the tube mentioned in the embodiment of the present invention may be the drain of the tube, and the drain of the tube may also be the source of the tube.
  • the first end and the second end of the capacitor just to clearly describe the connection relationship of the capacitors.
  • Another aspect of the present invention provides a display device having the above-described pixel circuit, and the pixel circuit provided in the display device is described in detail above, and will not be described again.

Abstract

一种像素电路及其驱动方法、显示装置，所述像素电路包括：第一开关管，源极与数据信号端连接，栅极与第一控制信号端连接；第一电容，第一端与第一开关管的漏极连接；第二电容，第一端与第二电压信号端连接，第二端与第一电容的第二端连接；第三电容，第一端与第一控制信号端连接，第二端与驱动管的栅极连接；第二开关管，源极与驱动管的栅极连接，漏极与驱动管的漏极连接，栅极与第一控制信号端连接；以及第三、第四、第五和第六开关管。该像素电路用于对像素电路中的驱动管进行阈值电压均匀度的补偿，解决发光二极管发光亮度均匀性差的问题。

Description

像素电路及其驱动方法、 显示装置 技术领域
本发明涉及液晶显示技术领域， 尤其是指一种像素电路及其驱动方法、 显示装置。 背景技术
有源矩阵有机发光二极管 （ Active Matrix/Organic Light Emitting Diode, AMOLED )显示作为新型的显示技术，与场效应薄膜管（ Thin Film Transistor, TFT )液晶显示器（Liquid Crystal Display, LCD )相比， AMOLED不管在视 角范围、 画质、 效能及成本上都有很多优势， 在显示器制造领域有巨大的发 展潜力。
有源发光二极管显示因为其发光亮度和提供给 OLED器件的驱动电流的 大小成正比， 故为了实现最佳的显示效果， 需要较大的驱动电流， 而低温多 晶硅（ LTPS, Low Temperature Poly-silicon )背板技术由于可以提供较高的迁 移率， 是 AMOLED显示背板技术的最佳选择， 但是低温多晶硅技术固有的 阈值电压漂移的问题， 造成了像素电路产生的驱动电流的不均匀性， 给显示 亮度的均匀性提出了挑战。 不同的驱动电压会产生不同的驱动电流， 造成电 流的一致性很差， 亮度均匀性一直很差。
如图 1所示的传统的 2T1C电路， 电路只包含两个 TFT, T1为开关管，
DTFT为像素驱动的驱动管， 扫描线 Scan开启开关管 T1 , 数据电压 Data对 存储电容 C充电， 发光期间开关管 T1关闭， 电容上的存储的电压使驱动管 DTFT保持导通， 导通电流使 OLED发光。 要实现稳定显示， 就要为 OLED 提供稳定电流。 电压控制电路的优点是结构筒单、 电容充电速度快， 但是缺 点是驱动电流的线性控制困难， 原因是低温多晶硅制程上使 DTFT的 νώ (阈 值电压）的均匀性非常差， 同时 Vth (阈值电压）也有漂移， 即便是同样工艺 参数制造出来的不同 TFT的 νώ (阈值电压）也有较大差异， 造成驱动发光 电路的发光亮度均匀性很差和亮度衰减的问题。 发明内容
根据以上，本发明技术方案提供一种像素电路及其驱动方法、显示装置， 用于对像素电路中的驱动管进行 vth均勾度的补偿，解决发光二极管发光亮度 均匀性差的问题。
本发明实施例提供一种像素电路， 所述像素电路包括：
发光器件， 所述发光器件的第一端连接第一电压信号端；
用于驱动所述发光器件的驱动管；
第一开关管， 所述第一开关管的源极与数据信号端连接， 所述第一开关 管的栅极与第一控制信号端连接；
第一电容， 所述第一电容的第一端与所述第一开关管的漏极连接； 第二电容， 所述第二电容的第一端与第二电压信号端连接， 所述第二电 容的第二端与所述第一电容的第二端连接；
第三电容， 所述第三电容的第一端与所述第一控制信号端连接， 所述第 三电容的第二端与所述驱动管的栅极连接；
第二开关管， 所述第二开关管的源极与所述驱动管的栅极连接， 所述第 二开关管的漏极与所述驱动管的漏极连接， 所述第二开关管的栅极与所述第 一控制信号端连接；
第三开关管， 所述第三开关管的源极分别与所述驱动管的栅极和所述第 一电容的第二端连接， 所述第三开关管的漏极与第二控制信号端连接， 所述 第三开关管的栅极与第三控制信号端连接；
第四开关管， 所述第四开关管的源极与所述驱动管的漏极连接， 所述第 四开关管的漏极与所述发光器件的第二端连接， 所述第四开关管的栅极与第 四控制信号端连接；
第五开关管， 所述第五开关管的源极与所述第二电压信号端连接， 所述 第五开关管的漏极与所述驱动管的源极连接， 所述第五开关管的栅极与所述 第四控制信号端连接；
第六开关管， 所述第六开关管的栅极与所述第一控制信号端连接， 所述 第六开关管的源极与所述第二电容的第二端连接， 所述第六开关管的漏极与 所述第五开关管的漏极连接。
优选地， 在上述像素电路中， 所述驱动管、 所述第一开关管、 所述第二 开关管、 所述第三开关管、 所述第四开关管、 所述第五开关管和所述第六开 关管分别为 P型薄膜场效应管。
优选地， 在上述像素电路中， 所述第二控制信号端接地连接。 优选地， 在上述像素电路中， 所述发光器件为有机发光二极管， 也可以 为其它发光元件。
本发明实施例还提供一种显示装置， 包括上任一项所述的像素电路。 本发明实施例还提供一种如上所述像素电路的驱动方法， 所述驱动方法 包括：
在第一阶段， 所述第三开关管导通， 所述第一开关管、 所述第二开关管 和所述第六开关管关断， 所述驱动管的栅极为所述第二控制信号端输出的电 压；
在第二阶段，所述第三开关管、所述第四开关管和所述第五开关管关断， 所述第一开关管、 所述第二开关管和所述第六开关管导通， 所述数据信号端 的输出电压传输至所述驱动管的栅极， 且所述驱动管的栅极与漏极导通， 所 述驱动管形成二极管连接状态；
在第三阶段， 所述第一开关管、 所述第二开关管、 所述第三开关管和所 述第六开关管关断， 所述第四开关管和所述第五开关管导通， 所述驱动管的 栅极处的电压由所述第二电容保持， 所述驱动管处于饱和状态而导通， 所述 发光器件发光。
优选地， 在上述驱动方法中， 所述驱动管、 所述第一开关管、 所述第二 开关管、 所述第三开关管、 所述第四开关管、 所述第五开关管和所述第六开 关管分别为 P型薄膜场效应管。
优选地， 在上述驱动方法中， 在所述第一阶段， 所述第一控制信号端和 所述数据信号端分别输出高电平， 所述第三控制信号端和所述第四控制信号 端分别输出低电平； 在所述第二阶段， 所述第三控制信号端和所述第四控制 信号端分别输出高电平，所述第一控制信号端和所述数据信号端输出低电平； 在所述第三阶段， 所述第一控制信号端、 所述第三控制信号端和所述数据信 号端输出高电平， 所述第四控制信号端输出低电平。
优选地， 上述所述的驱动方法， 所述第二控制信号端在所述第一阶段、 所述第二阶段和所述第三阶段均接地连接。
本发明具体实施例上述技术方案中的至少一个具有以下有益效果： 采用上述像素电路及驱动方法， 使得在第二阶段的数据写入过程中， 驱 动管的电压值与数据写入信号的电压、 第二控制信号端的电压、 第一控制信 号端的电压及驱动管的阈值电压有关， 且由第二电容所保持； 在第三阶段， 驱动管工作在饱和区， 且由于驱动管的栅极处的电压由第二电容所保持， 使 得驱动管的漏极电流与驱动管的阈值 νώ无关，从而有效解决低温多晶硅薄膜 管的阈值电压漂移造成的像素驱动电流的不均匀问题， 确保显示亮度的均匀 性。 附图说明
图 1表示现有技术像素电路的电路结构示意图；
图 2表示本发明具体实施例所述像素电路的连接结构示意图；
图 3表示本发明具体实施例所述像素电路的控制信号时序图；
图 4表示本发明所述像素电路在第一阶段 tl的等效电路图；
图 5表示本发明所述像素电路在第二阶段 t2的等效电路图； 以及 图 6表示本发明所述像素电路在第三阶段 t3的等效电路图。 具体实施方式
为使本发明的目的、 技术方案和优点更加清楚， 下面将结合附图及具体 实施例对本发明进行详细描述， 显然， 所描述的实施例仅仅是本发明一部分 实施例， 而不是全部的实施例。
本发明具体实施例所述像素电路， 包括：
发光器件， 所述发光器件的第一端连接第一电压信号端；
用于驱动所述发光器件的驱动管；
第一开关管， 所述第一开关管的源极与数据信号端连接， 所述第一开关 管的栅极与第一控制信号端连接；
第一电容， 所述第一电容的第一端与所述第一开关管的漏极连接； 第二电容， 所述第二电容的第一端与第二电压信号端连接， 所述第二电 容的第二端与所述第一电容的第二端连接；
第三电容， 所述第三电容的第一端与所述第一控制信号端连接， 所述第 三电容的第二端与所述驱动管的栅极连接；
第二开关管， 所述第二开关管的源极与所述驱动管的栅极连接， 所述第 二开关管的漏极与所述驱动管的漏极连接， 所述第二开关管的栅极与所述第 一控制信号端连接；
第三开关管， 所述第三开关管的源极分别与所述驱动管的栅极和所述第 一电容的第二端连接， 所述第三开关管的漏极与第二控制信号端连接， 所述 第三开关管的栅极与第三控制信号端连接；
第四开关管， 所述第四开关管的源极与所述驱动管的漏极连接， 所述第 四开关管的漏极与所述发光器件的第二端连接， 所述第四开关管的栅极与第 四控制信号端连接；
第五开关管， 所述第五开关管的源极与所述第二电压信号端连接， 所述 第五开关管的漏极与所述驱动管的源极连接， 所述第五开关管的栅极与所述 第四控制信号端连接；
第六开关管， 所述第六开关管的栅极与所述第一控制信号端连接， 所述 第六开关管的源极与所述第二电容的第二端连接， 所述第六开关管的漏极与 所述第五开关管的漏极连接。
采用上述的像素电路的驱动方法， 包括：
在第一阶段， 所述第三开关管导通， 所述第一开关管、 所述第二开关管 和所述第六开关管关断， 所述驱动管的栅极为所述第二控制信号端输出的电 压；
在第二阶段， 所述第三开关管、 所述第四开关管和所述第五开关管关断, 所述第一开关管、 所述第二开关管和所述第六开关管导通， 所述数据信号端 的输出电压传输至所述驱动管的栅极， 且所述驱动管的栅极与漏极导通， 所 述驱动管形成二极管连接状态；
在第三阶段， 所述第一开关管、 所述第二开关管、 所述第三开关管和所 述第六开关管关断， 所述第四开关管和所述第五开关管导通， 所述驱动管的 栅极处的电压由所述第二电容保持， 所述驱动管处于饱和状态而导通， 所述 发光器件发光。
优选地， 上述所述的像素电路及其驱动方法中， 所述驱动管、 所述第一 开关管、 所述第二开关管、 所述第三开关管、 所述第四开关管、 所述第五开 关管和所述第六开关管分别为 P型薄膜场效应管。
其中， 所述第二控制信号端在所述第一阶段、 所述第二阶段和所述第三 阶段均接地连接。 在所述第一阶段， 所述第一控制信号端和所述数据信号端 分别输出高电平， 所述第三控制信号端和所述第四控制信号端分别输出低电 平； 在所述第二阶段， 所述第三控制信号端和所述第四控制信号端分别输出 高电平， 所述第一控制信号端和所述数据信号端输出低电平； 在所述第三阶 段， 所述第一控制信号端、 所述第三控制信号端和所述数据信号端输出高电 平， 所述第四控制信号端输出低电平。
采用上述的像素电路及驱动方法， 使得在第二阶段的数据写入过程中， 驱动管的电压值与数据写入信号的电压、 第二控制信号端的电压、 第一控制 信号端的电压及驱动管的阈值电压有关， 且由第二电容所保持； 在第三阶段, 驱动管工作在饱和区， 且由于驱动管的栅极处的电压由第二电容所保持， 使 得驱动管的漏极电流与驱动管的阈值 νώ无关，从而有效解决低温多晶硅薄膜 管的阈值电压漂移造成的像素驱动电流的不均匀问题， 确保显示亮度的均匀 性。
以下将对本发明实施例的像素电路的具体结构进行详细描述。
如图 2所示为本发明所述像素电路的结构示意图。 参阅图 2所示， 本实 施例的像素电路结构含有 7个 TFT和 3个电容 C, 其中， 7个 TFT皆为 P沟 道管， 其中 T1~T6为开关管， DTFT为驱动管。 此外本实施例使用了第一控 制信号端 SGate、 第二控制信号端8^、 第三控制信号端 SReset、 第四控制信号 端 SEM, —个数据信号端 SData, 和第一电压信号端、 第二电压信号端， 其中， 第一电压信号端输出的信号为 VDD、第二电压信号端输出的信号为 vss,控制 信号端 sCate、 sRef和数据信号端 sdata输出的电压分别为 VCate、 VRef和 VData。
如图 2所示， 在第一电压信号端和第二电压信号端之间依次串接有第五 开关管 T5、 驱动管 DTFT、 第四开关管 T4和发光器件 OLED, 其中第五开关 管 T5的栅极与第四控制信号端 SEM连接，用于响应该第四控制信号端 SEM输 出的电压， 断开或导通第二电压信号端与驱动管 DTFT的源极之间的连接； 第四开关管 T4的栅极也与第四控制信号端 SEM连接，用于响应该第四控制信 号端 SEM输出的电压， 断开或导通驱动管 DTFT的漏极与发光器件 OLED之 间的连接。
此外， 在图 2所示的像素电路中， 还包括：
依次串联设置在驱动管 DTFT的源极与数据信号端 SData之间的第六开关 管 T6、 第一电容 C1和第一开关管 T1 , 其中第六开关管 Τ6和第一开关管 T1 的栅极分别与第一控制信号端 SCate连接， 分别响应该第一控制信号端 SCat 出的电压而断开或导通。具体地第六开关管 T6的源极与驱动管 DTFT的源极 连接， 第六开关管 T6的漏极与第一电容 C1的第二端连接， 如图 2所示， 同 时第六开关管 T6的源极还与第二电容 C2的第二端连接， 第六开关管 T6的 漏极还与第五开关管 T5的漏极连接； 第一开关管 T1的漏极与第一电容 C1 的第一端连接， 第一开关管 T1的源极与数据信号端 SData连接；
第二电容 C2, 第一端与第二电压信号端连接， 第二端与第一电容 C1的 第二端连接；
第三电容 C3 ,第一端与第一控制信号端 SGate连接，第二端与驱动管 DTFT 的栅极连接；
第二开关管 T2,所述第二开关管 T2的源极与驱动管 DTFT的栅极连接， 第二开关管 T2的漏极与驱动管 DTFT的漏极连接， 第二开关管 T2的栅极与 第一控制信号端 SCate连接， 用于响应该第一控制信号端 SCate输出的电压， 使 驱动管 DTFT的栅极与漏极断开或导通；
第三开关管 T3, 所述第三开关管 T3的源极分别与驱动管 DTFT的栅极 和第一电容 C1的第二端连接， 所述第三开关管 T3的漏极与第二控制信号端 SRef连接， 所述第三开关管 T3的栅极与第三控制信号端 SReset连接。
具体地， 上述的第二控制信号端 SRef可以接地连接， 也即输出电压 VRef 为零； 而第一控制信号端 SGate输出显示面板的行扫描信号。
以下结合图 3、 图 4至图 6对本发明实施例上述结构的像素电路的工作 过程进行详细描述。 其中图 3为图 2所示像素电路的控制信号时序图； 图 4 至图 6分别为像素电路在第一阶段 11、第二阶段 t2和第三阶段 13的等效电路 图。
图 3所示的第一阶段 tl , 为像素电路的初始化阶段。 其中第三控制信号 端 SReset输入低电平，使第三开关管 T3响应该第三控制信号端 SReset输出的低 电压而导通， 将第二控制信号端 SRef输出的电压写入 A点 （也即驱动管的栅 极处）， 也即第三开关管 T3与第三电容 C3第二端的连接端点； 此时第一电 容 C1第二端和第三电容 C3第二端的电压也分别为第二控制信号端 SRef输出 的电压值 ]^, 完成像素状态的初始化。 同时， 在第一阶段 tl , 第一控制信 号端 SGate,第四控制信号端 SEM和数据信号端 SDate输出高电平， 第一开关管 Tl、 第二开关管 Τ2、 第五开关管和第六开关管 Τ6断开。
图 3所示的第二阶段 12, 为像素数据的写入阶段。 在该第二阶段 12, 第 三控制信号端 SReset输出的电压从低电平跳变为高电平，第三开关管 T3关闭， 第二控制信号端 SRef输出的电压值 VRef由第二电容 C2保持。
同时， 通过数据信号端 SData输入数据， 数据信号端 SData输出的电压处于 低电平， 输出行扫描信号的第一控制信号端 SCate也处于低电平而使控制信号 有效， 第一开关管 T1导通， 数据信号端 SData输出的电压写入该像素电路， 则此时驱动管 DTFT栅极处 A点的电压为 （ VData+VRef+VGate )。
同时由于第一控制信号端 SCate有效， 使得第二开关管 T2响应该控制信 号端 SGate输出的电压而导通， 则此时驱动管 DTFT栅极和漏极相连， 形成一 个二极管连接状态，而驱动管的阈值电压 νώ被记录下来且由第二电容 C2保 持。综合考虑，此时 A点电压，即驱动管 DTFT栅极的电压为（VData+VRef+VGate - νώ ), 且该电压由第二电容 C2存储。
此外第二阶段 t2时， 第四控制信号端 SEM输出的信号为高电平， 确保第 四开关管 T4关闭， 则数据写入像素这一动作， 并不会对发光器件 OLED的 发光状态产生影响， 避免了显示的闪烁。 同时第四控制信号端 SEM输出的信 号为高电平也保证了第五开关管 T5关闭，确保了此时驱动管 DTFT的源极和 第二电压信号端断开， 从而避免了由于驱动管 DTFT的漏电而间接影响驱动 管 DTFT栅极电压的不良影响， 这是因为此时驱动管 DTFT二极管状态的存 在， 使得驱动管 DTFT源极与漏极之间的漏电直接引入到栅极端， 从而对于 驱动管 DTFT的漏极电流， 即发光器件 OLED的驱动电流会造成影响。 另一 方面， 为了避免驱动管 DTFT的源极浮空， 在第一控制信号端 SGat 出信号 的控制下， 第六开关管 T6打开， 将 A点的电压引至驱动管 DTFT的源极， 再次情况下， 即使存在驱动管 DTFT的漏电现象， 也不会对驱动管 DTFT的 栅极电压造成影响， 从而影响驱动管 DTFT的漏电流。
图 3所示的第三阶段 t3, 为发光器件 OLED的发光阶段。 在该第三阶段 13 , 第三控制信号端 SReset输出的信号仍旧处于高电平， 第三开关管 T3关闭； 同时数据信号端 sdata停止写入数据， 为高电平； 第一控制信号端 SGate跳变为 高电平，第一开关管 T1、第二开关管 T2和第六开关管 T6关闭，驱动管 DTFT 栅极处 A点的电压 （ VData+VRef+VGate - Vth ) 由第二电容 C2所保持， 该电压 确保驱动管 DTFT工作在饱和区。 同时第四控制信号端 SEM输出的信号处于 低电平， 使第四开关管 T4和第五开关管 T5导通， 确保发光器件 OLED发光 显示。 则此时驱动管 DTFT的漏极电流 Id为： = Re/ +vGate -vth)-vth]2
= ate - VRef f
Figure imgf000011_0001
其中： 为驱动管 DTFT栅源极之间的电压； 为驱动管的迁移率， C。x(W/L)为栅极绝缘层的电容， W薄膜管的沟道宽度， L薄膜管的沟道长度。
根据上述公式可以看出， 驱动管 DTFT的漏极电流《与阈值电压 νώ无 关，则驱动管 DTFT的阈值电压 νώ的漂移，不会对驱动管 DTFT的漏极电流， 即像素电路的驱动电流产生影响。
另外， 优选地， VRef接地连接， 起到对 A点电位的复位作用， 同时如果 在第二电压信号端有导线电阻或寄生电阻引起的电压降， 即 IR drop, 则对 VRef的数值可以进行调整，使其能与 IR drop引起的电压降互相抵消，则此时， 该像素电路结构还可以补偿电源的 IR drop引起的像素电流波动的问题。
另外， 该像素电路引入第三电容 C3, 从而可以将 A点电位， 即驱动管 DTFT的栅极电位升高， 从而提供更大的驱动电流， 且由于栅极电压的增大， 使得驱动管 DTFT的响应速度也相应变快。 该第三电容 C3的电容值非常小， 为 10E-2pF量级， 占用的版图面积较小， 不影响整体的像素版图面积。
根据以上， 本发明具体实施例所述像素电路及其驱动方法， 不但能够对 驱动管进行 Vth均勾度的补偿，解决发光二极管发光亮度均勾性差的问题， 而 且能够解决补偿电源的 IR drop引起的像素波动问题， 同时也使得驱动管 DTFT的响应速度变快。
本发明实施例中提供的像素电路中的所有开关管和晶体管均为 P型薄膜 场效应管， 可选地， 所有开关管和晶体管也可以为 N型薄膜场效应管， 但是 第一电压信号端输出电压为 VDD, 第二电压信号端输出电压为 VSS, 有机发 光二极管的位置也要发生变化， 有机发光二极管的第一端与第二电压信号端 连接， 有机发光二极管的第二端连接第五开关管的源极， 所有开关管为高电 平导通， 所有控制信号端输出的电压信号作相应调整即可， 具体的工作原理 与上述类似， 不再赘述。
需要说明的是， 本发明中提到的开关管不限定为具有栅极、 源极和漏极 的薄膜场效应晶体管， 只要能起到与薄膜场效应晶体管功能相同的开关元件 都可以， 而且对于液晶显示领域的管来说， 漏极和源极没有明确的区别， 因 此本发明实施例中所提到的管的源极可以为管的漏极， 管的漏极也可以为管 的源极。 同时， 电容的第一端和第二端也没有明确的区分， 只是为了清楚的 描述电容的连接关系。
本发明另一方面还提供一种具有上述像素电路的显示装置， 该显示装置 所具备的像素电路如上详细描述， 在引不再赘述。
以上所述仅是本发明的优选实施方式， 应当指出， 对于本技术领域的普 通技术人员来说， 在不脱离本发明原理的前提下， 还可以做出若干改进和润 饰， 这些改进和润饰也应视为本发明的保护范围。

Claims

权 利 要 求 书
1. 一种像素电路， 包括：
发光器件， 所述发光器件的第一端连接第一电压信号端；
用于驱动所述发光器件的驱动管；
第一开关管， 所述第一开关管的源极与数据信号端连接， 所述第一开关 管的栅极与第一控制信号端连接；
第一电容， 所述第一电容的第一端与所述第一开关管的漏极连接； 第二电容， 所述第二电容的第一端与第二电压信号端连接， 所述第二电 容的第二端与所述第一电容的第二端连接；
第三电容， 所述第三电容的第一端与所述第一控制信号端连接， 所述第 三电容的第二端与所述驱动管的栅极连接；
第二开关管， 所述第二开关管的源极与所述驱动管的栅极连接， 所述第 二开关管的漏极与所述驱动管的漏极连接， 所述第二开关管的栅极与所述第 一控制信号端连接；
第三开关管， 所述第三开关管的源极分别与所述驱动管的栅极和所述第 一电容的第二端连接， 所述第三开关管的漏极与第二控制信号端连接， 所述 第三开关管的栅极与第三控制信号端连接；
第四开关管， 所述第四开关管的源极与所述驱动管的漏极连接， 所述第 四开关管的漏极与所述发光器件的第二端连接， 所述第四开关管的栅极与第 四控制信号端连接；
第五开关管， 所述第五开关管的源极与所述第二电压信号端连接， 所述 第五开关管的漏极与所述驱动管的源极连接， 所述第五开关管的栅极与所述 第四控制信号端连接； 以及
第六开关管， 所述第六开关管的栅极与所述第一控制信号端连接， 所述 第六开关管的源极与所述第二电容的第二端连接， 所述第六开关管的漏极与 所述第五开关管的漏极连接。
2. 如权利要求 1所述的像素电路，其中，所述驱动管、所述第一开关管、 所述第二开关管、 所述第三开关管、 所述第四开关管、 所述第五开关管和所 述第六开关管分别为 P型薄膜场效应管。
3. 如权利要求 2所述的像素电路，其中，所述第一电压信号端为低电平， 以及所述第二电压信号端为高电平。
4. 如权利要求 1所述的像素电路，其中，所述第二控制信号端接地连接。
5. 如权利要求 1所述的像素电路， 其中， 所述发光器件为有机发光二极 管。
6. 一种显示装置， 包括如权利要求 1至 5任一项所述的像素电路。
7. 一种如权利要求 1所述像素电路的驱动方法， 其中， 所述驱动方法包 括：
在第一阶段， 所述第三开关管导通， 所述第一开关管、 所述第二开关管 和所述第六开关管关断， 所述驱动管的栅极为所述第二控制信号端输出的电 压；
在第二阶段，所述第三开关管、所述第四开关管和所述第五开关管关断， 所述第一开关管、 所述第二开关管和所述第六开关管导通， 所述数据信号端 的输出电压传输至所述驱动管的栅极， 且所述驱动管的栅极与漏极导通， 所 述驱动管形成二极管连接状态； 以及
在第三阶段， 所述第一开关管、 所述第二开关管、 所述第三开关管和所 述第六开关管关断， 所述第四开关管和所述第五开关管导通， 所述驱动管的 栅极处的电压由所述第二电容保持， 所述驱动管处于饱和状态而导通， 所述 发光器件发光。
8. 如权利要求 6所述的驱动方法，其中，所述驱动管、所述第一开关管、 所述第二开关管、 所述第三开关管、 所述第四开关管、 所述第五开关管和所 述第六开关管分别为 P型薄膜场效应管。
9. 如权利要求 8所述的驱动方法，其中，所述第一电压信号端为低电平， 以及所述第二电压信号端为高电平。
10. 如权利要求 8所述的驱动方法， 其中， 在所述第一阶段， 所述第一 控制信号端和所述数据信号端分别输出高电平， 所述第三控制信号端和所述 第四控制信号端分别输出低电平； 在所述第二阶段， 所述第三控制信号端和 所述第四控制信号端分别输出高电平， 所述第一控制信号端和所述数据信号 端输出低电平； 以及在所述第三阶段， 所述第一控制信号端、 所述第三控制 信号端和所述数据信号端输出高电平， 所述第四控制信号端输出低电平。
11. 如权利要求 10所述的驱动方法， 其中， 所述第二控制信号端在所述 第一阶段、 所述第二阶段和所述第三阶段均接地连接。
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