WO2021012425A1 - 一种tft阵列基板、其制备方法及其显示面板 - Google Patents

一种tft阵列基板、其制备方法及其显示面板 Download PDF

Info

Publication number
WO2021012425A1
WO2021012425A1 PCT/CN2019/111900 CN2019111900W WO2021012425A1 WO 2021012425 A1 WO2021012425 A1 WO 2021012425A1 CN 2019111900 W CN2019111900 W CN 2019111900W WO 2021012425 A1 WO2021012425 A1 WO 2021012425A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
insertion portion
tft array
array substrate
insulating layer
Prior art date
Application number
PCT/CN2019/111900
Other languages
English (en)
French (fr)
Inventor
黄茜
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/624,789 priority Critical patent/US11398506B2/en
Publication of WO2021012425A1 publication Critical patent/WO2021012425A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate

Definitions

  • the present invention relates to the field of display technology, in particular, a TFT array substrate, a preparation method thereof and a display panel thereof.
  • the TFT array substrate is formed by stacking different functional layers to form electrical components with different functions, thereby realizing its design functions.
  • the bonding force between the surfaces of the two contacting functional layers is not necessarily strong.
  • PPN Planarization layer
  • ILD InterLayer Dielectric
  • the solution adopted by the industry is to add a through hole so that a part of the flat layer extends into the interlayer dielectric layer like a wedge structure, and even further extends into the functional layer below it.
  • the deep wedge structure enhances the bonding force between the two, which can improve the Peeling problem between the two to a certain extent.
  • One aspect of the present invention is to provide a TFT array substrate, which adopts a novel interlayer structure arrangement method, which effectively reduces the potential risk of separation between different layers, thereby improving the stability of the product.
  • a TFT array substrate includes a substrate layer.
  • a functional layer is provided on the substrate layer, and a flat layer is provided on the functional layer.
  • the flat layer includes a vertical insertion portion extending into the functional layer, and one side of the vertical insertion portion extends outwardly along the inner horizontal direction of the functional layer with a horizontal insertion portion.
  • the two sides of the vertical insertion portion respectively extend outwardly with a first horizontal insertion portion and a second horizontal insertion portion which are arranged oppositely.
  • the functional layer includes a metal layer and an insulating layer arranged in a stack, and the horizontal insertion portion is arranged in the insulating layer.
  • the insulating layer includes a first insulating layer and a second insulating layer provided thereon, and the horizontal insertion portion is provided in the first insulating layer.
  • the insulating layer includes a first insulating layer and a second insulating layer provided thereon, and the horizontal insertion portion is provided in the second insulating layer.
  • the insulating layer includes a first insulating layer and a second insulating layer disposed thereon, wherein the horizontal insertion portion includes a first horizontal insertion portion and a second horizontal insertion portion, wherein The first horizontal insertion portion is provided in the first insulating layer, and the second horizontal insertion portion is provided in the second insulating layer.
  • the functional layer further includes an interlayer dielectric layer
  • the flat layer is disposed on the interlayer dielectric layer
  • the horizontal insertion portion is disposed in the interlayer dielectric layer
  • the functional layer includes a metal layer, an insulating layer, and an interlayer dielectric layer arranged in a stack
  • the flat layer is arranged on the interlayer dielectric layer, and the horizontal insertion portion It is arranged in the insulating layer or the interlayer dielectric layer.
  • Another aspect of the present invention is to provide a method for preparing the TFT array substrate of the present invention, which includes the following steps:
  • Step S1 Provide a substrate layer and form a functional layer on it, wherein when forming the metal layer in the functional layer, in addition to the electrode layer, a reserved metal layer at a predetermined position is also reserved;
  • Step S2 performing pre-exposure and development of the flat layer on the functional layer, and forming a via hole extending into the functional layer, wherein the side portion of the via hole is in contact with the reserved metal layer;
  • Step S3 removing the reserved metal layer; then coating the flat layer and filling the via hole and the position where the reserved metal layer is removed, wherein after the filling is completed, the position of the via hole
  • the filling flat layer part of is the vertical insertion part, and the filling flat layer part at the position of the reserved metal layer is the horizontal insertion part connected with the side of the vertical insertion part.
  • Another aspect of the present invention is to provide a display panel, which uses the TFT array substrate of the present invention.
  • the present invention relates to a TFT array substrate, which is provided with a new horizontal insertion part configuration for the vertical insertion part of the flat layer, so that it does not only rely on a vertical wedge structure, but adds another
  • the horizontal wedge-shaped structure, through the combination of the two, makes the combination between the flat layer and the functional layer below it more tight, even in the case of bending, the problem of peeling between different layers is not easy to occur .
  • FIG. 1 is a schematic structural diagram of a TFT array substrate provided in an embodiment of the present invention.
  • FIG. 2 is a method for preparing a TFT array substrate provided in another embodiment of the present invention, a schematic diagram of the structure after step S1 is completed;
  • step S2 is completed
  • FIG. 4 is a schematic structural diagram of a TFT array substrate provided in another embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a TFT array substrate provided in another embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a TFT array substrate provided in another embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a TFT array substrate provided in another embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a TFT array substrate provided in another embodiment of the present invention.
  • an embodiment of the present invention provides a TFT array substrate, which includes a substrate layer 100.
  • a barrier layer (Barrier) 101, a buffer layer 102, a functional layer 110 and a flat layer 120 are sequentially arranged on the substrate layer 100.
  • the functional layer 110 is a general term for a multi-layer laminated structure, which usually includes a multi-layer laminated insulating layer, and these insulating layers are provided with a functional metal layer. In order to highlight the focus of this case, these laminated structures are temporarily referred to as It is the functional layer 110, and in the subsequent embodiments, the functional layer will be expounded and explained by way of example.
  • the flat layer 120 is not only provided with an inverted trapezoidal vertical insertion portion 121 that penetrates into the functional layer 110, but also on both sides of the vertical insertion portion 121.
  • a first horizontal insertion portion 122 and a second horizontal insertion portion 124 extending horizontally are respectively provided on the portions.
  • the horizontal insertion portion located on the left side of the vertical insertion portion 121 can be defined as the first horizontal insertion portion 122, and the horizontal insertion portion located on the right side thereof is the second horizontal insertion portion 124.
  • first horizontal insertion portion 122 and the second horizontal insertion portion 124 are both horizontal insertion portions that implement the same function, and there is no substantial functional difference between the two. The difference is only different in configuration.
  • the horizontal insertion part may be provided with only one, or the configuration of the first horizontal insertion part 122 and the second horizontal insertion part 124 are different, or the first horizontal insertion part 124
  • the inserting portion 122 and the second horizontal inserting portion 124 are not arranged in the same layer, etc.
  • the side ends of the horizontal insertion portions 122 and 124 are in a trapezoidal configuration with a certain inclination angle.
  • the side end of the horizontal insertion portion can also be in a zigzag configuration, a wave-curved configuration, etc., which can effectively increase the contact area between the side end and the surface of the functional layer.
  • the details can be determined as needed, and there is no limit.
  • Another embodiment of the present invention provides a method for preparing the TFT array substrate of the present invention, which includes the following steps.
  • Step S1 Provide a substrate layer 100, and form barrier layer 101, buffer layer 102, and functional layer 110 thereon.
  • barrier layer 101 When forming the metal layer in the functional layer, in addition to retaining the electrode layer, a predetermined position should be retained There are two reserved metal layers 103 and 104 arranged at intervals.
  • the completed structure is shown in Figure 2.
  • the detailed structure of the functional layer is still not shown. For the specific hierarchical structure that may be implemented, please refer to the subsequent description .
  • the reserved metal layers 103, 104 may not be arranged at intervals of the same layer as shown in FIG. 2, but may also be arranged at horizontal intervals of different layers, which can be specifically arranged as needed. There is no limit.
  • the exemplary embodiments involved please refer to the subsequent description.
  • Step S2 Perform pre-exposure and development of the planarization layer 120 on the functional layer 110, and etch the vias 130 extending into the functional layer by dry etching, wherein both sides of the vias 130 They are connected to the reserved metal layers 103 and 104 respectively. Please refer to FIG. 3 for the completed diagram.
  • Step S3 removing the reserved metal layers 103, 104 by wet etching, and coating the flat layer 120, and simultaneously removing the positions of the vias 130 and the reserved metal layers 103, 104 Fill the flat layer at the position, and the completed structure is the structure shown in Figure 1.
  • FIG. 4 illustrates the structure of a TFT array substrate provided by another embodiment of the present invention.
  • the functional layer 110 specifically includes a stacked active layer 111, a first gate layer 112, a first insulating layer 113, a second gate layer 114, a second insulating layer 115, and a source layer.
  • the drain layers 116 and 118 and the interlayer dielectric layer 117 are only an example description and is not limited.
  • the vertical insertion portion 121 provided on the flat layer 120 is in an inverted trapezoidal configuration, the bottom of which extends into the first insulating layer 113, and is respectively provided on the first side of the vertical insertion portion 121.
  • the horizontal insertion portion 122 and the second horizontal insertion portion 124 are disposed in the second insulating layer 115 in the same layer.
  • first horizontal insertion portion 122 and the second horizontal insertion portion 124 provided on both sides of the vertical insertion portion 121 may also be provided on the same layer. Intermediate layer 117.
  • first horizontal insertion portion 122 and the second horizontal insertion portion 124 are provided in each of the second insulating layer 115 and the interlayer dielectric layer 117.
  • FIG. 7 illustrates the structure of a TFT array substrate provided by another embodiment of the present invention.
  • first horizontal insertion portion 122 and the second horizontal insertion portion 124 are arranged in different layers and on different sides, that is, the two are arranged separately In the second insulating layer 115 and the interlayer dielectric layer 117 on different sides of the vertical insertion portion 121.
  • FIG. 8 illustrates the structure of a TFT array substrate provided by another embodiment of the present invention.
  • first horizontal insertion portion 122 and the second horizontal insertion portion 124 are arranged in different layers but on the same side, that is, they are located in the vertical In the second insulating layer 115 and the interlayer dielectric layer 117 on the same side of the insertion portion 121.
  • Another aspect of the present invention is to provide a display panel, which uses the TFT array substrate of the present invention.
  • the present invention relates to a TFT array substrate, which is provided with a new horizontal insertion part configuration for the vertical insertion part of the flat layer, so that it does not only rely on a vertical wedge structure, but adds another
  • the horizontal wedge-shaped structure, through the combination of the two, makes the combination between the flat layer and the functional layer below it more tight, even in the case of bending, it is not easy to cause peeling problems between different layers .

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种TFT阵列基板，其包括衬底层（100），所述衬底层（100）上设置有功能层（110），所述功能层（110）上设置有平坦层（120）。其中所述平坦层（120）包括伸入到所述功能层（110）内的竖直插入部（121），而所述竖直插入部（121）的一侧部向外沿所述功能层（110）的内部水平向延伸出有水平插入部（122，124）。采用新型的层间结构设置方式，有效的降低了不同层间存在的潜在相互脱离风险，进而提高了产品的稳定性。

Description

一种TFT阵列基板、其制备方法及其显示面板 技术领域
本发明涉及显示技术领域，尤其是，其中涉及的一种TFT阵列基板、其制备方法及其显示面板。
 背景技术
已知，TFT阵列基板是通过层叠设置不同的功能层，来构成不同功能的电器元件，进而实现其设计功能的。
而不同的功能层之间由于采用的材料不同，且相接触的表面之间均为平面接触，如此就会使得两相接触的功能层表面之间的结合力并不一定很强。例如，功能层中包括的常见的平坦层（PLN，Planarizationlayer）和层间介质层（ILD，InterLayer Dielectric）之间，两者之间由于是平面表面接触，使得两者接触面间的附着力就不是很强，两者之间存在一定的潜在相互脱离的风险，也就是业界通常所说的Peeling问题。
对此，业界采用的解决方案是增加一个通孔，使得所述平坦层的一部分如楔形结构一样，伸入到所述层间介质层内，甚至在进一步的伸入到其下方的功能层中的绝缘层内。如此，通过其深入的楔形结构使得两者间的结合力增强，从而可在一定程度上改善两者之间的Peeling问题。
但是，当所述TFT阵列基板需要进行弯折时，由于其弯折的状态，明显会使得不同层间的脱离风险显著上升，而上述增加的楔形插入结构并不能很好的解决这种问题，反而存在因为弯折，而使得所述楔形结构更容易的从所述通孔中抽出的问题。
进一步的，当不同功能层间的剥离现象发生时，表现出的最明显的问题，就是显示屏显示异常问题，这也就导致了产品的稳定性出现问题。因此，确有必要来开发一种新型的TFT阵列基板，来克服现有技术中的缺陷。
 技术问题
本发明的一个方面是提供一种TFT阵列基板，其采用新型的层间结构设置方式，有效的降低了不同层间存在的潜在相互脱离风险，进而提高了产品的稳定性。
 技术解决方案
本发明采用的技术方案如下：
一种TFT阵列基板，包括衬底层。所述衬底层上设置有功能层，所述功能层上设置有平坦层。其中所述平坦层包括伸入到所述功能层内的竖直插入部，而所述竖直插入部的一侧部向外沿所述功能层的内部水平向延伸出有水平插入部。
进一步的，在不同实施方式中，其中所述竖直插入部的两侧部分别向外延伸出有相对设置的第一水平插入部和第二水平插入部。
进一步的，在不同实施方式中，其中所述功能层包括层叠设置的金属层和绝缘层，其中所述水平插入部是设置在所述绝缘层中。
进一步的，在不同实施方式中，其中所述绝缘层包括第一绝缘层和其上设置的第二绝缘层，其中所述水平插入部设置在所述第一绝缘层中。
进一步的，在不同实施方式中，其中所述绝缘层包括第一绝缘层和其上设置的第二绝缘层，其中所述水平插入部设置在所述第二绝缘层中。
进一步的，在不同实施方式中，其中所述绝缘层包括第一绝缘层和其上设置的第二绝缘层，其中所述水平插入部包括第一水平插入部和第二水平插入部，其中所述第一水平插入部设置在所述第一绝缘层中，所述第二水平插入部设置在所述第二绝缘层中。
进一步的，在不同实施方式中，其中所述功能层还包括层间介质层，所述平坦层设置在所述层间介质层上，其中所述水平插入部设置在所述层间介质层中。
进一步的，在不同实施方式中，其中所述功能层包括层叠设置的金属层、绝缘层和层间介质层，其中所述平坦层设置在所述层间介质层上，其中所述水平插入部设置在所述绝缘层或层间介质层中。
本发明的又一方面是提供一种本发明涉及的所述TFT阵列基板的制备方法，其包括以下步骤：
步骤S1、提供一衬底层，并于其上形成功能层，其中在形成所述功能层中的金属层时，除了保留电极层外，还要保留一预定位置处的预留金属层；
步骤S2、于所述功能层上进行平坦层的前曝光显影，以及形成伸入到所述功能层内的过孔，其中所述过孔的侧部与所述预留金属层相接；
步骤S3、去除所述预留金属层；然后进行所述平坦层的涂布以及对所述过孔和去除了所述预留金属层位置的填充，其中填充完成后，所述过孔位置处的填充平坦层部为所述竖直插入部，而所述预留金属层位置处的填充平坦层部则为与所述竖直插入部的侧部相接的所述水平插入部。
进一步的，本发明的又一方面是提供一种显示面板，其采用的TFT阵列基板为本发明涉及的所述TFT阵列基板。
 有益效果
本发明涉及的一种TFT阵列基板，其通过对所述平坦层的竖直插入部设置新型的水平插入部构型，使得其不是仅仅依靠一个竖直向的楔形结构，而是又增加了一个水平向的楔形结构，通过两者间的结合，使得所述平坦层和其下方设置的功能层之间的结合更为紧密，即使在弯折的情况下，也不易发生不同层间的peeling问题。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明的一个实施方式中提供的一种TFT阵列基板的结构示意图；
图2为本发明的又一个实施方式中提供的一种TFT阵列基板的制备方法，其步骤S1完成后的结构示意图；
图3为图2所述的TFT阵列基板制备方法，其步骤S2完成后的结构示意图；
图4为本发明的又一个实施方式中提供的一种TFT阵列基板的结构示意图；
图5为本发明的又一个实施方式中提供的一种TFT阵列基板的结构示意图；
图6为本发明的又一个实施方式中提供的一种TFT阵列基板的结构示意图；
图7为本发明的又一个实施方式中提供的一种TFT阵列基板的结构示意图；
图8为本发明的又一个实施方式中提供的一种TFT阵列基板的结构示意图。
 本发明的实施方式
以下将结合附图和实施例，对本发明涉及的一种TFT阵列基板、其制备方法及其显示面板的技术方案作进一步的详细描述。
请参阅图1所示，本发明的一个实施方式提供了一种TFT阵列基板，其包括衬底层100。
所述衬底层100上依次设置有障碍层（Barrier）101、缓冲层102、功能层110和平坦层120。其中所述功能层110为多层层叠结构的统称，其内通常包括多层层叠设置的绝缘层，这些绝缘层内设置有功能金属层，而为了突出本案的重点，暂时将这些叠层结构统称为功能层110，而在后续的实施方式中，将会对所述功能层进行举例式的展开说明。
进一步的，如图1中所示，所述平坦层120除了设置向下深入所述功能层110内的倒梯形的竖直插入部121外，还会在所述竖直插入部121的两侧部上分别设置有水平延伸出的第一水平插入部122和第二水平插入部124。
其中为方便区别以及清楚说明，可将位于所述竖直插入部121左侧的水平插入部定义为第一水平插入部122，而位于其右侧的水平插入部为第二水平插入部124，但此仅为描述方便，而非限定，所述第一水平插入部122和所述第二水平插入部124均为实施相同功能的水平插入部，两者并无实质上的功能区别，若有区别，也只是在构型上有所不同。
在其他不同实施方式中，其中所述水平插入部可以是只设置一个，或者是，所述第一水平插入部122和第二水平插入部124的构型不同，或者是，所述第一水平插入部122和第二水平插入部124不是同层设置等等，具体不同实施方式，可参见后续说明。
进一步的，为保证配接的效果，其中所述水平插入部122、124的侧端部为具有一定倾角的梯形构型。而在其他实施方式中，其中所述水平插入部的侧端部也可以是锯齿状构型、波浪曲线构型等等能有效增加所述侧端部与其相接功能层表面接触面积的构型，具体可随需要而定，并无限定。
进一步的，本发明的又一个实施方式是提供一种本发明涉及的所述TFT阵列基板的制备方法，包括有以下步骤。
步骤S1、提供一衬底层100，并于其上形成障碍层101、缓冲层102以及功能层110，其中在形成所述功能层中的金属层时，除了保留电极层外，还要保留预定位置的两间隔设置的预留金属层103、104，其中完成后的结构如图2所示，其中所述功能层依旧未图示出具体的细节结构，其可能实施的具体层级结构可参阅后续说明。
另外，在其他不同实施方式中，所述预留金属层103、104可以不是如图2中所示的同层间隔设置，其也可以是不同层的水平相互间隔设置方式，具体可随需要而定，并无限定。另外，其中涉及的举例式的实施方式，可参看后续说明。
步骤S2、于所述功能层110上进行平坦层120的前曝光显影，以及通过干刻的方式刻蚀伸入到所述功能层内的过孔130，其中所述过孔130的两侧部分别与所述预留金属层103、104相接，完成后的图示请参阅图3所示。
步骤S3、通过湿刻法去除所述预留金属层103、104，以及进行所述平坦层120的涂布，以及同时对所述过孔130和去除了所述预留金属层103、104位置处的平坦层部填充，完成后的结构即为图1所示的结构。
进一步的，以下将结合附图对上述实施方式中涉及的所述功能层110进行举例式的展开细节结构的描述，同时对于所述平坦层120的水平延伸部，也会给出多个实施结构。
请参阅图4所示，其图示了本发明涉及的又一个实施方式提供的一种TFT阵列基板的结构。
如图4中所示，其中所述功能层110具体包括层叠设置的有源层111、第一栅极层112、第一绝缘层113、第二栅极层114、第二绝缘层115、源漏极层116、118以及层间介质层117。需要明确的是，这一功能层110的细节描述仅为举例式描述，并不限于。
其中所述平坦层120设置的竖直插入部121呈倒梯形构型，其底部伸入到所述第一绝缘层113中，而分别设置在所述竖直插入部121两侧部的第一水平插入部122和第二水平插入部124则是同层设置在所述第二绝缘层115中。
进一步的，在其他不同实施方式中，其中所述设置在所述竖直插入部121两侧部的第一水平插入部122和第二水平插入部124，也可以是同层设置在所述层间介质层117中。或者是在所述第二绝缘层115以及层间介质层117中的每一层内均设置有所述第一水平插入部122和第二水平插入部124，具体结构图示，可分别参阅图5、6所示。
进一步的，请参阅图7所示，其图示了本发明涉及的又一个实施方式提供的一种TFT阵列基板的结构。
其中与图4、5及6所示的实施方式不同之处在于，所述第一水平插入部122和所述第二水平插入部124采用了不同层且不同侧的设置方式，即两者分别位于所述竖直插入部121不同侧的所述第二绝缘层115和层间介质层117中。
进一步的，请参阅图8所示，其图示了本发明涉及的又一个实施方式提供的一种TFT阵列基板的结构。
其中与图7所示实施方式不同之处在于，所述第一水平插入部122和所述第二水平插入部124采用了不同层但同侧的设置方式，即两者分别位于所述竖直插入部121的同一侧的所述第二绝缘层115和层间介质层117中。
进一步的，本发明的又一方面是提供一种显示面板，其采用的TFT阵列基板为本发明涉及的所述TFT阵列基板。
本发明涉及的一种TFT阵列基板，其通过对所述平坦层的竖直插入部设置新型的水平插入部构型，使得其不是仅仅依靠一个竖直向的楔形结构，而是又增加了一个水平向的楔形结构，通过两者间的结合，使得所述平坦层和其下方设置的功能层之间的结合更为紧密，即使在弯折的情况下，也不易在不同层间发生peeling问题。
本发明的技术范围不仅仅局限于上述说明中的内容，本领域技术人员可以在不脱离本发明技术思想的前提下，对上述实施例进行多种变形和修改，而这些变形和修改均应当属于本发明的范围内。

Claims (10)

  1. 一种TFT阵列基板，包括衬底层；其中所述衬底层上设置有功能层，所述功能层上设置有平坦层；
    其中所述平坦层包括伸入到所述功能层内的竖直插入部，其中所述竖直插入部的一侧部向外沿所述功能层的内部水平向延伸出有水平插入部。
  2. 根据权利要求1所述的TFT阵列基板，其中所述竖直插入部的两侧部分别向外延伸出有相对设置的第一水平插入部和第二水平插入部。
  3. 根据权利要求1所述的TFT阵列基板，其中所述功能层包括层叠设置的金属层和绝缘层，其中所述水平插入部是设置在所述绝缘层中。
  4. 根据权利要求3所述的TFT阵列基板，其中所述绝缘层包括第一绝缘层和其上设置的第二绝缘层，其中所述水平插入部设置在所述第一绝缘层中。
  5. 根据权利要求3所述的TFT阵列基板，其中所述绝缘层包括第一绝缘层和其上设置的第二绝缘层，其中所述水平插入部设置在所述第二绝缘层中。
  6. 根据权利要求3所述的TFT阵列基板，其中所述绝缘层包括第一绝缘层和其上设置的第二绝缘层，其中所述水平插入部包括第一水平插入部和第二水平插入部，其中所述第一水平插入部设置在所述第一绝缘层中，所述第二水平插入部设置在所述第二绝缘层中。
  7. 根据权利要求1所述的TFT阵列基板，其中所述功能层还包括层间介质层，所述平坦层设置在所述层间介质层上，其中所述水平插入部设置在所述层间介质层中。
  8. 根据权利要求1所述的TFT阵列基板，其中所述功能层包括层叠设置的金属层、绝缘层和层间介质层，其中所述平坦层设置在所述层间介质层上，其中所述水平插入部设置在所述绝缘层或层间介质层中。
  9. 一种制备根据权利要求1所述TFT阵列基板的制备方法，包括以下步骤：
    步骤S1、提供一衬底层，并于其上形成功能层，其中在形成所述功能层中的金属层时，除了保留电极层外，还要保留一预定位置处的预留金属层；
    步骤S2、于所述功能层上进行平坦层的前曝光显影，以及形成伸入到所述功能层内的过孔，其中所述过孔的侧部与所述预留金属层相接；
    步骤S3、去除所述预留金属层；然后进行所述平坦层的涂布以及对所述过孔和去除了所述预留金属层位置的填充，其中填充完成后，所述过孔位置处的填充平坦层部为所述竖直插入部，而所述预留金属层位置处的填充平坦层部则为与所述竖直插入部的侧部相接的所述水平插入部。
  10. 一种显示面板，包括根据权利要求1所述的TFT阵列基板。
PCT/CN2019/111900 2019-07-23 2019-10-18 一种tft阵列基板、其制备方法及其显示面板 WO2021012425A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/624,789 US11398506B2 (en) 2019-07-23 2019-10-18 TFT array substrate, fabricating method thereof, and display panel thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910663797.6 2019-07-23
CN201910663797.6A CN110391255B (zh) 2019-07-23 2019-07-23 一种tft阵列基板、其制备方法及其显示面板

Publications (1)

Publication Number Publication Date
WO2021012425A1 true WO2021012425A1 (zh) 2021-01-28

Family

ID=68286955

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/111900 WO2021012425A1 (zh) 2019-07-23 2019-10-18 一种tft阵列基板、其制备方法及其显示面板

Country Status (3)

Country Link
US (1) US11398506B2 (zh)
CN (1) CN110391255B (zh)
WO (1) WO2021012425A1 (zh)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN206773356U (zh) * 2017-05-19 2017-12-19 厦门天马微电子有限公司 一种显示面板
CN107658333A (zh) * 2017-10-31 2018-02-02 京东方科技集团股份有限公司 一种柔性显示面板及其制造方法、柔性显示装置
CN107706224A (zh) * 2017-09-30 2018-02-16 武汉华星光电技术有限公司 一种显示面板及其制作方法
CN108231839A (zh) * 2017-12-27 2018-06-29 武汉华星光电半导体显示技术有限公司 柔性显示面板的弯折区结构及其制作方法
CN108550612A (zh) * 2018-05-29 2018-09-18 武汉华星光电半导体显示技术有限公司 显示面板及其制作方法
CN109065583A (zh) * 2018-08-06 2018-12-21 武汉华星光电半导体显示技术有限公司 柔性显示面板的制造方法及柔性显示面板
CN109065616A (zh) * 2018-08-06 2018-12-21 武汉华星光电半导体显示技术有限公司 柔性显示面板及制造方法
CN109166862A (zh) * 2018-07-25 2019-01-08 武汉华星光电半导体显示技术有限公司 柔性oled显示面板及其制备方法
US10236316B2 (en) * 2010-08-17 2019-03-19 Sony Corporation Display device with separation member including steps

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10236316B2 (en) * 2010-08-17 2019-03-19 Sony Corporation Display device with separation member including steps
CN206773356U (zh) * 2017-05-19 2017-12-19 厦门天马微电子有限公司 一种显示面板
CN107706224A (zh) * 2017-09-30 2018-02-16 武汉华星光电技术有限公司 一种显示面板及其制作方法
CN107658333A (zh) * 2017-10-31 2018-02-02 京东方科技集团股份有限公司 一种柔性显示面板及其制造方法、柔性显示装置
CN108231839A (zh) * 2017-12-27 2018-06-29 武汉华星光电半导体显示技术有限公司 柔性显示面板的弯折区结构及其制作方法
CN108550612A (zh) * 2018-05-29 2018-09-18 武汉华星光电半导体显示技术有限公司 显示面板及其制作方法
CN109166862A (zh) * 2018-07-25 2019-01-08 武汉华星光电半导体显示技术有限公司 柔性oled显示面板及其制备方法
CN109065583A (zh) * 2018-08-06 2018-12-21 武汉华星光电半导体显示技术有限公司 柔性显示面板的制造方法及柔性显示面板
CN109065616A (zh) * 2018-08-06 2018-12-21 武汉华星光电半导体显示技术有限公司 柔性显示面板及制造方法

Also Published As

Publication number Publication date
CN110391255B (zh) 2021-04-02
US20210366951A1 (en) 2021-11-25
CN110391255A (zh) 2019-10-29
US11398506B2 (en) 2022-07-26

Similar Documents

Publication Publication Date Title
KR20140018546A (ko) 반도체 장치 및 그 제조 방법
WO2021017243A1 (zh) 显示面板母板和显示面板母板的制备方法
WO2020173053A1 (zh) 阵列基板、其制备方法及显示屏
JP2005135988A (ja) 半導体装置の製造方法
JP2003142687A (ja) 半導体素子の製造方法及び半導体素子
JP2017152178A (ja) 表示装置の製造方法、及び、表示装置
WO2021012425A1 (zh) 一种tft阵列基板、其制备方法及其显示面板
CN101378035A (zh) 半导体装置的制造方法
JPH063804B2 (ja) 半導体装置製造方法
TW202021045A (zh) 半導體結構及其製備方法
WO2020047882A1 (zh) 一种阵列基板及其制备方法、显示面板
TWI489171B (zh) 畫素陣列基板、顯示面板、接觸窗結構及其製造方法
JPH01248537A (ja) 半導体集積回路
JP2757665B2 (ja) 半導体装置
CN113161372B (zh) 半导体器件及其制备方法、阵列基板
TWI425594B (zh) 製作埋入式金屬線之溝渠的方法
US20200111737A1 (en) Chip package
KR20020078885A (ko) 반도체 소자의 비어콘택 형성방법
JPS63161645A (ja) 半導体装置の製造方法
CN105633011A (zh) 互连结构的制作方法
KR101129862B1 (ko) 반도체 소자 및 그 제조 방법
WO2022233069A1 (zh) 阵列基板及显示面板
JP2001144178A (ja) 半導体装置の製造方法
JPH03125469A (ja) Ｍｉｍキャパシタの構造
JPH06236928A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19938820

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19938820

Country of ref document: EP

Kind code of ref document: A1