WO2020233319A1 - 基于系统封装技术的工艺设计方法、系统、介质及设备 - Google Patents

基于系统封装技术的工艺设计方法、系统、介质及设备 Download PDF

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WO2020233319A1
WO2020233319A1 PCT/CN2020/085999 CN2020085999W WO2020233319A1 WO 2020233319 A1 WO2020233319 A1 WO 2020233319A1 CN 2020085999 W CN2020085999 W CN 2020085999W WO 2020233319 A1 WO2020233319 A1 WO 2020233319A1
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design
data
model
packaging technology
manufacturing
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PCT/CN2020/085999
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English (en)
French (fr)
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钱胜杰
武纪宏
刘继硕
刘丰收
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上海望友信息科技有限公司
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Priority to EP20810778.9A priority Critical patent/EP3951632A4/en
Priority to KR1020217041099A priority patent/KR20220003623A/ko
Priority to US17/611,546 priority patent/US20220261525A1/en
Priority to JP2021568681A priority patent/JP7284962B2/ja
Publication of WO2020233319A1 publication Critical patent/WO2020233319A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/20—Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2113/00—Details relating to the application field
    • G06F2113/18—Chip packaging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2113/00—Details relating to the application field
    • G06F2113/20—Packaging, e.g. boxes or containers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability

Definitions

  • the present invention belongs to the technical field of system packaging, and relates to a design method of system packaging technology, in particular to a process design method, system, medium and equipment based on system packaging technology.
  • Packaging is the post-processing process of electronic products.
  • Traditional packaging mainly completes three major functions: one is to protect the core electronic functions to avoid external influence or damage; the other is to interconnect the electronic functions with the outside world to realize electronic devices The third is the compatibility of physical dimensions. Because the size of the bare chip is too small relative to the board-level connection circuit, it needs to be packaged to achieve external connections. With the emergence of integrated circuits, especially the emergence of very large-scale integrated circuits, the requirements for electronic devices have become higher and higher.
  • SIP System-in-package technology
  • the purpose of the present invention is to provide a process design method, system, medium and equipment based on system packaging technology to solve the problem that the prior art cannot avoid more repetitive work, and the manufacturing process A cumbersome and error-prone problem.
  • the process design method based on system packaging technology includes: obtaining design data of a layout and the data associated with the layout. Three-dimensional model data; associate and match the design data and the three-dimensional model data according to the design element attribute information in the design data, and assemble the design data and the three-dimensional model data into an overall package model;
  • the assembly process analysis of the package model is performed to analyze unreasonable design points used as design modification and reference.
  • the assembly process analysis is to perform design specifications and system performance testing of the overall package model; or directly from the overall
  • a packaging process manufacturing program for manufacturing is derived from the packaging model.
  • the step of associating and matching the design data and the three-dimensional model data according to the design element attribute information in the design data includes: extracting the design element attribute from the design data Information; wherein, the design component attribute information includes component supplier material code, bare chip supplier material code and/or component package size information, and the design data includes: the component, bare chip and/or frame Supplier’s material code, package size information, bonding wire information and/or three-dimensional coordinate information; a three-dimensional model of components and bare chips with the same material code in the design data is retrieved from a solid model library, and based on The retrieved three-dimensional model extracts relevant three-dimensional data and working parameters; using the material code information of the components and bare chips as the connection relationship, the component supplier material code, the bare chip supplier material code and the metaframe package of the design data are packaged The three-dimensional data and working parameters of components and bare chips with the same size information as the material codes in the entity model library are matched to the overall data of the same model.
  • the working parameters include: mass, material and/or specific heat capacity.
  • the step of performing assembly process analysis on the overall package model to analyze unreasonable design points for design modification and reference includes: performing analysis on the substrate in the overall package model Information detection; or bond wire analysis of the overall package model according to the bonding wire process manufacturing rules; or assembly analysis of each design element in the overall package model; or according to the bare chip/chip manufacturing process rules Perform process analysis on the overall package model.
  • the detection of substrate information in the overall package model includes detection of devices, pads, traces, vias, and/or copper on the substrate.
  • the assembly analysis of the components in the overall package model refers to the simulation of the overall package model.
  • the step of directly deriving a packaging process manufacturing program for manufacturing from the overall packaging model includes: converting the bonding wire information in the design data according to a predetermined bonding machine Rule to generate a bonding machine program, the bonding machine program is a program executed by the bonding machine in the manufacturing process; or according to the information of the bare chip and the components to be mounted in the design data according to the predetermined placement
  • the machine rules generate a placement machine program, which is a program executed by the placement machine in the manufacturing process.
  • the process design system based on system packaging technology includes: an acquisition module for acquiring design data of a layout and three-dimensional model data associated with the layout Model generation module for associating and matching the design data and the three-dimensional model data according to the design element attribute information in the design data, and assemble the design data and three-dimensional model data into an overall package model; production
  • the analysis module is used to analyze the assembly process of the overall package model to analyze unreasonable design points used as design modification and reference; or directly derive a packaging process for manufacturing from the overall package model Manufacturing process.
  • Another aspect of the present invention provides a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, the process design method based on the system packaging technology is realized.
  • the last aspect of the present invention provides a device including: a processor and a memory; the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the device executes the Process design method of system packaging technology.
  • the process design method, system, medium and equipment based on the system packaging technology of the present invention have the following beneficial effects: Compared with the current traditional simulation production process, the present invention can eliminate a lot of repetitive work and replace it with automation. Compared with the original method, it saves 60%-80% of the time; at the same time, it reduces the difficulty of the work and simplifies the process from design to simulation and manufacturing.
  • the design data is assembled and manufactured & process virtual analysis is performed to make the problem in manufacturing The previous exposure reduces the manufacturing risk. The production cost is reduced, and the competitiveness of electronic products is greatly improved.
  • FIG. 1A shows the principle flow chart of the process design method based on system packaging technology in an embodiment of the present invention.
  • FIG. 1B shows a schematic flow diagram of the process design method based on the system packaging technology in an embodiment of the present invention.
  • FIG. 2 shows a schematic structural diagram of a process design system based on system packaging technology in an embodiment of the present invention.
  • FIG. 3 shows a device connection diagram in an embodiment of the process design method based on the system packaging technology of the present invention.
  • FIG. 4 shows a bare chip model diagram in an embodiment of the process design method based on system packaging technology of the present invention.
  • FIG. 5 shows a substrate analysis diagram in an embodiment of the process design method based on the system packaging technology of the present invention.
  • FIG. 6 shows a model diagram of a bonding wire in an embodiment of the process design method based on the system packaging technology of the present invention.
  • FIG. 7 shows a chip assembly model diagram in an embodiment of the process design method based on the system packaging technology of the present invention.
  • Fig. 8 is a diagram of the overall package model in an embodiment of the process design method based on the system package technology of the present invention.
  • the technical principles of the process design method, system, medium and equipment based on the system packaging technology of the present invention are as follows: obtain the design data of a layout and the three-dimensional model data associated with the layout; combine the design data with the three-dimensional model The data is correlated and matched according to the design element attribute information in the design data, and the design data and the three-dimensional model data are assembled into an overall package model; the overall package model is analyzed on the assembly process to analyze the design data Modify and refer to unreasonable design points; or directly derive a packaging process manufacturing program for production from the overall packaging model.
  • This embodiment provides a process design method based on system packaging technology.
  • the process design method based on system packaging technology includes:
  • a packaging process manufacturing program for manufacturing is directly derived from the overall packaging model.
  • FIG. 1A shows the principle flow chart of the process design method based on the system packaging technology in an embodiment of the present invention.
  • the process design method based on system packaging technology specifically includes the following steps:
  • S11 Acquire design data of a layout and three-dimensional model data associated with the layout.
  • the system packaging technology refers to the SIP packaging form of semiconductor devices.
  • SIP packaging integrates chips with multiple functions, including processors, memories, etc., into one package to achieve a basic Complete function; from the technological point of view, it is to put the bare chips (DIE, core or seed core, die) and components with certain functions into a frame that is suitable for the layout according to the layout design.
  • DIE bare chips
  • bonding wires are required for electrical interconnection.
  • the bare chip model is shown in FIG. 4, which shows the process design based on the system packaging technology of the present invention.
  • the design data in the layout design software is read into the memory.
  • the design data includes BOM data, such as Cadence SIP design data ".sip" file.
  • the layout design software includes Cadence SIP design software. In the process of designing the layout, the used components and design elements such as bare chips and frames have corresponding BOM data and other design data.
  • the three-dimensional model data of the bare chip is obtained in the bare chip library for storing the three-dimensional model data of the bare chip and the positional relationship of the pads, and the three-dimensional model data of the bare chip is named after the material code of the bare chip supplier;
  • the three-dimensional model data of the frame is named after the package type and size; it is used to store the three-dimensional model data and actual working parameter data of the components.
  • the three-dimensional model data of the component is obtained from the component library (quality, material, power consumption, etc.), and the three-dimensional model data of the component is named after the supplier's material code.
  • S12 Associate and match the design data and the three-dimensional model data according to the design element attribute information in the design data, and assemble the design data and the three-dimensional model data into an overall package model.
  • the supplier material code of the component in the design data the supplier material code of the bare chip, and the package size information are matched with the bare chip & frame library, and the component 3D entity model library, thereby combining the design data
  • the three-dimensional coordinate information and the three-dimensional model data generate an overall package model.
  • the S12 includes:
  • the design component attribute information includes component supplier material code, bare chip supplier material code, and meta-frame package size information and/or component name.
  • the design data includes: supplier material codes of the components, bare chips, and/or frames, package size information, bonding wire information, and/or three-dimensional coordinate information.
  • the component A, bare chip B, resistor C, and capacitor D are arranged at specific positions on the substrate according to their realized functions and routing rules, and the wiring design is performed.
  • the substrate also needs to be installed In a frame E for overall packaging.
  • the material code of component A is FU6008, FU6008 needs to be extracted from the design data; if the material code of bare chip B is QFP579Z, then QFP579Z needs to be extracted from the design data; if the material code of resistor C is RX080522K, RX080522K needs to be extracted from the design data; if the material code of capacitor D is CX060247U, then CX060247U needs to be extracted from the design data.
  • the package size information of the frame E needs to be extracted.
  • the package size information of the frame E includes the length, width, and height of the outer edge, the length, width, and height of the inner edge, the chamfer size, and the thickness information.
  • S122 retrieve three-dimensional models of components and bare chips with the same material codes in the design data from a solid model library, and extract relevant three-dimensional data and working parameters according to the retrieved three-dimensional models.
  • the physical model library prestores related devices for substrate design, including three-dimensional models of component A, bare chip B, resistor C, capacitor D, and frame E.
  • the three-dimensional model includes three-dimensional size information of the device.
  • working parameters and other device performance information the working parameters include: quality, material and/or specific heat capacity.
  • S123 Use the material code information of the components and bare chips as the connection relationship, and combine the component supplier material code, bare chip supplier material code, and meta-frame package size information of the design data with the material code in the entity model library The three-dimensional data and working parameters of the same components and bare chips are matched to the overall data of the same model.
  • the material codes FU6008, QFP579Z, RX080522K, CX060247U, and the two-dimensional coordinate information of the frame E on the substrate are retrieved from the design data, and component A, bare chip B, resistor C, The coordinate information of the capacitor D and the frame E on the substrate; the material codes of FU6008, QFP579Z, RX080522K, CX060247U and the frame E are also retrieved in the physical model library, and the components A, bare chip B,
  • the complete three-dimensional model data of the resistance C, the capacitance D and the frame E, and the extracted three-dimensional model data includes the device performance information such as the three-dimensional size information and working parameters of the device.
  • the overall data includes device parameter information used by the substrate, position information on the substrate, and three-dimensional data information and working parameter information carried when the solid model library is imported into the three-dimensional model.
  • the unreasonable design is fed back to the designer for modification, and the overall package model is regenerated after the modification is completed.
  • the regenerated overall package model is used to export the packaging process manufacturing procedure.
  • the assembly process analysis is not performed or there is no unreasonable point after the analysis, the overall package model is directly exported Packaging process manufacturing procedures.
  • the overall package model is not only a three-dimensional model, but also carries the working performance parameters of all involved devices, such as the overall data of the same model device described in S123.
  • FIG. 1B shows a schematic flow diagram of a process design method based on system packaging technology in an embodiment of the present invention.
  • the S13 includes:
  • the detection of the substrate information in the overall package model includes detection of the components, pads, traces, vias and/or copper laying of the substrate.
  • FIG. 5 shows a substrate analysis diagram in an embodiment of the process design method based on the system packaging technology of the present invention.
  • the substrate inspection in FIG. 5 includes whether the distance a between the pad and the component meets the safety design specification, the safety design specification is a safety threshold, and if the distance a is less than the safety threshold, the design problem is reported as an error.
  • the distance b between the via 1 and the pad, the distance between the trace and the via 2 and the distance between the vias in the substrate can be calculated through the coordinate information of the components, vias, pads, and traces on the substrate. Whether the distance and the aperture size of the via meet the processing requirements.
  • the bonding wire analysis is performed on the overall package model according to the bonding wire manufacturing rules.
  • the system packaging technology is a bonding wire packaging technology, and the bonding technology includes thermal compression welding and thermal ultrasonic welding. Therefore, please refer to FIG. 6, which shows a bonding wire model diagram in an embodiment of the process design method based on the system packaging technology of the present invention.
  • the bonding wire is used to make electrical connections between the pins of the mounted component and the pins of the bare chip.
  • the bonding wire analysis is based on whether the length of the bonding wire is appropriate, the diameter of the bonding wire, and the Whether the direction of the bonding wire is reasonable, whether the bonding wire is firmly fixed, and whether the distance between the bonding wire and the bonding wire meets the safety requirements, etc., the bonding wire process manufacturing rules are subject to regular inspection.
  • the overall package model is a whole composed of various components, substrates, bare chips and frames.
  • Figures 7 and 8 respectively show the process design method based on the system packaging technology of the present invention.
  • the chip assembly model diagram in the embodiment and the diagram shown are the overall package model diagram of the process design method based on the system packaging technology in an embodiment of the present invention.
  • the overall assembly analysis of the components in the package model refers to the simulation of the overall package model.
  • the simulation method includes finite element analysis.
  • the finite element analysis performs electromagnetic, thermal, structural and other simulation tests.
  • the analysis methods include: UG, ANSYS and/or Flotherm.
  • Process analysis is performed on the overall package model according to the die/chip manufacturing process rules.
  • design problems will arise due to each process flow. For example, whether the thinning of the wafer is of appropriate thickness, whether the cutting of the wafer causes edge damage, whether the soft solder is completely fixed when the chip is bonded, whether there is splashing to other positions, whether the amount and position of the polymer adhesive are appropriate, and whether the bare chip has Shift, whether the components are soldered, whether the components are correctly placed according to the model, and whether the components are damaged.
  • the process analysis checks the results one by one and feeds back the output report to the designer.
  • the bonding wire information in the design data is generated according to a predetermined bonding machine rule, and the predetermined bonding machine rule is based on the bonding wire position of the substrate design and the bonding wire of the overall package model
  • the direction, start and end points generate execution instructions for each bonding wire, the execution instructions can realize that each bond wire is fixed between the components according to the designed coordinates and start and end points, and the execution instructions of all bonding wires are combined to generate
  • the bonding machine program is the program executed by the bonding machine in the manufacturing process; or
  • a placement machine program is generated according to the predetermined placement machine rules, and the predetermined placement machine rules are based on the BOM table, coordinate file and Gerber substrate of the design file
  • the image generates an execution instruction corresponding to the model and position of each device.
  • each device can be welded and fixed on the coordinate position of the substrate design.
  • the execution instructions of all devices are combined to generate the placement machine program, which is The program executed by the placement machine in the manufacturing process.
  • This embodiment provides a computer storage medium on which a computer program is stored, and when the computer program is executed by a processor, the process design method based on the system packaging technology is implemented.
  • a person of ordinary skill in the art can understand that all or part of the steps in the foregoing method embodiments can be implemented by hardware related to a computer program.
  • the aforementioned computer program can be stored in a computer-readable storage computer storage medium.
  • the steps including the foregoing method embodiments are executed; and the foregoing storage computer storage medium includes: ROM, RAM, magnetic disk, or optical disk and other computer storage media that can store program codes.
  • the process design method based on system packaging technology described in this embodiment can remove more repetitive work, replace manual work with automation, and save 60%-80% of the time compared with the original method; at the same time, it reduces the difficulty of work and simplifies the design to simulation ,
  • the manufacturing process greatly enhances the competitiveness of electronic products.
  • This embodiment provides a process design system based on system packaging technology.
  • the process design system based on system packaging technology includes:
  • the acquisition module is used to acquire the design data of a layout and the three-dimensional model data associated with the layout;
  • a model generation module configured to associate and match the design data and the three-dimensional model data according to the design element attribute information in the design data, and assemble the design data and the three-dimensional model data into an overall package model;
  • the production analysis module is used to analyze the assembly process of the overall package model to analyze unreasonable design points for design modification and reference; or directly derive a package for manufacturing from the overall package model Process manufacturing procedures.
  • the x module can also be stored in the memory of the following design system in the form of program code, which is called by a certain processing element of the following design system and executes the function of the following x module.
  • the implementation of other modules is similar. All or part of these modules can be integrated together or implemented independently.
  • the processing element described here may be an integrated circuit with signal processing capability. In the implementation process, the steps of the above method or the following modules can be completed by hardware integrated logic circuits in the processor element or software instructions.
  • the following modules may be one or more integrated circuits configured to implement the above methods, for example: one or more specific integrated circuits (scanning application license Specific Integrated Circuit, ASIC for short), one or more microprocessors (Digital Singnal Processor, DSP for short), one or more Field Programmable Gate Arrays (FPGA for short), etc.
  • the processing element may be a general-purpose processor, such as a central processing unit (Central Processing Unit, CPU for short) or other processors that can call program codes.
  • CPU Central Processing Unit
  • SOC System-on-a-chip
  • FIG. 2 shows a schematic structural diagram of a process design system based on system packaging technology in an embodiment of the present invention.
  • the process design system 2 based on system packaging technology includes: an acquisition module 21, a model generation module 22 and a production analysis module 23.
  • the acquisition module 21 acquires design data of a layout and three-dimensional model data associated with the layout.
  • the model generation module 22 is configured to associate and match the design data and the three-dimensional model data according to the design element attribute information in the design data, and assemble the design data and the three-dimensional model data into an overall package model.
  • the model generation module 22 is used to extract design component attribute information from the design data; wherein, the design component attribute information includes component supplier material code, bare chip supplier material code, and/ Or component package size information, the design data includes: supplier material code, package size information, bonding wire information and/or three-dimensional coordinate information of the component, bare chip and/or frame; a physical model library The three-dimensional models of components and bare chips with the same material codes in the design data are retrieved in the design data, and relevant three-dimensional data and working parameters are extracted according to the retrieved three-dimensional models.
  • the design component attribute information includes component supplier material code, bare chip supplier material code, and/ Or component package size information
  • the design data includes: supplier material code, package size information, bonding wire information and/or three-dimensional coordinate information of the component, bare chip and/or frame
  • a physical model library The three-dimensional models of components and bare chips with the same material codes in the design data are retrieved in the design data, and relevant three-dimensional data and working parameters are extracted according to the retrieved
  • the working parameters include: quality, material and/or specific heat capacity ; Using the material code information of the components and bare chips as the connection relationship, the component supplier material code, bare chip supplier material code and meta-frame package size information of the design data are the same as the material code in the entity model library The three-dimensional data and working parameters of the components and bare chips match the overall data of the same model.
  • the production analysis module 23 is used to detect the substrate information in the overall package model, and the detection of the substrate information in the overall package model includes checking the components, pads, and pads of the substrate. Wires, vias and/or copper paving for inspection; or bonding wire analysis of the overall package model according to the bonding wire process manufacturing rules; or assembly analysis of each design element in the overall package model, so
  • the assembly analysis of the components in the overall package model refers to the simulation of the overall package model; or the process analysis of the overall package model according to die/chip manufacturing process rules.
  • the production analysis module 23 is also used to generate a bonding machine program from the bonding wire information in the design data according to a predetermined bonding machine rule, and the bonding machine program is used in the manufacturing process.
  • the process design system based on system packaging technology described in this embodiment can remove more repetitive work, replace manual work with automation, and save 60%-80% of the time compared with the original method; meanwhile, it reduces the difficulty of work and simplifies the process from design to simulation. , The manufacturing process greatly enhances the competitiveness of electronic products.
  • This embodiment provides a device that includes: a processor and a memory; the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the device executes the system-based package Technical process design method.
  • FIG. 3 shows a device connection diagram in an embodiment of the process design method based on the system packaging technology of the present invention.
  • the device includes: a processor 31, a memory 32, a transceiver 33, a communication interface 34 or/and a system bus 35; the memory 32 and the communication interface 34 are connected to the processor 31 and the transceiver 33 through the system bus 35 and complete mutual communication Communication, the memory 32 is used to store computer programs, the communication interface 34 is used to communicate with other devices, and the processor 31 and the transceiver 33 are used to run computer programs to enable the device to execute the process design method based on system packaging technology The various steps.
  • the aforementioned system bus 35 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc.
  • PCI Peripheral Component Interconnect
  • EISA Extended Industry Standard Architecture
  • the system bus 35 can be divided into an address bus, a data bus, a control bus, and the like.
  • the communication interface is used to realize the communication between the database access device and other devices (such as client, read-write library and read-only library).
  • the memory may include random access memory (Random Access Memory, RAM for short), and may also include non-volatile memory (non-volatile memory), such as at least one disk memory.
  • the above-mentioned processor 31 may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU for short), a network processor (Network Processor, NP), etc.; it may also be a digital signal processor (Digital Signal Processing, DSP for short). ), application specific integrated circuits (scanning application license Specific Integrated Circuit, ASIC for short), Field Programmable Gate Array (FPGA for short) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.
  • CPU Central Processing Unit
  • NP Network Processor
  • DSP Digital Signal Processing
  • ASIC application license Specific Integrated Circuit
  • FPGA Field Programmable Gate Array
  • the present invention also provides a process design system based on system packaging technology.
  • the process design system based on system packaging technology can implement the process design method based on system packaging technology of the present invention, but the system packaging technology-based process design method of the present invention
  • the implementation device of the technological process design method includes but is not limited to the structure of the process design system based on the system packaging technology listed in this embodiment. Any structural modification and replacement of the prior art made according to the principles of the present invention are included in this Within the scope of protection of the invention.
  • the process design method, system, medium and equipment based on system packaging technology of the present invention can eliminate a lot of repetitive work and replace manual work with automation, which is more original than the traditional simulation production process.
  • the design data is assembled and manufactured & process virtual analysis is performed to expose the problem before manufacturing and reduce To create a risk.
  • the production cost is reduced, and the competitiveness of electronic products is greatly improved.
  • the invention effectively overcomes various shortcomings in the prior art and has high industrial value.

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Abstract

本发明提供一种基于系统封装技术的工艺设计方法、系统、介质及设备，所述基于系统封装技术的工艺设计方法包括：获取一版图的设计数据及与该版图相关联的三维模型数据；将所述设计数据与所述三维模型数据按照所述设计数据中设计元件属性信息进行关联和匹配，且将所述设计数据和三维模型数据组装为整体封装模型；对所述整体封装模型进行组装工艺分析，以分析出用于作为设计修改及参考的不合理设计点；或直接从所述整体封装模型中导出一用于生产制造的封装工艺制造程序。本发明可去除较多重复的工作，用自动化代替人工，较原有方法节省60％-80％的时间；同时降低工作难度，简化了由设计到仿真、生产制造的过程，使得电子产品的竞争力大大提升。

Description

基于系统封装技术的工艺设计方法、系统、介质及设备 技术领域
本发明属于系统封装技术领域，涉及一种系统封装技术的设计方法，特别是涉及一种基于系统封装技术的工艺设计方法、系统、介质及设备。
背景技术
近百年来，随着电子技术的迅猛发展，电子产品的尺寸越来越小，电子产品的性能越来越高，从微米级到纳米级，从而导致对电子制造产业的要求也越来越高。封装是电子产品的后段加工过程，传统的封装主要完成三大功能：一是对电子核心功能部分进行保护，使其避免外界的影响或破坏；二是将电子功能与外界互联，实现电子器件的功能；三是物理尺度兼容，由于裸芯片的尺寸相对于板级的连接电路来说过小，所以需要通过封装来实现外部的连接。随着集成电路的出现尤其是超大规模集成电路的出现，使得对于电子器件的要求越来越高。系统级封装技术(SIP)是在单个封装内集成多个裸芯片及外围器件，通过使用堆叠、平铺、基板埋置等安装技术，实现了电子系统小型化、高性能、多功能、高可靠性和低成本的特点。
电子制造行业内目前在应用系统级封装技术进行芯片封装制造时，主要涉及到设计、仿真、生产三大步骤，但是目前行业内这三个步骤的联系较少，从设计数据开始到最后的批量生产制造过程中的整体流程非常复杂、繁冗，并且很耗时，这无形中降低了产品的竞争力，提高了生产成本。现有的操作方法存在诸多弊端，例如：(1)在整个过程中存在太多的人工操作，这使得生产制造稳定性降低。(2)在人工创建元器件模型时，将会耗费操作人员大量的时间，并且过程繁琐，还有可能出错导致重复建模。(3)现有方法对操作人员的能力要求比较高。(4)由于没有在生产制造前对设计数据进行相应的组装制造和工艺虚拟检测，这样如果在后续的生产中存在问题，那么整个生产周期将会大大延长，使得生产成本提升，产品竞争力下降。随着电子产品更新换代的加速，智能制造和工业4.0的推进，互联网+制造和智慧工厂理念的深入人心，使得整个电子制造业都在探寻更加高效及可靠的制造方法与技术。
因此，如何提供一种基于系统封装技术的工艺设计方法、系统、介质及设备，以解决现有技术无法避免较多重复的工作，生产制造过程繁琐且易出错等缺陷，成为本领域技术人员亟待解决的技术问题。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种基于系统封装技术的工艺设 计方法、系统、介质及设备，用于解决现有技术无法避免较多重复的工作，生产制造过程繁琐且易出错的问题。
为实现上述目的及其他相关目的，本发明一方面提供一种基于系统封装技术的工艺设计方法，所述基于系统封装技术的工艺设计方法包括：获取一版图的设计数据及与该版图相关联的三维模型数据；将所述设计数据与所述三维模型数据按照所述设计数据中设计元件属性信息进行关联和匹配，且将所述设计数据和三维模型数据组装为整体封装模型；对所述整体封装模型进行组装工艺分析，以分析出用于作为设计修改及参考的不合理设计点，所述组装工艺分析为对所述整体封装模型进行设计规范和系统性能的检测；或直接从所述整体封装模型中导出一用于生产制造的封装工艺制造程序。
于本发明的一实施例中，所述将所述设计数据与所述三维模型数据按照所述设计数据中设计元件属性信息进行关联和匹配的步骤包括：从所述设计数据中提取设计元件属性信息；其中，所述设计元件属性信息包括元器件供应商物料编码、裸芯片供应商物料编码和/或元器件封装尺寸信息，所述设计数据包括：所述元器件、裸芯片和/或框架的供应商物料编码、封装尺寸信息、键合线信息和/或三维坐标信息；在一实体模型库中检索出与所述设计数据中物料编码相同的元器件、裸芯片的三维模型，并根据检索到的三维模型提取相关三维数据和工作参数；以元器件、裸芯片的物料编码信息为连接关系，将所述设计数据的元器件供应商物料编码、裸芯片供应商物料编码和元框架封装尺寸信息与所述实体模型库中物料编码相同的元器件、裸芯片的三维数据和工作参数匹配为同一型号的整体数据。
于本发明的一实施例中，所述工作参数包括：质量、材料和/或比热容。
于本发明的一实施例中，所述对所述整体封装模型进行组装工艺分析，以分析出用于作为设计修改及参考的不合理设计点的步骤包括：对所述整体封装模型中的基板信息进行检测；或按照键合线工艺制造规则对所述整体封装模型进行键合线分析；或对所述整体封装模型中的各个设计元件进行组装分析；或根据裸片/贴片制造工艺规则对所述整体封装模型进行工艺分析。
于本发明的一实施例中，所述对所述整体封装模型中的基板信息进行检测，包括对基板的器件、焊盘、走线、过孔和/或铺铜进行检测。
于本发明的一实施例中，所述对所述整体封装模型中的各组件进行组装分析是指对所述整体封装模型进行仿真。
于本发明的一实施例中，所述直接从所述整体封装模型中导出一用于生产制造的封装工艺制造程序的步骤包括：将所述设计数据中的键合线信息按照预定键合机规则生成一键合机 程序，所述键合机程序为在生产制造过程中的键合机执行的程序；或根据所述设计数据中的裸芯片和待贴片的元器件信息按照预定贴片机规则生成一贴片机程序，所述贴片机程序为在生产制造过程中的贴片机执行的程序。
本发明另一方面提供一种基于系统封装技术的工艺设计系统，所述基于系统封装技术的工艺设计系统包括：获取模块，用于获取一版图的设计数据及与该版图相关联的三维模型数据；模型生成模块，用于将所述设计数据与所述三维模型数据按照所述设计数据中设计元件属性信息进行关联和匹配，且将所述设计数据和三维模型数据组装为整体封装模型；生产分析模块，用于对所述整体封装模型进行组装工艺分析，以分析出用于作为设计修改及参考的不合理设计点；或直接从所述整体封装模型中导出一用于生产制造的封装工艺制造程序。
本发明又一方面提供一种计算机可读存储介质，其上存储有计算机程序，该程序被处理器执行时实现所述的基于系统封装技术的工艺设计方法。
本发明最后一方面提供一种设备，包括：处理器及存储器；所述存储器用于存储计算机程序，所述处理器用于执行所述存储器存储的计算机程序，以使所述设备执行所述的基于系统封装技术的工艺设计方法。
如上所述，本发明所述的基于系统封装技术的工艺设计方法、系统、介质及设备，具有以下有益效果：相比于目前传统的仿真生产流程，本发明可以去除很多重复工作，用自动化代替人工，较原有方法节省60％-80％的时间；同时也降低了工作难度，简化了由设计到仿真、生产制造的过程，对设计数据进行了组装制造&工艺虚拟分析使问题在生产制造之前暴露，降低了制造风险。减少了生产成本，使得电子产品的竞争力大大提升。
附图说明
图1A显示为本发明的基于系统封装技术的工艺设计方法于一实施例中的原理流程图。
图1B显示为本发明的基于系统封装技术的工艺设计方法于一实施例中的流程示意图。
图2显示为本发明的基于系统封装技术的工艺设计系统于一实施例中的结构原理图。
图3显示为本发明的基于系统封装技术的工艺设计方法于一实施例中的设备连接图。
图4显示为本发明的基于系统封装技术的工艺设计方法于一实施例中的裸芯片模型图。
图5显示为本发明的基于系统封装技术的工艺设计方法于一实施例中的基板分析图。
图6显示为本发明的基于系统封装技术的工艺设计方法于一实施例中的键合线模型图。
图7显示为本发明的基于系统封装技术的工艺设计方法于一实施例中的芯片组装模型图。
图8显示为本发明的基于系统封装技术的工艺设计方法于一实施例中的整体封装模型 图。
元件标号说明
21        获取模块
22        模型生成模块
23        生产分析模块
31        处理器
32        存储器
33        收发器
34        通信接口
35        系统总线
S11～S13  基于系统封装技术的工艺设计方法的步骤
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。需说明的是，在不冲突的情况下，以下实施例及实施例中的特征可以相互组合。
需要说明的是，以下实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
本发明所述基于系统封装技术的工艺设计方法、系统、介质及设备的技术原理如下：获取一版图的设计数据及与该版图相关联的三维模型数据；将所述设计数据与所述三维模型数据按照所述设计数据中设计元件属性信息进行关联和匹配，且将所述设计数据和三维模型数据组装为整体封装模型；对所述整体封装模型进行组装工艺分析，以分析出用于作为设计修改及参考的不合理设计点；或直接从所述整体封装模型中导出一用于生产制造的封装工艺制造程序。
实施例一
本实施例提供一种基于系统封装技术的工艺设计方法，所述基于系统封装技术的工艺设计方法包括：
获取一版图的设计数据及与该版图相关联的三维模型数据；
将所述设计数据与所述三维模型数据按照所述设计数据中设计元件属性信息进行关联和匹配，且将所述设计数据和三维模型数据组装为整体封装模型；
对所述整体封装模型进行组装工艺分析，以分析出用于作为设计修改及参考的不合理设计点，所述组装工艺分析为对所述整体封装模型进行设计规范和系统性能的检测；或
直接从所述整体封装模型中导出一用于生产制造的封装工艺制造程序。
以下将结合图1A和图1B对本实施例所提供的基于系统封装技术的工艺设计方法进行详细描述。
请参阅图1A，显示为本发明的基于系统封装技术的工艺设计方法于一实施例中的原理流程图。如图1A所示，所述基于系统封装技术的工艺设计方法具体包括以下几个步骤：
S11，获取一版图的设计数据及与该版图相关联的三维模型数据。
在本实施例中，所述系统封装技术是指半导体器件的SIP封装形式，SIP封装从架构上讲，是将多种功能的芯片，包括处理器、存储器等集成在一个封装内，实现一个基本完整的功能；从工艺上讲，是将具有一定功能的裸芯片(DIE，芯粒或称籽芯、管芯)和元器件按照版图的设计，置入密封在与其相适应的一个框架内，形成一个完整的器件整体，即整体封装模型，在所述整体封装模型中需要键合线进行电气互连，所述裸芯片模型请参阅图4，显示为本发明的基于系统封装技术的工艺设计方法于一实施例中的裸芯片模型图。
具体地，读取版图设计软件中的设计数据至内存中，此外，如若缺少物料信息还需导入物料清单，将设计数据中的裸芯片、元器件位号与实物物料编码一一对应。所述设计数据包括BOM数据，如Cadence SIP设计数据”.sip”文件。所述版图设计软件包括Cadence SIP设计软件。在设计版图过程中，所用到的元器件及裸芯片、框架等设计元素均有相对应的BOM数据及其他设计数据。
于实际应用中，在用于存放裸芯片的三维模型数据和焊盘位置关系的裸芯片库中获取裸芯片的三维模型数据，所述裸芯片的三维模型数据以裸芯片供应商物料编码命名；在用于存放芯片框架的三维模型数据的框架库中获取框架的三维模型数据，所述框架的三维模型数据以封装类型与尺寸命名；在用于存放元器件的三维模型数据和实际工作参数数据(质量、材料、功耗等)的元器件库中获取元器件的三维模型数据，所述元器件的三维模型数据以供应商物料编码命名。
S12，将所述设计数据与所述三维模型数据按照所述设计数据中设计元件属性信息进行关联和匹配，且将所述设计数据和三维模型数据组装为整体封装模型。于实际应用中，根据设计数据中的元器件的供应商物料编码、裸芯片的供应商物料编码、封装尺寸信息与裸芯片&框架库、元器件3D实体模型库进行匹配，从而结合设计数据的三维坐标信息与所述三维模型数据生成整体封装模型。
在本实施例中，所述S12包括：
S121，从所述设计数据中提取设计元件属性信息。在本实施例中，所述设计元件属性信息包括元器件供应商物料编码、裸芯片供应商物料编码和元框架封装尺寸信息和/或元件名称。所述设计数据包括：所述元器件、裸芯片和/或框架的供应商物料编码、封装尺寸信息、键合线信息和/或三维坐标信息。
于实际应用中，例如在基板中，将元器件A、裸芯片B、电阻C及电容D根据其实现的功能及走线规则设置于基板特定位置，并进行布线设计，所述基板还需设置于一框架E内，以便进行整体封装。由此，若元器件A的物料编码为FU6008，则在该设计数据中需要提取FU6008；若裸芯片B的物料编码为QFP579Z，则在该设计数据中需要提取QFP579Z；若电阻C的物料编码为RX080522K，则在该设计数据中需要提取RX080522K；若电容D的物料编码为CX060247U，则在该设计数据中需要提取CX060247U。此外，还需提取所述框架E的封装尺寸信息，所述框架E的封装尺寸信息包括外沿长宽高、内沿长宽高、倒角尺寸及厚度信息等。
S122，在一实体模型库中检索出与所述设计数据中物料编码相同的元器件、裸芯片的三维模型，并根据检索到的三维模型提取相关三维数据和工作参数。
具体地，所述实体模型库中预存有用于基板设计的相关器件，包括元器件A、裸芯片B、电阻C、电容D及框架E的三维模型，所述三维模型中包括器件的三维尺寸信息及工作参数等器件性能方面的信息，所述工作参数包括：质量、材料和/或比热容。
S123，以元器件、裸芯片的物料编码信息为连接关系，将所述设计数据的元器件供应商物料编码、裸芯片供应商物料编码和元框架封装尺寸信息与所述实体模型库中物料编码相同的元器件、裸芯片的三维数据和工作参数匹配为同一型号的整体数据。
于实际应用中，在所述设计数据中检索到物料编码为FU6008、QFP579Z、RX080522K、CX060247U以及框架E在基板上的二维坐标信息，由此提取出元器件A、裸芯片B、电阻C、电容D及框架E在基板上的坐标信息；在所述实体模型库中同样检索出物料编码为FU6008、QFP579Z、RX080522K、CX060247U以及框架E的器件，由此提取出元器件A、裸芯片B、 电阻C、电容D及框架E完整的三维模型数据，且提取的三维模型数据中包括器件的三维尺寸信息及工作参数等器件性能方面的信息。通过相同的物料编码为FU6008、QFP579Z、RX080522K、CX060247U以及框架E在基板上的二维坐标信息将基板与所述实体模型库建立关系，例如，在所述实体模型库中提取基板设计中用到的器件的三维模型，根据基板中设计的器件所在位置，将同一物料编码的器件三维模型导入相应基板位置，且将框架E的三维模型也导入基板中进行封装组合，由此生成每个器件的整体数据，所述整体数据包括基板所用器件参数信息、在基板的位置信息以及所述实体模型库导入三维模型时携带的三维数据信息及工作参数信息。
S13，对所述整体封装模型进行组装工艺分析，以分析出用于作为设计修改及参考的不合理设计点；或直接从所述整体封装模型中导出一用于生产制造的封装工艺制造程序。
在本实施例中，所述整体封装模型进行组装工艺分析之后，将不合理设计之处反馈于设计人员修改，待修改完成后重新生成所述整体封装模型。当设计中存在不合理之处时，将重新生成的整体封装模型用于导出封装工艺制造程序，当未进行组装工艺分析或分析后不存在不合理之处时，直接将所述整体封装模型导出封装工艺制造程序。需要说明的是，所述整体封装模型不仅仅是一个三维立体模型，其中还携带有所涉及的所有器件的工作性能参数，如S123所述的同一型号器件的整体数据。
具体地，参阅图1B，显示为本发明的基于系统封装技术的工艺设计方法于一实施例中的流程示意图。
在本实施例中，所述S13包括：
对所述整体封装模型中的基板信息进行检测。在基本设计过程中，涉及到元器件的排布、走线、焊盘、设过孔等工艺，其中，器件与器件之间的安全距离、布线距离、焊盘、过孔与元器件相互之间的布线距离需要符合预定的距离范围，以保证设计的合理性和基板的性能。由此，所述对所述整体封装模型中的基板信息进行检测，包括对基板的器件、焊盘、走线、过孔和/或铺铜进行检测。
请参阅图5，显示为本发明的基于系统封装技术的工艺设计方法于一实施例中的基板分析图。图5中的基板检测包括：焊盘与元器件的距离a是否符合安全设计规范，所述安全设计规范为一安全阈值，若距离a小于该安全阈值，则将该设计问题报错。同理，通过基板上各元器件、过孔、焊盘、走线的坐标信息可计算过孔1与焊盘的距离b，走线与过孔2的距离以及基板中的过孔之间的距离和过孔的孔径大小是否符合加工要求。
按照键合线工艺制造规则对所述整体封装模型进行键合线分析。具体地，所述系统封装 技术为键合线封装技术，键合技术包括热压焊、热超声焊。因此，请参阅图6，显示为本发明的基于系统封装技术的工艺设计方法于一实施例中的键合线模型图。所述键合线是用于在贴装的元器件引脚与裸芯片的引脚之间作电气连接，所述键合线分析是依据键合线长度是否合适、键合线直径是否合适、键合线的走向是否合理、键合线的固定是否牢固、键合线与键合线之间的距离是否符合安全要求等键合线工艺制造规则进行规则检查。
对所述整体封装模型中的各个设计元件进行组装分析。于实际应用中，所述整体封装模型是由各元器件、基板、裸芯片及框架构成的整体，请参阅图7和图8，分别显示为本发明的基于系统封装技术的工艺设计方法于一实施例中的芯片组装模型图和显示为本发明的基于系统封装技术的工艺设计方法于一实施例中的整体封装模型图。在整体的系统中，如元器件1与元器件2之间、元器件与裸芯片之间、元器件与框架之间、裸芯片与框架之间的间距是否合理，若元器件2为高频器件，所设计的间距是否能有效避免电磁干扰；若元器件2为发热器件，整个系统设计及组装是否能够有效散热；若元器件2为敏感器件，其所处的位置是否能有效远离其他器件的干扰，图8中最外侧的框架封装之后结构是否充分利用空间，在美观的基础上符合排布规则，是否存在各器件的位置和边角的干涉，针对上述问题，所述对所述整体封装模型中的各组件进行组装分析是指对所述整体封装模型进行仿真，所述仿真的方法包括有限元分析，通过所述有限元分析进行电磁、热、结构等仿真测试，所述有限元分析的实现方式包括：UG、ANSYS和/或Flotherm。
根据裸片/贴片制造工艺规则对所述整体封装模型进行工艺分析。在键合线封装工艺中，由于各工艺流程会带来设计问题。如圆片的减薄是否厚度合适、圆片切割是否造成边沿损坏、芯片粘结时软焊料是否完全固定，是否有飞溅到其他位置、聚合物粘结剂用量和位置是否恰当、裸芯片是否有移位、元器件是否有虚焊、元器件是否依型号正确放置及元器件是否有损坏。所述工艺分析将结果逐条检查将输出报告反馈于设计人员。
将所述设计数据中的键合线信息按照预定键合机规则生成一键合机程序，所述预定键合机规则是根据基板设计的键合线位置及所述整体封装模型的键合线走向、起止点生成每一根键合线的执行指令，所述执行指令可实现每一根键合线按照设计的坐标与起止点固定在元器件之间，所有键合线的执行指令组合生成键合机程序，为在生产制造过程中的键合机执行的程序；或
根据所述设计数据中的裸芯片和待贴片的元器件信息按照预定贴片机规则生成一贴片机程序，所述预定贴片机规则是根据设计文件的BOM表、坐标文件及Gerber基板图像生成每一器件的型号与位置对应的执行指令，按照该执行指令可实现每一器件焊接固定在基板设计 的坐标位置上，所有器件的执行指令组合生成所述贴片机程序，为在生产制造过程中的贴片机执行的程序。
本实施例提供一种计算机存储介质，其上存储有计算机程序，该计算机程序被处理器执行时实现所述基于系统封装技术的工艺设计方法。
本领域普通技术人员可以理解：实现上述各方法实施例的全部或部分步骤可以通过计算机程序相关的硬件来完成。前述的计算机程序可以存储于一计算机可读存储计算机存储介质中。该程序在执行时，执行包括上述各方法实施例的步骤；而前述的存储计算机存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的计算机存储介质。
本实施例所述基于系统封装技术的工艺设计方法可去除较多重复的工作，用自动化代替人工，较原有方法节省60％-80％的时间；同时降低工作难度，简化了由设计到仿真、生产制造的过程，使得电子产品的竞争力大大提升。
实施例二
本实施例提供一种基于系统封装技术的工艺设计系统，所述基于系统封装技术的工艺设计系统包括：
获取模块，用于获取一版图的设计数据及与该版图相关联的三维模型数据；
模型生成模块，用于将所述设计数据与所述三维模型数据按照所述设计数据中设计元件属性信息进行关联和匹配，且将所述设计数据和三维模型数据组装为整体封装模型；
生产分析模块，用于对所述整体封装模型进行组装工艺分析，以分析出用于作为设计修改及参考的不合理设计点；或直接从所述整体封装模型中导出一用于生产制造的封装工艺制造程序。
以下将结合图示对本实施例所提供的基于系统封装技术的工艺设计系统进行详细描述。需要说明的是，应理解以下设计系统的各个模块的划分仅仅是一种逻辑功能的划分，实际实现时可以全部或部分集成到一个物理实体上，也可以物理上分开。且这些模块可以全部以软件通过处理元件调用的形式实现，也可以全部以硬件的形式实现，还可以部分模块通过处理元件调用软件的形式实现，部分模块通过硬件的形式实现。例如：x模块可以为单独设立的处理元件，也可以集成在下述设计系统的某一个芯片中实现。此外，x模块也可以以程序代码的形式存储于下述设计系统的存储器中，由下述设计系统的某一个处理元件调用并执行以下x模块的功能。其它模块的实现与之类似。这些模块全部或部分可以集成在一起，也可以独立实现。这里所述的处理元件可以是一种集成电路，具有信号的处理能力。在实现过程中，上述方法的各步骤或以下各个模块可以通过处理器元件中的硬件的集成逻辑电路或者软件形 式的指令完成。
以下这些模块可以是被配置成实施以上方法的一个或多个集成电路，例如：一个或多个特定集成电路(扫描应用程序lication Specific Integrated Circuit，简称ASIC)，一个或多个微处理器(Digital Singnal Processor，简称DSP)，一个或者多个现场可编程门阵列(Field Programmable GateArray，简称FPGA)等。当以下某个模块通过处理元件调用程序代码的形式实现时，该处理元件可以是通用处理器，如中央处理器(Central Processing Unit，简称CPU)或其它可以调用程序代码的处理器。这些模块可以集成在一起，以片上系统(System-on-a-chip，简称SOC)的形式实现。
请参阅图2，显示为本发明的基于系统封装技术的工艺设计系统于一实施例中的结构原理图。如图2所示，所述基于系统封装技术的工艺设计系统2包括：获取模块21、模型生成模块22和生产分析模块23。
通过所述获取模块21获取一版图的设计数据及与该版图相关联的三维模型数据。
模型生成模块22用于将所述设计数据与所述三维模型数据按照所述设计数据中设计元件属性信息进行关联和匹配，且将所述设计数据和三维模型数据组装为整体封装模型。
在本实施例中，所述模型生成模块22用于从所述设计数据中提取设计元件属性信息；其中，所述设计元件属性信息包括元器件供应商物料编码、裸芯片供应商物料编码和/或元器件封装尺寸信息，所述设计数据包括：所述元器件、裸芯片和/或框架的供应商物料编码、封装尺寸信息、键合线信息和/或三维坐标信息；在一实体模型库中检索出与所述设计数据中物料编码相同的元器件、裸芯片的三维模型，并根据检索到的三维模型提取相关三维数据和工作参数，所述工作参数包括：质量、材料和/或比热容；以元器件、裸芯片的物料编码信息为连接关系，将所述设计数据的元器件供应商物料编码、裸芯片供应商物料编码和元框架封装尺寸信息与所述实体模型库中物料编码相同的元器件、裸芯片的三维数据和工作参数匹配为同一型号的整体数据。
在所述生产分析模块23中对所述整体封装模型进行组装工艺分析，以分析出用于作为设计修改及参考的不合理设计点；或直接从所述整体封装模型中导出一用于生产制造的封装工艺制造程序。
于实际应用中，所述生产分析模块23用于对所述整体封装模型中的基板信息进行检测，所述对所述整体封装模型中的基板信息进行检测，包括对基板的器件、焊盘、走线、过孔和/或铺铜进行检测；或按照键合线工艺制造规则对所述整体封装模型进行键合线分析；或对所述整体封装模型中的各个设计元件进行组装分析，所述对所述整体封装模型中的各组件进行 组装分析是指对所述整体封装模型进行仿真；或根据裸片/贴片制造工艺规则对所述整体封装模型进行工艺分析。
在本实施例中，所述生产分析模块23还用于将所述设计数据中的键合线信息按照预定键合机规则生成一键合机程序，所述键合机程序为在生产制造过程中的键合机执行的程序；或根据所述设计数据中的裸芯片和待贴片的元器件信息按照预定贴片机规则生成一贴片机程序，所述贴片机程序为在生产制造过程中的贴片机执行的程序。
本实施例所述基于系统封装技术的工艺设计系统可去除较多重复的工作，用自动化代替人工，较原有方法节省60％-80％的时间；同时降低工作难度，简化了由设计到仿真、生产制造的过程，使得电子产品的竞争力大大提升。
实施例三
本实施例提供一种设备，包括：处理器及存储器；所述存储器用于存储计算机程序，所述处理器用于执行所述存储器存储的计算机程序，以使所述设备执行所述的基于系统封装技术的工艺设计方法。
请参阅图3，显示为本发明的基于系统封装技术的工艺设计方法于一实施例中的设备连接图。所述设备包括：处理器31、存储器32、收发器33、通信接口34或/和系统总线35；存储器32和通信接口34通过系统总线35与处理器31和收发器33连接并完成相互间的通信，存储器32用于存储计算机程序，通信接口34用于和其他设备进行通信，处理器31和收发器33用于运行计算机程序，使所述设备执行所述的基于系统封装技术的工艺设计方法的各个步骤。
上述提到的系统总线35可以是外设部件互连标准(Peripheral Component Interconnect，简称PCI)总线或扩展工业标准结构(Extended Industry Standard Architecture，简称EISA)总线等。该系统总线35可以分为地址总线、数据总线、控制总线等。通信接口用于实现数据库访问装置与其他设备(如客户端、读写库和只读库)之间的通信。存储器可能包含随机存取存储器(Random Access Memory，简称RAM)，也可能还包括非易失性存储器(non-volatile memory)，例如至少一个磁盘存储器。
上述的处理器31可以是通用处理器，包括中央处理器(Central Processing Unit，简称CPU)、网络处理器(Network Processor，简称NP)等；还可以是数字信号处理器(Digital Signal Processing，简称DSP)、专用集成电路(扫描应用程序lication Specific Integrated Circuit，简称ASIC)、现场可编程门阵列(Field Programmable Gate Array，简称FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。
本发明所述的基于系统封装技术的工艺设计方法的保护范围不限于本实施例列举的步骤执行顺序，凡是根据本发明的原理所做的现有技术的步骤增减、步骤替换所实现的方案都包括在本发明的保护范围内。
本发明还提供一种基于系统封装技术的工艺设计系统，所述基于系统封装技术的工艺设计系统可以实现本发明所述的基于系统封装技术的工艺设计方法，但本发明所述的基于系统封装技术的工艺设计方法的实现装置包括但不限于本实施例列举的基于系统封装技术的工艺设计系统的结构，凡是根据本发明的原理所做的现有技术的结构变形和替换，都包括在本发明的保护范围内。
综上所述，本发明所述的基于系统封装技术的工艺设计方法、系统、介质及设备，相比于目前传统的仿真生产流程，本发明可以去除很多重复工作，用自动化代替人工，较原有方法节省60％-80％的时间；同时也降低了工作难度，简化了由设计到仿真、生产制造的过程，对设计数据进行了组装制造&工艺虚拟分析使问题在生产制造之前暴露，降低了制造风险。减少了生产成本，使得电子产品的竞争力大大提升。本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

  1. 一种基于系统封装技术的工艺设计方法，其特征在于，所述基于系统封装技术的工艺设计方法包括：
    获取一版图的设计数据及与该版图相关联的三维模型数据；
    将所述设计数据与所述三维模型数据按照所述设计数据中设计元件属性信息进行关联和匹配，且将所述设计数据和三维模型数据组装为整体封装模型；
    对所述整体封装模型进行组装工艺分析，以分析出用于作为设计修改及参考的不合理设计点，所述组装工艺分析为对所述整体封装模型进行设计规范和系统性能的检测；或直接从所述整体封装模型中导出一用于生产制造的封装工艺制造程序。
  2. 根据权利要求1所述的基于系统封装技术的工艺设计方法，其特征在于，所述将所述设计数据与所述三维模型数据按照所述设计数据中设计元件属性信息进行关联和匹配的步骤包括：
    从所述设计数据中提取设计元件属性信息；其中，所述设计元件属性信息包括元器件供应商物料编码、裸芯片供应商物料编码和/或元器件封装尺寸信息；所述设计数据包括：所述元器件、裸芯片和/或框架的供应商物料编码、封装尺寸信息、键合线信息和/或三维坐标信息；
    在一实体模型库中检索出与所述设计数据中物料编码相同的元器件、裸芯片的三维模型，并根据检索到的三维模型提取相关三维数据和工作参数；
    以元器件、裸芯片的物料编码信息为连接关系，将所述设计数据的元器件供应商物料编码、裸芯片供应商物料编码和元框架封装尺寸信息与所述实体模型库中物料编码相同的元器件、裸芯片的三维数据和工作参数匹配为同一型号的整体数据。
  3. 根据权利要求2所述的基于系统封装技术的工艺设计方法，其特征在于，
    所述工作参数包括：质量、材料和/或比热容。
  4. 根据权利要求1所述的基于系统封装技术的工艺设计方法，其特征在于，所述对所述整体封装模型进行组装工艺分析，以分析出用于作为设计修改及参考的不合理设计点的步骤包括：
    对所述整体封装模型中的基板信息进行检测；或
    按照键合线工艺制造规则对所述整体封装模型进行键合线分析；或
    对所述整体封装模型中的各个设计元件进行组装分析；或
    根据裸片/贴片制造工艺规则对所述整体封装模型进行工艺分析。
  5. 根据权利要求4所述的基于系统封装技术的工艺设计方法，其特征在于，
    所述对所述整体封装模型中的基板信息进行检测，包括对基板的器件、焊盘、走线、过孔和/或铺铜进行检测。
  6. 根据权利要求4所述的基于系统封装技术的工艺设计方法，其特征在于，
    所述对所述整体封装模型中的各组件进行组装分析是指对所述整体封装模型进行仿真。
  7. 根据权利要求1所述的基于系统封装技术的工艺设计方法，其特征在于，所述直接从所述整体封装模型中导出一用于生产制造的封装工艺制造程序的步骤包括：
    将所述设计数据中的键合线信息按照预定键合机规则生成一键合机程序，所述键合机程序为在生产制造过程中的键合机执行的程序；或
    根据所述设计数据中的裸芯片和待贴片的元器件信息按照预定贴片机规则生成一贴片机程序，所述贴片机程序为在生产制造过程中的贴片机执行的程序。
  8. 一种基于系统封装技术的工艺设计系统，其特征在于，所述基于系统封装技术的工艺设计系统包括：
    获取模块，用于获取一版图的设计数据及与该版图相关联的三维模型数据；
    模型生成模块，用于将所述设计数据与所述三维模型数据按照所述设计数据中设计元件属性信息进行关联和匹配，且将所述设计数据和三维模型数据组装为整体封装模型；
    生产分析模块，用于对所述整体封装模型进行组装工艺分析，以分析出用于作为设计修改及参考的不合理设计点；或直接从所述整体封装模型中导出一用于生产制造的封装工艺制造程序。
  9. 一种计算机可读存储介质，其上存储有计算机程序，其特征在于，该程序被处理器执行时实现权利要求1至7任一项所述的基于系统封装技术的工艺设计方法。
  10. 一种设备，其特征在于，包括：处理器及存储器；
    所述存储器用于存储计算机程序，所述处理器用于执行所述存储器存储的计算机程 序，以使所述设备执行如权利要求1至7中任一项所述的基于系统封装技术的工艺设计方法。
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