WO2020217999A1 - Procédé de fabrication de cellule solaire et cellule solaire - Google Patents

Procédé de fabrication de cellule solaire et cellule solaire Download PDF

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Publication number
WO2020217999A1
WO2020217999A1 PCT/JP2020/015915 JP2020015915W WO2020217999A1 WO 2020217999 A1 WO2020217999 A1 WO 2020217999A1 JP 2020015915 W JP2020015915 W JP 2020015915W WO 2020217999 A1 WO2020217999 A1 WO 2020217999A1
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semiconductor layer
layer
region
material film
intrinsic semiconductor
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PCT/JP2020/015915
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English (en)
Japanese (ja)
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小西　克典
勇人 河▲崎▼
足立　大輔
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株式会社カネカ
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Priority to JP2021515969A priority Critical patent/JP7169440B2/ja
Publication of WO2020217999A1 publication Critical patent/WO2020217999A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a method for manufacturing a back electrode type (back contact type) solar cell and a solar cell.
  • Patent Document 1 discloses a back electrode type solar cell.
  • the solar cell described in Patent Document 1 includes a semiconductor substrate that functions as a photoelectric conversion layer, and a first intrinsic semiconductor layer, a first conductive semiconductor layer, and a first electrode layer that are sequentially laminated on a part of the back surface side of the semiconductor substrate.
  • a second intrinsic semiconductor layer, a second conductive semiconductor layer, and a second electrode layer, which are sequentially laminated on the other part on the back surface side of the semiconductor substrate, are provided.
  • a photolithography technique is used in the patterning of the first intrinsic semiconductor layer and the first conductive semiconductor layer (first patterning) and the patterning of the second intrinsic semiconductor layer and the second conductive semiconductor layer (second patterning).
  • the etching method used is used.
  • photoresist coating by the spin coating method for example, photoresist drying, photoresist exposure, photoresist development, etching of a semiconductor layer using a photoresist as a mask, and photoresist peeling are performed. A process was required and the process was complicated.
  • Patent Document 1 knows a technique for simplifying the patterning process by a lift-off method using a lift-off layer (sacrificial layer) in the second patterning.
  • the lift-off layer is formed before the first patterning and is patterned with the semiconductor layer in the first patterning. At the time of this first patterning, the other part on the back surface side of the semiconductor substrate is exposed, so it is necessary to clean the surface of the exposed semiconductor substrate after that.
  • the lift-off layer was etched by the cleaning solution (for example, hydrofluoric acid), and the film thickness of the lift-off layer was sometimes reduced. If the film thickness of the lift-off layer is reduced, the lift-off property of the lift-off layer is reduced in the second patterning (for example, the lift-off layer is peeled off before the second patterning, and the lift-off process is performed in the second patterning. Will not be performed normally).
  • the cleaning solution for example, hydrofluoric acid
  • An object of the present invention is to provide a method for manufacturing a solar cell that avoids a decrease in lift-off property due to a lift-off layer, and a solar cell manufactured by the manufacturing method.
  • a first conductive semiconductor layer is sequentially laminated on a semiconductor substrate and a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate.
  • a back electrode type sun including a first electrode layer, a second conductive semiconductor layer and a second electrode layer sequentially laminated in a second region which is a part of the other main surface side of the semiconductor substrate.
  • a method for manufacturing a battery which is a first semiconductor layer material film forming step of sequentially forming a material film of a first intrinsic semiconductor layer and a material film of the first conductive semiconductor layer on the other main surface side of the semiconductor substrate.
  • the 1st intrinsic semiconductor layer, the patterned first conductive semiconductor layer, and the lift-off layer are formed in the 1st region.
  • the material film of the second intrinsic semiconductor layer and the second conductive semiconductor layer are placed on the lift-off layer in the first region and the first intrinsic semiconductor layer in the second region.
  • the second region includes a second semiconductor layer forming step of forming the first intrinsic semiconductor layer, the patterned second intrinsic semiconductor layer, and the second conductive semiconductor layer.
  • the solar cell according to the present invention includes a semiconductor substrate, a first conductive semiconductor layer and a first conductive semiconductor layer, which are sequentially laminated in a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate.
  • a back electrode type solar cell including an electrode layer, a second conductive semiconductor layer and a second electrode layer sequentially laminated in a second region which is another part of the other main surface side of the semiconductor substrate.
  • the first intrinsic semiconductor layer formed in the first region and the second region on the other main surface side of the semiconductor substrate, and the first intrinsic semiconductor layer formed in the first region.
  • the first conductive semiconductor layer, the second intrinsic semiconductor layer formed on the first intrinsic semiconductor layer in the second region, and the second conductive semiconductor layer are provided, and the second in the second region.
  • the thickness of the 1 intrinsic semiconductor layer is thinner than the thickness of the 1st intrinsic semiconductor layer in the 1st region, and the total thickness of the 1st intrinsic semiconductor layer and the 2nd intrinsic semiconductor layer in the 2nd region is
  • the second intrinsic semiconductor layer is thicker than the thickness of the first intrinsic semiconductor layer in the first region, and contains the second conductive type dopant.
  • the present invention in the method for manufacturing a solar cell, it is possible to avoid a decrease in lift-off property due to the lift-off layer. Further, according to the present invention, it is possible to provide a solar cell manufactured by the manufacturing method.
  • FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG. It is a figure which shows the 1st semiconductor layer material film formation process and lift-off layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment.
  • FIG. 1 is a view of the solar cell according to the present embodiment as viewed from the back surface side.
  • the solar cell 1 shown in FIG. 1 is a back electrode type solar cell.
  • the solar cell 1 includes a semiconductor substrate 11 having two main surfaces, and has a first region 7 and a second region 8 on the main surface of the semiconductor substrate 11.
  • the first region 7 has a so-called comb-shaped shape, and has a plurality of finger portions 7f corresponding to comb teeth and a bus bar portion 7b corresponding to a support portion of the comb teeth.
  • the bus bar portion 7b extends in the first direction (X direction) along one side of the semiconductor substrate 11, and the finger portion 7f intersects the bus bar portion 7b in the first direction (X direction). It extends in the direction (Y direction).
  • the second region 8 has a so-called comb-shaped shape, and has a plurality of finger portions 8f corresponding to the comb teeth and a bus bar portion 8b corresponding to the support portion of the comb teeth.
  • the bus bar portion 8b extends in the first direction (X direction) along the other side portion facing one side portion of the semiconductor substrate 11, and the finger portion 8f extends from the bus bar portion 8b in the second direction (Y). Extends in the direction).
  • the finger portions 7f and the finger portions 8f are alternately provided in the first direction (X direction).
  • the first region 7 and the second region 8 may be formed in a striped shape.
  • FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG.
  • the solar cell 1 includes a semiconductor substrate 11, an intrinsic semiconductor layer 13 and optics, which are sequentially laminated on the light receiving surface side, which is one of the main surfaces of the semiconductor substrate 11 on the light receiving side.
  • the adjusting layer 15 is provided.
  • the solar cell 1 is a first intrinsic semiconductor layer 23 which is sequentially laminated on a part (first region 7) of the back surface side which is the other main surface of the main surface of the semiconductor substrate 11 opposite to the light receiving surface.
  • a first conductive semiconductor layer 25 and a first electrode layer 27 are provided.
  • the solar cell 1 includes a first intrinsic semiconductor layer 23, a second intrinsic semiconductor layer 33, and a second conductive semiconductor layer 35, which are sequentially laminated on another part (second region 8) on the back surface side of the semiconductor substrate 11. And a second electrode layer 37 is provided.
  • the semiconductor substrate 11 is formed of a crystalline silicon material such as single crystal silicon or polycrystalline silicon.
  • the semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which a crystalline silicon material is doped with an n-type dopant. Examples of the n-type dopant include phosphorus (P).
  • the semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light receiving surface side to generate optical carriers (electrons and holes). By using crystalline silicon as the material of the semiconductor substrate 11, a relatively high output (stable output regardless of the illuminance) can be obtained even when the dark current is relatively small and the intensity of the incident light is low.
  • the intrinsic semiconductor layer 13 is formed on the light receiving surface side of the semiconductor substrate 11.
  • the first intrinsic semiconductor layer 23 is formed in the first region 7 and the second region 8 on the back surface side of the semiconductor substrate 11.
  • the second intrinsic semiconductor layer 33 is formed in the second region 8 on the back surface side of the semiconductor substrate 11, that is, on the first intrinsic semiconductor layer 23 in the second region 8.
  • the film thickness of the first intrinsic semiconductor layer 23 in the second region 8 is thinner than the film thickness of the first intrinsic semiconductor layer 23 in the first region 7. Further, the total film thickness of the first intrinsic semiconductor layer 23 and the second intrinsic semiconductor layer 33 in the second region 8 is thicker than the film thickness of the first intrinsic semiconductor layer 23 in the first region 7.
  • the intrinsic semiconductor layer 13, the first intrinsic semiconductor layer 23, and the second intrinsic semiconductor layer 33 are formed of, for example, a material containing intrinsic (i-type) amorphous silicon as a main component.
  • the intrinsic semiconductor layer 13, the first intrinsic semiconductor layer 23, and the second intrinsic semiconductor layer 33 function as a so-called passivation layer, suppress recombination of carriers generated in the semiconductor substrate 11, and increase carrier recovery efficiency.
  • the optical adjustment layer 15 is formed on the intrinsic semiconductor layer 13 on the light receiving surface side of the semiconductor substrate 11.
  • the optical adjustment layer 15 functions as an antireflection layer for preventing reflection of incident light, and also functions as a protective layer for protecting the light receiving surface side of the semiconductor substrate 11 and the intrinsic semiconductor layer 13.
  • the optical adjustment layer 15 is formed of an insulating material such as a composite thereof such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON).
  • the first conductive semiconductor layer 25 is formed on the first intrinsic semiconductor layer 23 in the first region 7, that is, in the first region 7 on the back surface side of the semiconductor substrate 11.
  • the first conductive semiconductor layer 25 is formed of, for example, an amorphous silicon material.
  • the first conductive semiconductor layer 25 is, for example, a p-type semiconductor layer in which an amorphous silicon material is doped with a p-type dopant. Examples of the p-type dopant include boron (B).
  • the second conductive semiconductor layer 35 is formed on the second intrinsic semiconductor layer 33, that is, in the second region 8 on the back surface side of the semiconductor substrate 11.
  • the second conductive semiconductor layer 35 is formed of, for example, an amorphous silicon material.
  • the second conductive semiconductor layer 35 is, for example, an n-type semiconductor layer in which an amorphous silicon material is doped with an n-type dopant (for example, phosphorus (P) described above).
  • the first conductive semiconductor layer 25 may be an n-type semiconductor layer
  • the second conductive semiconductor layer 35 may be a p-type semiconductor layer
  • the semiconductor substrate 11 may be a p-type semiconductor substrate in which a crystalline silicon material is doped with a p-type dopant (for example, the above-mentioned boron (B)).
  • the first electrode layer 27 is formed on the first conductive semiconductor layer 25, and the second electrode layer 37 is formed on the second conductive semiconductor layer 35.
  • the first electrode layer 27 has a transparent electrode layer 28 and a metal electrode layer 29, which are sequentially laminated on the first conductive semiconductor layer 25.
  • the second electrode layer 37 has a transparent electrode layer 38 and a metal electrode layer 39, which are sequentially laminated on the second conductive semiconductor layer 35.
  • the transparent electrode layers 28 and 38 are formed of a transparent conductive material. Examples of the transparent conductive material include ITO (Indium Tin Oxide: a composite oxide of indium tin oxide and tin oxide) and ZnO (Zinc Oxide: zinc oxide).
  • the metal electrode layers 29 and 39 are formed of a conductive paste material containing a metal powder such as silver.
  • FIG. 3A is a diagram showing a first semiconductor layer material film forming step and a lift-off layer forming step in the method for manufacturing a solar cell according to the present embodiment
  • FIGS. 3B to 3D are views for manufacturing the solar cell according to the present embodiment. It is a figure which shows the 1st semiconductor layer formation process in a method.
  • FIG. 3E is a diagram showing a second semiconductor layer material film forming step in the method for manufacturing a solar cell according to the present embodiment
  • FIG. 3A is a diagram showing a first semiconductor layer material film forming step and a lift-off layer forming step in the method for manufacturing a solar cell according to the present embodiment
  • FIGS. 3B to 3D are views for manufacturing the solar cell according to the present embodiment. It is a figure which shows the 1st semiconductor layer formation process in a method.
  • FIG. 3E is a diagram showing a second semiconductor layer material film forming step in the method for manufacturing a solar cell according to the present embodiment
  • FIG. 3F is a diagram showing a second semiconductor layer in the method for manufacturing a solar cell according to the present embodiment. It is a figure which shows the forming process. Further, FIG. 3G is a diagram showing an electrode layer forming step in the method for manufacturing a solar cell according to the present embodiment.
  • the first intrinsic semiconductor layer material film 23Z and the first conductive semiconductor layer material film 25Z are laminated in order on the entire back surface side of the semiconductor substrate 11 (film formation). ) (First semiconductor layer material film forming step). Further, for example, using a CVD method, the intrinsic semiconductor layer 13 and the optical adjustment layer 15 are laminated (film-formed) in order on the entire surface of the semiconductor substrate 11 on the light receiving surface side.
  • a lift-off layer (sacrificial layer) 40 is laminated (film formation) on the entire surface of the back surface side of the semiconductor substrate 11, specifically, on the entire surface of the first conductive semiconductor layer material film 25Z. ) (Lift-off layer forming process).
  • the lift-off layer 40 is formed of a material such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON).
  • hydrofluoric acid treatment treatment with hydrofluoric acid or a mixture of hydrofluoric acid and other types of acids.
  • the lift-off layer 40 in the second region 8 on the back surface side of the semiconductor substrate 11, the lift-off layer 40 in the second region 8, the first conductive semiconductor layer material film 25Z, and the first conductive semiconductor layer material film 25Z.
  • the first intrinsic semiconductor layer 23, the patterned first conductive semiconductor layer 25, and the lift-off layer 40 are formed in the first region 7 by removing a part of the material film 23Z in the film thickness direction. (First semiconductor layer forming step).
  • a resist 90 is formed in the first region 7 on the back surface side of the semiconductor substrate 11 by using a photolithography technique. Then, the lift-off layer 40 in the second region 8 is etched using the resist 90 as a mask to form the patterned lift-off layer 40 in the first region 7.
  • the etching solution for the lift-off layer 40 for example, hydrofluoric acid or a mixture of hydrofluoric acid and another kind of acid is used.
  • the first conductive semiconductor layer material film 25Z and the first intrinsic semiconductor layer material film 23Z in the second region 8 are masked by the resist 90 and the patterned lift-off layer 40.
  • a first intrinsic semiconductor layer 23 and a patterned first conductive semiconductor layer 25 are formed in the first region 7 by etching a part in the film thickness direction.
  • an acidic solution such as a mixed solution of ozone dissolved in hydrofluoric acid or a mixed solution of hydrofluoric acid and nitric acid is used. Be done.
  • the resist 90 is removed.
  • An organic solvent such as acetone is used as the etching solution for the resist 90.
  • the substrate cleaning step for example, ozone treatment is followed by hydrofluoric acid treatment.
  • the hydrofluoric acid treatment includes not only hydrofluoric acid but also treatment with a mixture of hydrofluoric acid and other types of acids.
  • the lift-off layer 40 is etched, and the film thickness of the lift-off layer 40 is reduced.
  • the lift-off property of the lift-off layer 40 is lowered in the patterning of the second conductive semiconductor layer 35 (for example, the lift-off layer is formed before the patterning of the second conductive semiconductor layer 35). It will be peeled off, and the lift-off process will not be performed normally in the patterning of the second conductive semiconductor layer 35).
  • the lift-off layer 40 is not etched by the cleaning solution (for example, hydrofluoric acid) in the substrate cleaning step, and the film thickness of the lift-off layer 40 is not reduced. As a result, it is possible to avoid a decrease in lift-off property due to the lift-off layer 40.
  • the cleaning solution for example, hydrofluoric acid
  • a resist is used to etch a part of the first conductive semiconductor layer material film and the first intrinsic semiconductor layer material film in the second region in the film thickness direction. After forming the first intrinsic semiconductor layer and the patterned first conductive semiconductor layer in the first region, the resist is removed. In this case, the etching solution for removing the resist touches the surface of the first intrinsic semiconductor layer in the second region, which reduces the lifetime and increases the contact resistance on the surface of the first intrinsic semiconductor layer. ..
  • the lift-off layer 40 may be effectively used to solve this problem.
  • the resist 90 may be removed after forming the patterned lift-off layer 40 in the first region 7 by etching the lift-off layer 40 in the second region 8 with the resist 90.
  • the patterned lift-off layer 40 is used as a mask, and a part of the first conductive semiconductor layer material film 25Z and the first intrinsic semiconductor layer material film 23Z in the second region 8 in the film thickness direction is etched.
  • the first intrinsic semiconductor layer 23 and the patterned first conductive semiconductor layer 25 are formed in the first region 7.
  • the etching solution for removing the resist 90 comes into contact with the first conductive semiconductor layer material film 25Z of the portion to be removed, and the etching solution does not come into contact with the first intrinsic semiconductor layer 23. Therefore, it is possible to avoid a decrease in lifetime and an increase in contact resistance on the surface of the first intrinsic semiconductor layer.
  • a dry etching method mainly composed of an etching gas for example, a plasma etching method using a gas mainly composed of hydrogen is used, and the lift-off layer 40 in the second region 8 is used.
  • the first intrinsic semiconductor layer 23 is patterned in the first region 7 by etching a part of the first conductive semiconductor layer material film 25Z and the first intrinsic semiconductor layer material film 23Z in the film thickness direction.
  • the first conductive semiconductor layer 25 and the lift-off layer 40 may be formed.
  • a metal mask is used instead of the resist. This facilitates control to stop etching in the middle of the film thickness direction of the first intrinsic semiconductor layer material film 23Z.
  • the lift-off layer 40 in the second region 8 is etched with a metal mask to form the patterned lift-off layer 40 in the first region 7, and then the patterned lift-off layer 40 is formed.
  • the metal mask is removed, and a part of the first conductive semiconductor layer material film 25Z and the first intrinsic semiconductor layer material film 23Z in the second region 8 in the film thickness direction is etched using the patterned lift-off layer 40 as a mask. By doing so, the first intrinsic semiconductor layer 23 and the patterned first conductive semiconductor layer 25 may be formed in the first region 7.
  • plasma etching Compared with etching with hydrofluoric acid or a mixture containing hydrofluoric acid, plasma etching has less selectivity in etching rate between the lift-off layer and the first conductive semiconductor layer, and both can be etched by several nm. Therefore, plasma etching may be performed using the lift-off layer 40 as a mask.
  • the second intrinsic semiconductor layer material film 33Z and the second conductive semiconductor layer material film 35Z are laminated (film-formed) in this order on the layer 23 (second semiconductor layer material film forming step).
  • the conductive semiconductor layer material film 35Z is removed, and the first intrinsic semiconductor layer 23, the patterned second intrinsic semiconductor layer 33, and the second conductive semiconductor layer 35 are formed in the second region 8 (second semiconductor layer). Formation process).
  • the second intrinsic semiconductor layer material film 33Z and the second conductive semiconductor layer material film 35Z on the lift-off layer 40 are removed, and the second intrinsic semiconductor layer 33 and the second.
  • the conductive semiconductor layer 35 is formed.
  • an acidic solution such as hydrofluoric acid is used.
  • the first electrode layer 27 and the second electrode layer 37 are formed on the back surface side of the semiconductor substrate 11 (electrode layer forming step).
  • a PVD method such as a sputtering method is used to laminate (form) a transparent electrode layer material film on the entire surface of the back surface side of the semiconductor substrate 11.
  • the transparent electrode layers 28 and 38 are patterned by removing a part of the transparent electrode layer material film by, for example, an etching method using an etching paste.
  • the etching solution for the transparent electrode layer material film for example, hydrochloric acid or an aqueous ferric chloride solution is used.
  • a metal electrode layer 29 is formed on the transparent electrode layer 28, and a metal electrode layer 39 is formed on the transparent electrode layer 38, whereby the first electrode layer 27 and The second electrode layer 37 is formed.
  • the back electrode type solar cell 1 of the present embodiment shown in FIGS. 1 and 2 can be obtained.
  • the second conductive semiconductor layer 35 utilizes the lift-off method using the lift-off layer (sacrificial layer) 40. Since the patterning is performed, the manufacturing process of the solar cell can be simplified and the cost can be reduced.
  • the lift-off layer 40 is not etched by the cleaning solution (for example, hydrofluoric acid) in the substrate cleaning step, and the film thickness of the lift-off layer 40 is not reduced. As a result, it is possible to avoid a decrease in lift-off property due to the lift-off layer 40, and it is possible to avoid a decrease in the yield of the solar cell.
  • the cleaning solution for example, hydrofluoric acid
  • the material film of the first conductive semiconductor layer and the material of the first intrinsic semiconductor layer in the second region are used by using the resist in the first semiconductor layer forming step.
  • the resist is removed after the first intrinsic semiconductor layer and the patterned first conductive semiconductor layer are formed in the first region.
  • the resist removing solution comes into contact with the first intrinsic semiconductor layer in the second region, resulting in a decrease in lifetime and an increase in contact resistance on the surface of the first intrinsic semiconductor layer.
  • the lift-off layer 40 in the second region 8 is removed by using the resist 90, so that the pattern is formed in the first region 7.
  • the resist 90 is removed, and the first conductive semiconductor layer material film 25Z and the first intrinsic semiconductor layer material in the second region 8 are used as a mask with the patterned lift-off layer 40.
  • the first intrinsic semiconductor layer 23 and the patterned first conductive semiconductor layer 25 are formed in the first region 7.
  • the resist removing solution touches the first conductive semiconductor layer material film 25Z of the portion to be removed, and the resist removing solution does not touch the first intrinsic semiconductor layer 23. Therefore, it is possible to avoid a decrease in lifetime and an increase in contact resistance on the surface of the first intrinsic semiconductor layer.
  • the first semiconductor layer forming step it is difficult to stop the etching of the first intrinsic semiconductor layer in the middle by the etching method using the etching solution.
  • a dry etching method mainly containing an etching gas for example, a plasma etching method using a gas mainly containing hydrogen is used, and a second method is used.
  • a dry etching method mainly containing an etching gas for example, a plasma etching method using a gas mainly containing hydrogen is used, and a second method is used.
  • the etching of the first intrinsic semiconductor layer if the etching of the first intrinsic semiconductor layer is stopped in the middle of the film thickness direction, the etching causes damage to the first intrinsic semiconductor layer.
  • the damage caused by the etching of the first intrinsic semiconductor layer 23 is recovered by forming the second intrinsic semiconductor layer 33 on the first intrinsic semiconductor layer 23. It is possible to suppress the deterioration of the performance of the solar cell 1.
  • the first conductive semiconductor layer 25 is formed at the boundary between the first region 7 and the second region 8. And the second conductive semiconductor layer 35 overlap each other.
  • the first intrinsic semiconductor layer 23 is not exposed when the second conductive semiconductor layer 35 is patterned, and the damage of the first intrinsic semiconductor layer 23 due to the etching solution of the second conductive semiconductor layer 35 is reduced. can do.
  • the lift-off method using the lift-off layer 40 is used, so that the boundary between the first region 7 and the second region 8 is as shown in FIG. There is no region where the first conductive semiconductor layer 25 and the second conductive semiconductor layer 35 overlap. Therefore, the distance W between the electrodes can be reduced, and as a result, the electrode area can be increased and the resistance can be reduced.
  • an amorphous silicon material is exemplified as the material of the first intrinsic semiconductor layer 23 and the second intrinsic semiconductor layer 33.
  • the second intrinsic semiconductor layer 33 may contain a microcrystalline material and may further contain a trace amount of a second conductive type dopant (for example, N-type phosphorus).
  • the resistance of the second intrinsic semiconductor layer 33 can be reduced. Therefore, even if the total film thickness of the first intrinsic semiconductor layer 23 and the second intrinsic semiconductor layer 33 in the second region 8 is thick, the increase in the total resistance of the first intrinsic semiconductor layer 23 and the second intrinsic semiconductor layer 33 is reduced. be able to. Further, according to the solar cell 1 of this modification, the etching rates of the first intrinsic semiconductor layer 23 and the second intrinsic semiconductor layer 33 can be different, so that the damage of the first intrinsic semiconductor layer 23 due to the etching can be caused. It can be reduced.
  • the second intrinsic semiconductor layer material film 33Z and the second intrinsic semiconductor layer 33 are formed with a second conductive type. Dopant may be included.
  • the modified solar cell 1 may be manufactured by a manufacturing method that uses a lift-off layer (sacrificial layer) and does not utilize the lift-off method.
  • the method for manufacturing a solar cell according to the above-described embodiment does not include a lift-off layer forming step.
  • the first semiconductor layer forming step the first conductive type semiconductor layer material film 25Z and a part of the first intrinsic semiconductor layer material film 23Z in the second region 8 in the film thickness direction are removed.
  • a first intrinsic semiconductor layer 23 and a patterned first conductive semiconductor layer 25 are formed in the region 7.
  • the second intrinsic semiconductor layer material film 33Z and the second intrinsic semiconductor layer material film 33Z are placed on the first conductive semiconductor layer 25 in the first region 7 and on the first intrinsic semiconductor layer 23 in the second region 8.
  • 2 Conductive semiconductor layer material film 35Z is formed.
  • the second intrinsic semiconductor layer material film 35Z and the second intrinsic semiconductor layer 33 in the first region 7 are removed to form the second intrinsic pattern in the second region 8.
  • the semiconductor layer 33 and the second conductive semiconductor layer 35 are formed.
  • FIG. 1 A modified example solar cell 1 manufactured in this manner is shown in FIG.
  • the first conductive semiconductor layer 25 and the second conductive semiconductor layer 35 overlap each other at the boundary between the first region 7 and the second region 8.
  • the first intrinsic semiconductor layer 23 is not exposed when the second conductive semiconductor layer 35 is patterned, and the damage of the first intrinsic semiconductor layer 23 due to the etching solution of the second conductive semiconductor layer 35 is reduced. can do.
  • the present invention is not limited to the above-described embodiments, and various modifications and modifications can be made.
  • the method for manufacturing the heterozygous solar cell 1 has been illustrated as shown in FIGS. 2 and 4, but the feature of the present invention is not limited to the heterozygous solar cell and is homozygous. It can be applied to various methods for manufacturing solar cells such as solar cells of the type.
  • a solar cell having a crystalline silicon substrate has been exemplified, but the present invention is not limited to this.
  • a solar cell may have a gallium arsenide (GaAs) substrate.
  • GaAs gallium arsenide

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Abstract

La présente invention concerne un procédé de fabrication d'une cellule solaire dans lequel une diminution de la performance de décollement par une couche de décollement est évitée. Le procédé de fabrication d'une cellule solaire comprend : une étape consistant à former, sur le côté de surface arrière d'un substrat semi-conducteur (11), un film de matériau pour une première couche semi-conductrice intrinsèque, un film de matériau pour une couche semi-conductrice de premier type de conductivité, et une couche de décollement ; une étape pour retirer, dans une seconde région (8), la couche de décollement, le film de matériau pour la couche semi-conductrice de premier type de conductivité, et une partie, par rapport à la direction de l'épaisseur du film, du film de matériau pour la première couche semi-conductrice intrinsèque et former, dans une première région (7), la première couche semi-conductrice intrinsèque (23), la couche semi-conductrice de premier type de conductivité (25), et la couche de décollement (40) ; une étape de formation d'un film de matériau (33Z) pour une seconde couche semi-conductrice intrinsèque et un film de matériau (35Z) pour une couche semi-conductrice de second type de conductivité sur la première couche semi-conductrice intrinsèque (23) dans la seconde région (8) et la couche de décollement (40) dans la première région (7) ; et une étape de retrait de la couche de décollement (40), le retrait du film de matériau (33Z) pour la seconde couche semi-conductrice intrinsèque et le film de matériau (35Z) pour la couche semi-conductrice de second type de conductivité dans la première région (7), et la formation, dans la seconde région (8), de la première couche semi-conductrice intrinsèque (23), de la seconde couche semi-conductrice intrinsèque et de la couche semi-conductrice de second type de conductivité.
PCT/JP2020/015915 2019-04-23 2020-04-09 Procédé de fabrication de cellule solaire et cellule solaire WO2020217999A1 (fr)

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010129872A (ja) * 2008-11-28 2010-06-10 Kyocera Corp 太陽電池素子
JP2013191656A (ja) * 2012-03-13 2013-09-26 Sharp Corp 光電変換素子およびその製造方法
JP2014056918A (ja) * 2012-09-12 2014-03-27 Sharp Corp 光電変換素子および光電変換素子の製造方法
JP2014072209A (ja) * 2012-09-27 2014-04-21 Sharp Corp 光電変換素子および光電変換素子の製造方法
JP2014075526A (ja) * 2012-10-05 2014-04-24 Sharp Corp 光電変換素子および光電変換素子の製造方法
WO2014157525A1 (fr) * 2013-03-28 2014-10-02 シャープ株式会社 Élément de conversion photoélectrique
WO2016076300A1 (fr) * 2014-11-14 2016-05-19 シャープ株式会社 Élément de conversion photoélectrique
JP2016127252A (ja) * 2014-12-31 2016-07-11 新日光能源科技股▲ふん▼有限公司 ヘテロ接合型太陽電池及びその製造方法
JP2017157781A (ja) * 2016-03-04 2017-09-07 シャープ株式会社 光電変換素子および光電変換素子の製造方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010129872A (ja) * 2008-11-28 2010-06-10 Kyocera Corp 太陽電池素子
JP2013191656A (ja) * 2012-03-13 2013-09-26 Sharp Corp 光電変換素子およびその製造方法
JP2014056918A (ja) * 2012-09-12 2014-03-27 Sharp Corp 光電変換素子および光電変換素子の製造方法
JP2014072209A (ja) * 2012-09-27 2014-04-21 Sharp Corp 光電変換素子および光電変換素子の製造方法
JP2014075526A (ja) * 2012-10-05 2014-04-24 Sharp Corp 光電変換素子および光電変換素子の製造方法
WO2014157525A1 (fr) * 2013-03-28 2014-10-02 シャープ株式会社 Élément de conversion photoélectrique
WO2016076300A1 (fr) * 2014-11-14 2016-05-19 シャープ株式会社 Élément de conversion photoélectrique
JP2016127252A (ja) * 2014-12-31 2016-07-11 新日光能源科技股▲ふん▼有限公司 ヘテロ接合型太陽電池及びその製造方法
JP2017157781A (ja) * 2016-03-04 2017-09-07 シャープ株式会社 光電変換素子および光電変換素子の製造方法

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