WO2020217999A1 - Method for manufacturing solar cell and solar cell - Google Patents

Method for manufacturing solar cell and solar cell Download PDF

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Publication number
WO2020217999A1
WO2020217999A1 PCT/JP2020/015915 JP2020015915W WO2020217999A1 WO 2020217999 A1 WO2020217999 A1 WO 2020217999A1 JP 2020015915 W JP2020015915 W JP 2020015915W WO 2020217999 A1 WO2020217999 A1 WO 2020217999A1
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Prior art keywords
semiconductor layer
layer
region
material film
intrinsic semiconductor
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PCT/JP2020/015915
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French (fr)
Japanese (ja)
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小西　克典
勇人 河▲崎▼
足立　大輔
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株式会社カネカ
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Priority to JP2021515969A priority Critical patent/JP7169440B2/en
Publication of WO2020217999A1 publication Critical patent/WO2020217999A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a method for manufacturing a back electrode type (back contact type) solar cell and a solar cell.
  • Patent Document 1 discloses a back electrode type solar cell.
  • the solar cell described in Patent Document 1 includes a semiconductor substrate that functions as a photoelectric conversion layer, and a first intrinsic semiconductor layer, a first conductive semiconductor layer, and a first electrode layer that are sequentially laminated on a part of the back surface side of the semiconductor substrate.
  • a second intrinsic semiconductor layer, a second conductive semiconductor layer, and a second electrode layer, which are sequentially laminated on the other part on the back surface side of the semiconductor substrate, are provided.
  • a photolithography technique is used in the patterning of the first intrinsic semiconductor layer and the first conductive semiconductor layer (first patterning) and the patterning of the second intrinsic semiconductor layer and the second conductive semiconductor layer (second patterning).
  • the etching method used is used.
  • photoresist coating by the spin coating method for example, photoresist drying, photoresist exposure, photoresist development, etching of a semiconductor layer using a photoresist as a mask, and photoresist peeling are performed. A process was required and the process was complicated.
  • Patent Document 1 knows a technique for simplifying the patterning process by a lift-off method using a lift-off layer (sacrificial layer) in the second patterning.
  • the lift-off layer is formed before the first patterning and is patterned with the semiconductor layer in the first patterning. At the time of this first patterning, the other part on the back surface side of the semiconductor substrate is exposed, so it is necessary to clean the surface of the exposed semiconductor substrate after that.
  • the lift-off layer was etched by the cleaning solution (for example, hydrofluoric acid), and the film thickness of the lift-off layer was sometimes reduced. If the film thickness of the lift-off layer is reduced, the lift-off property of the lift-off layer is reduced in the second patterning (for example, the lift-off layer is peeled off before the second patterning, and the lift-off process is performed in the second patterning. Will not be performed normally).
  • the cleaning solution for example, hydrofluoric acid
  • An object of the present invention is to provide a method for manufacturing a solar cell that avoids a decrease in lift-off property due to a lift-off layer, and a solar cell manufactured by the manufacturing method.
  • a first conductive semiconductor layer is sequentially laminated on a semiconductor substrate and a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate.
  • a back electrode type sun including a first electrode layer, a second conductive semiconductor layer and a second electrode layer sequentially laminated in a second region which is a part of the other main surface side of the semiconductor substrate.
  • a method for manufacturing a battery which is a first semiconductor layer material film forming step of sequentially forming a material film of a first intrinsic semiconductor layer and a material film of the first conductive semiconductor layer on the other main surface side of the semiconductor substrate.
  • the 1st intrinsic semiconductor layer, the patterned first conductive semiconductor layer, and the lift-off layer are formed in the 1st region.
  • the material film of the second intrinsic semiconductor layer and the second conductive semiconductor layer are placed on the lift-off layer in the first region and the first intrinsic semiconductor layer in the second region.
  • the second region includes a second semiconductor layer forming step of forming the first intrinsic semiconductor layer, the patterned second intrinsic semiconductor layer, and the second conductive semiconductor layer.
  • the solar cell according to the present invention includes a semiconductor substrate, a first conductive semiconductor layer and a first conductive semiconductor layer, which are sequentially laminated in a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate.
  • a back electrode type solar cell including an electrode layer, a second conductive semiconductor layer and a second electrode layer sequentially laminated in a second region which is another part of the other main surface side of the semiconductor substrate.
  • the first intrinsic semiconductor layer formed in the first region and the second region on the other main surface side of the semiconductor substrate, and the first intrinsic semiconductor layer formed in the first region.
  • the first conductive semiconductor layer, the second intrinsic semiconductor layer formed on the first intrinsic semiconductor layer in the second region, and the second conductive semiconductor layer are provided, and the second in the second region.
  • the thickness of the 1 intrinsic semiconductor layer is thinner than the thickness of the 1st intrinsic semiconductor layer in the 1st region, and the total thickness of the 1st intrinsic semiconductor layer and the 2nd intrinsic semiconductor layer in the 2nd region is
  • the second intrinsic semiconductor layer is thicker than the thickness of the first intrinsic semiconductor layer in the first region, and contains the second conductive type dopant.
  • the present invention in the method for manufacturing a solar cell, it is possible to avoid a decrease in lift-off property due to the lift-off layer. Further, according to the present invention, it is possible to provide a solar cell manufactured by the manufacturing method.
  • FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG. It is a figure which shows the 1st semiconductor layer material film formation process and lift-off layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment.
  • FIG. 1 is a view of the solar cell according to the present embodiment as viewed from the back surface side.
  • the solar cell 1 shown in FIG. 1 is a back electrode type solar cell.
  • the solar cell 1 includes a semiconductor substrate 11 having two main surfaces, and has a first region 7 and a second region 8 on the main surface of the semiconductor substrate 11.
  • the first region 7 has a so-called comb-shaped shape, and has a plurality of finger portions 7f corresponding to comb teeth and a bus bar portion 7b corresponding to a support portion of the comb teeth.
  • the bus bar portion 7b extends in the first direction (X direction) along one side of the semiconductor substrate 11, and the finger portion 7f intersects the bus bar portion 7b in the first direction (X direction). It extends in the direction (Y direction).
  • the second region 8 has a so-called comb-shaped shape, and has a plurality of finger portions 8f corresponding to the comb teeth and a bus bar portion 8b corresponding to the support portion of the comb teeth.
  • the bus bar portion 8b extends in the first direction (X direction) along the other side portion facing one side portion of the semiconductor substrate 11, and the finger portion 8f extends from the bus bar portion 8b in the second direction (Y). Extends in the direction).
  • the finger portions 7f and the finger portions 8f are alternately provided in the first direction (X direction).
  • the first region 7 and the second region 8 may be formed in a striped shape.
  • FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG.
  • the solar cell 1 includes a semiconductor substrate 11, an intrinsic semiconductor layer 13 and optics, which are sequentially laminated on the light receiving surface side, which is one of the main surfaces of the semiconductor substrate 11 on the light receiving side.
  • the adjusting layer 15 is provided.
  • the solar cell 1 is a first intrinsic semiconductor layer 23 which is sequentially laminated on a part (first region 7) of the back surface side which is the other main surface of the main surface of the semiconductor substrate 11 opposite to the light receiving surface.
  • a first conductive semiconductor layer 25 and a first electrode layer 27 are provided.
  • the solar cell 1 includes a first intrinsic semiconductor layer 23, a second intrinsic semiconductor layer 33, and a second conductive semiconductor layer 35, which are sequentially laminated on another part (second region 8) on the back surface side of the semiconductor substrate 11. And a second electrode layer 37 is provided.
  • the semiconductor substrate 11 is formed of a crystalline silicon material such as single crystal silicon or polycrystalline silicon.
  • the semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which a crystalline silicon material is doped with an n-type dopant. Examples of the n-type dopant include phosphorus (P).
  • the semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light receiving surface side to generate optical carriers (electrons and holes). By using crystalline silicon as the material of the semiconductor substrate 11, a relatively high output (stable output regardless of the illuminance) can be obtained even when the dark current is relatively small and the intensity of the incident light is low.
  • the intrinsic semiconductor layer 13 is formed on the light receiving surface side of the semiconductor substrate 11.
  • the first intrinsic semiconductor layer 23 is formed in the first region 7 and the second region 8 on the back surface side of the semiconductor substrate 11.
  • the second intrinsic semiconductor layer 33 is formed in the second region 8 on the back surface side of the semiconductor substrate 11, that is, on the first intrinsic semiconductor layer 23 in the second region 8.
  • the film thickness of the first intrinsic semiconductor layer 23 in the second region 8 is thinner than the film thickness of the first intrinsic semiconductor layer 23 in the first region 7. Further, the total film thickness of the first intrinsic semiconductor layer 23 and the second intrinsic semiconductor layer 33 in the second region 8 is thicker than the film thickness of the first intrinsic semiconductor layer 23 in the first region 7.
  • the intrinsic semiconductor layer 13, the first intrinsic semiconductor layer 23, and the second intrinsic semiconductor layer 33 are formed of, for example, a material containing intrinsic (i-type) amorphous silicon as a main component.
  • the intrinsic semiconductor layer 13, the first intrinsic semiconductor layer 23, and the second intrinsic semiconductor layer 33 function as a so-called passivation layer, suppress recombination of carriers generated in the semiconductor substrate 11, and increase carrier recovery efficiency.
  • the optical adjustment layer 15 is formed on the intrinsic semiconductor layer 13 on the light receiving surface side of the semiconductor substrate 11.
  • the optical adjustment layer 15 functions as an antireflection layer for preventing reflection of incident light, and also functions as a protective layer for protecting the light receiving surface side of the semiconductor substrate 11 and the intrinsic semiconductor layer 13.
  • the optical adjustment layer 15 is formed of an insulating material such as a composite thereof such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON).
  • the first conductive semiconductor layer 25 is formed on the first intrinsic semiconductor layer 23 in the first region 7, that is, in the first region 7 on the back surface side of the semiconductor substrate 11.
  • the first conductive semiconductor layer 25 is formed of, for example, an amorphous silicon material.
  • the first conductive semiconductor layer 25 is, for example, a p-type semiconductor layer in which an amorphous silicon material is doped with a p-type dopant. Examples of the p-type dopant include boron (B).
  • the second conductive semiconductor layer 35 is formed on the second intrinsic semiconductor layer 33, that is, in the second region 8 on the back surface side of the semiconductor substrate 11.
  • the second conductive semiconductor layer 35 is formed of, for example, an amorphous silicon material.
  • the second conductive semiconductor layer 35 is, for example, an n-type semiconductor layer in which an amorphous silicon material is doped with an n-type dopant (for example, phosphorus (P) described above).
  • the first conductive semiconductor layer 25 may be an n-type semiconductor layer
  • the second conductive semiconductor layer 35 may be a p-type semiconductor layer
  • the semiconductor substrate 11 may be a p-type semiconductor substrate in which a crystalline silicon material is doped with a p-type dopant (for example, the above-mentioned boron (B)).
  • the first electrode layer 27 is formed on the first conductive semiconductor layer 25, and the second electrode layer 37 is formed on the second conductive semiconductor layer 35.
  • the first electrode layer 27 has a transparent electrode layer 28 and a metal electrode layer 29, which are sequentially laminated on the first conductive semiconductor layer 25.
  • the second electrode layer 37 has a transparent electrode layer 38 and a metal electrode layer 39, which are sequentially laminated on the second conductive semiconductor layer 35.
  • the transparent electrode layers 28 and 38 are formed of a transparent conductive material. Examples of the transparent conductive material include ITO (Indium Tin Oxide: a composite oxide of indium tin oxide and tin oxide) and ZnO (Zinc Oxide: zinc oxide).
  • the metal electrode layers 29 and 39 are formed of a conductive paste material containing a metal powder such as silver.
  • FIG. 3A is a diagram showing a first semiconductor layer material film forming step and a lift-off layer forming step in the method for manufacturing a solar cell according to the present embodiment
  • FIGS. 3B to 3D are views for manufacturing the solar cell according to the present embodiment. It is a figure which shows the 1st semiconductor layer formation process in a method.
  • FIG. 3E is a diagram showing a second semiconductor layer material film forming step in the method for manufacturing a solar cell according to the present embodiment
  • FIG. 3A is a diagram showing a first semiconductor layer material film forming step and a lift-off layer forming step in the method for manufacturing a solar cell according to the present embodiment
  • FIGS. 3B to 3D are views for manufacturing the solar cell according to the present embodiment. It is a figure which shows the 1st semiconductor layer formation process in a method.
  • FIG. 3E is a diagram showing a second semiconductor layer material film forming step in the method for manufacturing a solar cell according to the present embodiment
  • FIG. 3F is a diagram showing a second semiconductor layer in the method for manufacturing a solar cell according to the present embodiment. It is a figure which shows the forming process. Further, FIG. 3G is a diagram showing an electrode layer forming step in the method for manufacturing a solar cell according to the present embodiment.
  • the first intrinsic semiconductor layer material film 23Z and the first conductive semiconductor layer material film 25Z are laminated in order on the entire back surface side of the semiconductor substrate 11 (film formation). ) (First semiconductor layer material film forming step). Further, for example, using a CVD method, the intrinsic semiconductor layer 13 and the optical adjustment layer 15 are laminated (film-formed) in order on the entire surface of the semiconductor substrate 11 on the light receiving surface side.
  • a lift-off layer (sacrificial layer) 40 is laminated (film formation) on the entire surface of the back surface side of the semiconductor substrate 11, specifically, on the entire surface of the first conductive semiconductor layer material film 25Z. ) (Lift-off layer forming process).
  • the lift-off layer 40 is formed of a material such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON).
  • hydrofluoric acid treatment treatment with hydrofluoric acid or a mixture of hydrofluoric acid and other types of acids.
  • the lift-off layer 40 in the second region 8 on the back surface side of the semiconductor substrate 11, the lift-off layer 40 in the second region 8, the first conductive semiconductor layer material film 25Z, and the first conductive semiconductor layer material film 25Z.
  • the first intrinsic semiconductor layer 23, the patterned first conductive semiconductor layer 25, and the lift-off layer 40 are formed in the first region 7 by removing a part of the material film 23Z in the film thickness direction. (First semiconductor layer forming step).
  • a resist 90 is formed in the first region 7 on the back surface side of the semiconductor substrate 11 by using a photolithography technique. Then, the lift-off layer 40 in the second region 8 is etched using the resist 90 as a mask to form the patterned lift-off layer 40 in the first region 7.
  • the etching solution for the lift-off layer 40 for example, hydrofluoric acid or a mixture of hydrofluoric acid and another kind of acid is used.
  • the first conductive semiconductor layer material film 25Z and the first intrinsic semiconductor layer material film 23Z in the second region 8 are masked by the resist 90 and the patterned lift-off layer 40.
  • a first intrinsic semiconductor layer 23 and a patterned first conductive semiconductor layer 25 are formed in the first region 7 by etching a part in the film thickness direction.
  • an acidic solution such as a mixed solution of ozone dissolved in hydrofluoric acid or a mixed solution of hydrofluoric acid and nitric acid is used. Be done.
  • the resist 90 is removed.
  • An organic solvent such as acetone is used as the etching solution for the resist 90.
  • the substrate cleaning step for example, ozone treatment is followed by hydrofluoric acid treatment.
  • the hydrofluoric acid treatment includes not only hydrofluoric acid but also treatment with a mixture of hydrofluoric acid and other types of acids.
  • the lift-off layer 40 is etched, and the film thickness of the lift-off layer 40 is reduced.
  • the lift-off property of the lift-off layer 40 is lowered in the patterning of the second conductive semiconductor layer 35 (for example, the lift-off layer is formed before the patterning of the second conductive semiconductor layer 35). It will be peeled off, and the lift-off process will not be performed normally in the patterning of the second conductive semiconductor layer 35).
  • the lift-off layer 40 is not etched by the cleaning solution (for example, hydrofluoric acid) in the substrate cleaning step, and the film thickness of the lift-off layer 40 is not reduced. As a result, it is possible to avoid a decrease in lift-off property due to the lift-off layer 40.
  • the cleaning solution for example, hydrofluoric acid
  • a resist is used to etch a part of the first conductive semiconductor layer material film and the first intrinsic semiconductor layer material film in the second region in the film thickness direction. After forming the first intrinsic semiconductor layer and the patterned first conductive semiconductor layer in the first region, the resist is removed. In this case, the etching solution for removing the resist touches the surface of the first intrinsic semiconductor layer in the second region, which reduces the lifetime and increases the contact resistance on the surface of the first intrinsic semiconductor layer. ..
  • the lift-off layer 40 may be effectively used to solve this problem.
  • the resist 90 may be removed after forming the patterned lift-off layer 40 in the first region 7 by etching the lift-off layer 40 in the second region 8 with the resist 90.
  • the patterned lift-off layer 40 is used as a mask, and a part of the first conductive semiconductor layer material film 25Z and the first intrinsic semiconductor layer material film 23Z in the second region 8 in the film thickness direction is etched.
  • the first intrinsic semiconductor layer 23 and the patterned first conductive semiconductor layer 25 are formed in the first region 7.
  • the etching solution for removing the resist 90 comes into contact with the first conductive semiconductor layer material film 25Z of the portion to be removed, and the etching solution does not come into contact with the first intrinsic semiconductor layer 23. Therefore, it is possible to avoid a decrease in lifetime and an increase in contact resistance on the surface of the first intrinsic semiconductor layer.
  • a dry etching method mainly composed of an etching gas for example, a plasma etching method using a gas mainly composed of hydrogen is used, and the lift-off layer 40 in the second region 8 is used.
  • the first intrinsic semiconductor layer 23 is patterned in the first region 7 by etching a part of the first conductive semiconductor layer material film 25Z and the first intrinsic semiconductor layer material film 23Z in the film thickness direction.
  • the first conductive semiconductor layer 25 and the lift-off layer 40 may be formed.
  • a metal mask is used instead of the resist. This facilitates control to stop etching in the middle of the film thickness direction of the first intrinsic semiconductor layer material film 23Z.
  • the lift-off layer 40 in the second region 8 is etched with a metal mask to form the patterned lift-off layer 40 in the first region 7, and then the patterned lift-off layer 40 is formed.
  • the metal mask is removed, and a part of the first conductive semiconductor layer material film 25Z and the first intrinsic semiconductor layer material film 23Z in the second region 8 in the film thickness direction is etched using the patterned lift-off layer 40 as a mask. By doing so, the first intrinsic semiconductor layer 23 and the patterned first conductive semiconductor layer 25 may be formed in the first region 7.
  • plasma etching Compared with etching with hydrofluoric acid or a mixture containing hydrofluoric acid, plasma etching has less selectivity in etching rate between the lift-off layer and the first conductive semiconductor layer, and both can be etched by several nm. Therefore, plasma etching may be performed using the lift-off layer 40 as a mask.
  • the second intrinsic semiconductor layer material film 33Z and the second conductive semiconductor layer material film 35Z are laminated (film-formed) in this order on the layer 23 (second semiconductor layer material film forming step).
  • the conductive semiconductor layer material film 35Z is removed, and the first intrinsic semiconductor layer 23, the patterned second intrinsic semiconductor layer 33, and the second conductive semiconductor layer 35 are formed in the second region 8 (second semiconductor layer). Formation process).
  • the second intrinsic semiconductor layer material film 33Z and the second conductive semiconductor layer material film 35Z on the lift-off layer 40 are removed, and the second intrinsic semiconductor layer 33 and the second.
  • the conductive semiconductor layer 35 is formed.
  • an acidic solution such as hydrofluoric acid is used.
  • the first electrode layer 27 and the second electrode layer 37 are formed on the back surface side of the semiconductor substrate 11 (electrode layer forming step).
  • a PVD method such as a sputtering method is used to laminate (form) a transparent electrode layer material film on the entire surface of the back surface side of the semiconductor substrate 11.
  • the transparent electrode layers 28 and 38 are patterned by removing a part of the transparent electrode layer material film by, for example, an etching method using an etching paste.
  • the etching solution for the transparent electrode layer material film for example, hydrochloric acid or an aqueous ferric chloride solution is used.
  • a metal electrode layer 29 is formed on the transparent electrode layer 28, and a metal electrode layer 39 is formed on the transparent electrode layer 38, whereby the first electrode layer 27 and The second electrode layer 37 is formed.
  • the back electrode type solar cell 1 of the present embodiment shown in FIGS. 1 and 2 can be obtained.
  • the second conductive semiconductor layer 35 utilizes the lift-off method using the lift-off layer (sacrificial layer) 40. Since the patterning is performed, the manufacturing process of the solar cell can be simplified and the cost can be reduced.
  • the lift-off layer 40 is not etched by the cleaning solution (for example, hydrofluoric acid) in the substrate cleaning step, and the film thickness of the lift-off layer 40 is not reduced. As a result, it is possible to avoid a decrease in lift-off property due to the lift-off layer 40, and it is possible to avoid a decrease in the yield of the solar cell.
  • the cleaning solution for example, hydrofluoric acid
  • the material film of the first conductive semiconductor layer and the material of the first intrinsic semiconductor layer in the second region are used by using the resist in the first semiconductor layer forming step.
  • the resist is removed after the first intrinsic semiconductor layer and the patterned first conductive semiconductor layer are formed in the first region.
  • the resist removing solution comes into contact with the first intrinsic semiconductor layer in the second region, resulting in a decrease in lifetime and an increase in contact resistance on the surface of the first intrinsic semiconductor layer.
  • the lift-off layer 40 in the second region 8 is removed by using the resist 90, so that the pattern is formed in the first region 7.
  • the resist 90 is removed, and the first conductive semiconductor layer material film 25Z and the first intrinsic semiconductor layer material in the second region 8 are used as a mask with the patterned lift-off layer 40.
  • the first intrinsic semiconductor layer 23 and the patterned first conductive semiconductor layer 25 are formed in the first region 7.
  • the resist removing solution touches the first conductive semiconductor layer material film 25Z of the portion to be removed, and the resist removing solution does not touch the first intrinsic semiconductor layer 23. Therefore, it is possible to avoid a decrease in lifetime and an increase in contact resistance on the surface of the first intrinsic semiconductor layer.
  • the first semiconductor layer forming step it is difficult to stop the etching of the first intrinsic semiconductor layer in the middle by the etching method using the etching solution.
  • a dry etching method mainly containing an etching gas for example, a plasma etching method using a gas mainly containing hydrogen is used, and a second method is used.
  • a dry etching method mainly containing an etching gas for example, a plasma etching method using a gas mainly containing hydrogen is used, and a second method is used.
  • the etching of the first intrinsic semiconductor layer if the etching of the first intrinsic semiconductor layer is stopped in the middle of the film thickness direction, the etching causes damage to the first intrinsic semiconductor layer.
  • the damage caused by the etching of the first intrinsic semiconductor layer 23 is recovered by forming the second intrinsic semiconductor layer 33 on the first intrinsic semiconductor layer 23. It is possible to suppress the deterioration of the performance of the solar cell 1.
  • the first conductive semiconductor layer 25 is formed at the boundary between the first region 7 and the second region 8. And the second conductive semiconductor layer 35 overlap each other.
  • the first intrinsic semiconductor layer 23 is not exposed when the second conductive semiconductor layer 35 is patterned, and the damage of the first intrinsic semiconductor layer 23 due to the etching solution of the second conductive semiconductor layer 35 is reduced. can do.
  • the lift-off method using the lift-off layer 40 is used, so that the boundary between the first region 7 and the second region 8 is as shown in FIG. There is no region where the first conductive semiconductor layer 25 and the second conductive semiconductor layer 35 overlap. Therefore, the distance W between the electrodes can be reduced, and as a result, the electrode area can be increased and the resistance can be reduced.
  • an amorphous silicon material is exemplified as the material of the first intrinsic semiconductor layer 23 and the second intrinsic semiconductor layer 33.
  • the second intrinsic semiconductor layer 33 may contain a microcrystalline material and may further contain a trace amount of a second conductive type dopant (for example, N-type phosphorus).
  • the resistance of the second intrinsic semiconductor layer 33 can be reduced. Therefore, even if the total film thickness of the first intrinsic semiconductor layer 23 and the second intrinsic semiconductor layer 33 in the second region 8 is thick, the increase in the total resistance of the first intrinsic semiconductor layer 23 and the second intrinsic semiconductor layer 33 is reduced. be able to. Further, according to the solar cell 1 of this modification, the etching rates of the first intrinsic semiconductor layer 23 and the second intrinsic semiconductor layer 33 can be different, so that the damage of the first intrinsic semiconductor layer 23 due to the etching can be caused. It can be reduced.
  • the second intrinsic semiconductor layer material film 33Z and the second intrinsic semiconductor layer 33 are formed with a second conductive type. Dopant may be included.
  • the modified solar cell 1 may be manufactured by a manufacturing method that uses a lift-off layer (sacrificial layer) and does not utilize the lift-off method.
  • the method for manufacturing a solar cell according to the above-described embodiment does not include a lift-off layer forming step.
  • the first semiconductor layer forming step the first conductive type semiconductor layer material film 25Z and a part of the first intrinsic semiconductor layer material film 23Z in the second region 8 in the film thickness direction are removed.
  • a first intrinsic semiconductor layer 23 and a patterned first conductive semiconductor layer 25 are formed in the region 7.
  • the second intrinsic semiconductor layer material film 33Z and the second intrinsic semiconductor layer material film 33Z are placed on the first conductive semiconductor layer 25 in the first region 7 and on the first intrinsic semiconductor layer 23 in the second region 8.
  • 2 Conductive semiconductor layer material film 35Z is formed.
  • the second intrinsic semiconductor layer material film 35Z and the second intrinsic semiconductor layer 33 in the first region 7 are removed to form the second intrinsic pattern in the second region 8.
  • the semiconductor layer 33 and the second conductive semiconductor layer 35 are formed.
  • FIG. 1 A modified example solar cell 1 manufactured in this manner is shown in FIG.
  • the first conductive semiconductor layer 25 and the second conductive semiconductor layer 35 overlap each other at the boundary between the first region 7 and the second region 8.
  • the first intrinsic semiconductor layer 23 is not exposed when the second conductive semiconductor layer 35 is patterned, and the damage of the first intrinsic semiconductor layer 23 due to the etching solution of the second conductive semiconductor layer 35 is reduced. can do.
  • the present invention is not limited to the above-described embodiments, and various modifications and modifications can be made.
  • the method for manufacturing the heterozygous solar cell 1 has been illustrated as shown in FIGS. 2 and 4, but the feature of the present invention is not limited to the heterozygous solar cell and is homozygous. It can be applied to various methods for manufacturing solar cells such as solar cells of the type.
  • a solar cell having a crystalline silicon substrate has been exemplified, but the present invention is not limited to this.
  • a solar cell may have a gallium arsenide (GaAs) substrate.
  • GaAs gallium arsenide

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Abstract

The present invention provides a method for manufacturing a solar cell in which a decrease in the liftoff performance by a liftoff layer is avoided. The method for manufacturing a solar cell includes: a step for forming, on the reverse surface side of a semiconductor substrate (11), a material film for a first intrinsic semiconductor layer, a material film for a first-conductivity-type semiconductor layer, and a liftoff layer; a step for removing, in a second region (8), the liftoff layer, the material film for the first-conductivity-type semiconductor layer, and a part, with respect to the film thickness direction, of the material film for the first intrinsic semiconductor layer and forming, in a first region (7), the first intrinsic semiconductor layer (23), the first-conductivity-type semiconductor layer (25), and the liftoff layer (40); a step for forming a material film (33Z) for a second intrinsic semiconductor layer and a material film (35Z) for a second-conductivity-type semiconductor layer on the first intrinsic semiconductor layer (23) in the second region (8) and the liftoff layer (40) in the first region (7); and a step for removing the liftoff layer (40), removing the material film (33Z) for the second intrinsic semiconductor layer and the material film (35Z) for the second-conductivity-type semiconductor layer in the first region (7), and forming, in the second region (8), the first intrinsic semiconductor layer (23), the second intrinsic semiconductor layer, and the second-conductivity-type semiconductor layer.

Description

太陽電池の製造方法および太陽電池Manufacturing method of solar cells and solar cells
　本発明は、裏面電極型（バックコンタクト型）の太陽電池の製造方法および太陽電池に関する。 The present invention relates to a method for manufacturing a back electrode type (back contact type) solar cell and a solar cell.
　半導体基板を用いた太陽電池として、受光面側および裏面側の両面に電極が形成された両面電極型の太陽電池と、裏面側のみに電極が形成された裏面電極型の太陽電池とがある。両面電極型の太陽電池では、受光面側に電極が形成されるため、この電極により太陽光が遮蔽されてしまう。一方、裏面電極型の太陽電池では、受光面側に電極が形成されないため、両面電極型の太陽電池と比較して太陽光の受光率が高い。特許文献１には、裏面電極型の太陽電池が開示されている。 As solar cells using a semiconductor substrate, there are a double-sided electrode type solar cell in which electrodes are formed on both the light receiving surface side and the back surface side, and a back surface electrode type solar cell in which electrodes are formed only on the back surface side. In a double-sided electrode type solar cell, since an electrode is formed on the light receiving surface side, sunlight is shielded by this electrode. On the other hand, in the back electrode type solar cell, since the electrode is not formed on the light receiving surface side, the light receiving rate of sunlight is higher than that of the double-sided electrode type solar cell. Patent Document 1 discloses a back electrode type solar cell.
　特許文献１に記載の太陽電池は、光電変換層として機能する半導体基板と、半導体基板の裏面側の一部に順に積層された第１真性半導体層、第１導電型半導体層および第１電極層と、半導体基板の裏面側の他の一部に順に積層された第２真性半導体層、第２導電型半導体層および第２電極層とを備える。 The solar cell described in Patent Document 1 includes a semiconductor substrate that functions as a photoelectric conversion layer, and a first intrinsic semiconductor layer, a first conductive semiconductor layer, and a first electrode layer that are sequentially laminated on a part of the back surface side of the semiconductor substrate. A second intrinsic semiconductor layer, a second conductive semiconductor layer, and a second electrode layer, which are sequentially laminated on the other part on the back surface side of the semiconductor substrate, are provided.
特開２０１４－７５５２６号公報Japanese Unexamined Patent Publication No. 2014-75526
　一般に、第１真性半導体層および第１導電型半導体層のパターニング（１回目のパターニング）と、第２真性半導体層および第２導電型半導体層のパターニング（２回目のパターニング）において、フォトリソグラフィ技術を用いたエッチング法が用いられる。しかし、フォトリソグラフィ技術を用いたエッチング法では、例えばスピンコート法によるフォトレジスト塗布、フォトレジスト乾燥、フォトレジスト露光、フォトレジスト現像、フォトレジストをマスクとして用いた半導体層のエッチング、およびフォトレジスト剥離のプロセスが必要であり、プロセスが複雑であった。 Generally, in the patterning of the first intrinsic semiconductor layer and the first conductive semiconductor layer (first patterning) and the patterning of the second intrinsic semiconductor layer and the second conductive semiconductor layer (second patterning), a photolithography technique is used. The etching method used is used. However, in the etching method using the photoresist technique, for example, photoresist coating by the spin coating method, photoresist drying, photoresist exposure, photoresist development, etching of a semiconductor layer using a photoresist as a mask, and photoresist peeling are performed. A process was required and the process was complicated.
　この点に関し、特許文献１には、２回目のパターニングにおいて、リフトオフ層（犠牲層）を用いたリフトオフ法により、パターニングのプロセスの簡略化を図る技術が知られている。リフトオフ層は、１回目のパターニングの前に形成され、１回目のパターニングにおいて半導体層とともにパターニングされる。この１回目のパターニングの際、半導体基板の裏面側の他の一部が露出するため、その後、露出した半導体基板の表面を洗浄する必要がある。 Regarding this point, Patent Document 1 knows a technique for simplifying the patterning process by a lift-off method using a lift-off layer (sacrificial layer) in the second patterning. The lift-off layer is formed before the first patterning and is patterned with the semiconductor layer in the first patterning. At the time of this first patterning, the other part on the back surface side of the semiconductor substrate is exposed, so it is necessary to clean the surface of the exposed semiconductor substrate after that.
　この基板洗浄工程において、洗浄溶液（例えば、フッ酸）によりリフトオフ層がエッチングされ、リフトオフ層の膜厚が減少してしまうことがあった。リフトオフ層の膜厚が減少すると、２回目のパターニングにおいて、リフトオフ層によるリフトオフ性が低下してしまう（例えば、２回目のパターニングの前にリフトオフ層が剥離してしまい、２回目のパターニングにおいてリフトオフプロセスが正常に行われなくなってしまう）。 In this substrate cleaning step, the lift-off layer was etched by the cleaning solution (for example, hydrofluoric acid), and the film thickness of the lift-off layer was sometimes reduced. If the film thickness of the lift-off layer is reduced, the lift-off property of the lift-off layer is reduced in the second patterning (for example, the lift-off layer is peeled off before the second patterning, and the lift-off process is performed in the second patterning. Will not be performed normally).
　本発明は、リフトオフ層によるリフトオフ性の低下を回避する太陽電池の製造方法、およびその製造方法によって製造された太陽電池を提供することを目的とする。 An object of the present invention is to provide a method for manufacturing a solar cell that avoids a decrease in lift-off property due to a lift-off layer, and a solar cell manufactured by the manufacturing method.
　本発明に係る太陽電池の製造方法は、半導体基板と、前記半導体基板の一方主面側と反対側の他方主面側の一部である第１領域に順に積層された第１導電型半導体層および第１電極層と、前記半導体基板の前記他方主面側の他の一部である第２領域に順に積層された第２導電型半導体層および第２電極層とを備える裏面電極型の太陽電池の製造方法であって、前記半導体基板の前記他方主面側に、第１真性半導体層の材料膜および前記第１導電型半導体層の材料膜を順に形成する第１半導体層材料膜形成工程と、前記第１導電型半導体層の材料膜の上に、リフトオフ層を形成するリフトオフ層形成工程と、前記第２領域における前記リフトオフ層、前記第１導電型半導体層の材料膜、および前記第１真性半導体層の材料膜の膜厚方向の一部を除去することにより、前記第１領域に、前記第１真性半導体層、パターン化された前記第１導電型半導体層および前記リフトオフ層を形成する第１半導体層形成工程と、前記第１領域における前記リフトオフ層および前記第２領域における前記第１真性半導体層の上に、第２真性半導体層の材料膜および前記第２導電型半導体層の材料膜を順に形成する第２半導体層材料膜形成工程と、前記リフトオフ層を除去することにより、前記第１領域における前記第２導電型半導体層の材料膜および前記第２真性半導体層の材料膜を除去し、前記第２領域に、前記第１真性半導体層、パターン化された前記第２真性半導体層および前記第２導電型半導体層を形成する第２半導体層形成工程と、を含む。 In the method for manufacturing a solar cell according to the present invention, a first conductive semiconductor layer is sequentially laminated on a semiconductor substrate and a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate. A back electrode type sun including a first electrode layer, a second conductive semiconductor layer and a second electrode layer sequentially laminated in a second region which is a part of the other main surface side of the semiconductor substrate. A method for manufacturing a battery, which is a first semiconductor layer material film forming step of sequentially forming a material film of a first intrinsic semiconductor layer and a material film of the first conductive semiconductor layer on the other main surface side of the semiconductor substrate. A lift-off layer forming step of forming a lift-off layer on the material film of the first conductive semiconductor layer, the lift-off layer in the second region, the material film of the first conductive semiconductor layer, and the first. By removing a part of the material film of the 1 intrinsic semiconductor layer in the film thickness direction, the 1st intrinsic semiconductor layer, the patterned first conductive semiconductor layer, and the lift-off layer are formed in the 1st region. In the first semiconductor layer forming step, the material film of the second intrinsic semiconductor layer and the second conductive semiconductor layer are placed on the lift-off layer in the first region and the first intrinsic semiconductor layer in the second region. A second semiconductor layer material film forming step of sequentially forming a material film, and a material film of the second conductive semiconductor layer and a material film of the second intrinsic semiconductor layer in the first region by removing the lift-off layer. The second region includes a second semiconductor layer forming step of forming the first intrinsic semiconductor layer, the patterned second intrinsic semiconductor layer, and the second conductive semiconductor layer.
　本発明に係る太陽電池は、半導体基板と、前記半導体基板の一方主面側と反対側の他方主面側の一部である第１領域に順に積層された第１導電型半導体層および第１電極層と、前記半導体基板の前記他方主面側の他の一部である第２領域に順に積層された第２導電型半導体層および第２電極層とを備える裏面電極型の太陽電池であって、前記半導体基板の前記他方主面側の前記第１領域および前記第２領域に形成された第１真性半導体層と、前記第１領域における前記第１真性半導体層の上に形成された前記第１導電型半導体層と、前記第２領域における前記第１真性半導体層の上に形成された第２真性半導体層および前記第２導電型半導体層と、を備え、前記第２領域における前記第１真性半導体層の膜厚は、前記第１領域における前記第１真性半導体層の膜厚よりも薄く、前記第２領域における前記第１真性半導体層および前記第２真性半導体層の総膜厚は、前記第１領域における前記第１真性半導体層の膜厚よりも厚く、前記第２真性半導体層は、前記第２導電型のドーパントを含む。 The solar cell according to the present invention includes a semiconductor substrate, a first conductive semiconductor layer and a first conductive semiconductor layer, which are sequentially laminated in a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate. A back electrode type solar cell including an electrode layer, a second conductive semiconductor layer and a second electrode layer sequentially laminated in a second region which is another part of the other main surface side of the semiconductor substrate. The first intrinsic semiconductor layer formed in the first region and the second region on the other main surface side of the semiconductor substrate, and the first intrinsic semiconductor layer formed in the first region. The first conductive semiconductor layer, the second intrinsic semiconductor layer formed on the first intrinsic semiconductor layer in the second region, and the second conductive semiconductor layer are provided, and the second in the second region. The thickness of the 1 intrinsic semiconductor layer is thinner than the thickness of the 1st intrinsic semiconductor layer in the 1st region, and the total thickness of the 1st intrinsic semiconductor layer and the 2nd intrinsic semiconductor layer in the 2nd region is The second intrinsic semiconductor layer is thicker than the thickness of the first intrinsic semiconductor layer in the first region, and contains the second conductive type dopant.
　本発明によれば、太陽電池の製造方法において、リフトオフ層によるリフトオフ性の低下を回避することができる。また、本発明によれば、その製造方法によって製造された太陽電池を提供することができる。 According to the present invention, in the method for manufacturing a solar cell, it is possible to avoid a decrease in lift-off property due to the lift-off layer. Further, according to the present invention, it is possible to provide a solar cell manufactured by the manufacturing method.
本実施形態に係る太陽電池を裏面側からみた図である。It is the figure which looked at the solar cell which concerns on this embodiment from the back side. 図１の太陽電池におけるII－II線断面図である。FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG. 本実施形態に係る太陽電池の製造方法における第１半導体層材料膜形成工程およびリフトオフ層形成工程を示す図である。It is a figure which shows the 1st semiconductor layer material film formation process and lift-off layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. 本実施形態に係る太陽電池の製造方法における第１半導体層形成工程を示す図である。It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. 本実施形態に係る太陽電池の製造方法における第１半導体層形成工程を示す図である。It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. 本実施形態に係る太陽電池の製造方法における第１半導体層形成工程を示す図である。It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. 本実施形態に係る太陽電池の製造方法における第２半導体層材料膜形成工程を示す図である。It is a figure which shows the 2nd semiconductor layer material film formation process in the manufacturing method of the solar cell which concerns on this embodiment. 本実施形態に係る太陽電池の製造方法における第２半導体層形成工程を示す図である。It is a figure which shows the 2nd semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. 本実施形態に係る太陽電池の製造方法における電極層形成工程を示す図である。It is a figure which shows the electrode layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. 本実施形態の変形例に係る太陽電池の断面図であって、図１のII－II線断面に相当する断面図である。It is sectional drawing of the solar cell which concerns on the modification of this Embodiment, and is the sectional view corresponding to the section II-II of FIG.
　以下、添付の図面を参照して本発明の実施形態の一例について説明する。なお、各図面において同一または相当の部分に対しては同一の符号を附すこととする。また、便宜上、ハッチングや部材符号等を省略する場合もあるが、かかる場合、他の図面を参照するものとする。 Hereinafter, an example of the embodiment of the present invention will be described with reference to the accompanying drawings. In addition, the same reference numerals are given to the same or corresponding parts in each drawing. Further, for convenience, hatching, member codes, etc. may be omitted, but in such cases, other drawings shall be referred to.
（太陽電池）
　図１は、本実施形態に係る太陽電池を裏面側からみた図である。図１に示す太陽電池１は、裏面電極型の太陽電池である。太陽電池１は、２つの主面を備える半導体基板１１を備え、半導体基板１１の主面において第１領域７と第２領域８とを有する。 (Solar cell)
FIG. 1 is a view of the solar cell according to the present embodiment as viewed from the back surface side. The solar cell 1 shown in FIG. 1 is a back electrode type solar cell. The solar cell 1 includes a semiconductor substrate 11 having two main surfaces, and has a first region 7 and a second region 8 on the main surface of the semiconductor substrate 11.
　第１領域７は、いわゆる櫛型の形状をなし、櫛歯に相当する複数のフィンガー部７ｆと、櫛歯の支持部に相当するバスバー部７ｂとを有する。バスバー部７ｂは、半導体基板１１の一方の辺部に沿って第１方向（Ｘ方向）に延在し、フィンガー部７ｆは、バスバー部７ｂから、第１方向（Ｘ方向）に交差する第２方向（Ｙ方向）に延在する。
　同様に、第２領域８は、いわゆる櫛型の形状であり、櫛歯に相当する複数のフィンガー部８ｆと、櫛歯の支持部に相当するバスバー部８ｂとを有する。バスバー部８ｂは、半導体基板１１の一方の辺部に対向する他方の辺部に沿って第１方向（Ｘ方向）に延在し、フィンガー部８ｆは、バスバー部８ｂから、第２方向（Ｙ方向）に延在する。
　フィンガー部７ｆとフィンガー部８ｆとは、第１方向（Ｘ方向）に交互に設けられている。
　なお、第１領域７および第２領域８は、ストライプ状に形成されてもよい。 The first region 7 has a so-called comb-shaped shape, and has a plurality of finger portions 7f corresponding to comb teeth and a bus bar portion 7b corresponding to a support portion of the comb teeth. The bus bar portion 7b extends in the first direction (X direction) along one side of the semiconductor substrate 11, and the finger portion 7f intersects the bus bar portion 7b in the first direction (X direction). It extends in the direction (Y direction).
Similarly, the second region 8 has a so-called comb-shaped shape, and has a plurality of finger portions 8f corresponding to the comb teeth and a bus bar portion 8b corresponding to the support portion of the comb teeth. The bus bar portion 8b extends in the first direction (X direction) along the other side portion facing one side portion of the semiconductor substrate 11, and the finger portion 8f extends from the bus bar portion 8b in the second direction (Y). Extends in the direction).
The finger portions 7f and the finger portions 8f are alternately provided in the first direction (X direction).
The first region 7 and the second region 8 may be formed in a striped shape.
　図２は、図１の太陽電池におけるII－II線断面図である。図２に示すように、太陽電池１は、半導体基板１１と、半導体基板１１の主面のうちの受光する側の一方の主面である受光面側に順に積層された真性半導体層１３および光学調整層１５を備える。また、太陽電池１は、半導体基板１１の主面のうちの受光面の反対側の他方の主面である裏面側の一部（第１領域７）に順に積層された第１真性半導体層２３、第１導電型半導体層２５および第１電極層２７を備える。また、太陽電池１は、半導体基板１１の裏面側の他の一部（第２領域８）に順に積層された第１真性半導体層２３、第２真性半導体層３３、第２導電型半導体層３５および第２電極層３７を備える。 FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG. As shown in FIG. 2, the solar cell 1 includes a semiconductor substrate 11, an intrinsic semiconductor layer 13 and optics, which are sequentially laminated on the light receiving surface side, which is one of the main surfaces of the semiconductor substrate 11 on the light receiving side. The adjusting layer 15 is provided. Further, the solar cell 1 is a first intrinsic semiconductor layer 23 which is sequentially laminated on a part (first region 7) of the back surface side which is the other main surface of the main surface of the semiconductor substrate 11 opposite to the light receiving surface. , A first conductive semiconductor layer 25 and a first electrode layer 27 are provided. Further, the solar cell 1 includes a first intrinsic semiconductor layer 23, a second intrinsic semiconductor layer 33, and a second conductive semiconductor layer 35, which are sequentially laminated on another part (second region 8) on the back surface side of the semiconductor substrate 11. And a second electrode layer 37 is provided.
　半導体基板１１は、単結晶シリコンまたは多結晶シリコン等の結晶シリコン材料で形成される。半導体基板１１は、例えば結晶シリコン材料にｎ型ドーパントがドープされたｎ型の半導体基板である。ｎ型ドーパントとしては、例えばリン（Ｐ）が挙げられる。
　半導体基板１１は、受光面側からの入射光を吸収して光キャリア（電子および正孔）を生成する光電変換基板として機能する。
　半導体基板１１の材料として結晶シリコンが用いられることにより、暗電流が比較的に小さく、入射光の強度が低い場合であっても比較的高出力（照度によらず安定した出力）が得られる。 The semiconductor substrate 11 is formed of a crystalline silicon material such as single crystal silicon or polycrystalline silicon. The semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which a crystalline silicon material is doped with an n-type dopant. Examples of the n-type dopant include phosphorus (P).
The semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light receiving surface side to generate optical carriers (electrons and holes).
By using crystalline silicon as the material of the semiconductor substrate 11, a relatively high output (stable output regardless of the illuminance) can be obtained even when the dark current is relatively small and the intensity of the incident light is low.
　真性半導体層１３は、半導体基板１１の受光面側に形成されている。第１真性半導体層２３は、半導体基板１１の裏面側の第１領域７および第２領域８に形成されている。第２真性半導体層３３は、半導体基板１１の裏面側の第２領域８に、すなわち第２領域８における第１真性半導体層２３上に形成されている。
　第２領域８における第１真性半導体層２３の膜厚は、第１領域７における第１真性半導体層２３の膜厚よりも薄い。また、第２領域８における第１真性半導体層２３および第２真性半導体層３３の総膜厚は、第１領域７における第１真性半導体層２３の膜厚よりも厚い。 The intrinsic semiconductor layer 13 is formed on the light receiving surface side of the semiconductor substrate 11. The first intrinsic semiconductor layer 23 is formed in the first region 7 and the second region 8 on the back surface side of the semiconductor substrate 11. The second intrinsic semiconductor layer 33 is formed in the second region 8 on the back surface side of the semiconductor substrate 11, that is, on the first intrinsic semiconductor layer 23 in the second region 8.
The film thickness of the first intrinsic semiconductor layer 23 in the second region 8 is thinner than the film thickness of the first intrinsic semiconductor layer 23 in the first region 7. Further, the total film thickness of the first intrinsic semiconductor layer 23 and the second intrinsic semiconductor layer 33 in the second region 8 is thicker than the film thickness of the first intrinsic semiconductor layer 23 in the first region 7.
　真性半導体層１３、第１真性半導体層２３および第２真性半導体層３３は、例えば真性（ｉ型）アモルファスシリコンを主成分とする材料で形成される。
　真性半導体層１３、第１真性半導体層２３および第２真性半導体層３３は、いわゆるパッシベーション層として機能し、半導体基板１１で生成されたキャリアの再結合を抑制し、キャリアの回収効率を高める。 The intrinsic semiconductor layer 13, the first intrinsic semiconductor layer 23, and the second intrinsic semiconductor layer 33 are formed of, for example, a material containing intrinsic (i-type) amorphous silicon as a main component.
The intrinsic semiconductor layer 13, the first intrinsic semiconductor layer 23, and the second intrinsic semiconductor layer 33 function as a so-called passivation layer, suppress recombination of carriers generated in the semiconductor substrate 11, and increase carrier recovery efficiency.
　光学調整層１５は、半導体基板１１の受光面側の真性半導体層１３上に形成されている。光学調整層１５は、入射光の反射を防止する反射防止層として機能するとともに、半導体基板１１の受光面側および真性半導体層１３を保護する保護層として機能する。光学調整層１５は、例えば酸化珪素（ＳｉＯ）、窒化珪素（ＳｉＮ）、または酸窒化珪素（ＳｉＯＮ）のようなそれらの複合物等の絶縁体材料で形成される。 The optical adjustment layer 15 is formed on the intrinsic semiconductor layer 13 on the light receiving surface side of the semiconductor substrate 11. The optical adjustment layer 15 functions as an antireflection layer for preventing reflection of incident light, and also functions as a protective layer for protecting the light receiving surface side of the semiconductor substrate 11 and the intrinsic semiconductor layer 13. The optical adjustment layer 15 is formed of an insulating material such as a composite thereof such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON).
　第１導電型半導体層２５は、第１領域７における第１真性半導体層２３上に、すなわち半導体基板１１の裏面側の第１領域７に形成されている。第１導電型半導体層２５は、例えばアモルファスシリコン材料で形成される。第１導電型半導体層２５は、例えばアモルファスシリコン材料にｐ型ドーパントがドープされたｐ型の半導体層である。ｐ型ドーパントとしては、例えばホウ素（Ｂ）が挙げられる。 The first conductive semiconductor layer 25 is formed on the first intrinsic semiconductor layer 23 in the first region 7, that is, in the first region 7 on the back surface side of the semiconductor substrate 11. The first conductive semiconductor layer 25 is formed of, for example, an amorphous silicon material. The first conductive semiconductor layer 25 is, for example, a p-type semiconductor layer in which an amorphous silicon material is doped with a p-type dopant. Examples of the p-type dopant include boron (B).
　第２導電型半導体層３５は、第２真性半導体層３３上に、すなわち半導体基板１１の裏面側の第２領域８に形成されている。第２導電型半導体層３５は、例えばアモルファスシリコン材料で形成される。第２導電型半導体層３５は、例えばアモルファスシリコン材料にｎ型ドーパント（例えば、上述したリン（Ｐ））がドープされたｎ型半導体層である。 The second conductive semiconductor layer 35 is formed on the second intrinsic semiconductor layer 33, that is, in the second region 8 on the back surface side of the semiconductor substrate 11. The second conductive semiconductor layer 35 is formed of, for example, an amorphous silicon material. The second conductive semiconductor layer 35 is, for example, an n-type semiconductor layer in which an amorphous silicon material is doped with an n-type dopant (for example, phosphorus (P) described above).
　なお、第１導電型半導体層２５がｎ型半導体層であり、第２導電型半導体層３５がｐ型半導体層であってもよい。
　また、半導体基板１１は、結晶シリコン材料にｐ型ドーパント（例えば、上述したホウ素（Ｂ））がドープされたｐ型半導体基板であってもよい。 The first conductive semiconductor layer 25 may be an n-type semiconductor layer, and the second conductive semiconductor layer 35 may be a p-type semiconductor layer.
Further, the semiconductor substrate 11 may be a p-type semiconductor substrate in which a crystalline silicon material is doped with a p-type dopant (for example, the above-mentioned boron (B)).
　第１電極層２７は、第１導電型半導体層２５上に形成されており、第２電極層３７は、第２導電型半導体層３５上に形成されている。
　第１電極層２７は、第１導電型半導体層２５上に順に積層された透明電極層２８と金属電極層２９とを有する。第２電極層３７は、第２導電型半導体層３５上に順に積層された透明電極層３８と金属電極層３９とを有する。
　透明電極層２８，３８は、透明な導電性材料で形成される。透明導電性材料としては、ＩＴＯ（Indium Tin Oxide：酸化インジウムおよび酸化スズの複合酸化物）、ＺｎＯ（Zinc Oxide：酸化亜鉛）が挙げられる。金属電極層２９，３９は、銀等の金属粉末を含有する導電性ペースト材料で形成される。 The first electrode layer 27 is formed on the first conductive semiconductor layer 25, and the second electrode layer 37 is formed on the second conductive semiconductor layer 35.
The first electrode layer 27 has a transparent electrode layer 28 and a metal electrode layer 29, which are sequentially laminated on the first conductive semiconductor layer 25. The second electrode layer 37 has a transparent electrode layer 38 and a metal electrode layer 39, which are sequentially laminated on the second conductive semiconductor layer 35.
The transparent electrode layers 28 and 38 are formed of a transparent conductive material. Examples of the transparent conductive material include ITO (Indium Tin Oxide: a composite oxide of indium tin oxide and tin oxide) and ZnO (Zinc Oxide: zinc oxide). The metal electrode layers 29 and 39 are formed of a conductive paste material containing a metal powder such as silver.
（太陽電池の製造方法）
　以下、図３Ａ～図３Ｇを参照して、図１および図２に示す本実施形態の太陽電池１の製造方法について説明する。図３Ａは、本実施形態に係る太陽電池の製造方法における第１半導体層材料膜形成工程およびリフトオフ層形成工程を示す図であり、図３Ｂ～図３Ｄは、本実施形態に係る太陽電池の製造方法における第１半導体層形成工程を示す図である。また、図３Ｅは、本実施形態に係る太陽電池の製造方法における第２半導体層材料膜形成工程を示す図であり、図３Ｆは、本実施形態に係る太陽電池の製造方法における第２半導体層形成工程を示す図である。また、図３Ｇは、本実施形態に係る太陽電池の製造方法における電極層形成工程を示す図である。 (Solar cell manufacturing method)
Hereinafter, the method for manufacturing the solar cell 1 of the present embodiment shown in FIGS. 1 and 2 will be described with reference to FIGS. 3A to 3G. FIG. 3A is a diagram showing a first semiconductor layer material film forming step and a lift-off layer forming step in the method for manufacturing a solar cell according to the present embodiment, and FIGS. 3B to 3D are views for manufacturing the solar cell according to the present embodiment. It is a figure which shows the 1st semiconductor layer formation process in a method. Further, FIG. 3E is a diagram showing a second semiconductor layer material film forming step in the method for manufacturing a solar cell according to the present embodiment, and FIG. 3F is a diagram showing a second semiconductor layer in the method for manufacturing a solar cell according to the present embodiment. It is a figure which shows the forming process. Further, FIG. 3G is a diagram showing an electrode layer forming step in the method for manufacturing a solar cell according to the present embodiment.
　まず、図３Ａに示すように、例えばＣＶＤ法を用いて、半導体基板１１の裏面側の全面に、第１真性半導体層材料膜２３Ｚおよび第１導電型半導体層材料膜２５Ｚを順に積層（製膜）する（第１半導体層材料膜形成工程）。
　また、例えばＣＶＤ法を用いて、半導体基板１１の受光面側の全面に、真性半導体層１３および光学調整層１５を順に積層（製膜）する。 First, as shown in FIG. 3A, for example, using the CVD method, the first intrinsic semiconductor layer material film 23Z and the first conductive semiconductor layer material film 25Z are laminated in order on the entire back surface side of the semiconductor substrate 11 (film formation). ) (First semiconductor layer material film forming step).
Further, for example, using a CVD method, the intrinsic semiconductor layer 13 and the optical adjustment layer 15 are laminated (film-formed) in order on the entire surface of the semiconductor substrate 11 on the light receiving surface side.
　次に、例えばＣＶＤ法を用いて、半導体基板１１の裏面側の全面に、具体的には第１導電型半導体層材料膜２５Ｚ上の全面に、リフトオフ層（犠牲層）４０を積層（製膜）する（リフトオフ層形成工程）。
　リフトオフ層４０は、酸化珪素（ＳｉＯ）、窒化珪素（ＳｉＮ）、または酸窒化珪素（ＳｉＯＮ）のようなそれらの複合物等の材料で形成される。これにより、リフトオフ層４０は、フッ酸処理（フッ酸、またはフッ酸と他の種類の酸との混合物での処理）で容易に除去される。 Next, for example, using a CVD method, a lift-off layer (sacrificial layer) 40 is laminated (film formation) on the entire surface of the back surface side of the semiconductor substrate 11, specifically, on the entire surface of the first conductive semiconductor layer material film 25Z. ) (Lift-off layer forming process).
The lift-off layer 40 is formed of a material such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON). Thereby, the lift-off layer 40 is easily removed by hydrofluoric acid treatment (treatment with hydrofluoric acid or a mixture of hydrofluoric acid and other types of acids).
　次に、図３Ｂ～図３Ｄに示すように、例えばフォトリソグラフィ技術を用いて、半導体基板１１の裏面側において、第２領域８におけるリフトオフ層４０、第１導電型半導体層材料膜２５Ｚ、および第１真性半導体層材料膜２３Ｚの膜厚方向の一部を除去することにより、第１領域７に、第１真性半導体層２３、パターン化された第１導電型半導体層２５およびリフトオフ層４０を形成する（第１半導体層形成工程）。 Next, as shown in FIGS. 3B to 3D, for example, using photolithography technology, on the back surface side of the semiconductor substrate 11, the lift-off layer 40 in the second region 8, the first conductive semiconductor layer material film 25Z, and the first conductive semiconductor layer material film 25Z. 1 The first intrinsic semiconductor layer 23, the patterned first conductive semiconductor layer 25, and the lift-off layer 40 are formed in the first region 7 by removing a part of the material film 23Z in the film thickness direction. (First semiconductor layer forming step).
　具体的には、図３Ｂに示すように、半導体基板１１の裏面側の第１領域７に、フォトリソグラフィ―技術を用いてレジスト９０を形成する。その後、レジスト９０をマスクとして、第２領域８におけるリフトオフ層４０をエッチングすることにより、第１領域７に、パターン化されたリフトオフ層４０を形成する。リフトオフ層４０に対するエッチング溶液としては、例えばフッ酸、またはフッ酸と他の種類の酸との混合物が用いられる。 Specifically, as shown in FIG. 3B, a resist 90 is formed in the first region 7 on the back surface side of the semiconductor substrate 11 by using a photolithography technique. Then, the lift-off layer 40 in the second region 8 is etched using the resist 90 as a mask to form the patterned lift-off layer 40 in the first region 7. As the etching solution for the lift-off layer 40, for example, hydrofluoric acid or a mixture of hydrofluoric acid and another kind of acid is used.
　次に、図３Ｃに示すように、レジスト９０、およびパターン化されたリフトオフ層４０をマスクとして、第２領域８における第１導電型半導体層材料膜２５Ｚ、および第１真性半導体層材料膜２３Ｚの膜厚方向の一部をエッチングすることにより、第１領域７に、第１真性半導体層２３、およびパターン化された第１導電型半導体層２５を形成する。第１導電型半導体層材料膜２５Ｚおよび第１真性半導体層材料膜２３Ｚに対するエッチング溶液としては、オゾンをフッ酸に溶解させた混合液、またはフッ酸と硝酸との混合液等の酸性溶液が用いられる。
　その後、図３Ｄに示すように、レジスト９０を除去する。レジスト９０に対するエッチング溶液としては、アセトンなどの有機溶剤が用いられる。 Next, as shown in FIG. 3C, the first conductive semiconductor layer material film 25Z and the first intrinsic semiconductor layer material film 23Z in the second region 8 are masked by the resist 90 and the patterned lift-off layer 40. A first intrinsic semiconductor layer 23 and a patterned first conductive semiconductor layer 25 are formed in the first region 7 by etching a part in the film thickness direction. As the etching solution for the first conductive semiconductor layer material film 25Z and the first intrinsic semiconductor layer material film 23Z, an acidic solution such as a mixed solution of ozone dissolved in hydrofluoric acid or a mixed solution of hydrofluoric acid and nitric acid is used. Be done.
Then, as shown in FIG. 3D, the resist 90 is removed. An organic solvent such as acetone is used as the etching solution for the resist 90.
　ここで、第２領域８における第１真性半導体層材料膜２３Ｚを全て除去し、半導体基板１１の表面を露出させると、露出した半導体基板１１の表面を洗浄する必要がある。基板洗浄工程では、例えばオゾン処理を行った後、フッ酸処理が行われる。フッ酸処理とは、フッ酸のみならず、フッ酸に他の種類の酸を含めた混合物での処理も含む。この際、リフトオフ層４０がエッチングされ、リフトオフ層４０の膜厚が減少してしまう。リフトオフ層４０の膜厚が減少すると、第２導電型半導体層３５のパターニングにおいて、リフトオフ層４０によるリフトオフ性が低下してしまう（例えば、第２導電型半導体層３５のパターニングの前にリフトオフ層が剥離してしまい、第２導電型半導体層３５のパターニングにおいてリフトオフプロセスが正常に行われなくなってしまう）。 Here, when all the first intrinsic semiconductor layer material film 23Z in the second region 8 is removed to expose the surface of the semiconductor substrate 11, it is necessary to clean the surface of the exposed semiconductor substrate 11. In the substrate cleaning step, for example, ozone treatment is followed by hydrofluoric acid treatment. The hydrofluoric acid treatment includes not only hydrofluoric acid but also treatment with a mixture of hydrofluoric acid and other types of acids. At this time, the lift-off layer 40 is etched, and the film thickness of the lift-off layer 40 is reduced. When the film thickness of the lift-off layer 40 is reduced, the lift-off property of the lift-off layer 40 is lowered in the patterning of the second conductive semiconductor layer 35 (for example, the lift-off layer is formed before the patterning of the second conductive semiconductor layer 35). It will be peeled off, and the lift-off process will not be performed normally in the patterning of the second conductive semiconductor layer 35).
　これに対して、本実施形態では、第２領域８における第１真性半導体層材料膜２３Ｚの一部が残るので、半導体基板１１の表面が露出せず、その後、基板洗浄工程が不要である。そのため、基板洗浄工程における洗浄溶液（例えば、フッ酸）によりリフトオフ層４０がエッチングされず、リフトオフ層４０の膜厚が減少しない。これにより、リフトオフ層４０によるリフトオフ性の低下を回避することができる。 On the other hand, in the present embodiment, since a part of the first intrinsic semiconductor layer material film 23Z in the second region 8 remains, the surface of the semiconductor substrate 11 is not exposed, and the substrate cleaning step is not required thereafter. Therefore, the lift-off layer 40 is not etched by the cleaning solution (for example, hydrofluoric acid) in the substrate cleaning step, and the film thickness of the lift-off layer 40 is not reduced. As a result, it is possible to avoid a decrease in lift-off property due to the lift-off layer 40.
　ここで、リフトオフ層４０を用いない場合、レジストを用いて、第２領域における第１導電型半導体層材料膜、および第１真性半導体層材料膜の膜厚方向の一部をエッチングすることにより、第１領域に、第１真性半導体層、パターン化された第１導電型半導体層を形成した後に、レジストを除去することとなる。この場合、レジストを除去するためのエッチング溶液が第２領域における第１真性半導体層の表面に触れ、ライフタイムが低下したり、第１真性半導体層の表面の接触抵抗が増加したりしてしまう。 Here, when the lift-off layer 40 is not used, a resist is used to etch a part of the first conductive semiconductor layer material film and the first intrinsic semiconductor layer material film in the second region in the film thickness direction. After forming the first intrinsic semiconductor layer and the patterned first conductive semiconductor layer in the first region, the resist is removed. In this case, the etching solution for removing the resist touches the surface of the first intrinsic semiconductor layer in the second region, which reduces the lifetime and increases the contact resistance on the surface of the first intrinsic semiconductor layer. ..
　これに対して、本実施形態では、リフトオフ層４０を有効利用して、この問題を解決してもよい。例えば、レジスト９０を用いて、第２領域８におけるリフトオフ層４０をエッチングすることにより、第１領域７に、パターン化されたリフトオフ層４０を形成した後に、レジスト９０を除去してもよい。この場合、パターン化されたリフトオフ層４０をマスクとして、第２領域８における第１導電型半導体層材料膜２５Ｚ、および第１真性半導体層材料膜２３Ｚの膜厚方向の一部をエッチングすることにより、第１領域７に、第１真性半導体層２３、およびパターン化された第１導電型半導体層２５を形成する。これにより、レジスト９０を除去するためのエッチング溶液が触れるのは、除去される部分の第１導電型半導体層材料膜２５Ｚであり、このエッチング液が第１真性半導体層２３に触れることがない。そのため、ライフタイムの低下および第１真性半導体層の表面の接触抵抗の増加を回避することができる。 On the other hand, in the present embodiment, the lift-off layer 40 may be effectively used to solve this problem. For example, the resist 90 may be removed after forming the patterned lift-off layer 40 in the first region 7 by etching the lift-off layer 40 in the second region 8 with the resist 90. In this case, the patterned lift-off layer 40 is used as a mask, and a part of the first conductive semiconductor layer material film 25Z and the first intrinsic semiconductor layer material film 23Z in the second region 8 in the film thickness direction is etched. , The first intrinsic semiconductor layer 23 and the patterned first conductive semiconductor layer 25 are formed in the first region 7. As a result, the etching solution for removing the resist 90 comes into contact with the first conductive semiconductor layer material film 25Z of the portion to be removed, and the etching solution does not come into contact with the first intrinsic semiconductor layer 23. Therefore, it is possible to avoid a decrease in lifetime and an increase in contact resistance on the surface of the first intrinsic semiconductor layer.
　ところで、エッチング溶液を用いたエッチング法では、第１真性半導体層材料膜のエッチングを途中で止めることが難しい。 By the way, in the etching method using an etching solution, it is difficult to stop the etching of the first intrinsic semiconductor layer material film in the middle.
　この点に関し、本実施形態では、第１半導体層形成工程において、エッチングガスを主体としたドライエッチング法、例えば水素を主体とするガスによるプラズマエッチング法を用いて、第２領域８におけるリフトオフ層４０、第１導電型半導体層材料膜２５Ｚ、および第１真性半導体層材料膜２３Ｚの膜厚方向の一部をエッチングすることにより、第１領域７に、第１真性半導体層２３、パターン化された第１導電型半導体層２５およびリフトオフ層４０を形成してもよい。この場合、レジストに代えて例えば金属マスクが用いられる。
　これにより、第１真性半導体層材料膜２３Ｚの膜厚方向の途中でエッチングを止める制御が容易となる。 In this regard, in the present embodiment, in the first semiconductor layer forming step, a dry etching method mainly composed of an etching gas, for example, a plasma etching method using a gas mainly composed of hydrogen is used, and the lift-off layer 40 in the second region 8 is used. , The first intrinsic semiconductor layer 23 is patterned in the first region 7 by etching a part of the first conductive semiconductor layer material film 25Z and the first intrinsic semiconductor layer material film 23Z in the film thickness direction. The first conductive semiconductor layer 25 and the lift-off layer 40 may be formed. In this case, for example, a metal mask is used instead of the resist.
This facilitates control to stop etching in the middle of the film thickness direction of the first intrinsic semiconductor layer material film 23Z.
　なお、プラズマエッチング法でも、上述したように、金属マスクを用いて、第２領域８におけるリフトオフ層４０をエッチングすることにより、第１領域７に、パターン化されたリフトオフ層４０を形成した後に、金属マスクを除去し、パターン化されたリフトオフ層４０をマスクとして、第２領域８における第１導電型半導体層材料膜２５Ｚ、および第１真性半導体層材料膜２３Ｚの膜厚方向の一部をエッチングすることにより、第１領域７に、第１真性半導体層２３、およびパターン化された第１導電型半導体層２５を形成してもよい。 Also in the plasma etching method, as described above, the lift-off layer 40 in the second region 8 is etched with a metal mask to form the patterned lift-off layer 40 in the first region 7, and then the patterned lift-off layer 40 is formed. The metal mask is removed, and a part of the first conductive semiconductor layer material film 25Z and the first intrinsic semiconductor layer material film 23Z in the second region 8 in the film thickness direction is etched using the patterned lift-off layer 40 as a mask. By doing so, the first intrinsic semiconductor layer 23 and the patterned first conductive semiconductor layer 25 may be formed in the first region 7.
　フッ酸またはフッ酸を含む混合物によるエッチングと比較して、プラズマエッチングはリフトオフ層と第１導電型半導体層とのエッチングレートの選択性が小さく、共に数ｎｍのエッチングで済む。そのため、リフトオフ層４０をマスクとしてプラズマエッチングを行ってもよい。 Compared with etching with hydrofluoric acid or a mixture containing hydrofluoric acid, plasma etching has less selectivity in etching rate between the lift-off layer and the first conductive semiconductor layer, and both can be etched by several nm. Therefore, plasma etching may be performed using the lift-off layer 40 as a mask.
　次に、図３Ｅに示すように、例えばＣＶＤ法を用いて、半導体基板１１の裏面側の全面に、具体的には第１領域７におけるリフトオフ層４０上および第２領域８における第１真性半導体層２３上に、第２真性半導体層材料膜３３Ｚおよび第２導電型半導体層材料膜３５Ｚを順に積層（製膜）する（第２半導体層材料膜形成工程）。 Next, as shown in FIG. 3E, for example, by using the CVD method, the entire surface of the back surface side of the semiconductor substrate 11, specifically, the first intrinsic semiconductor on the lift-off layer 40 in the first region 7 and the first intrinsic semiconductor in the second region 8. The second intrinsic semiconductor layer material film 33Z and the second conductive semiconductor layer material film 35Z are laminated (film-formed) in this order on the layer 23 (second semiconductor layer material film forming step).
　次に、図３Ｆに示すように、リフトオフ層（犠牲層）を用いたリフトオフ法を利用して、半導体基板１１の裏面側において、第１領域７における第２真性半導体層材料膜３３Ｚおよび第２導電型半導体層材料膜３５Ｚを除去し、第２領域８に、第１真性半導体層２３、パターン化された第２真性半導体層３３および第２導電型半導体層３５を形成する（第２半導体層形成工程）。 Next, as shown in FIG. 3F, the second intrinsic semiconductor layer material film 33Z and the second intrinsic semiconductor layer material film 33Z in the first region 7 on the back surface side of the semiconductor substrate 11 by using the lift-off method using the lift-off layer (sacrificial layer). The conductive semiconductor layer material film 35Z is removed, and the first intrinsic semiconductor layer 23, the patterned second intrinsic semiconductor layer 33, and the second conductive semiconductor layer 35 are formed in the second region 8 (second semiconductor layer). Formation process).
　具体的には、リフトオフ層４０を除去することにより、リフトオフ層４０上の第２真性半導体層材料膜３３Ｚおよび第２導電型半導体層材料膜３５Ｚを除去し、第２真性半導体層３３および第２導電型半導体層３５を形成する。リフトオフ層４０の除去溶液としては、例えばフッ酸等の酸性溶液が用いられる。 Specifically, by removing the lift-off layer 40, the second intrinsic semiconductor layer material film 33Z and the second conductive semiconductor layer material film 35Z on the lift-off layer 40 are removed, and the second intrinsic semiconductor layer 33 and the second. The conductive semiconductor layer 35 is formed. As the removal solution for the lift-off layer 40, for example, an acidic solution such as hydrofluoric acid is used.
　次に、図３Ｇに示すように、半導体基板１１の裏面側に、第１電極層２７および第２電極層３７を形成する（電極層形成工程）。
　具体的には、例えばスパッタリング法等のＰＶＤ法を用いて、半導体基板１１の裏面側の全面に、透明電極層材料膜を積層（製膜）する。その後、例えばエッチングペーストを用いたエッチング法を用いて、透明電極層材料膜の一部を除去することにより、透明電極層２８，３８のパターニングを行う。透明電極層材料膜に対するエッチング溶液としては、例えば塩酸または塩化第二鉄水溶液が用いられる。
　その後、例えばパターン印刷法または塗布法を用いて、透明電極層２８上に金属電極層２９を形成し、透明電極層３８の上に金属電極層３９を形成することにより、第１電極層２７および第２電極層３７を形成する。 Next, as shown in FIG. 3G, the first electrode layer 27 and the second electrode layer 37 are formed on the back surface side of the semiconductor substrate 11 (electrode layer forming step).
Specifically, for example, a PVD method such as a sputtering method is used to laminate (form) a transparent electrode layer material film on the entire surface of the back surface side of the semiconductor substrate 11. After that, the transparent electrode layers 28 and 38 are patterned by removing a part of the transparent electrode layer material film by, for example, an etching method using an etching paste. As the etching solution for the transparent electrode layer material film, for example, hydrochloric acid or an aqueous ferric chloride solution is used.
Then, for example, by using a pattern printing method or a coating method, a metal electrode layer 29 is formed on the transparent electrode layer 28, and a metal electrode layer 39 is formed on the transparent electrode layer 38, whereby the first electrode layer 27 and The second electrode layer 37 is formed.
　以上の工程により、図１および図２に示す本実施形態の裏面電極型の太陽電池１が得られる。 Through the above steps, the back electrode type solar cell 1 of the present embodiment shown in FIGS. 1 and 2 can be obtained.
　以上説明したように、本実施形態の太陽電池の製造方法によれば、第２半導体層形成工程において、リフトオフ層（犠牲層）４０を用いたリフトオフ法を利用して第２導電型半導体層３５のパターニングを行うので、太陽電池の製造プロセスの簡略化、低コスト化が可能となる。 As described above, according to the method for manufacturing a solar cell of the present embodiment, in the second semiconductor layer forming step, the second conductive semiconductor layer 35 utilizes the lift-off method using the lift-off layer (sacrificial layer) 40. Since the patterning is performed, the manufacturing process of the solar cell can be simplified and the cost can be reduced.
　また、本実施形態の太陽電池の製造方法によれば、第１半導体層形成工程において、第１真性半導体層２３の一部を残すので、半導体基板１１の表面が露出せず、その後、基板洗浄工程が不要である。そのため、基板洗浄工程における洗浄溶液（例えば、フッ酸）によりリフトオフ層４０がエッチングされず、リフトオフ層４０の膜厚が減少しない。これにより、リフトオフ層４０によるリフトオフ性の低下を回避することができ、太陽電池の歩留りの低下を回避することができる。 Further, according to the method for manufacturing a solar cell of the present embodiment, since a part of the first intrinsic semiconductor layer 23 is left in the first semiconductor layer forming step, the surface of the semiconductor substrate 11 is not exposed, and then the substrate is washed. No process is required. Therefore, the lift-off layer 40 is not etched by the cleaning solution (for example, hydrofluoric acid) in the substrate cleaning step, and the film thickness of the lift-off layer 40 is not reduced. As a result, it is possible to avoid a decrease in lift-off property due to the lift-off layer 40, and it is possible to avoid a decrease in the yield of the solar cell.
　ここで、リフトオフ層を用いたリフトオフ法を利用しない場合、第１半導体層形成工程において、レジストを用いて、第２領域における第１導電型半導体層の材料膜、および第１真性半導体層の材料膜の膜厚方向の一部を除去することにより、第１領域に、第１真性半導体層、パターン化された第１導電型半導体層を形成した後に、レジストを除去することとなる。この場合、レジスト除去溶液が第２領域における第１真性半導体層に触れ、ライフタイムが低下したり、第１真性半導体層の表面の接触抵抗が増加したりしてしまう。 Here, when the lift-off method using the lift-off layer is not used, the material film of the first conductive semiconductor layer and the material of the first intrinsic semiconductor layer in the second region are used by using the resist in the first semiconductor layer forming step. By removing a part of the film in the film thickness direction, the resist is removed after the first intrinsic semiconductor layer and the patterned first conductive semiconductor layer are formed in the first region. In this case, the resist removing solution comes into contact with the first intrinsic semiconductor layer in the second region, resulting in a decrease in lifetime and an increase in contact resistance on the surface of the first intrinsic semiconductor layer.
　この点に関し、本実施形態の太陽電池の製造方法では、第１半導体層形成工程において、レジスト９０を用いて、第２領域８におけるリフトオフ層４０を除去することにより、第１領域７に、パターン化されたリフトオフ層４０を形成した後に、レジスト９０を除去し、パターン化されたリフトオフ層４０をマスクとして、第２領域８における第１導電型半導体層材料膜２５Ｚ、および第１真性半導体層材料膜２３Ｚの膜厚方向の一部を除去することにより、第１領域７に、第１真性半導体層２３、およびパターン化された第１導電型半導体層２５を形成する。これにより、レジスト除去溶液が触れるのは、除去される部分の第１導電型半導体層材料膜２５Ｚであり、レジスト除去溶液が第１真性半導体層２３に触れることがない。そのため、ライフタイムの低下および第１真性半導体層の表面の接触抵抗の増加を回避することができる。 Regarding this point, in the method for manufacturing a solar cell of the present embodiment, in the first semiconductor layer forming step, the lift-off layer 40 in the second region 8 is removed by using the resist 90, so that the pattern is formed in the first region 7. After forming the formed lift-off layer 40, the resist 90 is removed, and the first conductive semiconductor layer material film 25Z and the first intrinsic semiconductor layer material in the second region 8 are used as a mask with the patterned lift-off layer 40. By removing a part of the film 23Z in the film thickness direction, the first intrinsic semiconductor layer 23 and the patterned first conductive semiconductor layer 25 are formed in the first region 7. As a result, the resist removing solution touches the first conductive semiconductor layer material film 25Z of the portion to be removed, and the resist removing solution does not touch the first intrinsic semiconductor layer 23. Therefore, it is possible to avoid a decrease in lifetime and an increase in contact resistance on the surface of the first intrinsic semiconductor layer.
　ここで、第１半導体層形成工程において、エッチング溶液を用いたエッチング法では、第１真性半導体層のエッチングを途中で止めることが難しい。 Here, in the first semiconductor layer forming step, it is difficult to stop the etching of the first intrinsic semiconductor layer in the middle by the etching method using the etching solution.
　この点に関し、本実施形態の太陽電池の製造方法では、第１半導体層形成工程において、エッチングガスを主体としたドライエッチング法、例えば水素を主体とするガスによるプラズマエッチング法を用いて、第２領域８におけるリフトオフ層４０、第１導電型半導体層材料膜２５Ｚ、および第１真性半導体層材料膜２３Ｚの膜厚方向の一部をエッチングすることにより、第１領域７に、第１真性半導体層２３、パターン化された第１導電型半導体層２５およびリフトオフ層４０を形成してもよい。
　これにより、第１真性半導体層材料膜２３Ｚの膜厚方向の途中でエッチングを止める制御が容易となる。 Regarding this point, in the method for manufacturing a solar cell of the present embodiment, in the first semiconductor layer forming step, a dry etching method mainly containing an etching gas, for example, a plasma etching method using a gas mainly containing hydrogen is used, and a second method is used. By etching a part of the lift-off layer 40, the first conductive semiconductor layer material film 25Z, and the first intrinsic semiconductor layer material film 23Z in the film thickness direction in the region 8, the first intrinsic semiconductor layer is formed in the first region 7. 23. The patterned first conductive semiconductor layer 25 and the lift-off layer 40 may be formed.
This facilitates control to stop etching in the middle of the film thickness direction of the first intrinsic semiconductor layer material film 23Z.
　ここで、第１真性半導体層のエッチングを膜厚方向の途中で止めると、エッチングにより第１真性半導体層にダメージが生じる。
　この点に関し、本実施形態の太陽電池１によれば、第１真性半導体層２３上に第２真性半導体層３３を形成することにより、第１真性半導体層２３のエッチングにより生じたダメージを回復させることができ、太陽電池１の性能低下を抑制することができる。 Here, if the etching of the first intrinsic semiconductor layer is stopped in the middle of the film thickness direction, the etching causes damage to the first intrinsic semiconductor layer.
In this regard, according to the solar cell 1 of the present embodiment, the damage caused by the etching of the first intrinsic semiconductor layer 23 is recovered by forming the second intrinsic semiconductor layer 33 on the first intrinsic semiconductor layer 23. It is possible to suppress the deterioration of the performance of the solar cell 1.
　ところで、リフトオフ層を用いたリフトオフ法を利用しない場合、図４を用いて後述するように、太陽電池１では、第１領域７と第２領域８との境界において、第１導電型半導体層２５と第２導電型半導体層３５とが重なり合う。これにより、第２導電型半導体層３５のパターニングの際に、第１真性半導体層２３が露出することがなく、第２導電型半導体層３５のエッチング溶液による第１真性半導体層２３のダメージを低減することができる。
　しかし、重なり領域おいて第１導電型半導体層２５から第２導電型半導体層３５へのリークを低減するため、重なり領域上には電極を形成しないようにする必要がある。そのため、電極間距離Ｗが大きくなり、その結果、電極面積が小さくなり、抵抗が大きくなる。 By the way, when the lift-off method using the lift-off layer is not used, as will be described later with reference to FIG. 4, in the solar cell 1, the first conductive semiconductor layer 25 is formed at the boundary between the first region 7 and the second region 8. And the second conductive semiconductor layer 35 overlap each other. As a result, the first intrinsic semiconductor layer 23 is not exposed when the second conductive semiconductor layer 35 is patterned, and the damage of the first intrinsic semiconductor layer 23 due to the etching solution of the second conductive semiconductor layer 35 is reduced. can do.
However, in order to reduce leakage from the first conductive semiconductor layer 25 to the second conductive semiconductor layer 35 in the overlapping region, it is necessary not to form an electrode on the overlapping region. Therefore, the distance W between the electrodes becomes large, and as a result, the electrode area becomes small and the resistance becomes large.
　これに対して、本実施形態の太陽電池１によれば、リフトオフ層４０を用いたリフトオフ法を利用するので、図２に示すように、第１領域７と第２領域８との境界に、第１導電型半導体層２５と第２導電型半導体層３５とが重なり合う領域がない。そのため、電極間距離Ｗを小さくでき、その結果、電極面積を大きくでき、抵抗を小さくできる。 On the other hand, according to the solar cell 1 of the present embodiment, the lift-off method using the lift-off layer 40 is used, so that the boundary between the first region 7 and the second region 8 is as shown in FIG. There is no region where the first conductive semiconductor layer 25 and the second conductive semiconductor layer 35 overlap. Therefore, the distance W between the electrodes can be reduced, and as a result, the electrode area can be increased and the resistance can be reduced.
（変形例）
　上述した実施形態の太陽電池１では、第１真性半導体層２３および第２真性半導体層３３の材料としてアモルファスシリコン材料を例示した。しかし、上述した実施形態の太陽電池１では、第２真性半導体層３３は、微結晶材料を含み、更に第２導電型のドーパント（例えば、Ｎ型のリン）を微量含んでもよい。 (Modification example)
In the solar cell 1 of the above-described embodiment, an amorphous silicon material is exemplified as the material of the first intrinsic semiconductor layer 23 and the second intrinsic semiconductor layer 33. However, in the solar cell 1 of the above-described embodiment, the second intrinsic semiconductor layer 33 may contain a microcrystalline material and may further contain a trace amount of a second conductive type dopant (for example, N-type phosphorus).
　この変形例の太陽電池１によれば、第２真性半導体層３３の抵抗を低減することができる。そのため、第２領域８における第１真性半導体層２３および第２真性半導体層３３の総膜厚が厚くても、第１真性半導体層２３および第２真性半導体層３３の総抵抗の増加を低減することができる。
　更に、この変形例の太陽電池１によれば、第１真性半導体層２３と第２真性半導体層３３とのエッチングレートに差をつけることができるため、エッチングによる第１真性半導体層２３のダメージを低減することができる。 According to the solar cell 1 of this modification, the resistance of the second intrinsic semiconductor layer 33 can be reduced. Therefore, even if the total film thickness of the first intrinsic semiconductor layer 23 and the second intrinsic semiconductor layer 33 in the second region 8 is thick, the increase in the total resistance of the first intrinsic semiconductor layer 23 and the second intrinsic semiconductor layer 33 is reduced. be able to.
Further, according to the solar cell 1 of this modification, the etching rates of the first intrinsic semiconductor layer 23 and the second intrinsic semiconductor layer 33 can be different, so that the damage of the first intrinsic semiconductor layer 23 due to the etching can be caused. It can be reduced.
　この変形例の太陽電池の製造方法としては、第２半導体層材料膜形成工程および第２半導体層形成工程において、第２真性半導体層材料膜３３Ｚおよび第２真性半導体層３３に、第２導電型のドーパントが含まれればよい。 As a method for manufacturing a solar cell of this modification, in the second semiconductor layer material film forming step and the second semiconductor layer forming step, the second intrinsic semiconductor layer material film 33Z and the second intrinsic semiconductor layer 33 are formed with a second conductive type. Dopant may be included.
　なお、変形例の太陽電池の製造方法はこれに限定されない。例えば変形例の太陽電池１は、リフトオフ層（犠牲層）を用いたリフトオフ法を利用しない製造方法で製造されてもよい。
　例えば、上述した実施形態の太陽電池の製造方法において、リフトオフ層形成工程を含まない。この場合、第１半導体層形成工程では、第２領域８における第１導電型半導体層材料膜２５Ｚ、および第１真性半導体層材料膜２３Ｚの膜厚方向の一部を除去することにより、第１領域７に、第１真性半導体層２３、およびパターン化された第１導電型半導体層２５を形成する。
　その後、第２半導体層材料膜形成工程では、第１領域７における第１導電型半導体層２５上および第２領域８における第１真性半導体層２３上に、第２真性半導体層材料膜３３Ｚおよび第２導電型半導体層材料膜３５Ｚを形成する。
　その後、第２半導体層形成工程では、第１領域７における第２導電型半導体層材料膜３５Ｚおよび第２真性半導体層３３を除去することにより、第２領域８に、パターン化された第２真性半導体層３３および第２導電型半導体層３５を形成する。 The method for manufacturing the solar cell of the modified example is not limited to this. For example, the modified solar cell 1 may be manufactured by a manufacturing method that uses a lift-off layer (sacrificial layer) and does not utilize the lift-off method.
For example, the method for manufacturing a solar cell according to the above-described embodiment does not include a lift-off layer forming step. In this case, in the first semiconductor layer forming step, the first conductive type semiconductor layer material film 25Z and a part of the first intrinsic semiconductor layer material film 23Z in the second region 8 in the film thickness direction are removed. A first intrinsic semiconductor layer 23 and a patterned first conductive semiconductor layer 25 are formed in the region 7.
After that, in the second semiconductor layer material film forming step, the second intrinsic semiconductor layer material film 33Z and the second intrinsic semiconductor layer material film 33Z are placed on the first conductive semiconductor layer 25 in the first region 7 and on the first intrinsic semiconductor layer 23 in the second region 8. 2 Conductive semiconductor layer material film 35Z is formed.
After that, in the second semiconductor layer forming step, the second intrinsic semiconductor layer material film 35Z and the second intrinsic semiconductor layer 33 in the first region 7 are removed to form the second intrinsic pattern in the second region 8. The semiconductor layer 33 and the second conductive semiconductor layer 35 are formed.
　このようにして製造された変形例の太陽電池１を図４に示す。図４に示す太陽電池１では、第１領域７と第２領域８との境界において、第１導電型半導体層２５と第２導電型半導体層３５とが重なり合う。
　これにより、第２導電型半導体層３５のパターニングの際に、第１真性半導体層２３が露出することがなく、第２導電型半導体層３５のエッチング溶液による第１真性半導体層２３のダメージを低減することができる。 A modified example solar cell 1 manufactured in this manner is shown in FIG. In the solar cell 1 shown in FIG. 4, the first conductive semiconductor layer 25 and the second conductive semiconductor layer 35 overlap each other at the boundary between the first region 7 and the second region 8.
As a result, the first intrinsic semiconductor layer 23 is not exposed when the second conductive semiconductor layer 35 is patterned, and the damage of the first intrinsic semiconductor layer 23 due to the etching solution of the second conductive semiconductor layer 35 is reduced. can do.
　以上、本発明の実施形態について説明したが、本発明は上述した実施形態に限定されることなく、種々の変更および変形が可能である。例えば、上述した実施形態では、図２および図４に示すようにヘテロ接合型の太陽電池１の製造方法を例示したが、本発明の特徴は、ヘテロ接合型の太陽電池に限らず、ホモ接合型の太陽電池等の種々の太陽電池の製造方法に適用可能である。 Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications and modifications can be made. For example, in the above-described embodiment, the method for manufacturing the heterozygous solar cell 1 has been illustrated as shown in FIGS. 2 and 4, but the feature of the present invention is not limited to the heterozygous solar cell and is homozygous. It can be applied to various methods for manufacturing solar cells such as solar cells of the type.
　また、上述した実施形態では、結晶シリコン基板を有する太陽電池を例示したが、これに限定されない。例えば、太陽電池は、ガリウムヒ素（ＧａＡｓ）基板を有していてもよい。 Further, in the above-described embodiment, a solar cell having a crystalline silicon substrate has been exemplified, but the present invention is not limited to this. For example, a solar cell may have a gallium arsenide (GaAs) substrate.
　１　太陽電池
　７　第１領域
　７ｂ，８ｂ　バスバー部
　７ｆ，８ｆ　フィンガー部
　８　第２領域
　１１　半導体基板
　１３　真性半導体層
　１５　光学調整層
　２３　第１真性半導体層
　２３Ｚ　第１真性半導体層材料膜
　２５　第１導電型半導体層
　２５Ｚ　第１導電型半導体層材料膜
　２７　第１電極層
　２８，３８　透明電極層
　２９，３９　金属電極層
　３３　第２真性半導体層
　３３Ｚ　第２真性半導体層材料膜
　３５　第２導電型半導体層
　３５Ｚ　第２導電型半導体層材料膜
　３７　第２電極層
　４０　リフトオフ層（犠牲層）
　９０　レジスト 1 Solar cell 7 1st area 7b, 8b Bus bar part 7f, 8f Finger part 8 2nd area 11 Semiconductor substrate 13 Intrinsic semiconductor layer 15 Optical adjustment layer 23 1st intrinsic semiconductor layer 23Z 1st intrinsic semiconductor layer Material film 25 1st conductivity Type semiconductor layer 25Z 1st conductive type semiconductor layer Material film 27 1st electrode layer 28,38 Transparent electrode layer 29,39 Metal electrode layer 33 2nd intrinsic semiconductor layer 33Z 2nd intrinsic semiconductor layer Material film 35 2nd conductive type semiconductor layer 35Z 2nd conductive semiconductor layer Material film 37 2nd electrode layer 40 Lift-off layer (sacrificial layer)
90 resist

Claims (5)

  1. 　半導体基板と、前記半導体基板の一方主面側と反対側の他方主面側の一部である第１領域に順に積層された第１導電型半導体層および第１電極層と、前記半導体基板の前記他方主面側の他の一部である第２領域に順に積層された第２導電型半導体層および第２電極層とを備える裏面電極型の太陽電池の製造方法であって、
    　前記半導体基板の前記他方主面側に、第１真性半導体層の材料膜および前記第１導電型半導体層の材料膜を順に形成する第１半導体層材料膜形成工程と、
    　前記第１導電型半導体層の材料膜の上に、リフトオフ層を形成するリフトオフ層形成工程と、
    　前記第２領域における前記リフトオフ層、前記第１導電型半導体層の材料膜、および前記第１真性半導体層の材料膜の膜厚方向の一部を除去することにより、前記第１領域に、前記第１真性半導体層、パターン化された前記第１導電型半導体層および前記リフトオフ層を形成する第１半導体層形成工程と、
    　前記第１領域における前記リフトオフ層および前記第２領域における前記第１真性半導体層の上に、第２真性半導体層の材料膜および前記第２導電型半導体層の材料膜を順に形成する第２半導体層材料膜形成工程と、
    　前記リフトオフ層を除去することにより、前記第１領域における前記第２導電型半導体層の材料膜および前記第２真性半導体層の材料膜を除去し、前記第２領域に、前記第１真性半導体層、パターン化された前記第２真性半導体層および前記第２導電型半導体層を形成する第２半導体層形成工程と、
    を含む、太陽電池の製造方法。     A semiconductor substrate, a first conductive semiconductor layer and a first electrode layer laminated in order in a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and the semiconductor substrate. A method for manufacturing a back electrode type solar cell including a second conductive semiconductor layer and a second electrode layer which are sequentially laminated in a second region which is another part on the other main surface side.
    A first semiconductor layer material film forming step of sequentially forming a material film of the first intrinsic semiconductor layer and a material film of the first conductive type semiconductor layer on the other main surface side of the semiconductor substrate.
    A lift-off layer forming step of forming a lift-off layer on the material film of the first conductive semiconductor layer,
    By removing a part of the lift-off layer, the material film of the first conductive semiconductor layer, and the material film of the first intrinsic semiconductor layer in the film thickness direction in the second region, the first region is covered with the above. A first semiconductor layer forming step for forming the first intrinsic semiconductor layer, the patterned first conductive semiconductor layer, and the lift-off layer,
    A second semiconductor in which a material film of the second intrinsic semiconductor layer and a material film of the second conductive semiconductor layer are sequentially formed on the lift-off layer in the first region and the first intrinsic semiconductor layer in the second region. Layer material film formation process and
    By removing the lift-off layer, the material film of the second conductive semiconductor layer and the material film of the second intrinsic semiconductor layer in the first region are removed, and the first intrinsic semiconductor layer is removed in the second region. The second semiconductor layer forming step of forming the patterned second intrinsic semiconductor layer and the second conductive semiconductor layer, and
    Manufacturing methods for solar cells, including.
  2. 　前記第１半導体層形成工程において、
    　レジストを用いて、前記第２領域における前記リフトオフ層を除去することにより、前記第１領域に、パターン化された前記リフトオフ層を形成した後に、前記レジストを除去し、
    　パターン化された前記リフトオフ層をマスクとして、前記第２領域における前記第１導電型半導体層の材料膜、および前記第１真性半導体層の材料膜の膜厚方向の一部を除去することにより、前記第１領域に、前記第１真性半導体層、およびパターン化された前記第１導電型半導体層を形成する、
    請求項１に記載の太陽電池の製造方法。     In the first semiconductor layer forming step,
    By removing the lift-off layer in the second region using a resist, after forming the patterned lift-off layer in the first region, the resist is removed.
    Using the patterned lift-off layer as a mask, a part of the material film of the first conductive semiconductor layer and a part of the material film of the first intrinsic semiconductor layer in the film thickness direction in the second region are removed. The first intrinsic semiconductor layer and the patterned first conductive semiconductor layer are formed in the first region.
    The method for manufacturing a solar cell according to claim 1.
  3. 　前記第１半導体層形成工程において、プラズマエッチング法を用いて、前記第２領域における前記リフトオフ層、前記第１導電型半導体層の材料膜、および前記第１真性半導体層の材料膜の膜厚方向の一部を除去する、請求項１に記載の太陽電池の製造方法。 In the first semiconductor layer forming step, a plasma etching method is used to film the lift-off layer, the material film of the first conductive semiconductor layer, and the material film of the first intrinsic semiconductor layer in the second region. The method for manufacturing a solar cell according to claim 1, wherein a part of the solar cell is removed.
  4. 　前記第２半導体層材料膜形成工程および前記第２半導体層形成工程において、前記第２真性半導体層の材料膜および前記第２真性半導体層は、前記第２導電型のドーパントを含む、請求項１～３のいずれか１項に記載の太陽電池の製造方法。 In the second semiconductor layer material film forming step and the second semiconductor layer forming step, the material film of the second intrinsic semiconductor layer and the second intrinsic semiconductor layer include the second conductive type dopant. The method for manufacturing a solar cell according to any one of 3 to 3.
  5. 　半導体基板と、前記半導体基板の一方主面側と反対側の他方主面側の一部である第１領域に順に積層された第１導電型半導体層および第１電極層と、前記半導体基板の前記他方主面側の他の一部である第２領域に順に積層された第２導電型半導体層および第２電極層とを備える裏面電極型の太陽電池であって、
    　前記半導体基板の前記他方主面側の前記第１領域および前記第２領域に形成された第１真性半導体層と、
    　前記第１領域における前記第１真性半導体層の上に形成された前記第１導電型半導体層と、
    　前記第２領域における前記第１真性半導体層の上に形成された第２真性半導体層および前記第２導電型半導体層と、
    を備え、
    　前記第２領域における前記第１真性半導体層の膜厚は、前記第１領域における前記第１真性半導体層の膜厚よりも薄く、
    　前記第２領域における前記第１真性半導体層および前記第２真性半導体層の総膜厚は、前記第１領域における前記第１真性半導体層の膜厚よりも厚く、
    　前記第２真性半導体層は、前記第２導電型のドーパントを含む、
    太陽電池。     A semiconductor substrate, a first conductive semiconductor layer and a first electrode layer laminated in order in a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and the semiconductor substrate. A back electrode type solar cell including a second conductive semiconductor layer and a second electrode layer which are sequentially laminated in a second region which is another part of the other main surface side.
    The first intrinsic semiconductor layer formed in the first region and the second region on the other main surface side of the semiconductor substrate, and
    The first conductive semiconductor layer formed on the first intrinsic semiconductor layer in the first region,
    The second intrinsic semiconductor layer and the second conductive semiconductor layer formed on the first intrinsic semiconductor layer in the second region,
    With
    The film thickness of the first intrinsic semiconductor layer in the second region is thinner than the film thickness of the first intrinsic semiconductor layer in the first region.
    The total film thickness of the first intrinsic semiconductor layer and the second intrinsic semiconductor layer in the second region is thicker than the film thickness of the first intrinsic semiconductor layer in the first region.
    The second intrinsic semiconductor layer contains the second conductive type dopant.
    Solar cell.
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