JP7433152B2 - Solar cells and solar cell manufacturing methods - Google Patents

Description

The present invention relates to a back electrode type (back contact type) solar cell and a method for manufacturing the solar cell.

Solar cells using semiconductor substrates include double-sided electrode solar cells, in which electrodes are formed on both the light-receiving surface and the back surface, and back-electrode solar cells, in which electrodes are formed only on the back surface. In a double-sided electrode type solar cell, an electrode is formed on the light-receiving surface side, so the metallic luster caused by this electrode is noticeable. On the other hand, in a back-electrode type solar cell, since no electrode is formed on the light-receiving surface side, the light-receiving surface side is uniformly black and has a high design quality. Patent Document 1 discloses a back electrode type solar cell.

The solar cell described in Patent Document 1 includes a semiconductor substrate, a first conductivity type semiconductor layer and a first electrode layer formed in this order on the back side of the semiconductor substrate, and a first conductivity type semiconductor layer and a first electrode layer formed in order on another part of the back side of the semiconductor substrate. a second conductive type semiconductor layer and a second electrode layer. The first electrode layer and the second electrode layer include metal electrode layers and are separated from each other to prevent short circuits. Further, this solar cell includes an antireflection layer formed on the light-receiving surface side of the semiconductor substrate.

Japanese Patent Application Publication No. 2013-131586

In order to simplify the manufacturing process of such solar cells, the inventors of the present application have devised a method of forming a metal electrode layer using a plating method using a resist as a mask. However, when a base layer for a metal electrode layer is formed using a vacuum chamber such as CVD or PVD, the base layer wraps around the side surface of the semiconductor substrate and the peripheral edge of the light-receiving surface of the semiconductor substrate. It will be formed. Therefore, the plating layer of the metal electrode layer is also formed on the side surface of the semiconductor substrate and the peripheral edge of the semiconductor substrate on the light-receiving surface side.

As a result, metallic luster becomes noticeable at the peripheral edge of the light-receiving surface of the solar cell, and the design on the light-receiving surface side deteriorates.

An object of the present invention is to provide a solar cell and a method for manufacturing a solar cell that can suppress deterioration in design on the light-receiving surface side even if the manufacturing process is simplified.

The solar cell according to the present invention includes: a semiconductor substrate; a first conductivity type semiconductor layer and a first metal electrode layer formed in this order in a first region that is a part of the back side of the semiconductor substrate; A back electrode comprising a second conductivity type semiconductor layer and a second metal electrode layer formed in order on a second region that is another part of the back surface side, and an antireflection layer formed on the light receiving surface side of the semiconductor substrate. type solar cell, wherein each of the first metal electrode layer and the second metal electrode layer has a base layer and a plating layer, and a side surface of the semiconductor substrate and a side surface of the light-receiving surface of the semiconductor substrate. The base layer and the antireflection layer are formed in this order from the semiconductor substrate side, and the plating layer is not formed on the peripheral edge.

The method for manufacturing a solar cell according to the present invention includes: a semiconductor substrate; a first conductivity type semiconductor layer and a first metal electrode layer formed in this order in a first region that is a part of the back side of the semiconductor substrate; a second conductivity type semiconductor layer and a second metal electrode layer formed in this order in a second region that is another part of the back surface side of the substrate; and an antireflection layer formed on the light receiving surface side of the semiconductor substrate. A method for manufacturing a back electrode type solar cell comprising: each of the first metal electrode layer and the second metal electrode layer having a base layer and a plating layer; Using a chamber, a series of the base layers is formed over the first conductivity type semiconductor layer and the second conductivity type semiconductor layer on the back surface side of the semiconductor substrate, spanning the first region and the second region. A base layer material film forming step for forming a material film, wherein the material film of the base layer is formed by wrapping around a side surface of the semiconductor substrate and a peripheral portion of the light receiving surface side of the semiconductor substrate. , an anti-reflection layer forming step of forming the anti-reflection layer on the light-receiving surface side of the semiconductor substrate using a vacuum chamber, the anti-reflection layer forming the anti-reflection layer on the side surface of the semiconductor substrate and on the light-receiving surface side of the semiconductor substrate; a step of forming a resist around the peripheral edge of the back surface side; a resist forming step of forming a resist on the material film of the base layer at the boundary between the first region and the second region; A plating layer forming step of forming the patterned plating layer on the material film of the base layer in each of the first region and the second region using a plating method used as a mask, a step in which the antireflection layer functions as a mask so that the plating layer is not formed on a side surface of the semiconductor substrate and a peripheral edge of the light-receiving surface of the semiconductor substrate; a resist removal step of removing the resist; A patterned underlayer is formed in each of the first region and the second region by etching the material film of the underlayer using an etching method using the plating layer as a mask. A geological formation step.

According to the present invention, even if the manufacturing process of the solar cell is simplified, it is possible to suppress deterioration of the design on the light-receiving surface side of the solar cell.

FIG. 2 is a diagram of the solar cell according to the present embodiment viewed from the back side. 2 is a sectional view taken along line II-II of the solar cell shown in FIG. 1. FIG. It is a figure showing the semiconductor layer formation process in the manufacturing method of the solar cell concerning this embodiment. It is a figure which shows the transparent electrode layer material film formation process and the base layer material film formation process of a metal electrode layer in the manufacturing method of the solar cell based on this embodiment. It is a figure showing the antireflection layer formation process in the manufacturing method of the solar cell concerning this embodiment. It is a figure showing a resist formation process in a manufacturing method of a solar cell concerning this embodiment. It is a figure which shows the plating layer formation process of the metal electrode layer in the manufacturing method of the solar cell based on this embodiment. It is a figure showing a resist removal process in a manufacturing method of a solar cell concerning this embodiment. It is a figure which shows the transparent electrode layer formation process and the base layer formation process of a metal electrode layer in the manufacturing method of the solar cell based on this embodiment. 2 is a cross-sectional view of a solar cell according to a comparative example, taken along line II-II in FIG. 1. FIG. It is a figure which shows the antireflection layer formation process in the manufacturing method of the solar cell based on a comparative example. It is a figure which shows the transparent electrode layer material film formation process and the base layer material film formation process of a metal electrode layer in the manufacturing method of the solar cell based on a comparative example. It is a figure which shows the resist formation process in the manufacturing method of the solar cell based on a comparative example. It is a figure which shows the plating layer formation process of the metal electrode layer in the manufacturing method of the solar cell based on a comparative example. It is a figure which shows the resist removal process in the manufacturing method of the solar cell based on a comparative example. It is a figure which shows the transparent electrode layer formation process and the base layer formation process of a metal electrode layer in the manufacturing method of the solar cell based on a comparative example.

Hereinafter, an example of an embodiment of the present invention will be described with reference to the accompanying drawings. In addition, the same reference numerals are given to the same or corresponding parts in each drawing. Further, for convenience, hatching, member symbols, etc. may be omitted, but in such cases, other drawings shall be referred to.

(Solar cell according to this embodiment)
FIG. 1 is a diagram of the solar cell according to the present embodiment viewed from the back side, and FIG. 2 is a sectional view taken along the line II-II of the solar cell shown in FIG. The solar cell 1 shown in FIGS. 1 and 2 is a back electrode type (also referred to as a back contact type or a back bond type), and is a heterojunction type solar cell.

The solar cell 1 includes a semiconductor substrate 11 having two main surfaces, and has a first region 7 and a second region 8 on the main surface of the semiconductor substrate 11 . Hereinafter, the main surface of the semiconductor substrate 11 on the side that receives light will be referred to as a light-receiving surface, and the main surface of the semiconductor substrate 11 that is opposite to the light-receiving surface will be referred to as a back surface.

The first region 7 has a so-called comb-shaped shape and includes a plurality of finger portions 7f corresponding to comb teeth and a bus bar portion 7b corresponding to a support portion of the comb teeth. The bus bar portion 7b extends in a first direction (X direction) along one side of the semiconductor substrate 11, and the finger portion 7f extends from the bus bar portion 7b in a second direction (Y direction) intersecting the first direction. ).

Similarly, the second region 8 has a so-called comb-like shape and includes a plurality of finger portions 8f corresponding to comb teeth and a bus bar portion 8b corresponding to a support portion of the comb teeth. The busbar portion 8b extends in a first direction (X direction) along the other side opposite to one side of the semiconductor substrate 11, and the finger portion 8f extends from the busbar portion 8b in a second direction (Y direction). direction).

The finger portions 7f and 8f have a band shape extending in the second direction (Y direction), and are provided alternately in the first direction (X direction). Note that the first region 7 and the second region 8 may be formed in a stripe shape.

As shown in FIG. 2, the solar cell 1 includes an antireflection layer 15 formed on the light-receiving surface side of the semiconductor substrate 11. Furthermore, the solar cell 1 includes a first conductive type semiconductor layer 25 and a first electrode layer 27 that are formed in this order on a portion of the back surface side (the first region 7 ) of the semiconductor substrate 11 . Furthermore, the solar cell 1 includes a second conductive type semiconductor layer 35 and a second electrode layer 37 which are formed in this order on another part (second region 8) of the back surface side of the semiconductor substrate 11.

Semiconductor substrate 11 is formed of a crystalline silicon material such as single crystal silicon or polycrystalline silicon. The semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which a crystalline silicon material is doped with an n-type dopant. Note that the semiconductor substrate 11 may be, for example, a p-type semiconductor substrate in which a crystalline silicon material is doped with a p-type dopant. An example of the n-type dopant is phosphorus (P). An example of the p-type dopant is boron (B). The semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light receiving surface side and generates optical carriers (electrons and holes).

By using crystalline silicon as the material for the semiconductor substrate 11, dark current is relatively small, and even when the intensity of incident light is low, relatively high output (stable output regardless of illumination intensity) can be obtained.

The semiconductor substrate 11 may have a pyramid-shaped fine uneven structure called a texture structure on the back side. This increases the recovery efficiency of light that has passed through without being absorbed by the semiconductor substrate 11.

Further, the semiconductor substrate 11 may have a pyramid-shaped fine uneven structure called a texture structure on the light-receiving surface side. This reduces reflection of incident light on the light-receiving surface and improves the light confinement effect in the semiconductor substrate 11.

The antireflection layer 15 is formed on the light-receiving surface side of the semiconductor substrate 11. The antireflection layer 15 functions as an antireflection layer that prevents reflection of incident light, and also functions as a protective layer that protects the light-receiving surface side of the semiconductor substrate 11. The antireflection layer 15 is formed of an insulating material such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or a composite thereof.

The first conductive type semiconductor layer 25 is formed in the first region 7 on the back side of the semiconductor substrate 11 . On the other hand, the second conductive type semiconductor layer 35 is formed in the second region 8 on the back side of the semiconductor substrate 11. That is, the first conductive type semiconductor layer 25 and the second conductive type semiconductor layer 35 have a band-like shape and extend in the Y direction. The first conductive type semiconductor layers 25 and the second conductive type semiconductor layers 35 are arranged alternately in the X direction. A portion of the second conductive type semiconductor layer 35 may overlap a portion of the adjacent first conductive type semiconductor layer 25 (not shown).

The first conductive type semiconductor layer 25 is made of, for example, an amorphous silicon material. The first conductive type semiconductor layer 25 is, for example, a p-type semiconductor layer in which an amorphous silicon material is doped with a p-type dopant (for example, the above-mentioned boron (B)).

The second conductive type semiconductor layer 35 is made of, for example, an amorphous silicon material. The second conductive type semiconductor layer 35 is, for example, an n-type semiconductor layer in which an amorphous silicon material is doped with an n-type dopant (for example, the above-mentioned phosphorus (P)). Note that the first conductive type semiconductor layer 25 may be an n-type semiconductor layer, and the second conductive type semiconductor layer 35 may be a p-type semiconductor layer.

Note that a passivation layer may be formed between the first conductive type semiconductor layer 25 and the semiconductor substrate 11, and a passivation layer may be formed between the second conductive type semiconductor layer 35. Further, a passivation layer may be formed between the antireflection layer 15 and the semiconductor substrate 11. These passivation layers are formed of, for example, a material whose main component is an intrinsic (i-type) amorphous silicon material. Such a passivation layer suppresses recombination of carriers generated in the semiconductor substrate 11 and increases carrier recovery efficiency.

The first electrode layer 27 is formed on the first conductivity type semiconductor layer 25, that is, in the first region 7 on the back side of the semiconductor substrate 11. On the other hand, the second electrode layer 37 is formed on the second conductivity type semiconductor layer 35, that is, in the second region 8 on the back side of the semiconductor substrate 11. That is, the first electrode layer 27 and the second electrode layer 37 have a band-like shape and extend in the Y direction. The first electrode layer 27 and the second electrode layer 37 are provided alternately in the X direction.

The first electrode layer 27 includes a first transparent electrode layer 28 and a first metal electrode layer 29 formed in this order on the first conductivity type semiconductor layer 25 . On the other hand, the second electrode layer 37 includes a second transparent electrode layer 38 and a second metal electrode layer 39 formed in this order on the second conductivity type semiconductor layer 35. The first metal electrode layer 29 has a two-layer structure of a base layer 29l and a plating layer 29u, and the second metal electrode layer 39 has a two-layer structure of a base layer 39l and a plating layer 39u.

The first transparent electrode layer 28 and the second transparent electrode layer 38 are formed of a transparent conductive material. Examples of the transparent conductive material include ITO (Indium Tin Oxide: a composite oxide of indium oxide and tin oxide), ZnO (Zinc Oxide), and the like.

The base layer 29l in the first metal electrode layer 29 and the base layer 39l in the second metal electrode layer 39 include a metal material such as silver, copper, or aluminum formed using a PVD method such as sputtering. On the other hand, the plating layer 29u in the first metal electrode layer 29 and the plating layer 39u in the second metal electrode layer 39 include metal materials such as silver, copper, nickel, etc. formed using a plating method, for example.

The first electrode layer 27 and the second electrode layer 37 have a band shape extending in the second direction (Y direction), and are arranged alternately in the first direction (X direction). That is, the first transparent electrode layer 28 and the second transparent electrode layer 38 have a band shape extending in the second direction (Y direction), and are arranged alternately in the first direction (X direction). Further, the first metal electrode layer 29 and the second metal electrode layer 39 have a band shape extending in the second direction (Y direction), and are arranged alternately in the first direction (X direction). The first transparent electrode layer 28 and the second transparent electrode layer 38 are separated from each other, and the first metal electrode layer 29 and the second metal electrode layer 39 are also separated from each other.

Next, the side surface of the semiconductor substrate 11, the peripheral edge R1 on the light-receiving surface side of the semiconductor substrate 11, and the peripheral edge R1 on the back side of the semiconductor substrate 11 will be described. The second transparent electrode layer 38 (or the first transparent electrode layer 28) is formed so as to wrap around the side surface of the semiconductor substrate 11 and the peripheral edge R1 on the light-receiving surface side of the semiconductor substrate 11. Further, the base layer 39l of the second metal electrode layer 39 (or the base layer 29l of the first metal electrode layer 29) wraps around the side surface of the semiconductor substrate 11 and the peripheral edge R1 on the light-receiving surface side of the semiconductor substrate 11 to form a film. has been done. Further, the antireflection layer 15 is formed so as to wrap around the side surface of the semiconductor substrate 11 and the peripheral edge R1 on the back surface side of the semiconductor substrate 11 .

On the other hand, the plating layer 39u of the second metal electrode layer 39 (or the plating layer 29u of the first metal electrode layer 29) is formed so as to wrap around the side surface of the semiconductor substrate 11 and the periphery of the light-receiving surface side of the semiconductor substrate 11. Not yet.

As a result, on the side surface of the semiconductor substrate 11, the peripheral edge R1 on the light-receiving surface side of the semiconductor substrate 11, and the peripheral edge R1 on the back side of the semiconductor substrate 11,
- In order from the semiconductor substrate 11 side, the second transparent electrode layer 38 (or the first transparent electrode layer 28), the base layer 39l of the second metal electrode layer 39 (or the base layer 29l of the first metal electrode layer 29), and , an antireflection layer 15 is formed,
- The plating layer 39u of the second metal electrode layer 39 (or the plating layer 29u of the first metal electrode layer 29) is not formed.

Further, the thickness of each of the first metal electrode layer 29 and the second metal electrode layer 39 at the central part on the back side of the semiconductor substrate 11 is the same as that at the side surface of the semiconductor substrate 11 and the peripheral edge R1 on the light receiving surface side of the semiconductor substrate 11. The thickness is at least twice the thickness of the base layer 39l of the second metal electrode layer 39 (or the base layer 29l of the first metal electrode layer 29).

For example, the thickness of the base layer 29l of the first metal electrode layer 29 and the base layer 39l of the second metal electrode layer 39 is, for example, 100 nm or more and 500 nm or less, and the plating layer 29u of the first metal electrode layer 29 and The thickness of the plating layer 39u of the second metal electrode layer 39 is, for example, 1 μm or more and 20 μm or less.

(Solar cell according to comparative example)
FIG. 4 is a cross-sectional view of a solar cell according to a comparative example, and is a cross-sectional view taken along line II-II in FIG. Compared to the solar cell 1 shown in FIG. 2, the solar cell 1X of the comparative example shown in FIG. In the side peripheral edge R1,
- In order from the semiconductor substrate 11 side, the antireflection layer 15, the second transparent electrode layer 38 (or the first transparent electrode layer 28), and the base layer 39l of the second metal electrode layer 39 (or the first metal electrode layer 29) A base layer 29l) is formed,
- Furthermore, a plating layer 39u of the second metal electrode layer 39 (or a plating layer 29u of the first metal electrode layer 29) is formed.
This is different from this embodiment in this point.

(Manufacturing method of solar cell according to comparative example)
Below, with reference to FIGS. 5A to 5F, the manufacturing process of the antireflection layer 15 and the electrode layers 27 and 37 in the method of manufacturing a solar cell according to a comparative example will be mainly described. In the manufacturing process of the comparative example, the electrode layers 27 and 37 are formed after the antireflection layer 15 is formed.

FIG. 5A is a diagram showing an antireflection layer forming step in a method for manufacturing a solar cell according to a comparative example, and FIG. 5B is a diagram showing a step for forming a transparent electrode layer material film and a metal electrode layer in a method for manufacturing a solar cell according to a comparative example. It is a figure which shows the base layer material film formation process of. Further, FIG. 5C is a diagram showing a resist forming step in a method for manufacturing a solar cell according to a comparative example, and FIG. 5D is a diagram showing a step for forming a plating layer of a metal electrode layer in a method for manufacturing a solar cell according to a comparative example. It is. Further, FIG. 5E is a diagram showing a resist removal step in a method for manufacturing a solar cell according to a comparative example, and FIG. It is a figure showing a stratum formation process.

First, as shown in FIG. 5A, the antireflection layer 15 is formed on the entire surface of the light-receiving surface of the semiconductor substrate 11 using, for example, a CVD method using a vacuum chamber (antireflection layer forming step). At this time, the antireflection layer 15 is formed around the side surface of the semiconductor substrate 11 and the peripheral edge R1 on the back surface side of the semiconductor substrate 11 .

Next, as shown in FIG. 5B, a first region is formed on the first conductive type semiconductor layer 25 and the second conductive type semiconductor layer 35 on the back side of the semiconductor substrate 11 using, for example, a CVD method using a vacuum chamber. A series of transparent electrode layer material films 28Z are formed across 7 and the second region 8 (transparent electrode layer material film forming step). At this time, the transparent electrode layer material film 28Z is formed to wrap around the side surface of the semiconductor substrate 11 and the peripheral edge R1 on the light-receiving surface side of the semiconductor substrate 11.

Next, using a PVD method such as sputtering using a vacuum chamber, a series of base layers are formed over the transparent electrode layer material film 28Z on the back side of the semiconductor substrate 11 over the first region 7 and the second region 8. A material film 29lZ is formed (base layer material film forming step). At this time, the base layer material film 29lZ is formed to wrap around the side surface of the semiconductor substrate 11 and the peripheral edge R1 on the light-receiving surface side of the semiconductor substrate 11.

Next, as shown in FIG. 5C, a resist 40 is formed on the base layer material film 29lZ at the boundary between the first region 7 and the second region 8 (resist forming step).

Next, as shown in FIG. 5D, a patterned plating layer 29u is formed on the base layer material film 29lZ in the first region 7 using a plating method using the resist 40 as a mask, and a patterned plating layer 29u is formed in the second region 7. A patterned plating layer 39u is formed on the base layer material film 29lZ in step 8 (plating layer forming step). At this time, the plating layers 29u and 39u are also formed on the base layer material film 29lZ formed on the side surface of the semiconductor substrate 11 and the peripheral edge R1 on the light-receiving surface side of the semiconductor substrate 11.

Next, as shown in FIG. 5E, the resist 40 is removed (resist removal step).

Next, as shown in FIG. 5F, the first region 7 is etched by etching the base layer material film 29lZ and the transparent electrode layer material film 28Z using an etching method using the plating layer 29u and the plating layer 39u as masks. , a patterned first transparent electrode layer 28 and a base layer 29l are formed, and a patterned second transparent electrode layer 38 and a base layer 39l are formed in the second region 8 (transparent electrode layer forming step, and base layer formation step). As a result, a first metal electrode layer 29 consisting of the base layer 29l and the plating layer 29u, and a second metal electrode layer 39 consisting of the base layer 39l and the plating layer 39u are formed. Further, a first electrode layer 27 consisting of a first transparent electrode layer 28 and a first metal electrode layer 29, and a second electrode layer 37 consisting of a second transparent electrode layer 38 and a second metal electrode layer 39 are formed. Ru.

According to the solar cell manufacturing method of this comparative example, the metal electrode layers 29 and 39 are formed using a plating method. Furthermore, the plating layers 29u and 39u in the metal electrode layers 29 and 39 are directly formed (film formation and patterning are performed simultaneously) using a plating method using the resist 40 as a mask. This makes it possible to simplify the solar cell manufacturing process and reduce costs.

However, when the base layers 29l, 39l of the metal electrode layers 29, 39 are formed using, for example, a CVD method or a PVD method using a vacuum chamber, the base layers 29l, 39l are formed on the side surface of the semiconductor substrate 11 and on the side surface of the semiconductor substrate 11. It is also formed around the peripheral edge R1 on the light-receiving surface side. Therefore, the plating layers 29u and 39u of the metal electrode layers 29 and 39 are also formed on the side surface of the semiconductor substrate 11 and the peripheral edge R1 on the light-receiving surface side of the semiconductor substrate 11.

Then, in a solar cell module using this solar cell 1X, the metallic luster of the peripheral edge on the light-receiving surface side of the solar cell 1X becomes conspicuous, and the design of the light-receiving surface side of the solar cell module is impaired.

In addition, since the plating layers 29u and 39u on the side surface and the peripheral edge R1 of the semiconductor substrate 11 are easily peeled off, when the solar cell 1X is being transported, for example, it may get caught in the transport system, causing damage to the solar cell 1X due to transport trouble. Possible (decreased yield). Furthermore, it is conceivable that the electrodes on the back surface of the solar cell 1X may be short-circuited due to the peeled plating layers 29u and 39u.

Further, as shown in FIG. 5C, since the ends of the transparent electrode layer material film 28Z and the base layer material film 29lZ are exposed at the peripheral edge on the light-receiving surface side of the semiconductor substrate 11, the base layer that has wrapped around the peripheral edge If the material film 29lZ is thin and the transparent electrode layer material film 28Z is exposed, side etching of the end of the transparent electrode layer material film 28Z is performed using a plating solution in the plating layer forming step shown in FIG. 5D. It is conceivable that this may occur.

As a result, the plating solution may penetrate to the semiconductor layers 25 and 35 on the back side of the semiconductor substrate 11, and the performance and reliability of the solar cell 1X may be reduced (performance deterioration, reliability deterioration). In particular, when the material of the base layer material film 29lZ is Cu, the Cu may penetrate to the semiconductor layers 25, 35 on the back side of the semiconductor substrate 11, and furthermore, due to some factor (for example, a defect in the semiconductor layers 25, 35), the Cu When this diffuses into the semiconductor substrate 11, the performance of the solar cell 1X is significantly reduced.

Further, the disappearance of the transparent electrode layer material film 28Z is considered to be a cause of electrode peeling (yield decrease).

In this regard, the inventors of the present application have found that even if the manufacturing process is simplified and costs are reduced, the deterioration of the design on the light-receiving surface side, the decrease in yield, the decrease in performance, and the decrease in reliability can be suppressed. We will devise a method for manufacturing solar cells that can

(Method for manufacturing a solar cell according to this embodiment)
Next, a method for manufacturing a solar cell according to this embodiment will be described with reference to FIGS. 3A to 3G. FIG. 3A is a diagram showing a semiconductor layer forming step in the solar cell manufacturing method according to the present embodiment, and FIG. 3B is a diagram showing the transparent electrode layer material film forming step and the metal electrode layer forming step in the solar cell manufacturing method according to the present embodiment. It is a figure which shows the base layer material film formation process of a layer. Further, FIG. 3C is a diagram showing an antireflection layer forming step in the solar cell manufacturing method according to the present embodiment, and FIG. 3D is a diagram showing a resist forming step in the solar cell manufacturing method according to the present embodiment. be. Further, FIG. 3E is a diagram showing a plating layer forming step of a metal electrode layer in the method for manufacturing a solar cell according to the present embodiment, and FIG. 3F is a diagram showing a resist removing step in the method for manufacturing a solar cell according to the present embodiment. FIG. Moreover, FIG. 3G is a diagram showing a transparent electrode layer forming step and a base layer forming step of a metal electrode layer in the method for manufacturing a solar cell according to the present embodiment.

First, as shown in FIG. 3A, the first conductive type semiconductor layer 25 is formed on a part of the back surface side of the semiconductor substrate 11, specifically in the first region 7 (semiconductor layer forming step). For example, after forming a first conductivity type semiconductor layer material film on the entire back surface side of the semiconductor substrate 11 using, for example, a CVD method or a PVD method using a vacuum chamber, a film of the first conductivity type semiconductor layer material is formed using a photolithography technique or a printing technique. The first conductive type semiconductor layer 25 may be patterned using an etching method using a resist or a metal mask.

Note that the etching solution for the p-type semiconductor layer material film includes, for example, an acidic solution such as hydrofluoric acid containing ozone or a mixed solution of nitric acid and hydrofluoric acid, and the etching solution for the n-type semiconductor layer material film includes , for example, an alkaline solution such as an aqueous potassium hydroxide solution.

Alternatively, when forming the first conductivity type semiconductor layer on the back side of the semiconductor substrate 11 using the CVD method or the PVD method, the film formation and patterning of the first conductivity type semiconductor layer 25 are performed simultaneously using a mask. It's okay.

Next, a second conductive type semiconductor layer 35 is formed on another part of the back surface side of the semiconductor substrate 11, specifically in the second region 8 (semiconductor layer forming step). For example, as described above, after forming a film of the second conductivity type semiconductor layer material on the entire back surface side of the semiconductor substrate 11 using the CVD method or the PVD method, a resist produced using the photolithography technique or the printing technique. The second conductive type semiconductor layer 35 may be patterned using an etching method using a metal mask or a metal mask.

Alternatively, when forming the second conductive type semiconductor layer on the back side of the semiconductor substrate 11 using the CVD method or the PVD method, the film formation and patterning of the second conductive type semiconductor layer 35 are performed simultaneously using a mask. It's okay.

Note that in this semiconductor layer forming step, a passivation layer may be formed on the back surface side and the light-receiving surface side of the semiconductor substrate 11.

Next, as shown in FIG. 3B, using, for example, a CVD method or a PVD method using a vacuum chamber, on the first conductive type semiconductor layer 25 and the second conductive type semiconductor layer 35 on the back side of the semiconductor substrate 11, A series of transparent electrode layer material films 28Z is formed across the first region 7 and the second region 8 (transparent electrode layer material film forming step). At this time, the transparent electrode layer material film 28Z is formed around the side surface of the semiconductor substrate 11 and the peripheral edge R1 on the light-receiving surface side of the semiconductor substrate 11.

Next, using a PVD method such as sputtering using a vacuum chamber, the first conductive type semiconductor layer 25 and the second conductive type semiconductor layer 35 are deposited on the transparent electrode layer material film 28Z on the back side of the semiconductor substrate 11. A series of base layer material films 29lZ is formed on the first region 7 and the second region 8 (base layer material film forming step). At this time, the base layer material film 29lZ is formed to wrap around the side surface of the semiconductor substrate 11 and the peripheral edge R1 on the light-receiving surface side of the semiconductor substrate 11.

Next, as shown in FIG. 3C, an antireflection layer 15 is formed on the entire surface of the light-receiving surface of the semiconductor substrate 11 using, for example, a CVD method or a PVD method using a vacuum chamber (antireflection layer forming step). . At this time, the antireflection layer 15 is formed around the side surface of the semiconductor substrate 11 and the peripheral edge R1 on the back surface side of the semiconductor substrate 11 .

Next, as shown in FIG. 3D, an insulating resist 40 is formed on the base layer material film 29lZ at the boundary between the first region 7 and the second region 8 (resist forming step). Examples of methods for forming the resist 40 include pattern printing methods such as screen printing, press printing such as gravure printing, and discharge printing such as inkjet printing. In the pattern printing method, a patterned resist 40 is formed by printing and baking (hardening) a printing material containing a resin material and a solvent.

Next, as shown in FIG. 3E, a patterned plating layer is formed on the base layer material film 29lZ in the first region 7 using a plating method using the insulating resist 40 as a mask, for example, electrolytic plating. 29u is formed, and a patterned plating layer 39u is formed on the base layer material film 29lZ in the second region 8 (plating layer forming step). At this time, the insulating antireflection layer 15 formed around the side surface of the semiconductor substrate 11 and the peripheral edge R1 on the back surface side of the semiconductor substrate 11 functions as a mask. Therefore, the plating layers 29u and 39u are not formed around the side surface of the semiconductor substrate 11 and the peripheral edge R1 on the light-receiving surface side of the semiconductor substrate 11.

Next, as shown in FIG. 3F, the resist 40 is removed (resist removal step). As the resist removal solution, an alkaline aqueous solution such as a sodium hydroxide aqueous solution is used.

Next, as shown in FIG. 3G, the first region 7 is etched by etching the base layer material film 29lZ and the transparent electrode layer material film 28Z using an etching method using the plating layer 29u and the plating layer 39u as masks. , a patterned first transparent electrode layer 28 and a base layer 29l are formed, and a patterned second transparent electrode layer 38 and a base layer 39l are formed in the second region 8 (transparent electrode layer forming step, and base layer formation step). As a result, a first metal electrode layer 29 consisting of the base layer 29l and the plating layer 29u, and a second metal electrode layer 39 consisting of the base layer 39l and the plating layer 39u are formed. Further, a first electrode layer 27 consisting of a first transparent electrode layer 28 and a first metal electrode layer 29, and a second electrode layer 37 consisting of a second transparent electrode layer 38 and a second metal electrode layer 39 are formed. Ru.

As an etching solution for simultaneous etching of the base layer material film 29lZ and the transparent electrode layer material film 28Z, for example, when the transparent electrode layer material film 28Z is ITO and the base layer material film 29lZ is copper, ammonium persulfate (ammonium persulfate) is used. A mixed solution of an oxidizing agent such as oxidizing agent and an acidic solution such as hydrochloric acid (HCl) can be mentioned.

Through the above steps, the back electrode type solar cell 1 of this embodiment shown in FIGS. 1 and 2 is obtained.

As explained above, also in the solar cell manufacturing method of this embodiment, the metal electrode layers 29 and 39 are formed using a plating method. Furthermore, the plating layers 29u and 39u in the metal electrode layers 29 and 39 are directly formed (film formation and patterning are performed simultaneously) using a plating method using the resist 40 as a mask. This makes it possible to simplify the solar cell manufacturing process and reduce costs.

In addition, according to the method for manufacturing a solar cell of the present embodiment, a pattern printing method is used to print and bake (cure) a printing material containing a resin material and a solvent, thereby directly (film formation and patterning). simultaneously) to form a patterned resist 40. This makes it possible to simplify and reduce the cost of resist formation compared to, for example, resist formation using photolithography technology. Therefore, it is possible to simplify the solar cell manufacturing process and reduce costs.

Furthermore, according to the solar cell manufacturing method of this embodiment, the antireflection layer 15 is formed between the formation of the base layers 29l, 39l of the metal electrode layers 29, 39 and the formation of the plating layers 29u, 39u. As a result, the insulating antireflection layer 15 formed around the side surface of the semiconductor substrate 11 and the peripheral edge R1 on the back side of the semiconductor substrate 11 functions as a mask, and the plating layers 29u and 39u It is not formed to wrap around the side surface and the peripheral edge R1 on the light-receiving surface side of the semiconductor substrate 11.

As a result, in a solar cell module using this solar cell 1, there is no metallic luster at the peripheral edge of the light-receiving surface of the solar cell 1, and the design of the light-receiving surface of the solar cell module is not impaired (design suppression of decline).

Moreover, damage to the solar cell 1 due to transportation troubles caused by peeling of the plating layer on the side surface and the peripheral edge R1 of the semiconductor substrate 11 can be prevented during transportation of the solar cell 1 (suppression of decrease in yield). Furthermore, short circuiting of the electrodes on the back surface of the solar cell 1 due to the peeled plating layer does not occur.

Furthermore, as shown in FIG. 3D, on the back side of the semiconductor substrate 11, the ends of the transparent electrode layer material film 28Z and the base layer material film 29lZ are covered with the antireflection layer 15, so that the plating layer formation shown in FIG. 3E is prevented. In the process, side etching of the end portion of the transparent electrode layer material film 28Z does not occur due to the plating solution.

This prevents the plating solution from penetrating into the semiconductor layers 25 and 35 on the back side of the semiconductor substrate 11 as in the comparative example, making it possible to suppress a decline in the performance of the solar cell 1 and also to suppress a decline in reliability. (suppression of performance deterioration, suppression of reliability deterioration).

Moreover, unlike the comparative example, the transparent electrode layer material film 28Z does not disappear and does not become a cause of electrode peeling (suppression of yield drop).

In this way, even if the manufacturing process is simplified and costs are reduced, deterioration in design on the light-receiving surface side, yield, performance, and reliability can be suppressed.

Furthermore, according to the solar cell manufacturing method of the present embodiment, a relatively inexpensive metal such as Cu is used as the material for the metal electrode layers 29 and 39 instead of a relatively expensive known Ag paste. Good too. This makes it possible to reduce the cost of solar cells.

Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above, and various changes and modifications are possible. For example, in the embodiments described above, a solar cell including an electrode layer including a transparent electrode layer and a metal electrode layer was exemplified. However, the present invention is not limited thereto, and can also be applied to a solar cell having an electrode layer containing only a metal electrode layer.

Further, in the embodiment described above, the solar cell 1 using a crystalline silicon material is illustrated, but the present invention is not limited thereto. For example, various materials such as gallium arsenide (GaAs) may be used as the material for the solar cell.

Further, in the embodiment described above, a heterojunction type solar cell 1 was illustrated as shown in FIG. 2 . However, the present invention is not limited thereto, and can also be applied to various solar cells such as homojunction solar cells.

1 Solar cell 7 First region 7f Finger portion 7b Busbar portion 8 Second region 8f Finger portion 8b Busbar portion 11 Semiconductor substrate 15 Antireflection layer 25 First conductivity type semiconductor layer 27 First electrode layer 28 First transparent electrode layer 28Z Transparent Electrode layer material film 29 First metal electrode layer 29l Base layer 29lZ Base layer material film 29u Plating layer 35 Second conductivity type semiconductor layer 37 Second electrode layer 38 Second transparent electrode layer 39 Second metal electrode layer 39l Base layer 39u Plating layer 40 resist

Claims (6)

A semiconductor substrate, a first conductivity type semiconductor layer and a first metal electrode layer formed in order in a first region that is a part of the back side of the semiconductor substrate, and another part of the back side of the semiconductor substrate. A back electrode type solar cell comprising a second conductivity type semiconductor layer and a second metal electrode layer sequentially formed in a certain second region, and an antireflection layer formed on the light-receiving surface side of the semiconductor substrate,
Each of the first metal electrode layer and the second metal electrode layer has a base layer and a plating layer,
A side surface of the semiconductor substrate and a peripheral edge of the semiconductor substrate on the light-receiving surface side,
The base layer and the antireflection layer are formed in order from the semiconductor substrate side,
the plating layer is not formed;
solar cells. The thickness of each of the first metal electrode layer and the second metal electrode layer at the center portion of the back side of the semiconductor substrate is the same as the thickness of each of the first metal electrode layer and the second metal electrode layer at the center portion of the back surface side of the semiconductor substrate, and the thickness of each of the first metal electrode layer and the second metal electrode layer at the center portion of the back surface side of the semiconductor substrate. It is more than twice the thickness of the base layer,
The solar cell according to claim 1. formed between the first conductive type semiconductor layer and the first metal electrode layer and between the second conductive type semiconductor layer and the second metal electrode layer on the back surface side of the semiconductor substrate; and further comprising a transparent electrode layer formed between the semiconductor substrate and the base layer on a side surface of the semiconductor substrate and a peripheral portion of the light-receiving surface side of the semiconductor substrate. solar cells. A semiconductor substrate, a first conductivity type semiconductor layer and a first metal electrode layer formed in order in a first region that is a part of the back side of the semiconductor substrate, and another part of the back side of the semiconductor substrate. A method for manufacturing a back electrode type solar cell, comprising a second conductive type semiconductor layer and a second metal electrode layer formed in order in a certain second region, and an antireflection layer formed on the light-receiving surface side of the semiconductor substrate. There it is,
Each of the first metal electrode layer and the second metal electrode layer has a base layer and a plating layer,
The method for manufacturing the solar cell includes:
Using a vacuum chamber, a series of the base layers are formed over the first conductivity type semiconductor layer and the second conductivity type semiconductor layer on the back surface side of the semiconductor substrate, spanning the first region and the second region. A base layer material film forming step for forming a material film of the base layer, in which the material film of the base layer is formed by wrapping around the side surface of the semiconductor substrate and the peripheral portion of the light receiving surface side of the semiconductor substrate. and,
An antireflection layer forming step of forming the antireflection layer on the light-receiving surface side of the semiconductor substrate using a vacuum chamber, the antireflection layer forming the antireflection layer on the side surface of the semiconductor substrate and the back surface of the semiconductor substrate. A process of wrapping around and forming the side periphery;
a resist forming step of forming a resist on the material film of the base layer at the boundary between the first region and the second region;
A plating layer forming step of forming the patterned plating layer on the material film of the base layer in each of the first region and the second region using a plating method using the resist as a mask. the anti-reflection layer functions as a mask and the plating layer is not formed on a side surface of the semiconductor substrate and a peripheral edge of the light-receiving surface of the semiconductor substrate;
a resist removal step of removing the resist;
A patterned underlayer is formed in each of the first region and the second region by etching the material film of the underlayer using an etching method using the plating layer as a mask. strata formation process;
including,
Method of manufacturing solar cells. The method for manufacturing a solar cell according to claim 4, wherein the plating method in the plating layer forming step is an electrolytic plating method. 6. The solar cell according to claim 4, wherein in the resist forming step, the patterned resist is formed by printing and curing a printing material containing a resin material and a solvent using a pattern printing method. Production method.

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