JP2023111632A - Method for manufacturing solar cell and solar cell - Google Patents

Abstract

To provide a method for manufacturing a solar cell capable of suppressing a decrease in designability on a light-receiving surface side even if a manufacturing process is simplified.SOLUTION: A method for manufacturing a backside electrode type solar cell comprising a first metal electrode layer 29 and a second metal electrode layer 39 including a ground layer and a plating layer in a first region and a second region on a rear surface side of a semiconductor substrate includes steps of: forming a material film of the ground layer on the rear surface side of the semiconductor substrate; forming a scribe groove 50 in a peripheral part boundary on the rear surface side of the semiconductor substrate; forming patterned plating layers 29u and 39u using a plating method in which a resist in the boundary between the first region and the second region is used; and forming patterned ground layers 29l and 39l using an etching method in which the plating layer is used as a mask. In the plating layer forming step, a feeding point in the electrolytic plating method is disposed inside of the scribe groove. In the ground layer forming step, the plating layer and the ground layer formed on a side surface of the semiconductor substrate are etched and removed.SELECTED DRAWING: Figure 2

Description

The present invention relates to a method for manufacturing a back electrode type solar cell and a back electrode type solar cell.

As solar cells, there are double-sided electrode type solar cells in which electrodes are formed on both the light-receiving side and the back side, and back electrode type solar cells in which electrodes are formed only on the back side (also called back contact type or back contact type). of solar cells. In the double-sided electrode type solar cell, since the electrodes are formed on the light receiving surface side, the metallic luster due to the electrodes is conspicuous. On the other hand, in the back electrode type solar cell, since no electrode is formed on the light receiving surface side, the light receiving surface side is uniformly black and has a high designability.

For example, a back electrode type solar cell is formed on a semiconductor substrate, a first conductivity type semiconductor layer and a first electrode layer which are sequentially formed on the back side of the semiconductor substrate, and another part of the back side of the semiconductor substrate. and a second conductivity type semiconductor layer and a second electrode layer. The first electrode layer and the second electrode layer comprise metal electrode layers and are separated from each other to prevent short circuits.

As a manufacturing process for such a back electrode type solar cell, Patent Document 1 discloses a manufacturing process for forming a metal electrode layer using a plating method using a resist as a mask. In this manufacturing process,
・On the base layer (seed layer) formed on the entire back surface, a resist is formed at the electrode layer separation location,
・After that, a separate plating layer is formed using a resist as a mask,
・Then, the resist is removed, and the underlying layer of the electrode layer separation portion is etched.
Thereby, a separated metal electrode layer composed of the underlying layer and the plating layer is formed. Thus, the manufacturing process of forming the metal electrode layer using the plating method can simplify the manufacturing process of the solar cell.

WO2012/132854

However, if the underlayer of the metal electrode layer is formed by using, for example, the CVD method or the PVD method using a vacuum chamber, the underlayer is formed around the side surfaces of the semiconductor substrate. Therefore, the plating layer of the metal electrode layer is also formed on the side surfaces of the semiconductor substrate.

As a result, metallic luster is conspicuous in the periphery of the solar cell on the light-receiving surface side, and the design of the light-receiving surface side deteriorates.

SUMMARY OF THE INVENTION An object of the present invention is to provide a solar cell manufacturing method and a solar cell capable of suppressing deterioration in the design of the light-receiving surface side even if the manufacturing process is simplified.

A method for manufacturing a solar cell according to the present invention comprises: a semiconductor substrate; A method for manufacturing a back electrode type solar cell comprising a second semiconductor layer and a second metal electrode layer formed in order in a second region which is another part of the back side, wherein the first metal electrode layer and each of the second metal electrode layers has an underlying layer and a plating layer. In the method for manufacturing the solar cell, the material of the series of underlying layers extending over the first region and the second region is formed on the first semiconductor layer and the second semiconductor layer on the back surface side of the semiconductor substrate. a base layer material film forming step of forming a film; a scribing step of forming a scribed groove at a boundary of a peripheral edge portion of the semiconductor substrate on the back surface side using a laser scribing method; In each of the first region and the second region, a resist forming step of forming a resist on the material film of the underlying layer at the boundary with the region and a plating method using the resist as a mask A plating layer forming step of forming the patterned plating layer on the material film of the base layer, a resist removing step of removing the resist, and an etching method using the plating layer as a mask to remove the lower layer. and a base layer forming step of forming the patterned base layer in each of the first region and the second region by etching a material film of the base layer. In the plating layer forming step, a feeding point of the electroplating method is arranged inside the scribed groove, and in the base layer forming step, the plating layer and the base layer formed on the side surface of the semiconductor substrate are etched. removed.

A solar cell according to the present invention comprises a semiconductor substrate, a first semiconductor layer and a first metal electrode layer formed in order in a first region that is part of the back surface of the semiconductor substrate, and the back surface of the semiconductor substrate. A back electrode type solar cell comprising a second semiconductor layer and a second metal electrode layer formed in order in a second region that is another part of the first metal electrode layer and the second metal electrode Each of the layers has an underlying layer and a plating layer, and the plating layer and the underlying layer are not formed on the side surface of the semiconductor substrate.

ADVANTAGE OF THE INVENTION According to this invention, even if it aims at the simplification of the manufacturing process of a solar cell, the deterioration of the designability of the light-receiving surface side of a solar cell can be suppressed.

It is the figure which looked at the solar cell which concerns on this embodiment from the back surface side. FIG. 2 is a sectional view taken along the line II-II in the solar cell shown in FIG. 1; FIG. 4 is a diagram showing a semiconductor layer forming step and an optical adjustment layer forming step in the method for manufacturing a solar cell according to this embodiment; FIG. 4 is a diagram showing a transparent electrode layer material film forming step and a base layer material film forming step of a metal electrode layer in the method for manufacturing a solar cell according to the present embodiment; FIG. 4 is a diagram showing a scribing step and a resist forming step in the method for manufacturing a solar cell according to this embodiment; It is a figure which shows the plating layer formation process of the metal electrode layer in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the resist removal process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the transparent electrode layer formation process and the base layer formation process of a metal electrode layer in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the electric power feeding point of an electroplating method. FIG. 4 is a cross-sectional view of a solar cell according to Modification 1 of the present embodiment; It is a figure which shows the scribing process and the resist formation process in the manufacturing method of the solar cell which concerns on the modification 1 of this embodiment. It is a figure which shows the plating layer formation process of the metal electrode layer in the manufacturing method of the solar cell which concerns on the modification 1 of this embodiment. It is a figure which shows the resist removal process in the manufacturing method of the solar cell based on the modified example 1 of this embodiment. It is a figure which shows the base layer formation process of a transparent electrode layer formation process and a metal electrode layer in the manufacturing method of the solar cell which concerns on the modification 1 of this embodiment. FIG. 5 is a cross-sectional view of a solar cell according to Modification 2 of the present embodiment; It is a figure which shows the scribing process and the resist formation process in the manufacturing method of the solar cell based on the modified example 2 of this embodiment. It is a figure which shows the plating layer formation process of the metal electrode layer in the manufacturing method of the solar cell which concerns on the modification 2 of this embodiment. It is a figure which shows the resist removal process in the manufacturing method of the solar cell based on the modified example 2 of this embodiment. It is a figure which shows the base layer formation process of a transparent electrode layer formation process and a metal electrode layer in the manufacturing method of the solar cell which concerns on the modification 2 of this embodiment. FIG. 11 is a cross-sectional view of an example of a solar cell according to Modification 3 of the present embodiment; FIG. 11 is a cross-sectional view of an example of a solar cell according to Modification 3 of the present embodiment; FIG. 11 is a cross-sectional view of an example of a solar cell according to Modification 3 of the present embodiment; It is a figure which shows the scribing process and the resist formation process in the manufacturing method of the solar cell based on the modified example 3 of this embodiment. It is a figure which shows the plating layer formation process of the metal electrode layer in the manufacturing method of the solar cell which concerns on the modification 3 of this embodiment. It is a figure which shows the resist removal process in the manufacturing method of the solar cell based on the modified example 3 of this embodiment. It is a figure which shows an example of the base layer formation process of the transparent electrode layer formation process and the metal electrode layer in the manufacturing method of the solar cell which concerns on the modification 3 of this embodiment. It is a figure which shows an example of the base layer formation process of the transparent electrode layer formation process and the metal electrode layer in the manufacturing method of the solar cell which concerns on the modification 3 of this embodiment. It is a figure which shows an example of the base layer formation process of the transparent electrode layer formation process and the metal electrode layer in the manufacturing method of the solar cell which concerns on the modification 3 of this embodiment.

An example of an embodiment of the present invention will be described below with reference to the accompanying drawings. In each drawing, the same reference numerals are given to the same or corresponding parts. Also, for convenience, hatching, member numbers, etc. may be omitted, but in such cases, other drawings shall be referred to.

(solar cell)
FIG. 1 is a view of the solar cell according to the present embodiment viewed from the back side, and FIG. 2 is a cross-sectional view of the solar cell shown in FIG. 1 taken along the line II-II. The solar cell 1 shown in FIGS. 1 and 2 is a back electrode type (also referred to as back contact type or back contact type) and heterojunction type solar cell.

The solar cell 1 has a semiconductor substrate 11 with two main surfaces, and has a first region 7 and a second region 8 on the main surface of the semiconductor substrate 11 . Hereinafter, the main surface of the semiconductor substrate 11 on the light receiving side is referred to as a light receiving surface, and the main surface opposite to the light receiving surface (one main surface) of the main surfaces of the semiconductor substrate 11 is referred to as the rear surface.

The first region 7 has a so-called comb shape, and includes a plurality of finger portions 7f corresponding to comb teeth and busbar portions 7b corresponding to support portions of the comb teeth. The busbar portion 7b extends in a first direction (X direction) along one side portion of the semiconductor substrate 11, and the finger portions 7f extend from the busbar portion 7b in a second direction (Y direction) crossing the first direction. ).

Similarly, the second region 8 has a so-called comb shape, and includes a plurality of finger portions 8f corresponding to comb teeth and busbar portions 8b corresponding to support portions for the comb teeth. The busbar portion 8b extends in a first direction (X direction) along one side portion of the semiconductor substrate 11 opposite to the other side portion, and the finger portions 8f extend in a second direction (Y direction) from the busbar portion 8b. direction).

The finger portions 7f and the finger portions 8f are band-shaped extending in the second direction (Y direction) and are alternately provided in the first direction (X direction). Note that the first region 7 and the second region 8 may be formed in stripes.

As shown in FIG. 2 , the solar cell 1 includes a semiconductor layer (third semiconductor layer) 13 and an optical adjustment layer 15 that are laminated in order on the light receiving surface side of the semiconductor substrate 11 . Solar cell 1 also includes a first semiconductor layer 25 and a first electrode layer 27 that are laminated in order on a portion (first region 7 ) of the back surface of semiconductor substrate 11 . Solar cell 1 also includes a second semiconductor layer 35 and a second electrode layer 37 that are laminated in order on another part (second region 8 ) of the back surface side of semiconductor substrate 11 .

Semiconductor substrate 11 is formed of a crystalline silicon material such as monocrystalline silicon or polycrystalline silicon. The semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which a crystalline silicon material is doped with an n-type dopant. The semiconductor substrate 11 may be, for example, a p-type semiconductor substrate in which a crystalline silicon material is doped with a p-type dopant. Examples of n-type dopants include phosphorus (P). Examples of p-type dopants include boron (B). The semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light receiving surface side and generates photocarriers (electrons and holes).

Since crystalline silicon is used as the material of the semiconductor substrate 11, dark current is relatively small, and relatively high output (stable output regardless of illuminance) can be obtained even when the intensity of incident light is low.

The semiconductor substrate 11 has a pyramid-shaped fine uneven structure called a texture structure on the back surface side. As a result, the efficiency of collecting the light that has passed through the semiconductor substrate 11 without being absorbed increases.

Further, the semiconductor substrate 11 may have a pyramid-shaped fine uneven structure called a texture structure on the light receiving surface side. As a result, the reflection of incident light on the light receiving surface is reduced, and the light confinement effect in the semiconductor substrate 11 is improved.

The third semiconductor layer 13 is formed on the light receiving surface side of the semiconductor substrate 11 . The third semiconductor layer 13 is made of a material whose main component is, for example, an intrinsic (i-type) amorphous silicon material. The third semiconductor layer 13 functions as a passivation layer, suppresses recombination of carriers generated in the semiconductor substrate 11, and enhances carrier recovery efficiency.

The optical adjustment layer 15 is formed on the third semiconductor layer 13 on the light receiving surface side of the semiconductor substrate 11 . The optical adjustment layer 15 functions as an antireflection layer that prevents reflection of incident light, and also functions as a protective layer that protects the light receiving surface side of the semiconductor substrate 11 and the third semiconductor layer 13 . The optical adjustment layer 15 is formed of an insulator material such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON).

The first semiconductor layer 25 is formed in the first region 7 on the back side of the semiconductor substrate 11 . On the other hand, the second semiconductor layer 35 is formed in the second region 8 on the back side of the semiconductor substrate 11 . That is, the first semiconductor layer 25 and the second semiconductor layer 35 have a strip shape and extend in the Y direction. The first semiconductor layers 25 and the second semiconductor layers 35 are alternately arranged in the X direction. A portion of the second semiconductor layer 35 may overlap a portion of the adjacent first semiconductor layer 25 (not shown).

The first semiconductor layer 25 is made of, for example, an amorphous silicon material. The first semiconductor layer 25 is, for example, a p-type semiconductor layer in which an amorphous silicon material is doped with a p-type dopant (for example, boron (B) described above). Note that the first semiconductor layer 25 may include a passivation layer. The passivation layer is made of a material containing, for example, an intrinsic (i-type) amorphous silicon material as a main component. The passivation layer suppresses recombination of carriers generated in the semiconductor substrate 11 and enhances carrier recovery efficiency.

The second semiconductor layer 35 is made of, for example, an amorphous silicon material. The second semiconductor layer 35 is, for example, an n-type semiconductor layer formed by doping an n-type dopant (for example, phosphorus (P) described above) into an amorphous silicon material. The first semiconductor layer 25 may be an n-type semiconductor layer, and the second semiconductor layer 35 may be a p-type semiconductor layer. In addition, the second semiconductor layer 35 may include a passivation layer. The passivation layer is made of a material containing, for example, an intrinsic (i-type) amorphous silicon material as a main component. The passivation layer suppresses recombination of carriers generated in the semiconductor substrate 11 and enhances carrier recovery efficiency.

The first electrode layer 27 is formed on the first semiconductor layer 25 , that is, in the first region 7 on the back side of the semiconductor substrate 11 . On the other hand, the second electrode layer 37 is formed on the second semiconductor layer 35 , that is, in the second region 8 on the back side of the semiconductor substrate 11 . That is, the first electrode layer 27 and the second electrode layer 37 are strip-shaped and extend in the Y direction. The first electrode layers 27 and the second electrode layers 37 are alternately provided in the X direction.

The first electrode layer 27 has a first transparent electrode layer 28 and a first metal electrode layer 29 that are sequentially laminated on the first semiconductor layer 25 . On the other hand, the second electrode layer 37 has a second transparent electrode layer 38 and a second metal electrode layer 39 that are sequentially laminated on the second semiconductor layer 35 . The first metal electrode layer 29 has a two-layer structure of an underlying layer 29l and a plating layer 29u, and the second metal electrode layer 39 has a two-layer structure of an underlying layer 39l and a plating layer 39u.

The first transparent electrode layer 28 and the second transparent electrode layer 38 are made of a transparent conductive material. Transparent conductive materials include ITO (Indium Tin Oxide: composite oxide of indium oxide and tin oxide), ZnO (Zinc Oxide: zinc oxide), and the like.

The base layer 29l in the first metal electrode layer 29 and the base layer 39l in the second metal electrode layer 39 contain metal materials such as silver, copper, and aluminum formed using a PVD method such as sputtering. On the other hand, the plated layer 29u of the first metal electrode layer 29 and the plated layer 39u of the second metal electrode layer 39 contain a metal material such as silver, copper, nickel, etc. formed by plating, for example.

The first electrode layers 27 and the second electrode layers 37 are strip-shaped extending in the second direction (Y direction) and are alternately arranged in the first direction (X direction). That is, the first transparent electrode layers 28 and the second transparent electrode layers 38 are band-shaped extending in the second direction (Y direction) and are alternately arranged in the first direction (X direction). The first metal electrode layers 29 and the second metal electrode layers 39 are strip-shaped extending in the second direction (Y direction) and are alternately arranged in the first direction (X direction). The first transparent electrode layer 28 and the second transparent electrode layer 38 are separated from each other, and the first metal electrode layer 29 and the second metal electrode layer 39 are also separated from each other.

None of the plating layers 29u, 39u and the base layers 29l, 39l of the metal electrode layers 29, 39, the transparent electrode layers 28, 38, and the semiconductor layers 25, 35 are formed on the side surface of the solar cell 1, A semiconductor substrate 11 is exposed.

A scribed groove 50 is formed at the boundary of the peripheral edge portion R1 on the back side of the solar cell 1 . The depth of the scribed groove 50 is at least equal to or greater than the film thickness of the underlying layers 29l and 39l. Plated layers 29u and 39u of metal electrode layers 29 and 39, underlying layers 29l and 39l, and transparent electrode layers 28 and 38 are formed on peripheral edge portion R1 outside scribed groove 50 on the back side of solar cell 1. The semiconductor layer 35 is exposed.

At least one feeding point 60 (feeding point for electroplating, which will be described later) is arranged in a central portion R2 inside the scribed groove 50 on the back surface of the solar cell 1 . The feeding points 60 have a shape such as a circle, and are arranged, for example, at two diagonal corners of the four corners. Feeding points may be provided on the busbar portions 7b and 8b. When the feeding point is provided on the busbar portions 7b and 8b, the feeding point 60 may have a recessed structure. Specifically, the plating layers 29u, 39u and the underlying layers 29l, 39l of the metal electrode layers 29, 39 and the transparent electrode layers 28, 38 are not formed on at least part of the feeding point, and the semiconductor layer 35 is exposed. On the other hand, the plating layers 29u and 39u of the metal electrode layers 29 and 39, the base layers 29l and 39l, and the transparent electrode layers 28 and 38 are formed in the peripheral portion of the power feeding portion, and the power feeding point has a recessed structure. may be

(Method for manufacturing solar cell)
Next, a method for manufacturing a solar cell according to this embodiment will be described with reference to FIGS. 3A to 3F. FIG. 3A is a diagram showing a semiconductor layer forming step and an optical adjustment layer forming step in the method for manufacturing a solar cell according to this embodiment, and FIG. 3B shows a transparent electrode layer material in the method for manufacturing a solar cell according to this embodiment. It is a figure which shows the film|membrane formation process and the base layer material film|membrane formation process of a metal electrode layer. FIG. 3C is a diagram showing a scribing step and a resist forming step in the method for manufacturing a solar cell according to this embodiment, and FIG. It is a figure which shows a formation process. FIG. 3E is a diagram showing a resist removing step in the method for manufacturing a solar cell according to this embodiment, and FIG. is a diagram showing a base layer forming step of No.

First, as shown in FIG. 3A, a first semiconductor layer 25 is formed on a portion of the back surface of the semiconductor substrate 11, specifically in the first region 7 (semiconductor layer forming step). For example, after forming a first semiconductor layer material film on the entire back surface side of the semiconductor substrate 11 using the CVD method or the PVD method, a resist or a metal mask generated using a photolithography technique or a printing technique is used. The first semiconductor layer 25 may be patterned using the etching method utilized.

The etching solution for the p-type semiconductor layer material film includes, for example, an acidic solution such as hydrofluoric acid containing ozone or a mixed solution of nitric acid and hydrofluoric acid. and alkaline solutions such as aqueous potassium hydroxide.

Alternatively, when laminating the first semiconductor layer on the back surface side of the semiconductor substrate 11 using the CVD method or the PVD method, the first semiconductor layer 25 may be formed and patterned at the same time using a mask.

Next, a second semiconductor layer 35 is formed on another part of the back surface side of the semiconductor substrate 11, specifically in the second region 8 (semiconductor layer forming step). For example, in the same manner as described above, after forming a second semiconductor layer material film on the entire back surface side of the semiconductor substrate 11 using the CVD method or the PVD method, a resist generated using a photolithography technique or a printing technique, or The second semiconductor layer 35 may be patterned using an etching method using a metal mask.

Alternatively, when laminating the second semiconductor layer on the back side of the semiconductor substrate 11 using the CVD method or the PVD method, the second semiconductor layer 35 may be formed and patterned at the same time using a mask.

In this semiconductor layer forming step, the first semiconductor layer 25 or the second semiconductor layer 35 is also formed on the side surface of the semiconductor substrate 11 . The thickness of the semiconductor layer formed on the side surface of the semiconductor substrate 11 is thinner than the thickness of the semiconductor layer formed on the back side of the semiconductor substrate 11 . In the example of FIG. 3A, a second semiconductor layer 35 is formed on the side surface of the semiconductor substrate 11 .

In this semiconductor layer forming step, the third semiconductor layer 13 and the optical adjustment layer 15 may be formed on the entire light receiving surface side of the semiconductor substrate 11 (optical adjustment layer forming step).

Next, as shown in FIG. 3B, a series of transparent electrode layer material films 28Z are formed on the first semiconductor layer 25 and the second semiconductor layer 35 over the first region 7 and the second region 8 (transparent electrode layer material film 28Z). layer material film forming step). As a method for forming the transparent electrode layer material film 28Z, for example, a CVD method or a PVD method is used.

In this transparent electrode layer material film formation process, the transparent electrode layer material film 28Z is also formed on the side surface of the semiconductor substrate 11. As shown in FIG. The film thickness of the transparent electrode layer material film formed on the side surface of the semiconductor substrate 11 is thinner than the film thickness of the transparent electrode layer material film formed on the back surface side of the semiconductor substrate 11 .

Next, on the transparent electrode layer material film 28Z, that is, on the first semiconductor layer 25 and the second semiconductor layer 35, a series of underlying layer material films 29lZ are formed across the first region 7 and the second region 8 ( base layer material film forming step). As a method for forming the underlying layer material film 29lZ, for example, a PVD method such as sputtering is used.

In this base layer material film forming step, the base layer material film 29lZ is also formed on the side surface of the semiconductor substrate 11. Next, as shown in FIG. The film thickness of the underlying layer material film formed on the side surface of the semiconductor substrate 11 is thinner than the film thickness of the underlying layer material film formed on the back surface side of the semiconductor substrate 11 .

Next, as shown in FIG. 3C, a laser scribing method is used to form a scribed groove 50 at the boundary of the peripheral portion R1 on the back side of the semiconductor substrate 11 (scribing step). It is preferable that the depth of the scribed groove 50 is at least equal to or greater than the film thickness of the underlying layer material film 29lZ. In other words, it is preferable that the depth of the scribed groove 50 passes through the underlying layer material film 29lZ and reaches at least the transparent electrode layer material film 28Z.
As a result, the base layer material film 29lZ, which has a relatively low resistance, is separated by the scribed grooves 50. FIG. The transparent electrode layer material film 28Z, which has a relatively high resistance, may or may not be separated.

Further, a resist 40 is formed on the underlying layer material film 29lZ at the boundary between the first region 7 and the second region 8 (resist forming step). A method of forming the resist 40 is not particularly limited, but includes, for example, a photolithography method and a printing method. Among these, the printing method is preferable from the viewpoint of simplification of the manufacturing process. In particular, pattern printing methods such as press printing such as screen printing or gravure printing, or ejection printing such as inkjet printing are preferred. In the pattern printing method, a patterned resist 40 is formed by printing and baking (hardening) a printing material containing a resin material and a solvent.

Next, as shown in FIG. 3D, a patterned plating layer 29u is formed on the underlying layer material film 29lZ in the first region 7 by using a plating method using the resist 40 as a mask. A patterned plated layer 39u is formed on the base layer material film 29lZ in step 8 (plated metal electrode layer forming step).

Specifically, as shown in FIG. 4 , a feeding point 60 for electroplating is arranged inside the scribed groove 50 . As described above, the scribed groove 50 separates the underlying layer material film 29lZ, which has a relatively low resistance. 11 is not supplied to the peripheral edge portion R1 outside the scribed groove 50. As shown in FIG. Since the transparent electrode layer material film 28Z has a relatively high resistance, the current supplied to the peripheral portion R1 outside the scribe groove 50 in the semiconductor substrate 11 through the transparent electrode layer material film 28Z is small. Therefore, it is possible to suppress the formation of a plating layer in the peripheral portion R1 outside the scribe groove 50 in the semiconductor substrate 11 .

As a result, as shown in FIG. 3D, even if the plating layer 39u is formed on the peripheral edge portion R1 outside the scribe groove 50 on the back surface side of the semiconductor substrate 11, the plating layer 39u formed on the peripheral edge portion R1 will not be formed. is thinner than the film thickness of the plating layers 29u and 39u formed in the central portion R2 inside the scribe groove 50 on the back surface side of the semiconductor substrate 11. As shown in FIG. Alternatively, the plating layer 39u is not formed on the peripheral edge portion R1 outside the scribe groove 50 on the back surface side of the semiconductor substrate 11. As shown in FIG.

Further, even if the plating layer 39u is formed on the side surface of the semiconductor substrate 11, the film thickness of the plating layer 39u formed on the side surface of the semiconductor substrate 11 does not reach the central portion R2 inside the scribe groove 50 on the back surface side of the semiconductor substrate 11. It is thinner than the film thickness of the plated layers 29u and 39u to be formed. Alternatively, the side surface of the semiconductor substrate 11 is not formed with the plating layer 39u.

Next, as shown in FIG. 3E, the resist 40 is removed (resist removing step). As the resist removing solution, an alkaline aqueous solution such as a sodium hydroxide aqueous solution or an organic solvent such as acetone is used.

Next, as shown in FIG. 3F, an etching method using the plating layer 29u and the plating layer 39u as a mask is used to etch the base layer material film 29lZ and the transparent electrode layer material film 28Z, thereby forming the first region 7. , a patterned first transparent electrode layer 28 and an underlying layer 29l are formed, and a patterned second transparent electrode layer 38 and an underlying layer 39l are formed in the second region 8 (transparent electrode layer forming step, and a base layer forming step). As a result, a first metal electrode layer 29 consisting of the underlying layer 29l and the plating layer 29u and a second metal electrode layer 39 consisting of the underlying layer 39l and the plating layer 39u are formed. Also, a first electrode layer 27 consisting of a first transparent electrode layer 28 and a first metal electrode layer 29, and a second electrode layer 37 consisting of a second transparent electrode layer 38 and a second metal electrode layer 39 are formed. be.

As the etching solution for etching the base layer material film 29lZ and the transparent electrode layer material film 28Z, for example, when the transparent electrode layer material film 28Z is ITO and the base layer material film 29lZ is copper, ammonium persulfate (ammonium persulfate) or the like is used. and acid solutions such as hydrochloric acid (HCl).

In this base layer forming step, the plating layer 39u, the base layer material film 29lZ, and the transparent electrode layer material film 28Z formed on the side surface of the semiconductor substrate 11 are etched and removed. Specifically, the plated layer and underlying layer of the metal electrode layer formed on the side surface of the semiconductor substrate 11 and the transparent electrode layer are etched and removed. If the plating layer 39u is not formed on the side surface of the semiconductor substrate 11, the base layer of the metal electrode layer and the transparent electrode layer formed on the side surface of the semiconductor substrate 11 are etched and removed. At this time, the semiconductor layers 35 and 13 and the optical adjustment layer 15 formed on the side surfaces of the semiconductor substrate 11 remain.

In addition, the plated layer and underlying layer of the metal electrode layer and the transparent electrode layer formed in the peripheral portion R1 outside the scribe groove 50 on the back side of the semiconductor substrate 11 are etched and removed, exposing the semiconductor layer. When the plated layer 39u is not formed on the peripheral edge portion R1 on the back side of the semiconductor substrate 11, the underlying layer of the metal electrode layer and the transparent electrode layer formed on the peripheral edge portion R1 on the back side of the semiconductor substrate 11 are not etched. removed to expose the semiconductor layer.

Through the above steps, the back electrode type solar cell 1 of the present embodiment shown in FIGS. 1 and 2 is obtained.

As described above, according to the solar cell manufacturing method of the present embodiment, the plating layers 29u and 39u in the metal electrode layers 29 and 39 are formed using the plating method. Furthermore, the plating layers 29u and 39u on the metal electrode layers 29 and 39 are formed directly (film formation and patterning are performed simultaneously) using a plating method using the resist 40 as a mask. This enables simplification and cost reduction of the solar cell manufacturing process.

In addition, according to the method for manufacturing a solar cell of the present embodiment, in the plating method, a printing material containing a resin material and a solvent is printed using a pattern printing method and baked (cured) to directly (manufacture The film and patterning may be performed simultaneously) to form a patterned resist 40 . This enables simplification and cost reduction of resist formation as compared with resist formation using photolithography technology, for example. Therefore, the manufacturing process of the solar cell can be simplified and the cost can be reduced.

Further, according to the method of manufacturing the solar cell of the present embodiment, as the material of the metal electrode layers 29 and 39, a relatively inexpensive metal such as Cu is used instead of the relatively expensive known Ag paste. good too. As a result, the cost of the solar cell can be reduced.

By the way, when forming an underlying layer of a metal electrode layer for forming a metal electrode layer by using a plating method using a resist as a mask, if a CVD method or a PVD method using a vacuum chamber, for example, is used, the underlying layer may be damaged. , and is formed around the side surfaces of the semiconductor substrate. Therefore, the plating layer of the metal electrode layer is also formed on the side surfaces of the semiconductor substrate.
As a result, metallic luster is conspicuous in the periphery of the solar cell on the light-receiving surface side, and the design of the light-receiving surface side deteriorates.

Regarding this point, according to the method for manufacturing a solar cell of the present embodiment,
- After the step of forming the underlying layer material film of the metal electrode layer, a scribed groove 50 having a thickness equal to or larger than the thickness of the underlying layer material film of the metal electrode layer is formed at the boundary of the peripheral portion on the back surface side of the semiconductor substrate 11,
- In the step of forming the plating layer of the metal electrode layer, the feed point of the electroplating method is arranged inside the scribed groove 50 .
As a result, the plating layer 39u is not formed on the peripheral edge portion R1 outside the scribe groove 50 on the back surface side of the semiconductor substrate 11 and on the side surface of the semiconductor substrate 11 .

Alternatively, even if the plating layer 39u is formed on the peripheral edge portion R1 outside the scribe groove 50 on the back surface side of the semiconductor substrate 11 and on the side surface of the semiconductor substrate 11, the peripheral edge portion R1 on the back surface side of the semiconductor substrate 11 and the side surface of the semiconductor substrate 11 are formed. The film thickness of the plating layer 39u formed on the side surface of the semiconductor substrate 11 is thin. Therefore, in the subsequent etching of the underlying layer in the underlying layer material film formation step of the metal electrode layer, the peripheral edge portion R1 on the back surface side of the semiconductor substrate 11 and the plated layer formed on the side surface of the semiconductor substrate 11 are etched and removed. be.

As described above, according to the solar cell manufacturing method and the solar cell of the present embodiment, the plating layer of the metal electrode layer is formed on the side surface of the semiconductor substrate even if the plating method is used to simplify the manufacturing process. It is possible to suppress the deterioration of the design of the light-receiving surface side.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various changes and modifications are possible. For example, in the embodiment described above, in the scribing step shown in FIG. 3C, the depth of the scribed grooves 50 is about the film thickness of the underlying layer of the metal electrode layer. However, the present invention is not limited to this, and the depth of the scribed groove 50 can be variously changed as shown in Modified Examples 1 to 3 below.

(Modification 1)
For example, the depth of the scribed grooves 50 may be at least equal to or greater than the film thicknesses of the underlying layer of the metal electrode layer and the transparent electrode layer. In other words, the depth of the scribed grooves 50 may reach at least the semiconductor layer through the underlying layer of the metal electrode layer and the transparent electrode layer.
FIG. 5 is a cross-sectional view of a solar cell according to Modification 1 of the present embodiment.
FIG. 6A is a diagram showing a scribing step and a resist forming step in the method for manufacturing a solar cell according to Modification 1 of the present embodiment, and FIG. It is a figure which shows the plating layer formation process of a metal electrode layer. FIG. 6C is a diagram showing a resist removing step in the method for manufacturing a solar cell according to Modification 1 of this embodiment, and FIG. It is a figure which shows the base layer formation process of an electrode layer formation process and a metal electrode layer.

As shown in FIG. 6A, a laser scribing method is used to form a scribed groove 50 at the boundary of the peripheral portion R1 on the back side of the semiconductor substrate 11 (scribing step). The depth of the scribed groove 50 may be at least equal to or greater than the film thicknesses of the underlying layer material film 29lZ and the transparent electrode layer material film 28Z. In other words, the depth of the scribed groove 50 may reach at least the semiconductor layer 35 through the underlying layer material film 29lZ and the transparent electrode layer material film 28Z.
As a result, the scribe groove 50 separates the transparent electrode layer material film 28Z, which has a relatively high resistance, from the underlying layer material film 29lZ, which has a relatively low resistance.

Further, a resist 40 is formed on the underlying layer material film 29lZ at the boundary between the first region 7 and the second region 8 (resist forming step).

Next, as shown in FIG. 6B, a patterned plating layer 29u is formed on the base layer material film 29lZ in the first region 7 by using a plating method using the resist 40 as a mask. A patterned plated layer 39u is formed on the base layer material film 29lZ in step 8 (plated metal electrode layer forming step).

Specifically, as shown in FIG. 4 , a feeding point 60 for electroplating is arranged inside the scribed groove 50 . As described above, the underlying layer material film 29lZ and the transparent electrode layer material film 28Z are separated by the scribed grooves 50, so that the current supplied to the feeding point 60 is applied to the underlying layer material film 29lZ and the transparent electrode layer material film 29lZ. 28Z, it is not supplied to the peripheral edge portion outside the scribed groove 50 in the semiconductor substrate 11 . Since the semiconductor layer 35 has a relatively high resistance, the current supplied to the peripheral portion of the semiconductor substrate 11 outside the scribe groove 50 is small through the semiconductor layer 35 . Therefore, it is possible to suppress the formation of a plating layer in the peripheral portion R1 outside the scribe groove 50 in the semiconductor substrate 11 .

As a result, as shown in FIG. 6B, even if the plating layer 39u is formed on the peripheral edge portion R1 outside the scribe groove 50 on the back surface side of the semiconductor substrate 11, the plating layer 39u formed on the peripheral edge portion R1 will not be formed. is thinner than the film thickness of the plating layers 29u and 39u formed in the central portion R2 inside the scribe groove 50 on the back surface side of the semiconductor substrate 11. As shown in FIG. Alternatively, the plating layer 39u is not formed on the peripheral edge portion R1 outside the scribe groove 50 on the back surface side of the semiconductor substrate 11. As shown in FIG.

Further, even if the plating layer 39u is formed on the side surface of the semiconductor substrate 11, the film thickness of the plating layer 39u formed on the side surface of the semiconductor substrate 11 does not reach the central portion R2 inside the scribe groove 50 on the back surface side of the semiconductor substrate 11. It is thinner than the film thickness of the plated layers 29u and 39u to be formed. Alternatively, the side surface of the semiconductor substrate 11 is not formed with the plating layer 39u.

Next, as shown in FIG. 6C, the resist 40 is removed (resist removing step).

Next, as shown in FIG. 6D, an etching method using the plating layer 29u and the plating layer 39u as masks is used to etch the underlying layer material film 29lZ and the transparent electrode layer material film 28Z, thereby forming the first region 7. , a patterned first transparent electrode layer 28 and an underlying layer 29l are formed, and a patterned second transparent electrode layer 38 and an underlying layer 39l are formed in the second region 8 (transparent electrode layer forming step, and a base layer forming step).

In this base layer forming step, the plating layer 39u, the base layer material film 29lZ, and the transparent electrode layer material film 28Z formed on the side surface of the semiconductor substrate 11 are etched and removed. Specifically, the plated layer and underlying layer of the metal electrode layer formed on the side surface of the semiconductor substrate 11 and the transparent electrode layer are etched and removed. If the plating layer 39u is not formed on the side surface of the semiconductor substrate 11, the base layer of the metal electrode layer and the transparent electrode layer formed on the side surface of the semiconductor substrate 11 are etched and removed. At this time, the semiconductor layers 35 and 13 and the optical adjustment layer 15 formed on the side surfaces of the semiconductor substrate 11 remain.

In addition, the plated layer and underlying layer of the metal electrode layer and the transparent electrode layer formed in the peripheral portion R1 outside the scribe groove 50 on the back side of the semiconductor substrate 11 are etched and removed, exposing the semiconductor layer. When the plated layer 39u is not formed on the peripheral edge portion R1 on the back side of the semiconductor substrate 11, the underlying layer of the metal electrode layer and the transparent electrode layer formed on the peripheral edge portion R1 on the back side of the semiconductor substrate 11 are not etched. removed to expose the semiconductor layer.

In the solar cell 1 of Modification 1 thus obtained, as shown in FIG. And neither of the transparent electrode layers 28 and 38 are formed.

A scribed groove 50 is formed at the boundary of the peripheral edge portion R1 on the back surface side of the solar cell 1 . The depth of the scribed grooves 50 is at least equal to or greater than the thicknesses of the underlying layers 29 l and 39 l and the transparent electrode layers 28 and 38 . Plated layers 29u and 39u of metal electrode layers 29 and 39, underlying layers 29l and 39l, and transparent electrode layers 28 and 38 are formed on peripheral edge portion R1 outside scribed groove 50 on the back side of solar cell 1. The semiconductor layer 35 is exposed.

(Modification 2)
Alternatively, for example, the depth of the scribed grooves 50 may be equal to or greater than the film thicknesses of the underlying layer of the metal electrode layer, the transparent electrode layer, and the semiconductor layer. In other words, the depth of the scribed grooves 50 may reach the semiconductor substrate through the underlying layer of the metal electrode layer, the transparent electrode layer and the semiconductor layer.
FIG. 7 is a cross-sectional view of a solar cell according to Modification 2 of the present embodiment.
FIG. 8A is a diagram showing a scribing step and a resist forming step in a method for manufacturing a solar cell according to Modification 2 of the present embodiment, and FIG. It is a figure which shows the plating layer formation process of a metal electrode layer. FIG. 8C is a diagram showing a resist removing step in the method for manufacturing a solar cell according to Modification 2 of this embodiment, and FIG. It is a figure which shows the base layer formation process of an electrode layer formation process and a metal electrode layer.

As shown in FIG. 8A, a laser scribing method is used to form a scribed groove 50 at the boundary of the peripheral portion R1 on the back side of the semiconductor substrate 11 (scribing step). The depth of the scribed groove 50 may be equal to or greater than the film thicknesses of the underlying layer material film 29lZ, the transparent electrode layer material film 28Z, and the semiconductor layer 35 . In other words, the depth of the scribed groove 50 may reach the semiconductor substrate 11 through the underlying layer material film 29lZ, the transparent electrode layer material film 28Z, and the semiconductor layer 35 .
As a result, the scribe groove 50 separates the transparent electrode layer material film 28Z and the semiconductor layer 35, which have a relatively high resistance, from the underlying layer material film 29lZ, which has a relatively low resistance.

Further, a resist 40 is formed on the underlying layer material film 29lZ at the boundary between the first region 7 and the second region 8 (resist forming step).

Next, as shown in FIG. 8B, the plating method using the resist 40 as a mask is used to form a patterned plating layer 29u on the underlying layer material film 29lZ in the first region 7, and then the second region 7 is formed. A patterned plated layer 39u is formed on the base layer material film 29lZ in step 8 (plated metal electrode layer forming step).

Specifically, as shown in FIG. 4 , a feeding point 60 for electroplating is arranged inside the scribed groove 50 . As described above, the underlying layer material film 29lZ, the transparent electrode layer material film 28Z, and the semiconductor layer 35 are separated by the scribed grooves 50, so that the current supplied to the feeding point 60 is applied to the underlying layer material film 29lZ and the transparent electrode layer material film 29lZ. It is not supplied to the peripheral portion of the semiconductor substrate 11 outside the scribe groove 50 via the electrode layer material film 28Z. Since the semiconductor substrate 11 has a relatively high resistance, the current supplied to the peripheral portion of the semiconductor substrate 11 outside the scribe grooves 50 is small through the semiconductor substrate 11 . Therefore, it is possible to suppress the formation of a plating layer in the peripheral portion R1 outside the scribe groove 50 in the semiconductor substrate 11 .

As a result, as shown in FIG. 8B, even if the plating layer 39u is formed on the peripheral edge portion R1 outside the scribe groove 50 on the back surface side of the semiconductor substrate 11, the plating layer 39u formed on the peripheral edge portion R1 is removed. is thinner than the film thickness of the plating layers 29u and 39u formed in the central portion R2 inside the scribe groove 50 on the back surface side of the semiconductor substrate 11. As shown in FIG. Alternatively, the plating layer 39u is not formed on the peripheral edge portion R1 outside the scribe groove 50 on the back surface side of the semiconductor substrate 11. As shown in FIG.

Further, even if the plating layer 39u is formed on the side surface of the semiconductor substrate 11, the film thickness of the plating layer 39u formed on the side surface of the semiconductor substrate 11 does not reach the central portion R2 inside the scribe groove 50 on the back surface side of the semiconductor substrate 11. It is thinner than the film thickness of the plated layers 29u and 39u to be formed. Alternatively, the side surface of the semiconductor substrate 11 is not formed with the plating layer 39u.

Next, as shown in FIG. 8C, the resist 40 is removed (resist removing step).

Next, as shown in FIG. 6D, an etching method using the plating layer 29u and the plating layer 39u as masks is used to etch the underlying layer material film 29lZ and the transparent electrode layer material film 28Z, thereby forming the first region 7. , a patterned first transparent electrode layer 28 and an underlying layer 29l are formed, and a patterned second transparent electrode layer 38 and an underlying layer 39l are formed in the second region 8 (transparent electrode layer forming step, and a base layer forming step).

In this base layer forming step, the plating layer 39u, the base layer material film 29lZ, and the transparent electrode layer material film 28Z formed on the side surface of the semiconductor substrate 11 are etched and removed. Specifically, the plated layer and underlying layer of the metal electrode layer formed on the side surface of the semiconductor substrate 11 and the transparent electrode layer are etched and removed. If the plating layer 39u is not formed on the side surface of the semiconductor substrate 11, the base layer of the metal electrode layer and the transparent electrode layer formed on the side surface of the semiconductor substrate 11 are etched and removed. At this time, the semiconductor layers 35 and 13 and the optical adjustment layer 15 formed on the side surfaces of the semiconductor substrate 11 remain.

In addition, the plated layer and underlying layer of the metal electrode layer and the transparent electrode layer formed in the peripheral portion R1 outside the scribe groove 50 on the back side of the semiconductor substrate 11 are etched and removed, exposing the semiconductor layer. When the plated layer 39u is not formed on the peripheral edge portion R1 on the back side of the semiconductor substrate 11, the underlying layer of the metal electrode layer and the transparent electrode layer formed on the peripheral edge portion R1 on the back side of the semiconductor substrate 11 are not etched. removed to expose the semiconductor layer.

In the solar cell 1 of Modification Example 2 obtained in this way, as shown in FIG. And neither of the transparent electrode layers 28 and 38 are formed.

A scribed groove 50 is formed at the boundary of the peripheral edge portion R1 on the back surface side of the solar cell 1 . The depth of the scribed grooves 50 is at least equal to or greater than the film thicknesses of the underlying layers 29 l and 39 l, the transparent electrode layers 28 and 38 and the semiconductor layers 25 and 35 . Plated layers 29u and 39u of metal electrode layers 29 and 39, underlying layers 29l and 39l, and transparent electrode layers 28 and 38 are formed on peripheral edge portion R1 outside scribed groove 50 on the back side of solar cell 1. The semiconductor layer 35 is exposed.

(Modification 3)
Alternatively, for example, the depth of the scribed grooves 50 may be less than the film thickness of the underlying layer of the metal electrode layer.
9 to 11 are cross-sectional views of an example of a solar cell according to Modification 3 of the present embodiment.
FIG. 12A is a diagram showing a scribing step in a method for manufacturing a solar cell according to Modification 3 of this embodiment, and FIG. It is a figure which shows a plating layer formation process. FIG. 12C is a diagram showing a resist removing step in a method for manufacturing a solar cell according to Modification 3 of this embodiment, and FIGS. It is a figure which shows an example of the base layer formation process of the transparent electrode layer formation process and metal electrode layer in a method.

As shown in FIG. 12A, a laser scribing method is used to form a scribed groove 50 at the boundary of the peripheral portion R1 on the back side of the semiconductor substrate 11 (scribing step). The depth of the scribed groove 50 may be less than the film thickness of the underlying layer material film 29lZ. In other words, the depth of the scribed groove 50 does not have to pass through the underlying layer material film 29lZ and does not have to reach the transparent electrode layer material film 28Z.
As a result, in the scribed grooves 50, the film thickness of the underlying layer material film 29lZ, which has a relatively low resistance, can be reduced.

Further, a resist 40 is formed on the underlying layer material film 29lZ at the boundary between the first region 7 and the second region 8 (resist forming step).

Next, as shown in FIG. 12B, the plating method using the resist 40 as a mask is used to form a patterned plating layer 29u on the base layer material film 29lZ in the first region 7, and A patterned plated layer 39u is formed on the base layer material film 29lZ in step 8 (plated metal electrode layer forming step).

Specifically, as shown in FIG. 4 , a feeding point 60 for electroplating is arranged inside the scribed groove 50 . As described above, in the scribe groove 50, the film thickness of the underlying layer material film 29lZ, which has a relatively low resistance, is thin. 11 is suppressed from being supplied to the peripheral portion outside the scribed groove 50 . Therefore, it is possible to suppress the formation of a plating layer in the peripheral portion R1 outside the scribe groove 50 in the semiconductor substrate 11 .

As a result, as shown in FIG. 12B, even if the plating layer 39u is formed on the peripheral edge portion R1 outside the scribe groove 50 on the back surface side of the semiconductor substrate 11, the plating layer 39u formed on the peripheral edge portion R1 will not be formed. is thinner than the film thickness of the plating layers 29u and 39u formed in the central portion R2 inside the scribe groove 50 on the back surface side of the semiconductor substrate 11. As shown in FIG. Alternatively, the plating layer 39u is not formed on the peripheral edge portion R1 outside the scribe groove 50 on the back surface side of the semiconductor substrate 11. As shown in FIG.

Further, even if the plating layer 39u is formed on the side surface of the semiconductor substrate 11, the film thickness of the plating layer 39u formed on the side surface of the semiconductor substrate 11 does not reach the central portion R2 inside the scribe groove 50 on the back surface side of the semiconductor substrate 11. It is thinner than the film thickness of the plated layers 29u and 39u to be formed. Alternatively, the side surface of the semiconductor substrate 11 is not formed with the plating layer 39u.

Next, as shown in FIG. 12C, the resist 40 is removed (resist removal step).

Next, as shown in FIGS. 12D to 12F, the base layer material film 29lZ and the transparent electrode layer material film 28Z are etched using an etching method using the plating layer 29u and the plating layer 39u as a mask, thereby forming a second film. A patterned first transparent electrode layer 28 and an underlying layer 29l are formed in the first region 7, and a patterned second transparent electrode layer 38 and an underlying layer 39l are formed in the second region 8 (transparent electrode layer formation step, and base layer formation step).

In this base layer forming step, as shown in FIGS. 12D to 12F, the plated layer 39u, the base layer material film 29lZ and the transparent electrode layer material film 28Z formed on the side surface of the semiconductor substrate 11 are etched and removed. Specifically, the plated layer and underlying layer of the metal electrode layer formed on the side surface of the semiconductor substrate 11 and the transparent electrode layer are etched and removed. If the plating layer 39u is not formed on the side surface of the semiconductor substrate 11, the base layer of the metal electrode layer and the transparent electrode layer formed on the side surface of the semiconductor substrate 11 are etched and removed. At this time, the semiconductor layers 35 and 13 and the optical adjustment layer 15 formed on the side surfaces of the semiconductor substrate 11 remain.

Further, as shown in FIG. 12D, part of the plated layer of the metal electrode layer formed in the peripheral edge portion R1 outside the scribe groove 50 on the back surface side of the semiconductor substrate 11 may be etched and removed.
Alternatively, as shown in FIG. 12E, the plating layer and underlying layer of the metal electrode layer and the transparent electrode layer in the scribed grooves 50 may be etched and removed to expose the semiconductor layer.

Alternatively, as shown in FIG. 12F, the plated layer of the metal electrode layer formed in the peripheral portion R1 outside the scribe groove 50 on the back surface of the semiconductor substrate 11 and part of the underlying layer may be etched and removed. good. When the plating layer 39u is not formed on the peripheral edge portion R1 on the back side of the semiconductor substrate 11, part of the underlying layer of the metal electrode layer formed on the peripheral edge portion R1 on the back side of the semiconductor substrate 11 is etched and removed. , the semiconductor layer is exposed.
Also, the plating layer and base layer of the metal electrode layer and the transparent electrode layer in the scribed grooves 50 may be etched and removed to expose the semiconductor layer.

As shown in FIGS. 9 to 11, the solar cell 1 of Modification 3 obtained in this way also has the plating layers 29u, 39u of the metal electrode layers 29, 39 and the underlying layers 29l, Neither 39l nor the transparent electrode layers 28 and 38 are formed.

A scribed groove 50 is formed at the boundary of the peripheral edge portion R1 on the back surface side of the solar cell 1 . As shown in FIG. 9, the depth of the scribed grooves 50 may be less than the film thickness of the underlying layers 29l and 39l. In addition, a base layer 39l and a plating layer 39u of the semiconductor layer 35, the transparent electrode layer 38, and the metal electrode layer 39 may be formed on the peripheral portion R1 outside the scribed groove 50 on the back side of the solar cell 1. . The film thickness of the plating layer 39u at the peripheral edge portion R1 outside the scribed grooves 50 on the back surface side of the solar cell 1 is the thickness of the plating layers 29u, 39u at the central portion R2 inside the scribed grooves 50 on the back surface side of the solar cell 1. Thinner than film thickness.

Alternatively, as shown in FIG. 10, the depth of the scribed groove 50 may be at least equal to or greater than the film thickness of the underlying layers 29l and 39l. In addition, a base layer 39l and a plating layer 39u of the semiconductor layer 35, the transparent electrode layer 38, and the metal electrode layer 39 may be formed on the peripheral portion R1 outside the scribed groove 50 on the back side of the solar cell 1. . The film thickness of the plating layer 39u at the peripheral edge portion R1 outside the scribed grooves 50 on the back surface side of the solar cell 1 is the thickness of the plating layers 29u, 39u at the central portion R2 inside the scribed grooves 50 on the back surface side of the solar cell 1. Thinner than film thickness.

Alternatively, as shown in FIG. 11, the depth of the scribed groove 50 may be at least equal to or greater than the film thickness of the underlying layers 29l and 39l. In addition, a base layer 39l for the semiconductor layer 35, the transparent electrode layer 38, and the metal electrode layer 39 is formed on the peripheral edge portion R1 outside the scribed groove 50 on the back side of the solar cell 1, and the metal electrode layer 39 plated layer 39u may not be formed. The film thickness of the base layer 39l at the peripheral edge portion R1 outside the scribed grooves 50 on the back surface side of the solar cell 1 is the thickness of the base layers 29l, 39l at the central portion R2 inside the scribed grooves 50 on the back surface side of the solar cell 1. Thinner than film thickness.

Moreover, in the embodiment described above, the solar cell provided with the electrode layer including the transparent electrode layer and the metal electrode layer was exemplified. However, the present invention is not limited to this, and is also applicable to solar cells with electrode layers that include only metal electrode layers.

Moreover, in the above-described embodiment, the solar cell 1 using a crystalline silicon material was exemplified, but the present invention is not limited to this. For example, various materials such as gallium arsenide (GaAs) may be used as materials for solar cells.

Moreover, in the above-described embodiment, the heterojunction solar cell 1 is exemplified as shown in FIG. However, the present invention is not limited to this, and can be applied to various solar cells such as homojunction solar cells.

Reference Signs List 1 solar cell 7 first region 7f finger portion 7b busbar portion 8 second region 8f finger portion 8b busbar portion 11 semiconductor substrate 15 antireflection layer 25 first semiconductor layer 27 first electrode layer 28 first transparent electrode layer 28Z transparent electrode layer Material film 29 First metal electrode layer 29l Base layer 29lZ Base layer material film 29u Plated layer 35 Second semiconductor layer 37 Second electrode layer 38 Second transparent electrode layer 39 Second metal electrode layer 39l Base layer 39u Plated layer 40 Resist 50 Scribed groove 60 Feeding point (hollow)
R1 Peripheral part R2 Central part

Claims (13)

a semiconductor substrate; a first semiconductor layer and a first metal electrode layer formed in this order in a first region that is part of the back surface side of the semiconductor substrate; A method for manufacturing a back electrode type solar cell comprising a second semiconductor layer and a second metal electrode layer formed in order in two regions, comprising:
each of the first metal electrode layer and the second metal electrode layer has a base layer and a plating layer;
The method for manufacturing the solar cell comprises:
A base layer material film forming a series of material films of the base layer over the first region and the second region on the first semiconductor layer and the second semiconductor layer on the back surface side of the semiconductor substrate. a forming step;
a scribing step of forming a scribed groove at the boundary of the peripheral portion on the back surface side of the semiconductor substrate using a laser scribing method;
a resist forming step of forming a resist on the underlying layer material film at the boundary between the first region and the second region;
a plating layer forming step of forming the patterned plating layer on the material film of the underlying layer in each of the first region and the second region using a plating method using the resist as a mask; ,
a resist removing step of removing the resist;
forming the patterned underlying layer in each of the first region and the second region by etching the material film of the underlying layer using an etching method using the plating layer as a mask; a stratum formation process;
with
In the plating layer forming step, a feeding point for electrolytic plating is arranged inside the scribed groove,
In the base layer forming step, the plating layer and the base layer formed on the side surface of the semiconductor substrate are etched and removed.
A method for manufacturing a solar cell. In the scribing step, the scribed groove is formed with a depth equal to or greater than the film thickness of the underlying layer,
In the plating layer forming step, the plating layer on the peripheral portion outside the scribe groove on the back surface side of the semiconductor substrate and the plating layer on the side surface of the semiconductor substrate are formed on the back surface side of the semiconductor substrate. Formed thinner than the plating layer in the central portion inside the scribed groove,
In the base layer forming step,
removing the plating layer and the base layer formed on the side surface of the semiconductor substrate by etching;
the plating layer and the base layer formed in the peripheral portion outside the scribed groove on the back surface side of the semiconductor substrate are etched and removed;
A method for manufacturing a solar cell according to claim 1 . In the scribing step, the scribed groove is formed with a depth equal to or greater than the film thickness of the underlying layer,
In the plating layer forming step, the plating layer is not formed on the peripheral portion outside the scribed groove on the back surface side of the semiconductor substrate and on the side surface of the semiconductor substrate,
In the base layer forming step,
removing the base layer formed on the side surface of the semiconductor substrate by etching;
the base layer formed in the peripheral portion outside the scribed groove on the back surface side of the semiconductor substrate is etched and removed;
A method for manufacturing a solar cell according to claim 1 . In the scribing step, the scribed groove is formed with a depth less than the film thickness of the underlying layer,
In the plating layer forming step, the plating layer on the peripheral portion outside the scribe groove on the back surface side of the semiconductor substrate and the plating layer on the side surface of the semiconductor substrate are formed on the back surface side of the semiconductor substrate. Formed thinner than the plating layer in the central portion inside the scribed groove,
In the base layer forming step,
removing the plating layer and the base layer formed on the side surface of the semiconductor substrate by etching;
part of the plated layer formed in the peripheral portion outside the scribed groove on the back surface side of the semiconductor substrate and the underlying layer is etched away;
A method for manufacturing a solar cell according to claim 1 . In the scribing step, the scribed groove is formed with a depth less than the film thickness of the underlying layer,
In the plating layer forming step, the plating layer on the peripheral portion outside the scribe groove on the back surface side of the semiconductor substrate and the plating layer on the side surface of the semiconductor substrate are formed on the back surface side of the semiconductor substrate. Formed thinner than the plating layer in the central portion inside the scribed groove,
In the base layer forming step,
removing the plating layer and the base layer formed on the side surface of the semiconductor substrate by etching;
part of the plating layer formed in the peripheral portion outside the scribed groove on the back surface side of the semiconductor substrate is removed by etching;
A method for manufacturing a solar cell according to claim 1 . a semiconductor substrate; a first semiconductor layer and a first metal electrode layer formed in this order in a first region that is part of the back surface side of the semiconductor substrate; A back electrode type solar cell comprising a second semiconductor layer and a second metal electrode layer formed in order in two regions,
each of the first metal electrode layer and the second metal electrode layer has a base layer and a plating layer;
The plating layer and the underlying layer are not formed on the side surface of the semiconductor substrate,
solar cell. The plated layer and the base layer are not formed on the peripheral edge portion of the back surface side of the semiconductor substrate,
The solar cell according to claim 6. a scribed groove is formed at a boundary of the peripheral portion on the back surface side of the semiconductor substrate,
The depth of the scribed groove is at least equal to or greater than the film thickness of the underlying layer.
The solar cell according to claim 7. The plating layer is not formed on the peripheral portion of the back surface side of the semiconductor substrate,
The film thickness of the underlying layer at the peripheral edge portion on the back surface side of the semiconductor substrate is thinner than the film thickness of the underlying layer at the inner central portion of the peripheral edge portion on the back surface side of the semiconductor substrate,
The solar cell according to claim 6. a scribed groove is formed at a boundary of the peripheral portion on the back surface side of the semiconductor substrate,
The depth of the scribed groove is at least equal to or greater than the film thickness of the underlying layer.
The solar cell according to claim 9. The thickness of the plating layer at the peripheral edge portion on the back surface side of the semiconductor substrate is thinner than the thickness of the plating layer at the central portion inside the peripheral edge portion on the back surface side of the semiconductor substrate,
The solar cell according to claim 6. a scribed groove is formed at a boundary of the peripheral portion on the back surface side of the semiconductor substrate,
The depth of the scribed groove is at least equal to or greater than the film thickness of the underlying layer.
The solar cell according to claim 11. a scribed groove is formed at a boundary of the peripheral portion on the back surface side of the semiconductor substrate,
The depth of the scribed groove is less than the film thickness of the underlayer.
The solar cell according to claim 11.

Images