JP7274899B2 - Solar cell manufacturing method - Google Patents

Description

The present invention relates to a method for manufacturing a back electrode type (back contact type) solar cell.

As solar cells using semiconductor substrates, there are double-sided electrode solar cells in which electrodes are formed on both the light-receiving side and the back side, and back electrode-type solar cells in which electrodes are formed only on the back side. In a double-sided electrode type solar cell, since electrodes are formed on the light receiving surface side, the electrodes block sunlight. On the other hand, in the back electrode type solar cell, no electrode is formed on the light-receiving surface side, so the solar cell has a higher light receiving rate than the double-sided electrode type solar cell. Patent Literature 1 discloses a back electrode type solar cell.

The solar cell described in Patent Document 1 includes a semiconductor substrate that functions as a photoelectric conversion layer, a first conductivity type semiconductor layer and a first electrode layer that are sequentially laminated on a part of the back surface side of the semiconductor substrate, and a back surface of the semiconductor substrate. A second conductivity type semiconductor layer and a second electrode layer are laminated in order on the other part of the side.

JP 2014-75526 A

In general, an etching method using a photolithographic technique is used for patterning the first conductivity type semiconductor layer (first patterning) and patterning the second conductivity type semiconductor layer (second patterning). However, in the etching method using the photolithographic technique, for example, photoresist application by spin coating, photoresist drying, photoresist exposure, photoresist development, etching of a semiconductor layer using photoresist as a mask, and photoresist stripping are performed. A process was required and the process was complicated.

Regarding this point, Patent Document 1 describes a technique for simplifying the patterning process by a lift-off method using a lift-off layer (sacrificial layer) in the second patterning. The lift-off layer is formed before the first patterning and is patterned together with the semiconductor layer during the first patterning. During the first patterning, the lift-off layer may peel off depending on the combination of the type of lift-off layer and the resist used for patterning.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a solar cell capable of simplifying the manufacturing process and suppressing peeling of the lift-off layer.

A method for manufacturing a solar cell according to the present invention comprises: a semiconductor substrate; Manufacture of a back electrode type solar cell comprising a first electrode layer, and a second conductivity type semiconductor layer and a second electrode layer laminated in order on a second region which is another part of the other main surface of a semiconductor substrate a first semiconductor layer material film forming step of forming a first conductivity type semiconductor layer material film on the other main surface side of a semiconductor substrate; a lift-off layer forming step of forming a layer; a first protective layer forming step of forming a first protective layer for protecting the lift-off layer on the lift-off layer; forming a patterned first conductivity type semiconductor layer, a lift-off layer and a first protection layer in the first region by removing the material film of the layer, the lift-off layer and the first conductivity type semiconductor layer, and patterning the pattern printing resist a cleaning step of cleaning both main surfaces of the semiconductor substrate; and a second conductivity type semiconductor layer on the lift-off layer and the first protective layer in the first region and on the second region. a second semiconductor layer material film forming step of forming a material film; a second semiconductor layer forming step of forming a patterned second conductivity type semiconductor layer, wherein in the first semiconductor layer forming step, the first protective layer in the first region is removed from the solution used for patterning; Protecting the lift-off layer in one area, in a cleaning step, the first protective layer in the first area protects the lift-off layer in the first area from cleaning.

ADVANTAGE OF THE INVENTION According to this invention, the simplification of the manufacturing process of a solar cell and suppression of peeling of a lift-off layer are possible.

It is the figure which looked at the solar cell which concerns on this embodiment from the back surface side. FIG. 2 is a cross-sectional view taken along the line II-II in the solar cell of FIG. 1; FIG. 4 is a diagram showing a first semiconductor layer material film forming step, a lift-off layer forming step, a first protective layer forming step, an insulating layer forming step, and a second protective layer forming step in the method for manufacturing a solar cell according to the present embodiment; It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the 2nd semiconductor layer material film formation process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the 2nd semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the electrode layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the 1st semiconductor layer material film|membrane formation process and the lift-off layer formation process in the manufacturing method of the solar cell of a comparative example. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell of a comparative example. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell of a comparative example. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell of a comparative example. It is a figure which shows the 2nd semiconductor layer material film formation process in the manufacturing method of the solar cell of a comparative example. It is a figure which shows the 2nd semiconductor layer formation process in the manufacturing method of the solar cell of a comparative example. It is a figure which shows the electrode layer formation process in the manufacturing method of the solar cell of a comparative example. It is a figure which shows the optical adjustment layer formation process in the manufacturing method of the solar cell of a comparative example.

An example of an embodiment of the present invention will be described below with reference to the accompanying drawings. In each drawing, the same reference numerals are given to the same or corresponding parts. Also, for convenience, hatching, member numbers, etc. may be omitted, but in such cases, other drawings shall be referred to.

(solar cell)
FIG. 1 is a view of the solar cell according to this embodiment viewed from the back side. The solar cell 1 shown in FIG. 1 is a back electrode type solar cell. Solar cell 1 includes n-type (second conductivity type) semiconductor substrate 11 having two main surfaces, and has first region 7 and second region 8 on the main surface of semiconductor substrate 11 .

The first region 7 has a so-called comb shape, and includes a plurality of finger portions 7f corresponding to comb teeth and busbar portions 7b corresponding to support portions of the comb teeth. The busbar portion 7b extends in a first direction (X direction) along one side portion of the semiconductor substrate 11, and the finger portions 7f extend from the busbar portion 7b in a second direction intersecting the first direction (X direction). direction (Y direction).
Similarly, the second region 8 has a so-called comb shape, and includes a plurality of finger portions 8f corresponding to comb teeth and busbar portions 8b corresponding to support portions for the comb teeth. The busbar portion 8b extends in a first direction (X direction) along one side portion of the semiconductor substrate 11 opposite to the other side portion, and the finger portions 8f extend in a second direction (Y direction) from the busbar portion 8b. direction).
The finger portions 7f and the finger portions 8f are alternately provided in the first direction (X direction).
Note that the first region 7 and the second region 8 may be formed in stripes.

FIG. 2 is a cross-sectional view of the solar cell of FIG. 1 taken along the line II-II. As shown in FIG. 2, the solar cell 1 includes a semiconductor substrate 11, an intrinsic semiconductor layer 13 and an optical semiconductor layer 13 which are sequentially laminated on the light receiving surface side which is one of the main surfaces of the semiconductor substrate 11 on the light receiving side. An adjustment layer 15 is provided. In the solar cell 1, the intrinsic semiconductor layers 23, p type (first conductivity type) semiconductor layer 25 and a first electrode layer 27 . In addition, the solar cell 1 includes an intrinsic semiconductor layer 33, an n-type (second conductivity type) semiconductor layer 35, and a second electrode, which are sequentially laminated on another portion (second region 8) of the back surface side of the semiconductor substrate 11. A layer 37 is provided.

Semiconductor substrate 11 is formed of a crystalline silicon material such as monocrystalline silicon or polycrystalline silicon. The semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which a crystalline silicon material is doped with an n-type dopant. Examples of n-type dopants include phosphorus (P).
The semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light receiving surface side and generates photocarriers (electrons and holes).
Since crystalline silicon is used as the material of the semiconductor substrate 11, dark current is relatively small, and relatively high output (stable output regardless of illuminance) can be obtained even when the intensity of incident light is low.

The intrinsic semiconductor layer 13 is formed on the light receiving surface side of the semiconductor substrate 11 . The intrinsic semiconductor layer 23 is formed in the first region 7 on the back side of the semiconductor substrate 11 . The intrinsic semiconductor layer 33 is formed in the second region 8 on the back side of the semiconductor substrate 11 . The intrinsic semiconductor layers 13, 23, 33 are made of a material containing, for example, intrinsic (i-type) amorphous silicon as a main component.
The intrinsic semiconductor layers 13, 23, and 33 function as so-called passivation layers, suppress recombination of carriers generated in the semiconductor substrate 11, and enhance carrier recovery efficiency.

The optical adjustment layer 15 is formed on the intrinsic semiconductor layer 13 on the light receiving surface side of the semiconductor substrate 11 . The optical adjustment layer 15 functions as an antireflection layer that prevents reflection of incident light, and also functions as a protective layer that protects the light receiving surface side of the semiconductor substrate 11 and the intrinsic semiconductor layer 13 . The optical adjustment layer 15 is formed of an insulator material such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON).

The p-type semiconductor layer 25 is formed on the intrinsic semiconductor layer 23 , that is, in the first region 7 on the back side of the semiconductor substrate 11 . The p-type semiconductor layer 25 is made of, for example, an amorphous silicon material. The p-type semiconductor layer 25 is, for example, a p-type semiconductor layer in which an amorphous silicon material is doped with a p-type dopant. Examples of p-type dopants include boron (B).

The n-type semiconductor layer 35 is formed on the intrinsic semiconductor layer 33 , that is, in the second region 8 on the back side of the semiconductor substrate 11 . The n-type semiconductor layer 35 is made of, for example, an amorphous silicon material. The n-type semiconductor layer 35 is an n-type semiconductor layer in which, for example, an amorphous silicon material is doped with an n-type dopant (for example, phosphorus (P) described above).

The first electrode layer 27 is formed on the p-type semiconductor layer 25 and the second electrode layer 37 is formed on the n-type semiconductor layer 35 .
The first electrode layer 27 has a transparent electrode layer 28 and a metal electrode layer 29 that are sequentially laminated on the p-type semiconductor layer 25 . The second electrode layer 37 has a transparent electrode layer 38 and a metal electrode layer 39 that are sequentially laminated on the n-type semiconductor layer 35 .
The transparent electrode layers 28, 38 are made of a transparent conductive material. Transparent conductive materials include ITO (Indium Tin Oxide: composite oxide of indium oxide and tin oxide) and ZnO (Zinc Oxide: zinc oxide). The metal electrode layers 29 and 39 are made of a conductive paste material containing metal powder such as silver.

(Manufacturing method of solar cell of comparative example)
The inventors of the present application have devised the use of a pattern printing resist by a pattern printing method in the patterning (first patterning) of the p-type semiconductor layer. As a result, compared with the case of using a photoresist (photolithography method) by spin coating, the steps of exposure and development can be reduced, and the manufacturing process of solar cells can be simplified.
In addition, the inventors of the present application have devised adopting a lift-off method using a lift-off layer (sacrificial layer) in the patterning of the n-type semiconductor layer (second patterning). This enables simplification of the manufacturing process of the solar cell.
Furthermore, the inventors of the present application have devised the use of an inexpensive alkaline solution as a solution for removing the pattern printing resist in the patterning of the p-type semiconductor layer. As a result, the cost of the solar cell can be reduced.

Note that pattern printing is not printing that undergoes processes such as exposure and development after forming a resist film (non-pattern resist film) before patterning, as in the photolithography method, but screen printing or gravure printing. It means a printing method such as press printing such as printing, or ejection printing such as inkjet printing, in which a patterned resist (printing material) is directly adhered to a resist adhesion surface. A pattern printing resist means a printing material (resist material) used for pattern printing.

A method for manufacturing a solar cell 1X of a comparative example based on the invention of the inventors of the present application and problems thereof will be described below with reference to FIGS. 4A to 4H. FIG. 4A is a diagram showing a first semiconductor layer material film forming step and a lift-off layer forming step in a solar cell manufacturing method of a comparative example, and FIGS. It is a figure which shows a semiconductor layer formation process. FIG. 4E is a view showing a second semiconductor layer material film forming step in the method for manufacturing a solar cell of Comparative Example, and FIG. 4F shows a second semiconductor layer forming step in the method for manufacturing a solar cell of Comparative Example. It is a diagram. FIG. 4G is a diagram showing an electrode layer forming step in the solar cell manufacturing method of the comparative example, and FIG. 4H is a diagram showing an optical adjustment layer forming step in the solar cell manufacturing method of the comparative example.

First, as shown in FIG. 4A, an intrinsic semiconductor layer material film 23ZX and a p-type semiconductor layer material film 25ZX are sequentially laminated on the entire back surface side of the semiconductor substrate 11X using, for example, the CVD method (chemical vapor deposition method). (Film formation) (First semiconductor layer material film forming step).
Further, an intrinsic semiconductor layer 13X is stacked (film-formed) on the entire surface of the semiconductor substrate 11X on the light receiving surface side by using, for example, the CVD method. The order of forming the intrinsic semiconductor layer material film 23ZX, the p-type semiconductor layer material film 25ZX, and the intrinsic semiconductor layer 13X is not limited.

Next, a lift-off layer (sacrificial layer) 41X is laminated (formed) on the entire back surface side of the semiconductor substrate 11X, specifically, on the entire surface of the p-type semiconductor layer material film 25ZX, using, for example, the CVD method. (Lift-off layer forming step).
The lift-off layer 41X is formed of a material such as silicon oxide (SiO), silicon nitride (SiN), or a compound thereof such as silicon oxynitride (SiON).

Next, as shown in FIGS. 4B to 4D, a pattern printing resist is used to form an intrinsic semiconductor layer material film 23ZX, a p-type semiconductor layer material film 25ZX and a lift-off layer in the second region 8 on the back side of the semiconductor substrate 11X. By removing 41X, patterned intrinsic semiconductor layer 23X, p-type semiconductor layer 25X and lift-off layer 41X are formed in first region 7 (first semiconductor layer forming step).

Specifically, as shown in FIG. 4B, a pattern printing resist 90X is formed on the first region 7 on the back surface side of the semiconductor substrate 11X and on the entire light receiving surface side of the semiconductor substrate 11X using a pattern printing method. The film thickness of the pattern printing resist is, for example, 1 μm or more and 50 μm or less. According to the pattern-printed resist using the pattern printing method, the exposure and development of the resist (simplification of the manufacturing process) in the photoresist using the conventional spin coating method (photolithography method) are not required.

Thereafter, as shown in FIG. 4C, the lift-off layer 41X, the p-type semiconductor layer material film 25ZX, and the intrinsic semiconductor layer material film 23ZX in the second region 8 are etched using the pattern printing resist 90X as a mask, thereby forming the first region 7. Then, patterned intrinsic semiconductor layer 23X, p-type semiconductor layer 25X and lift-off layer 41X are formed. As an etching solution for the lift-off layer 41X, the p-type semiconductor layer material film 25ZX and the intrinsic semiconductor layer material film 23ZX, an acidic solution such as a mixed solution of hydrofluoric acid and nitric acid is used. At this time, a first problem arises (details will be described later).

After that, as shown in FIG. 4D, the pattern printing resist 90X is removed. An inexpensive alkaline solution is used as an etching solution for the pattern printing resist 90X (cost reduction). At this time, a second problem arises (details will be described later).

Next, both sides of the semiconductor substrate 11X are cleaned (cleaning process). In the cleaning process, for example, hydrofluoric acid treatment is performed after ozone treatment. The hydrofluoric acid treatment includes not only hydrofluoric acid, but also treatment with a mixture containing hydrofluoric acid and other kinds of acid (for example, hydrochloric acid in the washing step). At this time, a third problem arises (details will be described later).

Next, as shown in FIG. 4E, an intrinsic semiconductor layer material film 33ZX and an n-type semiconductor layer material film 35ZX are sequentially laminated (formed) on the entire back surface side of the semiconductor substrate 11X using, for example, the CVD method ( second semiconductor layer material film forming step).

Next, as shown in FIG. 4F, the intrinsic semiconductor layer material film 33ZX and the n-type semiconductor layer in the first region 7 are removed from the back surface of the semiconductor substrate 11X using a lift-off method using a lift-off layer (sacrificial layer). By removing the material film 35ZX, the patterned intrinsic semiconductor layer 33X and the n-type semiconductor layer 35X are formed in the second region 8 (second semiconductor layer forming step).

Specifically, by removing the lift-off layer 41X, the intrinsic semiconductor layer material film 33ZX and the n-type semiconductor layer material film 35ZX on the lift-off layer 41X are removed, and the intrinsic semiconductor layer 33X and the n-type semiconductor are formed in the second region 8. Form layer 35X. As a removal solution for the lift-off layer 41, for example, an acidic solution such as hydrofluoric acid is used.

Next, as shown in FIG. 4G, a first electrode layer 27X and a second electrode layer 37X are formed on the back surface side of the semiconductor substrate 11X (electrode layer forming step).
Specifically, a transparent electrode layer material film is laminated (formed) on the entire back surface side of the semiconductor substrate 11X using, for example, a PVD method (physical vapor deposition method) such as a sputtering method. After that, patterned transparent electrode layers 28X and 38X are formed by removing part of the transparent electrode layer material film, for example, using an etching method using an etching paste. As an etching solution for the transparent electrode layer material film, for example, hydrochloric acid or ferric chloride aqueous solution is used.
After that, for example, using a pattern printing method or a coating method, the metal electrode layer 29X is formed on the transparent electrode layer 28X, and the metal electrode layer 39X is formed on the transparent electrode layer 38X, whereby the first electrode layer 27X and the A second electrode layer 37X is formed.

Next, as shown in FIG. 4H, an optical adjustment layer 15X is laminated (formed) on the entire light receiving surface side of the semiconductor substrate 11X.
Through the above steps, the back electrode type solar cell 1X of the comparative example is completed.

(First issue)
In the first semiconductor layer forming step, when the intrinsic semiconductor layer 23X, the p-type semiconductor layer 25X, and the lift-off layer 41X are patterned, the lift-off layer 41X in the first region 7 covered with the pattern printing resist 90X is peeled off. There is
This is a pattern printing resist using a pattern printing method that does not require exposure and development of the resist (simplification of the manufacturing process) in place of the photoresist (photolithography method) using the conventional spin coating method. presumably due to the use of
The composition of the pattern-printed resist is expected to be coarser than that of the spin-coated photoresist. As a result, it is expected that hydrofluoric acid, which is a component of the etchant, will pass through the pattern printing resist 90X and soak into the lift-off layer 41X, causing the lift-off layer 41X to peel off.
If the lift-off layer 41X is peeled off, the lift-off process in the second semiconductor layer formation process cannot be performed normally.

(Second issue)
In the first semiconductor layer forming step, when the pattern printing resist 90X is removed, the intrinsic semiconductor layer 13X on the light-receiving surface side is dissolved by the alkaline solution, which deteriorates the performance of the solar cell 1X.
In this regard, an insulating layer of a material such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof, such as silicon oxynitride (SiON), which is resistant to alkaline solutions, is deposited on the intrinsic semiconductor layer 13X. It is possible to form
However, it is expected that a problem similar to the first problem described above will occur. That is, in the first semiconductor layer forming step, when the intrinsic semiconductor layer 23X, the p-type semiconductor layer 25X, and the lift-off layer 41X are patterned, the insulating layer on the light-receiving surface side covered with the pattern printing resist 90X is peeled off. is expected. Then, when the pattern printing resist 90X is removed, the intrinsic semiconductor layer 13X on the light receiving surface side is dissolved by the alkaline solution.

(Third issue)
In the cleaning process, when cleaning both sides of the semiconductor substrate 11X, the lift-off layer 41X in the first region 7 may be melted and peeled off by the ozone treatment and the hydrofluoric acid treatment.

With respect to the first problem, the inventors of the present application propose to form a protective layer on the lift-off layer on the back surface side to protect the lift-off layer from the p-type semiconductor layer etching solution.
Regarding the third problem, the protective layer is not removed (remaining) by the alkaline solution for removing the pattern printing resist of the p-type semiconductor layer, and is lifted off from the ozone treatment and hydrofluoric acid treatment for cleaning both sides of the semiconductor substrate. It is devised to form a protective layer on the back-side lift-off layer that protects the layer and is naturally removed during the lift-off process.
In relation to the second problem, the inventors of the present application propose to form an insulating layer on the intrinsic semiconductor layer on the light-receiving surface side to protect the intrinsic semiconductor layer from the alkaline solution used to remove the pattern printing resist. Furthermore, the inventors of the present application propose to form a protective layer on the insulating layer on the light-receiving surface side to protect the insulating layer from an etching solution for the p-type semiconductor layer.

(Method for manufacturing solar cell of the present embodiment)
A method for manufacturing the solar cell 1 of the present embodiment shown in FIGS. 1 and 2 will be described below with reference to FIGS. 3A to 3G. FIG. 3A is a diagram showing a first semiconductor layer material film forming step, a lift-off layer forming step, a first protective layer forming step, an insulating layer forming step, and a second protective layer forming step in the method for manufacturing a solar cell according to this embodiment; 3B to 3D are diagrams showing the first semiconductor layer forming step in the method for manufacturing a solar cell according to this embodiment. FIG. 3E is a diagram showing a second semiconductor layer material film formation step in the method for manufacturing a solar cell according to this embodiment, and FIG. It is a figure which shows a formation process. FIG. 3G is a diagram showing an electrode layer forming step in the method for manufacturing a solar cell according to this embodiment.

First, as shown in FIG. 3A, an intrinsic semiconductor layer material film 23Z and a p-type semiconductor layer material film 25Z are sequentially laminated (film-formed) on the entire back surface side of the semiconductor substrate 11 using, for example, the CVD method (second layer). 1 semiconductor layer material film forming step).
In addition, the intrinsic semiconductor layer 13 is laminated (film-formed) on the entire surface of the semiconductor substrate 11 on the light-receiving surface side by using, for example, the CVD method.

Next, a lift-off layer (sacrificial layer) 41 is laminated (formed) on the entire back surface side of the semiconductor substrate 11, specifically, on the entire surface of the p-type semiconductor layer material film 25Z, using, for example, the CVD method. (Lift-off layer forming step).
Further, an insulating layer 43 is laminated (formed) on the entire surface of the semiconductor substrate 11 on the light receiving surface side, specifically, on the entire surface of the intrinsic semiconductor layer 13 using, for example, the CVD method (insulating layer forming step).
Lift-off layer 41 and insulating layer 43 are formed of materials such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON). As a result, the lift-off layer 41 and the insulating layer 43 are resistant to alkaline solutions and can be easily removed by hydrofluoric acid treatment (treatment with hydrofluoric acid or a mixture of hydrofluoric acid and other types of acid). be. The film thicknesses of the lift-off layer 41 and the insulating layer 43 are preferably 1 nm or more and 1 μm or less, for example.

Next, the first protective layer 51 for protecting the lift-off layer 41 is laminated (formed) on the entire surface of the back surface side of the semiconductor substrate 11, specifically, on the entire surface of the lift-off layer 41 by using, for example, the CVD method. (First protective layer forming step).
Further, a second protective layer 53 for protecting the insulating layer 43 is laminated (formed) on the entire surface of the semiconductor substrate 11 on the light receiving surface side, specifically, on the entire surface of the insulating layer 43 using, for example, the CVD method. (Second protective layer forming step).
The first protective layer 51 and the second protective layer 53 are formed of a material containing silicon as a main component (for example, intrinsic amorphous silicon). As a result, the first protective layer 51 and the second protective layer 53 are resistant to acid treatment, such as hydrofluoric acid treatment (treatment with hydrofluoric acid or a mixture of hydrofluoric acid and other types of acid). , is easily removed with an alkaline solution. The film thicknesses of the first protective layer 51 and the second protective layer 53 are preferably, for example, 1 nm or more and 50 nm or less.

Next, as shown in FIGS. 3B to 3D, a pattern printing resist is used to form the first protective layer 51, the lift-off layer 41, and the p-type semiconductor layer material film 25Z in the second region 8 on the back side of the semiconductor substrate 11. Next, as shown in FIGS. and the intrinsic semiconductor layer material film 23Z are removed to form the patterned intrinsic semiconductor layer 23, the p-type semiconductor layer 25, the lift-off layer 41 and the first protective layer 51 in the first region 7 (first semiconductor layer 23). layer forming step).

Specifically, as shown in FIG. 3B, a pattern printing resist 90 is formed on the first region 7 on the back surface side of the semiconductor substrate 11X and on the entire light receiving surface side of the semiconductor substrate 11X using a pattern printing method. The film thickness of the pattern printing resist is, for example, 1 μm or more and 50 μm or less. Thereafter, as shown in FIG. 3C, using the pattern printing resist 90 as a mask, the first protective layer 51, the lift-off layer 41, the first conductivity type semiconductor layer material film 25Z and the intrinsic semiconductor layer material film 23Z in the second region 8 are etched. By doing so, the intrinsic semiconductor layer 23, the p-type semiconductor layer 25, the lift-off layer 41 and the first protective layer 51 are formed. As the etching solution for the first protective layer 51, the lift-off layer 41, the first conductivity type semiconductor layer material film 25Z, and the intrinsic semiconductor layer material film 23Z, for example, a mixed solution of ozone dissolved in hydrofluoric acid, or a mixture of hydrofluoric acid and nitric acid is used. An acidic solution such as a mixed solution of is used.

At this time, the first protective layer 51 protects the lift-off layer 41 from the etching solution passing through the pattern printing resist 90 . Here, to protect the lift-off layer 41 means that the first protective layer formed on the lift-off layer 41 so as to leave the lift-off layer 41 in the first region 7 on which the pattern printing resist 90 is formed remains when the first semiconductor layer forming process is completed. 51 means that the contact time and area between the lift-off layer 41 and the etching solution are suppressed.

From the viewpoint of achieving high pattern accuracy and reducing the amount of pattern printing resist used, the area of the lift-off layer 41 that remains after the completion of the first semiconductor layer forming process is 30% or more of the area where the pattern printing resist 90 is formed. is preferably 50% or more, and even more preferably 70% or more.
The area of the first protective layer 51 that remains after the first semiconductor layer forming step is completed is preferably 30% or more, more preferably 50% or more, and more preferably 70% or more of the area where the pattern printing resist 90 is formed. is even more preferable.

The area of the region where the pattern printing resist 90 is formed and the region where the lift-off layer 41 and the first protective layer 51 remain after the completion of the first semiconductor layer forming process are, for example, after forming the pattern printing resist and after stripping the pattern printing resist described later. can be obtained by observing the same region with an optical microscope, a scanning electron microscope, or the like, and measuring the areas of the region where the pattern printing resist 90 is formed and the regions of the lift-off layer 41 and the first protective layer 51, respectively. .

Further, it is preferable that the difference between the thickness of the lift-off layer 41 remaining after the completion of the first semiconductor layer forming step and the thickness of the lift-off layer 41 immediately after the formation of the lift-off layer 41 is small. This is because the formation film thickness of the lift-off layer 41 can be reduced as the reduction amount of the film thickness is smaller. Specifically, the thickness of the lift-off layer 41 remaining after the first semiconductor layer forming step is completed is preferably 20% or more, more preferably 50% or more, of the thickness immediately after the lift-off layer 41 is formed. More preferably 80% or more.

The ratio between the thickness of the lift-off layer 41 remaining after the completion of the first semiconductor layer forming step and the thickness of the lift-off layer 41 and the first protective layer 51 immediately after the formation of the lift-off layer 41 can be obtained, for example, as follows. can be done. Two in-process products having the lift-off layer 41 formed to have the same film thickness are prepared. The film thickness of the lift-off layer 41 of one in-process product is measured immediately after the formation of the lift-off layer 41 and the first protective layer 51 . The first semiconductor layer forming step is performed on the other in-process product, and the film thicknesses of the lift-off layer 41 and the first protective layer 51 are measured after the completion of this step. By comparing the film thicknesses of the two in-process products, the film thickness ratio can be calculated. The film thicknesses of the lift-off layer 41 and the first protective layer 51 can be measured by observing the cross section of the in-process product with a scanning microscope or the like. In addition, when there is a distribution in the thickness of the lift-off layer 41 and the first protective layer 51, the thickness of the lift-off layer 41 and the first protective layer 51 is measured at about 10 locations for one in-process product. and find the average value.

Considering an example here, when hydrofluoric acid (HF) and nitric acid (HNO ₃ ) are used as the etchant, if the content of hydrofluoric acid is small, even if the etchant passes through the pattern printing resist 90, the first It is considered that the protective layer 51 having an appropriate thickness protects the lift-off layer 41 from the etching solution.
Also, if a mixed solution of ozone dissolved in hydrofluoric acid is used as the etchant, the first protective layer 51 that is not covered with the pattern printing resist 90 can be dissolved. Specifically, the surface of the first protective layer 51 is oxidized to SiO ₂ by ozone (O ₃ ), and SiO ₂ is dissolved by hydrofluoric acid (HF). By repeating this, the first protective layer 51 is dissolved.
On the other hand, the first protective layer 51 covered with the pattern-printed resist 90 is deactivated when ozone passes through the pattern-printed resist 90, and the first protective layer 51 is not oxidized. Therefore, it is considered that the first protective layer 51 covered with the pattern printing resist 90 will not dissolve even if hydrofluoric acid (HF) passes through the pattern printing resist 90 .

Similarly, the second protective layer 53 protects the insulating layer 43 from the etching solution passing through the patterned printing resist 90 .

After that, as shown in FIG. 3D, the pattern printing resist 90 is removed. An inexpensive alkaline solution is used as an etching solution for the pattern printing resist 90 .
At this time, part of the first protective layer 51 on the back surface side is dissolved by the alkaline solution, but part of the first protective layer 51 remains.
On the other hand, the alkaline solution removes the second protective layer 53 on the light receiving surface side. At this time, the insulating layer 43 protects the intrinsic semiconductor layer 13 from the alkaline solution.

Next, both surfaces of the semiconductor substrate 11 are cleaned (cleaning process). In the cleaning process, for example, after ozone treatment, hydrofluoric acid treatment (treatment with hydrofluoric acid or a mixture of hydrofluoric acid and other types of acid) is performed.
At this time, the remaining portion of the first protective layer 51 protects the lift-off layer 41 from ozone treatment and hydrofluoric acid treatment (cleaning).
On the other hand, the surface of the insulating layer 43 on the light-receiving surface side is slightly dissolved by the ozone treatment and the hydrofluoric acid treatment, but a large portion remains.

Next, as shown in FIG. 3E, for example, the CVD method is used to form a semiconductor substrate 11 on the entire back surface side of the semiconductor substrate 11, specifically, on the lift-off layer 41 and the first protective layer 51 in the first region 7 and in the second region. 8, an intrinsic semiconductor layer material film 33Z and an n-type semiconductor layer material film 35Z are sequentially laminated (formed) (second semiconductor layer material film forming step).

Next, as shown in FIG. 3F, a lift-off method using a lift-off layer (sacrificial layer) is used to remove the first protective layer 51 and the intrinsic semiconductor layer material film in the first region 7 on the back surface side of the semiconductor substrate 11 . 33Z and n-type semiconductor layer material film 35Z are removed, and patterned intrinsic semiconductor layer 33 and n-type semiconductor layer 35 are formed in second region 8 (second semiconductor layer forming step).

Specifically, by removing the lift-off layer 41, the first protective layer 51, the intrinsic semiconductor layer material film 33Z and the n-type semiconductor layer material film 35Z on the lift-off layer 41 are removed, and the intrinsic semiconductor layer 33 and the n-type semiconductor layer are removed. A semiconductor layer 35 is formed. As a removal solution for the lift-off layer 41, for example, an acidic solution such as hydrofluoric acid is used.
At this time, the insulating layer 43 on the light receiving surface side of the semiconductor substrate 11 is also removed.

Next, as shown in FIG. 3G, the first electrode layer 27 and the second electrode layer 37 are formed on the back surface side of the semiconductor substrate 11 (electrode layer forming step).
Specifically, a transparent electrode layer material film is laminated (formed) on the entire back surface side of the semiconductor substrate 11 using, for example, a PVD method such as a sputtering method. After that, the transparent electrode layers 28 and 38 are patterned by removing part of the transparent electrode layer material film, for example, using an etching method using an etching paste. As an etching solution for the transparent electrode layer material film, for example, hydrochloric acid or ferric chloride aqueous solution is used.
After that, for example, using a pattern printing method or a coating method, a metal electrode layer 29 is formed on the transparent electrode layer 28, and a metal electrode layer 39 is formed on the transparent electrode layer 38, whereby the first electrode layer 27 and the A second electrode layer 37 is formed.

Next, an optical adjustment layer 15 is formed on the entire surface of the semiconductor substrate 11 on the light receiving surface side.
Through the above steps, the back electrode type solar cell 1 of the present embodiment shown in FIGS. 1 and 2 is obtained.

As described above, according to the solar cell manufacturing method of the present embodiment, the p-type semiconductor layer 25 is patterned using a pattern printing resist by a pattern printing method in the step of forming the first semiconductor layer. As compared with the case of using a photoresist (photolithography method) according to the method, the steps of exposure and development of the resist can be reduced, and the manufacturing process of the solar cell can be simplified and shortened.
In addition, in the second semiconductor layer forming step, the lift-off method using a lift-off layer (sacrificial layer) is used to pattern the n-type semiconductor layer 35, so the solar cell manufacturing process can be simplified and shortened. .
Moreover, in the first semiconductor layer forming step, an inexpensive alkaline solution is used as a solution for removing the pattern printing resist.
As a result, cost reduction and productivity improvement of solar cells are achieved.

Further, according to the solar cell manufacturing method of the present embodiment, since the first protective layer 51 is formed on the lift-off layer 41 on the back surface side, the p-type semiconductor layer 25 is patterned in the first semiconductor layer forming step. At this time, the first protective layer 51 protects the lift-off layer 41 from an etching solution that has passed through the pattern printing resist, such as a mixed solution of ozone dissolved in hydrofluoric acid. This suppresses peeling of the lift-off layer 41 when patterning the p-type semiconductor layer 25 .
Further, according to the method for manufacturing the solar cell of the present embodiment, when the pattern printing resist 90 is removed in the first semiconductor layer forming step, the first protective layer 51 is partially removed by the alkaline solution. dissolves, but a portion of the first protective layer 51 remains. Thereby, in the cleaning process, the first protective layer 51 protects the lift-off layer 41 from ozone treatment and hydrofluoric acid treatment (cleaning). As a result, peeling of the lift-off layer 41 is suppressed when both surfaces of the semiconductor substrate 11 are cleaned.
Note that the first protective layer 51 is naturally removed in the lift-off process.

Further, according to the method for manufacturing the solar cell of the present embodiment, since the insulating layer 43 is formed on the intrinsic semiconductor layer 13 on the light receiving surface side, in the step of forming the first semiconductor layer, when the pattern printing resist is removed, The insulating layer 43 protects the intrinsic semiconductor layer 13 from solutions that remove the patterned printing resist, such as alkaline solutions. This suppresses the dissolution of the intrinsic semiconductor layer 13 and suppresses deterioration of the performance of the solar cell.
The insulating layer 43 is naturally removed by a solution for removing the lift-off layer 41, such as an acid solution containing hydrofluoric acid, when removing the lift-off layer 41 in the second semiconductor layer forming step.

Furthermore, since the second protective layer 53 is formed on the insulating layer 43, when the p-type semiconductor layer 25 is patterned in the first semiconductor layer forming step, the second protective layer 53 is etched through the pattern printing resist. The insulating layer 43 is protected from a solution such as a mixed solution of ozone dissolved in hydrofluoric acid. This suppresses peeling of the insulating layer 43 when patterning the p-type semiconductor layer.
When removing the pattern printing resist, the second protective layer 53 is naturally removed with a solution for removing the pattern printing resist, such as an alkaline solution.

(Modification 1)
Although intrinsic amorphous silicon is used as the first protective layer 51 in the above-described embodiment, the first protective layer 51 may be amorphous silicon containing boron. Amorphous silicon containing boron is resistant to alkaline solutions. As a result, the first protective layer 51 remains undissolved by the alkaline solution used to remove the pattern printing resist 90 in the first semiconductor forming process, and protects the lift-off layer 41 from ozone treatment and hydrofluoric acid treatment (cleaning) in the cleaning process. . As a result, peeling of the lift-off layer 41 is suppressed when both surfaces of the semiconductor substrate 11 are cleaned.

By the way, in the cleaning process, the rinse treatment is performed after the ozone treatment and the hydrofluoric acid treatment.
When amorphous silicon is doped with boron, its affinity for acidic solutions increases, so the amount of hydrofluoric acid carried from the hydrofluoric acid treatment to the rinsing treatment increases, accelerating the weak acidification of the rinsing tank. In this regard, intrinsic amorphous silicon is preferred.

The first protective layer 51 is preferably amorphous silicon lightly doped with boron. Weak doping (light doping) means that the doping amount of boron is less than that of the p-type semiconductor layer.

The second protective layer 53 may also be amorphous silicon containing boron instead of intrinsic amorphous silicon.

(Modification 2)
In the above-described embodiment, the lift-off layer 41 may be composed of two layers with different densities. For example, the density of the first lift-off layer on the semiconductor substrate 11 side of the lift-off layer 41 is low (that is, the etching rate is high), and the density of the second lift-off layer on the side opposite to the semiconductor substrate 11 in the lift-off layer 41 is high. may be present (ie, the etch rate is slow). More specifically, the following relational expression (1) may be satisfied.
Etching rate of p-type semiconductor layer 25<etching rate of second lift-off layer<etching rate of first lift-off layer (1)
In this manner, by utilizing the difference in etching rate in the lift-off layer 41, the accuracy of each etching increases in the first semiconductor layer forming process shown in FIG. 3C and the second semiconductor layer forming process shown in FIG. 3F. .

Accuracy of etching, that is, formation of a conductive semiconductor layer with accuracy is important in order to prevent undesirable short circuits or leak currents in solar cells. In the first semiconductor layer forming step shown in FIG. 3C, that is, the step of selectively removing the p-type semiconductor layer 25 (hereinafter abbreviated as the p-type semiconductor layer patterning step), part of the lift-off layer 41 is removed as desired. It serves as a mask to prevent the etching solution from adhering to the p-type semiconductor layer 25 at a portion. Therefore, the width of the patterned p-type semiconductor layer 25 depends on the width of the remaining lift-off layer 41 . That is, in the p-type semiconductor layer patterning process, it is required to etch a pattern having a width of about several hundred μm with high precision, but precision in the thickness direction is not so important.

Therefore, if the etching rate of the lift-off layer 41 with respect to the etching solution is too high, the lift-off layer 41 tends to be excessively etched in the width direction (the width becomes narrower than the desired width). Therefore, the pattern accuracy of the lift-off layer 41 may deteriorate. Thus, it is not preferable that the etching rate of the lift-off layer 41 with respect to the etchant is too high.

On the other hand, in the lift-off step shown in FIG. 3F, the n-type semiconductor layer 35 not only covers the second lift-off layer remaining in the p-type semiconductor layer patterning step, but also covers the desired position (the remaining p-type semiconductor layer 25 is adjacent non-molding regions). Subsequently, while leaving the n-type semiconductor layer 35 at a desired position as a pattern, the top surface and side surfaces (end surfaces) of the second lift-off layer, and the side surfaces (end surfaces) of the first lift-off layer, the p-type semiconductor layer 25 and the intrinsic semiconductor layer 23 are removed. The upper n-type semiconductor layer 35 is removed. Therefore, it is preferable that the etchant has a higher etching rate for the lift-off layer than for the p-type semiconductor layer 25 . For example, while it is required that a widthwise region of about several tens of nm to several hundreds of nm be etched completely, precision in the width direction is not required. Also, from the viewpoint of productivity, a faster etching rate is preferable because the processing time is shortened.

Thus, the lift-off layer 41 is required to have contradictory etching characteristics between the p-type semiconductor layer patterning process and the lift-off process. This characteristic is realized if the relational expression (1) caused by the density difference between the first lift-off layer and the second lift-off layer is satisfied.

In the p-type semiconductor layer patterning step, if the relational expression (1) is satisfied, the first lift-off layer is melted fastest in the non-molding region, so the second lift-off layer thereon is also separated from the semiconductor substrate 11. (At this time, the second lift-off layer is not only dissociated but also dissolved), and the p-type semiconductor layer 25 exposed from the first lift-off layer is also dissolved.

More specifically, in the p-type semiconductor layer patterning step, for example, as shown in FIG. Through the sides, even if the first lift-off layer under the second lift-off layer is eroded by the etching, the uneroded first lift-off layer remains. Therefore, the second lift-off layer connected to it also remains. Thereby, the remaining second lift-off layer functions as the lift-off layer 41 in the lift-off process. Since the desired portion of the p-type semiconductor layer 25 must remain, the etching rate is slower than that of the first lift-off layer and the second lift-off layer.

Further, in the lift-off process, if the first lift-off layer as the lower layer is completely removed, the n-type semiconductor layer 35 is also removed even if the second lift-off layer remains on the first lift-off layer. That is, the second lift-off layer and the n-type semiconductor layer 35 thereon are lifted off.

As described above, the multi-layered lift-off layer 41 is intended to be almost completely removed in the lift-off process shown in FIG. 3F. step), the etching rate is set so that the etching rate of the p-type semiconductor layer 25 < the etching rate of the second lift-off layer < the etching rate of the first lift-off layer (relational expression (1)). Designed with density difference in the lift-off layer. In addition, as in the p-type semiconductor layer patterning step, the p-type semiconductor layer 25 must remain in a desired portion even in the lift-off step. The etching rate of the semiconductor layer 25 is slow.

Thus, when the p-type semiconductor layer 25 and the lift-off layer 41 that satisfy the relational expression (1) are used, the n-type semiconductor layer 35 is patterned without performing etching using a resist film in the lift-off process, for example. be done. In other words, the above-described method for manufacturing a solar cell simplifies the patterning process and efficiently manufactures a back-contact type solar cell. Moreover, since the pattern accuracy is also improved, short circuits or leak currents in the solar cell are prevented, and high output can be obtained from the solar cell.

Note that the number of layers of the lift-off layer 41 may be two or more, and may be two from the viewpoint of productivity.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various changes and modifications are possible. For example, in the above-described embodiment, the first conductivity type semiconductor layer 25 is a p-type semiconductor layer and the second conductivity type semiconductor layer 35 is an n-type semiconductor layer. The second conductivity type semiconductor layer 35 may be replaced with a p-type semiconductor layer.

In the above-described embodiment, the method for manufacturing the heterojunction solar cell 1 as shown in FIG. 2 was exemplified. It is applicable to various solar cell manufacturing methods such as batteries.

Further, in the above-described embodiment, an n-type semiconductor substrate is illustrated as the semiconductor substrate 11, but the semiconductor substrate 11 is a p-type semiconductor obtained by doping a p-type dopant (for example, boron (B) described above) into a crystalline silicon material. It may be a substrate.

Moreover, in the above-described embodiments, a solar cell having a crystalline silicon substrate was exemplified, but the present invention is not limited to this. For example, a solar cell may have a gallium arsenide (GaAs) substrate.

1, 1X solar cell 7 first region 7b, 8b busbar portion 7f, 8f finger portion 8 second region 11, 11X semiconductor substrate 13, 13X intrinsic semiconductor layer 15, 15X optical adjustment layer 23, 23X intrinsic semiconductor layer 23Z, 23ZX, 33Z, 33ZX intrinsic semiconductor layer material film 25, 25X first conductivity type semiconductor layer 25Z, 25ZX first conductivity type semiconductor layer material film 27, 27X first electrode layer 28, 28X, 38, 38X transparent electrode layer 29, 29X, 39 , 39X metal electrode layer 33, 33X intrinsic semiconductor layer 35, 35X second conductivity type semiconductor layer 35Z, 35ZX second conductivity type semiconductor layer material film 37, 37X second electrode layer 41 lift-off layer 43 insulating layer 51 first protective layer 53 Second protective layer

Claims (11)

a semiconductor substrate; a first conductivity type semiconductor layer and a first electrode layer laminated in order in a first region which is part of the other main surface side opposite to one main surface side of the semiconductor substrate; A method for manufacturing a back electrode type solar cell comprising a second conductivity type semiconductor layer and a second electrode layer laminated in order in a second region which is another part of the other main surface, the method comprising:
a first semiconductor layer material film forming step of forming a material film of the first conductivity type semiconductor layer on the other main surface side of the semiconductor substrate;
a lift-off layer forming step of forming a lift-off layer on the material film of the first conductivity type semiconductor layer;
a first protective layer forming step of forming a first protective layer on the lift-off layer to protect the lift-off layer;
By removing the material films of the first protective layer, the lift-off layer and the first conductivity type semiconductor layer in the second region using a pattern printing resist, the patterned first layer is formed in the first region. a first semiconductor layer forming step of forming a one conductivity type semiconductor layer, the lift-off layer and the first protective layer, and removing the pattern printing resist;
a cleaning step of cleaning both main surfaces of the semiconductor substrate;
a second semiconductor layer material film forming step of forming a material film of the second conductivity type semiconductor layer on the lift-off layer and the first protective layer in the first region and in the second region;
By removing the lift-off layer, material films of the first protective layer and the second conductivity type semiconductor layer in the first region are removed, and the patterned second conductivity type semiconductor is formed in the second region a second semiconductor layer forming step of forming a layer;
including
The first semiconductor layer forming step includes:
forming the pattern printing resist on the first protective layer in the first region using a pattern printing method;
Using the pattern printing resist as a mask, the material films of the first protective layer, the lift-off layer and the first conductivity type semiconductor layer in the second region are etched, thereby forming the patterned resist in the first region. forming a first conductivity type semiconductor layer, the lift-off layer and the first protective layer;
removing the patterned printing resist while leaving at least a portion of the first protective layer in the first region;
including
In the first semiconductor layer forming step, the first protective layer in the first region protects the lift-off layer in the first region from a solution used for the patterning,
In the cleaning step, the first protective layer in the first region protects the lift-off layer in the first region from cleaning.
A method for manufacturing a solar cell. The lift-off layer contains a material mainly composed of silicon oxide, silicon nitride, or a composite thereof,
The first protective layer contains a material containing silicon as a main component,
In the first semiconductor layer forming step, the solution used for patterning contains hydrofluoric acid,
In the first semiconductor layer forming step, the solution for removing the pattern printing resist is an alkaline solution,
In the cleaning step, cleaning includes ozone treatment and hydrofluoric acid treatment,
A method for manufacturing a solar cell according to claim 1 . 3. The method of manufacturing a solar cell according to claim 2 , wherein the material of said first protective layer is intrinsic amorphous silicon. 3. The method of manufacturing a solar cell according to claim 2 , wherein the material of said first protective layer is amorphous silicon containing boron. 5. The method for manufacturing a solar cell according to claim 1 , wherein said lift-off layer is composed of two layers having different densities. In the first protective layer forming step, the first protective layer is formed with a thickness of 1 nm or more and 50 nm or less.
3. A method of manufacturing a solar cell according to claim 1 or 2 . Before the first semiconductor layer forming step,
forming an intrinsic semiconductor layer on the one main surface side of the semiconductor substrate;
an insulating layer forming step of forming an insulating layer on the intrinsic semiconductor layer;
a second protective layer forming step of forming a second protective layer on the insulating layer to protect the insulating layer;
including
In the first semiconductor layer forming step,
the second protective layer is removed with a solution that protects the insulating layer from the solution used for patterning and removes the patterned printing resist;
the insulating layer protects the intrinsic semiconductor layer from solutions that remove the patterned printing resist;
In the step of forming the second semiconductor layer, the insulating layer is removed with a solution that removes the lift-off layer.
A method for manufacturing a solar cell according to any one of claims 1 to 6 . The intrinsic semiconductor layer includes a material containing silicon as a main component,
the lift-off layer and the insulating layer comprise a material mainly composed of silicon oxide, silicon nitride, or a composite thereof;
The first protective layer and the second protective layer contain a material containing silicon as a main component,
In the first semiconductor layer forming step, the solution used for patterning contains hydrofluoric acid,
In the first semiconductor layer forming step, the solution for removing the pattern printing resist is an alkaline solution,
In the cleaning step, cleaning includes ozone treatment and hydrofluoric acid treatment,
In the second semiconductor layer forming step, the solution for removing the lift-off layer contains hydrofluoric acid.
A method for manufacturing a solar cell according to claim 7 . 9. The method of manufacturing a solar cell according to claim 8 , wherein the material of said first protective layer and said second protective layer is intrinsic amorphous silicon. 9. The method of manufacturing a solar cell according to claim 8 , wherein the material of said first protective layer and said second protective layer is amorphous silicon containing boron. In the second protective layer forming step, the second protective layer is formed with a thickness of 1 nm or more and 50 nm or less.
A method for manufacturing a solar cell according to any one of claims 7 to 10 .

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