JP2023104310A - Solar cell manufacturing method - Google Patents

Abstract

To provide a method for manufacturing a solar cell, capable of improving performance of the solar cell while simplifying a manufacturing process.SOLUTION: A method for manufacturing a solar cell includes, in the following order: a step of forming material films of ground layers 29l and 39l; a step of forming a resist on the material films of the ground layers at a boundary between a first region 7 and a second region 8; a step of forming patterned plating layers 29u, 39u using a plating method in which the resist is used as a mask; a step of removing the resist; an annealing step of heating the plating layers and the material films of the ground layers; and a step of forming patterned ground layers 29I, 39I using an etching method in which the plating layers are used as a mask. In the annealing step, an oxide film is formed on the exposed surface of the plating layers and the exposed surface of the material films of the ground layers, and in the step of forming the ground layers, the oxide films formed on the exposed surface of the plating layers and the exposed surface of the material films of the ground layers are removed.SELECTED DRAWING: Figure 2

Description

The present invention relates to a method for manufacturing a back electrode type solar cell.

As a solar cell, a back electrode type (also referred to as back contact type or back contact type) solar cell in which an electrode is formed only on the back side is known. Such a solar cell includes a semiconductor substrate, a first conductivity type semiconductor layer and a first electrode layer laminated in order on the back side of the semiconductor substrate, and a first electrode layer laminated in order on another part of the back side of the semiconductor substrate. It comprises a two-conductivity-type semiconductor layer and a second electrode layer. The first electrode layer and the second electrode layer comprise metal electrode layers and are separated from each other to prevent short circuits.

Patent Document 1 discloses a manufacturing process for forming a metal electrode layer using a plating method using a resist as a mask. In this manufacturing process,
・On the base layer (seed layer) formed on the entire back surface, a resist is formed at the electrode layer separation location,
・After that, a separate plating layer is formed using a resist as a mask,
・Then, the resist is removed, and the underlying layer of the electrode layer separation portion is etched.
Thereby, a separated metal electrode layer composed of the underlying layer and the plating layer is formed. Thus, the manufacturing process of forming the metal electrode layer using the plating method can simplify the manufacturing process of the solar cell.

On the other hand, Patent Document 2 discloses a technique of heating a plating layer for the purpose of promoting crystallization of the plating layer. By heating the plating layer in this manner, the crystallization of the plating layer is promoted, and the resistance of the plating layer can be reduced.

WO2019/139020 JP-A-6-295662

The technique of crystallization of the plated layer described in Patent Document 2 is applied to the manufacturing process of the solar cell described in Patent Document 1 to reduce the resistance of the metal electrode layer (plated layer and underlying layer), and the solar cell It is conceivable to improve the output of the solar cell, that is, to improve the performance of the solar cell.

However, for example, if the plating layer crystallization technique described in Patent Document 2 is applied at the end of the solar cell manufacturing process described in Patent Document 1, in the heating step (annealing step), the metal electrode layer (plating layer and underlying layer) are oxidized, and an oxide film is formed on the exposed surface of the metal electrode layer. As a result, the contact resistance between the metal electrode layer and the wiring member increases, and the output of the solar cell decreases, that is, the performance of the solar cell decreases. As a result, the performance of the solar cell is degraded due to the increased contact resistance between the metal electrode layer and the wiring member, thereby reducing the effect of improving the performance of the solar cell by reducing the resistance of the metal electrode layer.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a solar cell capable of improving the performance of the solar cell while simplifying the manufacturing process.

A method for manufacturing a solar cell according to the present invention comprises: a semiconductor substrate; a first conductivity type semiconductor layer and a first metal electrode layer which are sequentially laminated in a first region which is part of one main surface side of the semiconductor substrate; The method for manufacturing a back electrode type solar cell comprising a second conductivity type semiconductor layer and a second metal electrode layer laminated in order on a second region which is another part of the one main surface side of the semiconductor substrate. and each of the first metal electrode layer and the second metal electrode layer has a base layer and a plating layer, and the method for manufacturing the solar cell includes: a base layer material film forming step of forming a series of material films of the base layer over the first region and the second region on the conductive semiconductor layer and the second conductive semiconductor layer; a resist forming step of forming a resist on the material film of the underlying layer at the boundary between the region and the second region; and a plating method using the resist as a mask to form the first region and the second region. a plating layer forming step of forming the patterned plating layer on the material film of the underlying layer; a resist removing step of removing the resist; The material film of the underlying layer is etched using an annealing step of heating and an etching method using the plating layer as a mask, thereby patterning the first region and the second region. and an underlying layer forming step of forming an underlying layer. In the annealing step, an oxide film is formed on the exposed surface of the plating layer and the exposed surface of the underlying layer material film, and in the underlying layer forming step, the exposed surface of the plating layer and the underlying layer material film are exposed. The oxide film formed on the surface is removed.

According to the present invention, it is possible to improve the performance of the solar cell while simplifying the manufacturing process.

It is the figure which looked at the solar cell which concerns on this embodiment from the back surface side. FIG. 2 is a sectional view taken along the line II-II in the solar cell shown in FIG. 1; FIG. 3 is an enlarged cross-sectional view of an example of a portion III in the solar cell shown in FIG. 2; It is a figure which shows the semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. FIG. 4 is a diagram showing a transparent electrode layer material film forming step and a base layer material film forming step of a metal electrode layer in the method for manufacturing a solar cell according to the present embodiment; It is a figure which shows the resist formation process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the plating layer formation process of the metal electrode layer in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the resist removal process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the annealing process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the transparent electrode layer formation process and the base layer formation process of a metal electrode layer in the manufacturing method of the solar cell which concerns on this embodiment. 4D is an enlarged cross-sectional view of an example of a portion V in a resist forming step and a plating layer forming step of a metal electrode layer in the solar cell manufacturing method shown in FIGS. 4C and 4D. FIG. FIG. 2 is a cross-sectional view corresponding to line II-II shown in FIG. 1, showing an example of an annealing step performed at the end of the manufacturing process in a method for manufacturing a solar cell according to a comparative example. FIG. 4 is a partially enlarged cross-sectional view of an example of the solar cell according to the present embodiment shown in FIG. 3, and is an enlarged cross-sectional view corresponding to the portion III shown in FIG. 2; FIG. 3 is a partially enlarged cross-sectional view of an example of a solar cell according to a modified example of the present embodiment, and is an enlarged cross-sectional view corresponding to the portion III shown in FIG. 2; FIG. 3 is a partially enlarged cross-sectional view of an example of a solar cell according to a modified example of the present embodiment, and is an enlarged cross-sectional view corresponding to the portion III shown in FIG. 2; FIG. 3 is a partially enlarged cross-sectional view of an example of a solar cell according to a modified example of the present embodiment, and is an enlarged cross-sectional view corresponding to the portion III shown in FIG. 2;

An example of an embodiment of the present invention will be described below with reference to the accompanying drawings. In each drawing, the same reference numerals are given to the same or corresponding parts. Also, for convenience, hatching, member numbers, etc. may be omitted, but in such cases, other drawings shall be referred to.

(solar cell)
FIG. 1 is a view of the solar cell according to the present embodiment viewed from the back side, and FIG. 2 is a cross-sectional view of the solar cell shown in FIG. 1 taken along the line II-II. The solar cell 1 shown in FIGS. 1 and 2 is a back electrode type (also referred to as back contact type or back contact type) and heterojunction type solar cell.

The solar cell 1 has a semiconductor substrate 11 with two main surfaces, and has a first region 7 and a second region 8 on the main surface of the semiconductor substrate 11 . Hereinafter, the main surface of the semiconductor substrate 11 on the light receiving side is referred to as a light receiving surface, and the main surface opposite to the light receiving surface (one main surface) of the main surfaces of the semiconductor substrate 11 is referred to as the rear surface.

The first region 7 has a so-called comb shape, and includes a plurality of finger portions 7f corresponding to comb teeth and busbar portions 7b corresponding to support portions of the comb teeth. The busbar portion 7b extends in a first direction (X direction) along one side portion of the semiconductor substrate 11, and the finger portions 7f extend from the busbar portion 7b in a second direction (Y direction) crossing the first direction. ).

Similarly, the second region 8 has a so-called comb shape, and includes a plurality of finger portions 8f corresponding to comb teeth and busbar portions 8b corresponding to support portions for the comb teeth. The busbar portion 8b extends in a first direction (X direction) along one side portion of the semiconductor substrate 11 opposite to the other side portion, and the finger portions 8f extend in a second direction (Y direction) from the busbar portion 8b. direction).

The finger portions 7f and the finger portions 8f are band-shaped extending in the second direction (Y direction) and are alternately provided in the first direction (X direction). Note that the first region 7 and the second region 8 may be formed in stripes.

As shown in FIG. 2 , the solar cell 1 includes a passivation layer 13 and an optical adjustment layer 15 that are laminated in order on the light receiving surface side of the semiconductor substrate 11 . The solar cell 1 also includes a passivation layer 23 , a first conductivity type semiconductor layer 25 and a first electrode layer 27 that are laminated in order on a portion (first region 7 ) of the back surface of the semiconductor substrate 11 . The solar cell 1 also includes a passivation layer 33 , a second conductive semiconductor layer 35 and a second electrode layer 37 that are laminated in order on another part (second region 8 ) of the back surface side of the semiconductor substrate 11 .

Semiconductor substrate 11 is formed of a crystalline silicon material such as monocrystalline silicon or polycrystalline silicon. The semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which a crystalline silicon material is doped with an n-type dopant. The semiconductor substrate 11 may be, for example, a p-type semiconductor substrate in which a crystalline silicon material is doped with a p-type dopant. Examples of n-type dopants include phosphorus (P). Examples of p-type dopants include boron (B). The semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light receiving surface side and generates photocarriers (electrons and holes).

Since crystalline silicon is used as the material of the semiconductor substrate 11, dark current is relatively small, and relatively high output (stable output regardless of illuminance) can be obtained even when the intensity of incident light is low.

The semiconductor substrate 11 may have a pyramid-shaped fine uneven structure called a texture structure on the back surface side. As a result, the efficiency of collecting the light that has passed through the semiconductor substrate 11 without being absorbed increases.

Further, the semiconductor substrate 11 may have a pyramid-shaped fine uneven structure called a texture structure on the light receiving surface side. As a result, the reflection of incident light on the light receiving surface is reduced, and the light confinement effect in the semiconductor substrate 11 is improved.

The passivation layer 13 is formed on the light receiving surface side of the semiconductor substrate 11 . The passivation layer 23 is formed in the first region 7 on the back side of the semiconductor substrate 11 . The passivation layer 33 is formed in the second region 8 on the back side of the semiconductor substrate 11 . The passivation layers 13, 23, 33 are made of a material containing, for example, an intrinsic (i-type) amorphous silicon material as a main component. The passivation layers 13 , 23 , 33 suppress recombination of carriers generated in the semiconductor substrate 11 and increase carrier recovery efficiency.

The optical adjustment layer 15 is formed on the passivation layer 13 on the light receiving surface side of the semiconductor substrate 11 . The optical adjustment layer 15 functions as an antireflection layer that prevents reflection of incident light, and also functions as a protective layer that protects the light receiving surface side of the semiconductor substrate 11 and the passivation layer 13 . The optical adjustment layer 15 is formed of an insulator material such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON).

The first conductivity type semiconductor layer 25 is formed on the passivation layer 23 , that is, in the first region 7 on the back side of the semiconductor substrate 11 . On the other hand, the second conductivity type semiconductor layer 35 is formed on the passivation layer 33 , that is, in the second region 8 on the back side of the semiconductor substrate 11 . That is, the first-conductivity-type semiconductor layer 25 and the second-conductivity-type semiconductor layer 35 are strip-shaped and extend in the Y direction. The first conductivity type semiconductor layers 25 and the second conductivity type semiconductor layers 35 are alternately arranged in the X direction. A portion of the second conductivity type semiconductor layer 35 may overlap a portion of the adjacent first conductivity type semiconductor layer 25 (not shown).

The first conductivity type semiconductor layer 25 is made of, for example, an amorphous silicon material. The first conductivity type semiconductor layer 25 is a p-type semiconductor layer in which, for example, an amorphous silicon material is doped with a p-type dopant (for example, boron (B) described above).

The second conductivity type semiconductor layer 35 is made of, for example, an amorphous silicon material. The second conductivity type semiconductor layer 35 is an n-type semiconductor layer in which an n-type dopant (for example, phosphorus (P) described above) is doped in an amorphous silicon material, for example. The first conductivity type semiconductor layer 25 may be an n-type semiconductor layer, and the second conductivity type semiconductor layer 35 may be a p-type semiconductor layer.

The first electrode layer 27 is formed on the first conductivity type semiconductor layer 25 , that is, in the first region 7 on the back side of the semiconductor substrate 11 . On the other hand, the second electrode layer 37 is formed on the second conductivity type semiconductor layer 35 , that is, in the second region 8 on the back side of the semiconductor substrate 11 . That is, the first electrode layer 27 and the second electrode layer 37 are strip-shaped and extend in the Y direction. The first electrode layers 27 and the second electrode layers 37 are alternately provided in the X direction.

The first electrode layer 27 has a first transparent electrode layer 28 and a first metal electrode layer 29 that are sequentially laminated on the first conductivity type semiconductor layer 25 . On the other hand, the second electrode layer 37 has a second transparent electrode layer 38 and a second metal electrode layer 39 which are sequentially laminated on the second conductivity type semiconductor layer 35 . The first metal electrode layer 29 has a two-layer structure of an underlying layer 29l and a plating layer 29u, and the second metal electrode layer 39 has a two-layer structure of an underlying layer 39l and a plating layer 39u.

The first transparent electrode layer 28 and the second transparent electrode layer 38 are made of a transparent conductive material. Transparent conductive materials include ITO (Indium Tin Oxide: composite oxide of indium oxide and tin oxide), ZnO (Zinc Oxide: zinc oxide), and the like.

The base layer 29l in the first metal electrode layer 29 and the base layer 39l in the second metal electrode layer 39 contain metal materials such as silver, copper, and aluminum formed using a PVD method such as sputtering. On the other hand, the plated layer 29u of the first metal electrode layer 29 and the plated layer 39u of the second metal electrode layer 39 contain a metal material such as silver, copper, nickel, etc. formed by plating, for example.

The first electrode layers 27 and the second electrode layers 37 are strip-shaped extending in the second direction (Y direction) and are alternately arranged in the first direction (X direction). That is, the first transparent electrode layers 28 and the second transparent electrode layers 38 are band-shaped extending in the second direction (Y direction) and are alternately arranged in the first direction (X direction). The first metal electrode layers 29 and the second metal electrode layers 39 are strip-shaped extending in the second direction (Y direction) and are alternately arranged in the first direction (X direction). The first transparent electrode layer 28 and the second transparent electrode layer 38 are separated from each other, and the first metal electrode layer 29 and the second metal electrode layer 39 are also separated from each other.

3 is an enlarged cross-sectional view of an example of portion III in the solar cell shown in FIG. 2. FIG. As will be described later, when a pattern printing resist is used as a resist for forming the plated layer 29u of the first metal electrode layer 29 and the plated layer 39u of the second metal electrode layer 39, the structure shown in FIG. 3 is obtained. may

As shown in FIG. 3, a resin film 41 is formed at least at the edge of the boundary between the first region 7 and the second region 8 between the base layer 29l and the plating layer 29u in the first metal electrode layer 29. It may be unevenly distributed.

Specifically, the base layer 29 l is relatively thin and has an uneven structure corresponding to the uneven structure (texture structure) of the semiconductor substrate 11 . The resin film 41 is interposed between the bottom layer 29l and the plated layer 29u and the uneven structure at least at the end of the base layer 29l. The resin film 41 may be formed in a sea-like shape of a sea-island structure (that is, continuously), or may be formed in an island-like shape of a sea-island structure (that is, discontinuously). It is preferable that the troughs of the uneven structure at least at the ends of the base layer 29l are flattened by the resin film 41. As shown in FIG.

On the other hand, the ridges of the concave-convex structure at least at the ends of the underlying layer 29l are in contact with the plating layer 29u. In addition, valleys and peaks of the uneven structure other than the ends of the base layer 29l are in contact with the plating layer 29u.

Similarly, the resin film 41 is unevenly distributed at least at the edge on the boundary side between the first region 7 and the second region 8 between the base layer 39l and the plating layer 39u in the second metal electrode layer 39. good too.

Specifically, the base layer 39 l is relatively thin and has an uneven structure corresponding to the uneven structure (texture structure) of the semiconductor substrate 11 . The resin film 41 is interposed between the bottom layer 39l and the plated layer 39u and the uneven structure at least at the end of the base layer 39l. The resin film 41 may be formed in a sea-like shape of a sea-island structure (that is, continuously), or may be formed in an island-like shape of a sea-island structure (that is, discontinuously). It is preferable that the troughs of the uneven structure at least at the ends of the base layer 39l are flattened by the resin film 41 .

On the other hand, the ridges of the concave-convex structure at least at the ends of the underlying layer 39l are in contact with the plating layer 39u. In addition, valleys and peaks of the uneven structure other than the ends of the base layer 39l are in contact with the plating layer 39u.

(Method for manufacturing solar cell)
Next, a method for manufacturing a solar cell according to this embodiment will be described with reference to FIGS. 4A to 4G. FIG. 4A is a diagram showing a semiconductor layer forming step in the method for manufacturing a solar cell according to this embodiment, and FIG. 4B is a diagram showing a transparent electrode layer material film forming step and a metal electrode in the method for manufacturing a solar cell according to this embodiment. It is a figure which shows the base layer material film|membrane formation process of a layer. FIG. 4C is a diagram showing a resist forming step in the solar cell manufacturing method according to this embodiment, and FIG. 4D shows a metal electrode layer plating layer forming step in the solar cell manufacturing method according to this embodiment. FIG. 4 is a diagram showing; FIG. 4E is a diagram showing a resist removing step in the method for manufacturing a solar cell according to this embodiment, and FIG. 4F is a diagram showing an annealing step in the method for manufacturing a solar cell according to this embodiment. FIG. 4G is a diagram showing a transparent electrode layer forming step and a base layer forming step for a metal electrode layer in the method for manufacturing a solar cell according to this embodiment. 4A to 4G show the back side of the semiconductor substrate 11, and the front side of the semiconductor substrate 11 is omitted.

First, as shown in FIG. 4A, a passivation layer 23 and a first conductivity type semiconductor layer 25 are formed on a portion of the back surface of the semiconductor substrate 11, specifically, on the first region 7 (semiconductor layer forming step). . For example, after forming a passivation layer material film and a first conductivity type semiconductor layer material film on the entire rear surface side of the semiconductor substrate 11 using the CVD method or the PVD method, the photolithography technique or the printing technique is used to generate the passivation layer material film and the first conductivity type semiconductor layer material film. The passivation layer 23 and the first conductivity type semiconductor layer 25 may be patterned using an etching method using a resist or a metal mask.

The etching solution for the p-type semiconductor layer material film includes, for example, an acidic solution such as hydrofluoric acid containing ozone or a mixed solution of nitric acid and hydrofluoric acid. and alkaline solutions such as aqueous potassium hydroxide.

Alternatively, when laminating the passivation layer and the first conductivity type semiconductor layer on the back surface side of the semiconductor substrate 11 using the CVD method or the PVD method, the passivation layer 23 and the first conductivity type semiconductor layer 25 are formed using a mask. Film formation and patterning may be performed simultaneously.

Next, a passivation layer 33 and a second-conductivity-type semiconductor layer 35 are formed on another part of the back surface side of the semiconductor substrate 11, specifically in the second region 8 (semiconductor layer forming step). For example, in the same manner as described above, after forming a passivation layer material film and a second conductivity type semiconductor layer material film on the entire rear surface side of the semiconductor substrate 11 using the CVD method or the PVD method, photolithography technology or printing technology is applied. The passivation layer 33 and the second-conductivity-type semiconductor layer 35 may be patterned by using an etching method using a resist generated using a metal mask or a metal mask.

Alternatively, when stacking the passivation layer and the second conductivity type semiconductor layer on the back surface side of the semiconductor substrate 11 using the CVD method or the PVD method, the passivation layer 33 and the second conductivity type semiconductor layer 35 are formed using a mask. Film formation and patterning may be performed simultaneously.

In this semiconductor layer forming step, a passivation layer 13 may be formed on the entire surface of the semiconductor substrate 11 on the light receiving surface side (not shown).

Next, as shown in FIG. 4B, a series of transparent electrode layer material films 28Z are formed over the first region 7 and the second region 8 on the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35. (transparent electrode layer material film forming step). As a method for forming the transparent electrode layer material film 28Z, for example, a CVD method or a PVD method is used.

Next, on the transparent electrode layer material film 28Z, that is, on the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35, a series of base layer material films 29lZ are formed across the first region 7 and the second region 8. is formed (underlying layer material film forming step). As a method for forming the underlying layer material film 29lZ, for example, a PVD method such as sputtering is used.

Next, as shown in FIG. 4C, a resist 40 is formed on the underlying layer material film 29lZ at the boundary between the first region 7 and the second region 8 (resist forming step). A method of forming the resist 40 is not particularly limited, but includes, for example, a photolithography method and a printing method. Among these, the printing method is preferable from the viewpoint of simplification of the manufacturing process. In particular, pattern printing methods such as press printing such as screen printing or gravure printing, or ejection printing such as inkjet printing are preferred.

In the pattern printing method, a patterned resist 40 is formed by printing and baking (hardening) a printing material containing a resin material and a solvent. The temperature at which the resist is baked (cured) is, for example, 80° C. or higher and 140° C. or lower. At this time, as shown in FIG. 5, a resin film 41 formed by exuding the resin material in the printing material is formed in the troughs of the uneven structure (texture structure) of the base layer material film 29lZ.

As shown in FIG. 5, the resin film 41 may be formed between the resists 40, that is, in the valleys of the uneven structure in all of the first region 7 and the second region 8, or as shown in FIG. It may be formed in the trough portion of the uneven structure at the end portion on the boundary side between the first region 7 and the second region 8 between the resists 40 .

Next, as shown in FIG. 4D, a patterned plating layer 29u is formed on the underlying layer material film 29lZ in the first region 7 by using a plating method using the resist 40 as a mask, and a patterned plating layer 29u is formed in the second region. A patterned plated layer 39u is formed on the base layer material film 29lZ in step 8 (plated metal electrode layer forming step). When the resist 40 is a pattern printing resist, as shown in FIG. 5, the plating layer 29u is formed on the resin film 41 in the valleys of the concave-convex structure at least at the ends of the base layer material film 29lZ and on the base layer. It is formed on the ridges of the uneven structure in the material film 29lZ.

Next, as shown in FIG. 4E, the resist 40 is removed (resist removing step). As the resist removing solution, an alkaline aqueous solution such as an aqueous sodium hydroxide solution is used.

Next, as shown in FIG. 4F, the plating layers 29u and 39u and the underlying layer material film 29lZ are annealed by heating the semiconductor substrate 11 in an air atmosphere (annealing step). This promotes crystallization of the plating layers 29u, 39u and the underlying layer material film 29lZ (that is, the underlying layers 29l, 39l). The heating temperature in the annealing step is preferably higher than the temperature at the time of baking (hardening) the resist in the above-described resist forming step. For example, the heating temperature is preferably 110° C. or higher and 250° C. or lower, more preferably 130° C. or higher and 200° C. or lower, and even more preferably 140° C. or higher and 170° C. or lower. If the heating temperature is less than 110° C., a sufficient annealing effect cannot be obtained. On the other hand, if the heating temperature exceeds 250° C., the amorphous silicon film quality may deteriorate. At this time, the exposed surfaces of the plating layers 29u and 39u and the underlying layer material film 29lZ are oxidized, and an oxide film 29O is formed on the exposed surfaces of the plating layers 29u and 39u and the exposed surface of the underlying layer material film 29lZ.

Next, as shown in FIG. 4G, an etching method using the plating layer 29u and the plating layer 39u as a mask is used to etch the base layer material film 29lZ and the transparent electrode layer material film 28Z, thereby forming the first region 7. , a patterned first transparent electrode layer 28 and an underlying layer 29l are formed, and a patterned second transparent electrode layer 38 and an underlying layer 39l are formed in the second region 8 (transparent electrode layer forming step, and a base layer forming step). At this time, the oxide film 29O formed on the exposed surfaces of the plating layers 29u and 39u and the exposed surface of the underlying layer material film 29lZ is removed. As a result, a first metal electrode layer 29 consisting of the underlying layer 29l and the plating layer 29u and a second metal electrode layer 39 consisting of the underlying layer 39l and the plating layer 39u are formed. Also, a first electrode layer 27 consisting of a first transparent electrode layer 28 and a first metal electrode layer 29, and a second electrode layer 37 consisting of a second transparent electrode layer 38 and a second metal electrode layer 39 are formed. be.

As an etching solution for simultaneous etching of the base layer material film 29lZ and the transparent electrode layer material film 28Z, for example, when the transparent electrode layer material film 28Z is ITO and the base layer material film 29lZ is copper, ammonium persulfate (ammonium persulfate) is used. and a mixed solution of an oxidizing agent such as and an acid solution such as hydrochloric acid (HCl).

After that, an optical adjustment layer 15 is formed on the entire surface of the semiconductor substrate 11 on the light receiving surface side (not shown). Through the above steps, the back electrode type solar cell 1 of the present embodiment shown in FIGS. 1 and 2 is obtained.

As described above, according to the solar cell manufacturing method of the present embodiment, the plating layers 29u and 39u in the metal electrode layers 29 and 39 are formed using the plating method. Furthermore, the plating layers 29u and 39u on the metal electrode layers 29 and 39 are formed directly (film formation and patterning are performed simultaneously) using a plating method using the resist 40 as a mask. This enables simplification and cost reduction of the solar cell manufacturing process.

In addition, according to the method for manufacturing a solar cell of the present embodiment, in the plating method, a printing material containing a resin material and a solvent is printed using a pattern printing method and baked (cured) to directly (manufacture The film and patterning may be performed simultaneously) to form a patterned resist 40 . This enables simplification and cost reduction of resist formation as compared with resist formation using photolithography technology, for example. Therefore, the manufacturing process of the solar cell can be simplified and the cost can be reduced.

Further, according to the method of manufacturing the solar cell of the present embodiment, as the material of the metal electrode layers 29 and 39, a relatively inexpensive metal such as Cu is used instead of the relatively expensive known Ag paste. good too. As a result, the cost of the solar cell can be reduced.

Furthermore, according to the solar cell manufacturing method of the present embodiment, the annealing step promotes the crystallization of the metal electrode layers 29 and 39 (the plating layers 29u and 39u and the underlying layers 29l and 39l). , 37 can be reduced in resistance, and the output of the solar cell 1 can be improved, that is, the performance of the solar cell 1 can be improved.

By the way, if the purpose is to crystallize the metal electrode layer (plating layer and underlying layer), it is generally considered that the annealing step is performed at the end of the manufacturing process, that is, after the etching step of the underlying layer. However, if the annealing process is performed after the underlying layer etching process, as shown in FIG. As a result, an oxide film 29O is formed on the exposed surfaces of the metal electrode layers 29 and 39. FIG. As a result, the contact resistance between the electrode layers 27 and 37 and the wiring member increases, and the output of the solar cell 1 decreases, that is, the performance of the solar cell 1 decreases. As a result, the performance of the solar cell 1 is degraded due to the increased contact resistance between the electrode layers 27 and 37 and the wiring members, and the effect of improving the performance of the solar cell 1 by lowering the resistance of the electrode layers 27 and 37 is reduced (problem Point 1).

In addition, the semiconductor layers 25 (23) and 35 (33) are exposed in the boundary region between the first region 7 and the second region 8 after the underlying layer etching step. Therefore, if the annealing process is performed after the underlying layer etching process, as shown in FIG. It diffuses into the substrate 11 . When Cu diffuses into the semiconductor layers 25 (23), 35 (33) and the semiconductor substrate 11, the photoelectric conversion characteristics of the solar cell 1 deteriorate, that is, the reliability of the solar cell 1 deteriorates (Problem 2).

Regarding Problem 1 described above, according to the solar cell manufacturing method of the present embodiment, the annealing step is performed before the etching step of the base layer. and the underlying layers 29l, 39l) are oxidized to form an oxide film 29O on the exposed surfaces of the metal electrode layers 29, 39 (FIG. 4F), the metal electrode layers 29l and 39l are not removed in the subsequent etching step of the underlying layers. The oxide film 29O on the exposed surfaces of 29, 39 is removed (FIG. 4G). Therefore, the contact resistance between the electrode layers 27 and 37 and the wiring members does not increase due to the oxide films 29O on the exposed surfaces of the metal electrode layers 29 and 39, and the output of the solar cell 1 is reduced. performance degradation does not occur. Therefore, the effect of improving the performance of the solar cell 1 by reducing the resistance of the electrode layers 27 and 37 is not reduced.

Regarding Problem 2 described above, according to the solar cell manufacturing method of the present embodiment, since the annealing step is performed before the etching step of the underlayer, that is, in the boundary region between the first region 7 and the second region 8, Since the annealing process is performed before the etching process of the underlying layer where the semiconductor layers 25 (23) and 35 (33) are not exposed (FIG. 4F), the Cu constituting the metal electrode layers 29 and 39 diffuses in the annealing process. However, they are not diffused into the semiconductor layers 25 ( 23 ) and 35 ( 33 ) and the semiconductor substrate 11 . Therefore, the deterioration of the photoelectric conversion characteristics of the solar cell 1, that is, the deterioration of the reliability of the solar cell 1 does not occur due to the diffusion of Cu.

Further, according to the solar cell manufacturing method of the present embodiment, the crystallization of the plated layers 29u and 39u is promoted in the annealing step, so that the plated layers 29u and 39u are less likely to be etched in the subsequent etching step of the base layer. and functions favorably as a mask.

By the way, if the annealing process is performed before the resist stripping process, the resist is heated in the annealing process, making it difficult to strip the resist.

In this respect, according to the solar cell manufacturing method of the present embodiment, since the annealing step is performed after the resist stripping step, the resist is not heated in the annealing step, and the resist is not difficult to strip. .

By the way, if the resist is left unpeeled in the resist stripping process, there may be a region where the underlying layer (and the transparent electrode layer) is not etched in the subsequent etching process of the underlying layer. This may result in current leakage in the solar cell.

Regarding this point, according to the method for manufacturing a solar cell of the present embodiment, if there is a peeling residue of the resist in the annealing step between the resist stripping step and the underlying layer etching step, the Cu constituting the underlying layer is oxidized. Does not tarnish without staining. For this reason, if the resist is transparent, for example, it is possible to visually observe the portions where the resist is left unpeeled before the etching process of the underlying layer. When the resist is colored, the optical characteristics before and after the annealing process are measured, and the locations where the optical characteristics are not changed before and after the annealing process can be found as the locations where the resist is left unpeeled. In this manner, the annealing step allows the resist to be removed and remaining portions to be easily confirmed.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various changes and modifications are possible. For example, in the above-described embodiment, as shown in FIG. A solar cell in which the resin film 41 is unevenly distributed between and in the valleys of the uneven structure is illustrated. However, the present invention is not limited to this, and various types of solar cells are conceivable depending on the degree of etching in the solar cell manufacturing process. Here, for comparison with a comparative example of a solar cell described below, FIG. 3 is a partial enlarged cross-sectional view of an example of the solar cell according to the present embodiment shown in FIG. The diagram is re-presented in FIG. 7A. FIG. 7A collectively shows the first conductivity type semiconductor layer 25 and the passivation layer 23 in FIG. 7B to 7D are partial enlarged cross-sectional views of examples of solar cells according to modifications of the present embodiment, and are enlarged cross-sectional views corresponding to part III shown in FIG.

As shown in FIG. 7B, in the solar cell 1, between the underlying layer 29l and the plating layer 29u in the first metal electrode layer 29 and between the underlying layer 39l and the plating layer 39u in the second metal electrode layer 39 Moreover, the resin film 41 unevenly distributed in the valleys of the uneven structure may be removed by etching. For example, in the resist removing process described above, the resin film 41 is etched and removed.

As a result, in the solar cell 1, at least at the end of the first metal electrode layer 29 on the boundary side between the first region 7 and the second region 8, there is a space below the plating layer 29u in the valley of the uneven structure. may be present. More specifically, at least at the end of the first metal electrode layer 29, under the plated layer 29u in the valleys of the uneven structure, the underlying layer 29l exists. A space may be interposed between the plated layer 29u and the resin film 41 not interposed therebetween.

Similarly, in the solar cell 1, at least at the edge of the second metal electrode layer 39 on the boundary side between the first region 7 and the second region 8, there is a space below the plating layer 39u in the valley of the uneven structure. may be present. More specifically, at least at the end of the second metal electrode layer 39, the base layer 39l exists under the plating layer 39u in the valleys of the uneven structure. A space may be interposed between the plated layer 39u and the resin film 41 not interposed therebetween.

Alternatively, as shown in FIG. 7C, in the solar cell 1, the base layers 29l and 39l may be etched and removed, and the transparent electrode layers 28 and 38 may be etched and removed. . For example, in the above-described transparent electrode layer forming step and base layer forming step, the base layers 29l and 39l and the transparent electrode layers 28 and 38 are etched and removed.

As a result, in the solar cell 1, at least at the end of the first metal electrode layer 29, the resin film 41 and the base layer 29l do not exist below the plated layer 29u in the valleys of the uneven structure, and a space exists. may Alternatively, in the solar cell 1, the resin film 41, the base layer 29l and the transparent electrode layer 28 do not exist under the plating layer 29u in the valleys of the uneven structure at least at the end of the first metal electrode layer 29, Space may exist.

Similarly, in the solar cell 1, at least at the end of the second metal electrode layer 39, the resin film 41 and the base layer 39l do not exist under the plated layer 39u in the valleys of the uneven structure, and a space exists. may Alternatively, in the solar cell 1, the resin film 41, the base layer 39l and the transparent electrode layer 38 do not exist under the plating layer 39u in the valleys of the uneven structure at least at the end of the second metal electrode layer 39, Space may exist.

Alternatively, as shown in FIG. 7D , in the solar cell 1, between the underlying layer 29l and the plating layer 29u in the first metal electrode layer 29, and between the underlying layer 39l and the plating layer 39u in the second metal electrode layer 39. The resin film 41 unevenly distributed in the valleys of the concave-convex structure may remain without being etched, the underlying layers 29l and 39l may be etched and removed, and the transparent electrode layers 28 and 38 may be removed. It may be removed by etching. As described above, the underlying layers 29l and 39l and the transparent electrode layers 28 and 38 are etched and removed, for example, in the transparent electrode layer forming step and the underlying layer forming step described above.

As a result, in the solar cell 1, at least at the end of the first metal electrode layer 29, the resin film 41 exists under the plated layer 29u in the valleys of the uneven structure, and the base layer 29l does not exist. , a space may exist under the resin film 41 in the troughs of the uneven structure. Alternatively, in the solar cell 1, the resin film 41 exists under the plated layer 29u in the valleys of the concave-convex structure at least at the end of the first metal electrode layer 29, and the base layer 29l and the transparent electrode layer 28 may not exist, and a space may exist under the resin film 41 in the troughs of the uneven structure.

Similarly, in the solar cell 1, at least at the end of the second metal electrode layer 39, under the plated layer 39u in the troughs of the uneven structure, the resin film 41 exists and the base layer 39l does not exist. , a space may exist under the resin film 41 in the troughs of the uneven structure. Alternatively, in the solar cell 1, the resin film 41 exists under the plated layer 39u in the valleys of the concave-convex structure at least at the end of the second metal electrode layer 39, and the underlying layer 39l and the transparent electrode layer 38 may not exist, and a space may exist under the resin film 41 in the troughs of the uneven structure.

Moreover, in the above-described embodiments, the method for manufacturing a solar cell having an electrode layer including a transparent electrode layer and a metal electrode layer has been exemplified. However, the present invention is not limited to this, and can also be applied to a method for manufacturing a solar cell having electrode layers containing only metal electrode layers.

Moreover, in the above-described embodiments, the method for manufacturing a solar cell using a crystalline silicon material was exemplified, but the present invention is not limited to this. For example, it can be applied to a method of manufacturing a solar cell using various materials such as gallium arsenide (GaAs).

Moreover, in the embodiment described above, the method for manufacturing a heterojunction solar cell is illustrated as shown in FIG. However, the present invention is not limited to this, and can be applied to methods for manufacturing various solar cells such as homojunction solar cells.

Reference Signs List 1 solar cell 7 first region 7f finger portion 7b busbar portion 8 second region 8f finger portion 8b busbar portion 11 semiconductor substrate 13, 23, 33 passivation layer 15 optical adjustment layer 25 first conductive semiconductor layer 27 first electrode layer 28 First transparent electrode layer 28Z Transparent electrode layer material film 29 First metal electrode layer 29l Underlying layer 29lZ Underlying layer material film 29u Plating layer 29O Oxide film 35 Second conductivity type semiconductor layer 37 Second electrode layer 38 Second transparent electrode layer 39 Second metal electrode layer 39l Base layer 39u Plating layer 40 Resist 41 Resin film

Claims (3)

A semiconductor substrate, a first conductivity type semiconductor layer and a first metal electrode layer which are sequentially laminated in a first region which is a part of the one main surface side of the semiconductor substrate, and the rest of the one main surface side of the semiconductor substrate. A method for manufacturing a back electrode type solar cell comprising a second conductivity type semiconductor layer and a second metal electrode layer laminated in order in a second region that is a part of the
each of the first metal electrode layer and the second metal electrode layer has a base layer and a plating layer;
The method for manufacturing the solar cell comprises:
forming a series of material films of the underlying layer over the first region and the second region on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer on the one main surface side of the semiconductor substrate; a base layer material film forming step to be formed;
a resist forming step of forming a resist on the underlying layer material film at the boundary between the first region and the second region;
a plating layer forming step of forming the patterned plating layer on the material film of the underlying layer in each of the first region and the second region using a plating method using the resist as a mask; ,
a resist removing step of removing the resist;
An annealing step of heating the material films of the plating layer and the underlying layer;
forming the patterned underlying layer in each of the first region and the second region by etching the material film of the underlying layer using an etching method using the plating layer as a mask; a stratum formation process;
in that order,
In the annealing step, an oxide film is formed on the exposed surface of the plating layer and the exposed surface of the material film of the underlying layer,
In the base layer forming step, the oxide film formed on the exposed surface of the plating layer and the exposed surface of the material film of the base layer is removed.
A method for manufacturing a solar cell. In the resist forming step, using a pattern printing method, a printing material containing a resin material and a solvent is printed and cured to form the patterned resist.
A method for manufacturing a solar cell according to claim 1 . 3. The method of manufacturing a solar cell according to claim 2, wherein a heating temperature in said annealing step is higher than a curing temperature in said resist forming step.

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