CN114830357B - Method for manufacturing solar cell - Google Patents
Method for manufacturing solar cell Download PDFInfo
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- CN114830357B CN114830357B CN202080088050.3A CN202080088050A CN114830357B CN 114830357 B CN114830357 B CN 114830357B CN 202080088050 A CN202080088050 A CN 202080088050A CN 114830357 B CN114830357 B CN 114830357B
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- 238000000034 method Methods 0.000 title claims abstract description 116
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 72
- 239000004065 semiconductor Substances 0.000 claims abstract description 390
- 239000000463 material Substances 0.000 claims abstract description 113
- 239000000758 substrate Substances 0.000 claims abstract description 110
- 238000007639 printing Methods 0.000 claims abstract description 71
- 238000000059 patterning Methods 0.000 claims description 35
- 229910052751 metal Inorganic materials 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 28
- 239000003513 alkali Substances 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 416
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 34
- 238000010586 diagram Methods 0.000 description 33
- 238000005530 etching Methods 0.000 description 26
- 239000000243 solution Substances 0.000 description 25
- 230000000052 comparative effect Effects 0.000 description 23
- 230000003287 optical effect Effects 0.000 description 14
- 238000000206 photolithography Methods 0.000 description 12
- 238000004140 cleaning Methods 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 239000003929 acidic solution Substances 0.000 description 9
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000002210 silicon-based material Substances 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229910021419 crystalline silicon Inorganic materials 0.000 description 5
- 230000018109 developmental process Effects 0.000 description 5
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010306 acid treatment Methods 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 239000002131 composite material Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000004528 spin coating Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 150000007513 acids Chemical class 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000007646 gravure printing Methods 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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- Engineering & Computer Science (AREA)
- Life Sciences & Earth Sciences (AREA)
- Sustainable Energy (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Photovoltaic Devices (AREA)
Abstract
The present invention aims to solve the following problems, and provides a method for manufacturing a solar cell, which reduces stripping residues of pattern printing resists and reduces damage of a third intrinsic semiconductor layer in a manufacturing process. The method for manufacturing the solar cell sequentially comprises the following steps: forming a material film of a first intrinsic semiconductor layer and a material film of a first conductivity type semiconductor layer on a back surface side of a semiconductor substrate (11); a step of forming a pattern printing resist on a material film of a first conductive semiconductor layer in a first region (7) on the back surface side of a semiconductor substrate (11), and not forming the pattern printing resist on the light receiving surface side of the semiconductor substrate (11); forming a patterned first intrinsic semiconductor layer (23) and a first conductivity type semiconductor layer (25) in a first region (7) on the back surface side of a semiconductor substrate (11) using a pattern printing resist; removing the pattern printing resist; and a step of forming a third intrinsic semiconductor layer (13) on the light-receiving surface side of the semiconductor substrate (11).
Description
Technical Field
The present invention relates to a method for manufacturing a back electrode type (back contact type) solar cell.
Background
Patent document 1 discloses a back electrode type solar cell. The back electrode type solar cell includes: a semiconductor substrate functioning as a photoelectric conversion layer; a first intrinsic semiconductor layer, a first conductivity type semiconductor layer, and a first electrode layer sequentially stacked on a portion of a back surface side of the semiconductor substrate; a second intrinsic semiconductor layer, a second conductive semiconductor layer, and a second electrode layer laminated in this order on the other portion of the back surface side of the semiconductor substrate. The solar cell further includes a third intrinsic semiconductor layer and an optical adjustment layer which are sequentially stacked on the light-receiving surface side of the semiconductor substrate.
In general, etching methods using photolithography are used for the first conductive type semiconductor layer patterning (first patterning) and the second conductive type semiconductor layer patterning (second patterning). However, in the etching method using the photolithography technique, for example, a process of coating a photoresist, drying the photoresist, exposing the photoresist, developing the photoresist, etching a semiconductor layer using the photoresist as a mask, and stripping the photoresist is required, and the process is complicated.
In this regard, patent document 1 describes a technique of simplifying a process of patterning a pattern by a lift-off method using a lift-off layer (sacrificial layer) in the second patterning.
Patent document 1: japanese patent application laid-open No. 2014-75526
The present inventors have devised using a pattern printing resist based on a pattern printing method in the first patterning of a pattern. Thus, compared with the case of using a photoresist (photolithography) by spin coating, the number of exposure and development steps can be reduced, and the process of patterning can be further simplified.
However, the third intrinsic semiconductor layer on the light receiving surface side of the semiconductor substrate is formed before the patterning of the first conductivity type semiconductor layer (first patterning). In the first semiconductor layer forming step (first patterning), a pattern printing resist is formed on the light-receiving surface side of the semiconductor substrate as in the back surface side, so that the third intrinsic semiconductor layer is protected from the etching solution.
However, when the pattern-printed resist on the back side is printed and fired (dried) and then the pattern-printed resist on the light-receiving side is printed and fired (dried), the thermal history of the pattern-printed resist on the back side becomes 2 times, and the pattern-printed resist on the back side becomes difficult to peel. Therefore, a lift-off residue of the pattern printing resist on the back side is generated.
In addition, if the third intrinsic semiconductor layer on the light-receiving surface side of the semiconductor substrate is formed before the patterning of the first conductivity type semiconductor layer (first patterning), the third intrinsic semiconductor layer may be damaged in a subsequent manufacturing process.
Disclosure of Invention
The invention aims to provide a method for manufacturing a solar cell, which reduces stripping residues of pattern printing resists and reduces damage of a third intrinsic semiconductor layer in a manufacturing process.
The method for manufacturing a solar cell according to the present invention is a method for manufacturing a back contact type solar cell, the back contact type solar cell including: a semiconductor substrate; a first intrinsic semiconductor layer and a first conductivity type semiconductor layer sequentially stacked in a first region, the first region being a part of the semiconductor substrate on the other main surface side opposite to the one main surface side; a second intrinsic semiconductor layer and a second conductivity type semiconductor layer sequentially stacked in a second region, the second region being another portion of the semiconductor substrate on the other main surface side; and a third intrinsic semiconductor layer laminated on the one principal surface side of the semiconductor substrate, the method of manufacturing the solar cell comprising, in order: a first semiconductor layer material film forming step of forming a material film of the first intrinsic semiconductor layer and a material film of the first conductivity type semiconductor layer on the other main surface side of the semiconductor substrate; a resist forming step of forming a pattern printing resist on a material film of the first conductive semiconductor layer in the first region on the other main surface side of the semiconductor substrate, the pattern printing resist not being formed on the one main surface side of the semiconductor substrate; a first semiconductor layer forming step of removing the material film of the first intrinsic semiconductor layer and the material film of the first intrinsic semiconductor layer in the second region on the other main surface side of the semiconductor substrate by using the pattern printing resist, thereby forming the patterned first intrinsic semiconductor layer and the first conductive semiconductor layer in the first region on the other main surface side of the semiconductor substrate; a resist removing step of removing the pattern printing resist; and a third semiconductor layer forming step of forming the third intrinsic semiconductor layer on the one principal surface side of the semiconductor substrate.
According to the present invention, in the method for manufacturing a solar cell, the peeling residue of the pattern printing resist can be reduced, and damage to the third intrinsic semiconductor layer in the manufacturing process can be reduced.
Drawings
Fig. 1 is a view of a solar cell according to the present embodiment from the back side.
Fig. 2 is a cross-sectional view of the solar cell of fig. 1 taken along line II-II.
Fig. 3A shows a first semiconductor layer material film forming step and an adjacent step in the method for manufacturing a solar cell according to the present embodiment
And a step of forming a semiconductor layer and a step of forming a release layer.
Fig. 3B is a diagram showing a resist forming process in the method for manufacturing a solar cell according to the present embodiment.
Fig. 3C is a diagram showing a first semiconductor layer forming process in the method for manufacturing a solar cell according to the present embodiment.
Fig. 3D is a diagram showing a resist removal process in the method for manufacturing a solar cell according to the present embodiment.
Fig. 3E is a diagram showing a second semiconductor layer material film forming step and a third semiconductor layer forming step in the method for manufacturing a solar cell according to the present embodiment.
Fig. 3F is a diagram showing a second semiconductor layer forming process in the method for manufacturing a solar cell according to the present embodiment.
Fig. 3G is a diagram showing an optical adjustment layer forming process in the method for manufacturing a solar cell according to the present embodiment.
Fig. 3H is a diagram showing an electrode layer forming process in the method for manufacturing a solar cell according to the present embodiment.
Fig. 3I is a diagram showing an electrode layer forming process in the method for manufacturing a solar cell according to the present embodiment.
Fig. 4A is a diagram showing a first semiconductor layer material film forming step, a third intrinsic semiconductor layer forming step, and a peeling layer forming step in the method for manufacturing a solar cell of the comparative example.
Fig. 4B is a diagram showing a resist forming process in the method for manufacturing a solar cell of the comparative example.
Fig. 4C is a diagram showing a first semiconductor layer forming process in the method for manufacturing a solar cell of the comparative example.
Fig. 4D is a diagram showing a resist removal process in the method for manufacturing a solar cell of the comparative example.
Fig. 4E is a diagram showing a second semiconductor layer material film forming process in the method for manufacturing a solar cell of the comparative example.
Fig. 4F is a diagram showing a second semiconductor layer forming process in the method for manufacturing a solar cell of the comparative example.
Fig. 4G is a diagram showing an optical adjustment layer forming process in the method for manufacturing a solar cell of the comparative example.
Fig. 4H is a diagram showing an electrode layer forming process in the method for manufacturing a solar cell of the comparative example.
Fig. 4I is a diagram showing an electrode layer forming process in the method for manufacturing a solar cell of the comparative example.
Detailed Description
An example of an embodiment of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding portions are denoted by the same reference numerals. For convenience, hatching, component symbols, and the like may be omitted, and in this case, reference may be made to other drawings.
(solar cell)
Fig. 1 is a view of a solar cell according to the present embodiment as viewed from the back side. The solar cell 1 shown in fig. 1 is a back electrode type (also referred to as a back contact type or a back junction type) solar cell. The solar cell 1 includes an n-type (second conductivity type) semiconductor substrate 11 having two main surfaces, and the semiconductor substrate 11 has a first region 7 and a second region 8 on the main surfaces.
The first region 7 is formed in a so-called comb shape, and has a plurality of finger portions 7f corresponding to the teeth of the comb and a bus portion 7b corresponding to the support portion of the teeth of the comb. The bus bar portion 7b extends in a first direction (X direction) along one edge portion of the semiconductor substrate 11, and the finger portion 7f extends from the bus bar portion 7b to a second direction (Y direction) intersecting the first direction (X direction).
Similarly, the second region 8 has a so-called comb shape, and includes a plurality of finger portions 8f corresponding to the teeth of the comb, and a bus bar portion 8b corresponding to the support portion of the teeth of the comb. The bus bar portion 8b extends in the first direction (X direction) along the other side portion of the semiconductor substrate 11 opposite to the one side portion, and the finger portion 8f extends from the bus bar portion 8b in the second direction (Y direction).
The finger 7f and the finger 8f are alternately arranged in the first direction (X direction). The first region 7 and the second region 8 may be formed in a stripe shape.
Fig. 2 is a cross-sectional view of the solar cell of fig. 1 taken along line II-II. As shown in fig. 2, the solar cell 1 includes an intrinsic semiconductor layer (third intrinsic semiconductor layer) 13 and an optical adjustment layer 15, which are sequentially stacked on a light receiving surface side, which is one of main surfaces of the semiconductor substrate 11 on which light is received. The solar cell 1 includes an intrinsic semiconductor layer (first intrinsic semiconductor layer) 23, a p-type (first conductivity type) semiconductor layer 25, and a first electrode layer 27, which are sequentially stacked on a part (mainly the first region 7) of the back surface side, which is the other main surface of the semiconductor substrate 11 opposite to the light receiving surface. The solar cell 1 includes an intrinsic semiconductor layer (second intrinsic semiconductor layer) 33, an n-type (second conductivity type) semiconductor layer 35, and a second electrode layer 37, which are sequentially stacked on the other portion (mainly the second region 8) of the back surface side of the semiconductor substrate 11.
The semiconductor substrate 11 is formed of a crystalline silicon material such as single crystal silicon or polycrystalline silicon. The semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which an n-type dopant is doped in a crystalline silicon material. As the n-type dopant, phosphorus (P) may be mentioned, for example.
The semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light receiving surface side to generate photocarriers (electrons and holes).
By using crystalline silicon as the material of the semiconductor substrate 11, a relatively high output (stable output irrespective of illuminance) can be obtained even when dark current is relatively small and the intensity of incident light is low.
The semiconductor substrate 11 may have a pyramid-shaped fine concave-convex structure called a texture structure on the back surface side. This improves the recovery efficiency of light passing through the semiconductor substrate 11 without being absorbed by the semiconductor substrate.
The semiconductor substrate 11 may have a pyramid-shaped fine uneven structure called a texture structure on the light receiving surface side. This reduces reflection of the incident light on the light receiving surface, and improves the light blocking effect of the semiconductor substrate 11.
The intrinsic semiconductor layer 13 is formed on the light receiving surface side of the semiconductor substrate 11. The intrinsic semiconductor layer 23 is formed in the first region 7 on the back surface side of the semiconductor substrate 11. The intrinsic semiconductor layer 33 is formed in the second region 8 on the back surface side of the semiconductor substrate 11. The intrinsic semiconductor layers 13, 23, and 33 are formed of a material containing intrinsic (i-type) amorphous silicon as a main component, for example.
The intrinsic semiconductor layers 13, 23, and 33 function as so-called passivation layers, and suppress recombination of carriers generated on the semiconductor substrate 11, thereby improving the recovery efficiency of carriers.
The optical adjustment layer 15 is formed on the intrinsic semiconductor layer 13 on the light receiving surface side of the semiconductor substrate 11. The optical adjustment layer 15 functions as an anti-reflection layer that prevents reflection of incident light, and also functions as a protective layer that protects the light-receiving surface side of the semiconductor substrate 11 and the intrinsic semiconductor layer 13. The optical adjustment layer 15 is formed of, for example, an insulator material such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON) or a composite thereof.
The p-type semiconductor layer 25 is formed on the intrinsic semiconductor layer 23, i.e., the first region 7 on the back surface side of the semiconductor substrate 11. The p-type semiconductor layer 25 is formed of, for example, an amorphous silicon material. The p-type semiconductor layer 25 is, for example, a p-type semiconductor layer doped with a p-type dopant in an amorphous silicon material. As the p-type dopant, for example, boron (B) is cited.
The n-type semiconductor layer 35 is formed on the intrinsic semiconductor layer 33, i.e., the second region 8 on the back surface side of the semiconductor substrate 11. The n-type semiconductor layer 35 is formed of, for example, an amorphous silicon material. The n-type semiconductor layer 35 is, for example, an n-type semiconductor layer in which an amorphous silicon material is doped with an n-type dopant (for example, phosphorus (P) described above).
The first electrode layer 27 is formed on the p-type semiconductor layer 25, and the second electrode layer 37 is formed on the n-type semiconductor layer 35. The first electrode layer 27 has a transparent electrode layer 28 and a metal electrode layer 29 laminated in this order on the p-type semiconductor layer 25. The second electrode layer 37 has a transparent electrode layer 38 and a metal electrode layer 39 laminated in order on the n-type semiconductor layer 35.
The transparent electrode layers 28, 38 are formed of a transparent conductive material. The transparent conductive material may be ITO (Indium Tin Oxide: composite Oxide of Indium Oxide and Tin Oxide). The metal electrode layers 29 and 39 are formed of a conductive paste material containing metal powder such as silver.
(method for manufacturing solar cell of comparative example)
The present inventors have devised using a pattern printing resist based on a pattern printing method in a pattern (first-time pattern) of a p-type semiconductor layer. Thus, compared with the case of using a photoresist (photolithography) by spin coating, the number of exposure and development steps can be reduced, and the manufacturing process of the solar cell can be simplified.
The pattern printing is not printing in which a resist film (non-pattern resist film) before patterning is formed by one step such as exposure and development as in the photolithography method, but printing in which a patterned resist (printing material) is directly attached to a resist attachment surface, such as punching printing such as screen printing or gravure printing, or jet printing such as ink-jet printing. The pattern printing resist means a printing material (resist material) used for pattern printing.
The inventors of the present application have also devised to use an inexpensive alkali solution as a solution for removing the pattern printing resist in patterning the p-type semiconductor layer. Thereby, the cost of the solar cell can be reduced.
The inventors of the present application have also conceived to use a lift-off method using a lift-off layer (sacrificial layer) for the pattern of the n-type semiconductor layer (second pattern). Thereby, simplification of the manufacturing process of the solar cell can be achieved.
The inventors of the present application have also conceived a two-layer structure having a lower layer and an upper layer, the lower layer and the upper layer having the characteristics to an acidic solution as shown below.
Etching rate of lower layer > etching rate of upper layer
Thus, the peeling of the peeling layer can be suppressed in the substrate cleaning step after patterning the p-type semiconductor layer (first patterning) by the upper layer having a relatively low etching rate, and the peeling property can be improved in the peeling step of patterning the n-type semiconductor layer (second patterning) by the lower layer having a relatively high etching rate.
In addition, the inventors of the present application have conceived to use a metal electrode layer as a mask in the patterning of the transparent electrode layer. Thus, it is not necessary to use a resist by photolithography or the like as a mask, and the manufacturing process of the solar cell can be simplified.
Hereinafter, a method for manufacturing the solar cell 1X according to the comparative example based on the idea of the present inventor and its problems will be described with reference to fig. 4A to 4I. Fig. 4A is a diagram showing a first semiconductor layer material film forming step, a third semiconductor layer forming step, and a release layer forming step in the method for manufacturing a solar cell of the comparative example, and fig. 4B is a diagram showing a resist forming step in the method for manufacturing a solar cell of the comparative example. Fig. 4C is a diagram showing a first semiconductor layer forming process in the method for manufacturing a solar cell of the comparative example, and fig. 4D is a diagram showing a resist removing process in the method for manufacturing a solar cell of the comparative example. Fig. 4E is a diagram showing a second semiconductor layer material film forming process in the method for manufacturing a solar cell of the comparative example, and fig. 4F is a diagram showing a second semiconductor layer forming process in the method for manufacturing a solar cell of the comparative example. Fig. 4G is a diagram showing an optical adjustment layer forming process in the method for manufacturing the solar cell of the comparative example, and fig. 4H and 4I are diagrams showing an electrode layer forming process in the method for manufacturing the solar cell of the comparative example.
First, as shown in fig. 4A, for example, an intrinsic semiconductor layer material film 23ZX and a p-type semiconductor layer material film 25ZX are sequentially stacked (formed) on the entire surface of the back surface side of a semiconductor substrate 11X using a CVD method (chemical vapor deposition method), and the semiconductor substrate 11X has a rugged structure (texture structure) on the light receiving surface side and/or the back surface side (first semiconductor layer material film forming step).
Further, for example, CVD is used, and an intrinsic semiconductor layer (third intrinsic semiconductor layer) 13X is laminated (formed) on the entire light-receiving surface side of the semiconductor substrate 11X (third semiconductor layer forming step). The order of forming the intrinsic semiconductor layer material film 23ZX and the p-type semiconductor layer material film 25ZX and the intrinsic semiconductor layer 13X is not limited.
Next, for example, a CVD method is used to laminate (film) a release layer (sacrificial layer) 41X on the entire surface of the back surface side of the semiconductor substrate 11X, specifically, on the entire surface of the p-type semiconductor layer material film 25ZX (release layer forming step).
The peeling layer 41X is formed of a material such as silicon oxide (SiO), silicon nitride (SiN), or a composite of these. The film thickness of the release layer 41X is preferably, for example, 1nm to 1 μm.
The peeling layer 41X may have a two-layer structure having a lower layer and an upper layer from the semiconductor substrate 11X side. The lower and upper layers have the characteristics for acidic solutions as shown below.
Etching rate of lower layer > etching rate of upper layer
For example, when the release layer 41X is a film containing silicon oxide as a main component, the value of X when the main component is SiOx satisfies the following relational expression.
X of lower layer > x of upper layer
Next, as shown in fig. 4B to 4D, the release layer 41X, p type semiconductor layer material film 25ZX and the intrinsic semiconductor layer material film 23ZX in the second region 8 are removed on the back surface side of the semiconductor substrate 11X by using the pattern printing resist 90X, whereby the patterned intrinsic semiconductor layer (first intrinsic semiconductor layer) 23X, p type semiconductor layer 25X and the release layer 41X are formed in the first region 7.
Specifically, as shown in fig. 4B, a pattern printing resist 90X is formed on the back surface side of the semiconductor substrate 11X by using a pattern printing method on the p-type semiconductor layer material film 25ZX and the release layer 41X in the first region 7 (resist forming step). The pattern printing resist 90X is formed on the entire light receiving surface side of the semiconductor substrate 11X by a pattern printing method (resist forming step). The film thickness of the pattern printing resist is, for example, 1 μm to 50 μm. If a resist is printed by a pattern using a pattern printing method, exposure and development of a resist (simplification of a manufacturing process) in a conventional photoresist (photolithography) using a spin coating method are not required. At this time, a first problem and a second problem (details will be described later) occur.
Thereafter, as shown in fig. 4C, the release layer 41X in the second region 8 is etched on the back surface side of the semiconductor substrate 11X using the pattern printing resist 90X as a mask, thereby forming a patterned release layer 41X in the first region 7. As an etching solution for the release layer 41X, for example, an acidic solution such as hydrofluoric acid can be used.
Then, the p-type semiconductor layer material film 25ZX and the intrinsic semiconductor layer material film 23ZX in the second region 8 are etched on the back surface side of the semiconductor substrate 11X with the pattern printing resist 90X as a mask, whereby the patterned intrinsic semiconductor layer 23X and the patterned p-type semiconductor layer 25X are formed in the first region 7 (first semiconductor layer forming step). As an etching solution for the p-type semiconductor layer material film 25ZX and the intrinsic semiconductor layer material film 23ZX, for example, an acidic solution such as a mixed solution obtained by dissolving ozone in hydrofluoric acid can be used.
Thereafter, as shown in fig. 4D, the pattern printing resist 90X on the back surface side and the light receiving surface side is removed (resist removing step). As an etching solution for the pattern printing resist 90X, an inexpensive alkali solution such as KOH (reduced cost) can be used. In this case, a second problem (details will be described later) occurs.
Next, both sides of the semiconductor substrate 11X are cleaned (first cleaning step). In the first cleaning step, for example, after ozone treatment, hydrofluoric acid treatment is performed. The hydrofluoric acid treatment also includes a treatment with a mixture containing other kinds of acids (for example, hydrochloric acid in the first cleaning step) in hydrofluoric acid, not only hydrofluoric acid. At this time, the peeling of the peeling layer 41X can be suppressed by the upper layer having a low etching rate in the peeling layer 41X. In this case, a second problem (details will be described later) occurs.
Next, as shown in fig. 4E, for example, an intrinsic semiconductor layer material film 33ZX and an n-type semiconductor layer material film 35ZX are sequentially stacked (formed) on the entire rear surface side of the semiconductor substrate 11X, specifically, on the peeling layer 41X in the first region 7 and the second region 8 by CVD (second semiconductor layer material film forming step).
Next, as shown in fig. 4F, the intrinsic semiconductor layer material film 33ZX and the n-type semiconductor layer material film 35ZX in the first region 7 are removed on the back surface side of the semiconductor substrate 11X by a lift-off method using a lift-off layer (sacrificial layer), whereby a patterned intrinsic semiconductor layer (second intrinsic semiconductor layer) 33X and an n-type semiconductor layer 35X are formed in the second region 8 (second semiconductor layer forming step).
Specifically, by removing the peeling layer 41X, the intrinsic semiconductor layer material film 33ZX and the n-type semiconductor layer material film 35ZX on the peeling layer 41X are removed, and the intrinsic semiconductor layer 33X and the n-type semiconductor layer 35X are formed in the second region 8. As the removing solution for the release layer 41X, for example, an acidic solution such as hydrofluoric acid can be used. In this case, the lower layer having a relatively high etching rate in the release layer 41X can improve the release property.
Next, as shown in fig. 4G, an optical adjustment layer 15X is formed on the entire light-receiving surface side of the semiconductor substrate 11X (optical adjustment layer forming step).
Next, as shown in fig. 4H and 4I, the first electrode layer 27X and the second electrode layer 37X are formed on the back surface side of the semiconductor substrate 11X (electrode layer forming step).
Specifically, for example, PVD (physical vapor deposition) such as sputtering is used, and a transparent electrode layer material film 28ZX is laminated (formed) on the back surface side of the semiconductor substrate 11X so as to extend over the first conductive semiconductor layer 25X and the second conductive semiconductor layer 35X (transparent electrode layer material film forming step).
Thereafter, for example, a pattern printing method or a coating method is used to form the metal electrode layer 29X on the first conductivity type semiconductor layer 25X through the transparent electrode layer material film 28ZX, and to form the metal electrode layer 39X on the second conductivity type semiconductor layer 35X through the transparent electrode layer material film 28ZX (metal electrode layer forming step).
Thereafter, the transparent electrode layer material film 28ZX is patterned using the metal electrode layer 29X and the metal electrode layer 39X as masks, thereby forming a first transparent electrode layer 28X and a second transparent electrode layer 38X which are separated from each other (transparent electrode layer forming step). As an etching solution for the transparent electrode layer material film 28ZX, for example, hydrochloric acid or an aqueous solution of ferric chloride can be used.
In the conventional method for manufacturing a solar cell, the transparent electrode layer is formed (patterned) after the transparent electrode layer material film is formed and before the metal electrode layer is formed.
In the formation (patterning) of the transparent electrode layer, for example, patterning of the transparent electrode layer material film is performed by photolithography, thereby forming a first transparent electrode layer and a second transparent electrode layer which are separated from each other. In the case of the photolithography process, the process is performed,
coating a resist on top of the transparent electrode layer material film,
exposing the resist to light, thereby forming an opening in the resist,
etching the transparent electrode layer material film exposed at the opening using the resist as a mask to form a first transparent electrode layer and a second transparent electrode layer separated from each other,
removing the resist.
In contrast, according to the method for manufacturing a solar cell of the comparative example, after the formation of the transparent electrode layer material film, the formation of the metal electrode layer and the formation of the transparent electrode layer (patterning) are sequentially included, and in the formation of the transparent electrode layer (patterning), the first transparent electrode layer 28X and the second transparent electrode layer 38X are formed separately by patterning the transparent electrode layer material film 28ZX using the first metal electrode layer 29X and the second metal electrode layer 39X as masks. Thus, according to the method for manufacturing a solar cell of the comparative example, it is not necessary to use a photolithography method using a mask or the like as in the conventional art, and simplification and shortening of the formation of the transparent electrode layer can be achieved.
Through the above steps, the back electrode type solar cell 1X of the comparative example was completed.
Here, in the method for manufacturing a solar cell of the comparative example, before the first semiconductor layer forming step (first patterning), the intrinsic semiconductor layer (third intrinsic semiconductor layer) 13X on the light-receiving surface side is formed. In the first semiconductor layer forming step (first patterning), a pattern printing resist is formed on the light receiving surface side as in the back surface side, so that the intrinsic semiconductor layer 13X is protected from the etching solution, and the intrinsic semiconductor layer 13X is left.
(first subject)
However, when the pattern-printed resist on the back side is printed and fired (dried) and then the pattern-printed resist on the light-receiving side is printed and fired (dried), the thermal history of the pattern-printed resist on the back side becomes 2 times, and the pattern-printed resist on the back side becomes difficult to peel. Therefore, a peeling residue of the pattern printing resist on the back surface side is generated.
(second subject)
In addition, if the intrinsic semiconductor layer 13X on the light-receiving surface side is formed before the first semiconductor layer forming step (first patterning), the intrinsic semiconductor layer 13X is damaged in the subsequent manufacturing process.
For example, the intrinsic semiconductor layer 13X on the light receiving surface side may be damaged due to contact with the pattern printing resist, contact with the resist stripping solution (alkali solution), and contact with the cleaning solution (hydrofluoric acid).
Regarding the first and second problems, the present inventors have devised: in the resist forming step of the first semiconductor layer forming step (first patterning), the resist is not patterned on the light-receiving surface side, but in the first semiconductor layer forming step (first patterning), the temporary intrinsic semiconductor layer on the light-receiving surface side which has been formed at this stage is peeled off, and in the second semiconductor layer material film forming step, the intrinsic semiconductor layer on the light-receiving surface side is re-formed.
(method for manufacturing solar cell of the embodiment)
The method for manufacturing the solar cell 1 according to the present embodiment shown in fig. 1 and 2 will be described below with reference to fig. 3A to 3I. Fig. 3A is a diagram showing a first semiconductor layer material film forming step, a temporary semiconductor layer forming step, and a release layer forming step in the method for manufacturing a solar cell according to the present embodiment, and fig. 3B is a diagram showing a resist forming step in the method for manufacturing a solar cell according to the present embodiment. Fig. 3C is a diagram showing a first semiconductor layer forming process in the method for manufacturing a solar cell according to the present embodiment, and fig. 3D is a diagram showing a resist removing process in the method for manufacturing a solar cell according to the present embodiment. Fig. 3E is a diagram showing a second semiconductor layer material film forming step and a third semiconductor layer forming step in the method for manufacturing a solar cell according to the present embodiment, and fig. 3F is a diagram showing a second semiconductor layer forming step in the method for manufacturing a solar cell according to the present embodiment. Fig. 3G is a diagram showing an optical adjustment layer forming process in the method for manufacturing a solar cell according to the present embodiment, and fig. 3H and 3I are diagrams showing an electrode layer forming process in the method for manufacturing a solar cell according to the present embodiment.
First, as shown in fig. 3A, for example, an intrinsic semiconductor layer material film 23Z and a p-type semiconductor layer material film 25Z are sequentially stacked (formed) on the entire surface of the back surface side of the semiconductor substrate 11 by CVD (first semiconductor layer material film forming step), and the semiconductor substrate 11 has a concave-convex structure (texture structure) on the light receiving surface side and/or the back surface side.
Further, for example, a CVD method may be used to laminate (film) the temporary semiconductor layer 13Z on the entire light-receiving surface side of the semiconductor substrate 11 (temporary semiconductor layer forming step). The temporary semiconductor layer 13Z is, for example, an intrinsic semiconductor layer. When the temporary semiconductor layer 13Z is formed, it is possible to prevent a contamination source (organic substance or the like) from being accidentally attached to the light receiving surface side of the semiconductor substrate 11 at the time of a resist forming process or the like described later. Further, the temporary semiconductor layer 13Z on the light receiving surface side may not be formed. The order of forming the intrinsic semiconductor layer material film 23Z and the p-type semiconductor layer material film 25Z and the temporary semiconductor layer 13Z is not limited.
Next, a release layer (sacrificial layer) 41 is laminated (formed) on the entire surface of the back surface side of the semiconductor substrate 11, specifically, on the entire surface of the p-type semiconductor layer material film 25Z by, for example, CVD (release layer forming step).
The peeling layer 41 is formed of a material such as silicon oxide (SiO), silicon nitride (SiN), or a composite of these, for example, silicon oxynitride (SiON). The film thickness of the release layer 41 is preferably, for example, 1nm to 1 μm.
The peeling layer 41 may have a two-layer structure having a lower layer and an upper layer from the semiconductor substrate 11 side. The lower and upper layers have the characteristics for acidic solutions as shown below.
Etching rate of lower layer > etching rate of upper layer
For example, when the release layer 41 is a film containing silicon oxide as a main component, the value of x when the main component is SiOx satisfies the following relational expression.
X of lower layer > x of upper layer
Next, as shown in fig. 3B to 3D, the lift-off layer 41, the p-type semiconductor layer material film 25Z, and the intrinsic semiconductor layer material film 23Z in the second region 8 are removed on the back surface side of the semiconductor substrate 11 using the pattern printing resist 90, thereby forming the patterned intrinsic semiconductor layer (first intrinsic semiconductor layer) 23, the p-type semiconductor layer 25, and the lift-off layer 41 in the first region 7.
Specifically, as shown in fig. 3B, a pattern printing resist 90 is formed on the back surface side of the semiconductor substrate 11 on the p-type semiconductor layer material film 25Z and the release layer 41 in the first region 7 by using a pattern printing method (resist forming step). The film thickness of the pattern printing resist 90 is, for example, 1 μm to 50 μm. If a resist is printed by a pattern using a pattern printing method, exposure and development of a resist (simplification of a manufacturing process) in a conventional photoresist (photolithography) using a spin coating method are not required.
On the other hand, no pattern printing resist is formed on the light receiving surface side of the semiconductor substrate 11 (resist forming step). Thus, after the pattern-printed resist 90 on the back side is printed and fired (dried), the pattern-printed resist on the light-receiving side does not need to be printed and fired (dried), and the thermal history of the pattern-printed resist 90 on the back side becomes 1 time. This reduces the thermal history of the back-side pattern printing resist 90, and reduces the difficulty in stripping the back-side pattern printing resist 90 in the resist removal step described later, thereby reducing the residual stripping of the back-side pattern printing resist 90 (first problem solving).
Since the pattern printed resist is not formed on the light receiving surface side and the intrinsic semiconductor layer 13 on the light receiving surface side is not formed as described below, the intrinsic semiconductor layer 13 on the light receiving surface side is not damaged by contact with the pattern printed resist (the second problem is solved).
Thereafter, as shown in fig. 3C, the release layer 41 in the second region 8 is etched on the back surface side of the semiconductor substrate 11 using the pattern printing resist 90 as a mask, thereby forming a patterned release layer 41 in the first region 7. As the etching solution for the release layer 41, for example, an acidic solution such as hydrofluoric acid can be used.
Then, the p-type semiconductor layer material film 25Z and the intrinsic semiconductor layer material film 23Z in the second region 8 are etched on the back surface side of the semiconductor substrate 11 using the pattern printing resist 90 as a mask, whereby the patterned intrinsic semiconductor layer (first intrinsic semiconductor layer) 23 and the p-type semiconductor layer 25 are formed in the first region 7 (first semiconductor layer forming step). As the etching solution for the p-type semiconductor layer material film 25Z and the intrinsic semiconductor layer material film 23Z, for example, an acidic solution such as a mixed solution obtained by dissolving ozone in hydrofluoric acid can be used.
At this time, since the pattern printing resist is not formed on the light-receiving surface side of the semiconductor substrate 11, the temporary semiconductor layer 13Z formed on the light-receiving surface side of the semiconductor substrate 11 is removed.
Thereafter, as shown in fig. 3D, the pattern printing resist 90 is removed (resist removal step). As an etching solution for the pattern printing resist 90, an inexpensive alkali solution such as KOH (reduced cost) can be used.
At this time, as described later, the intrinsic semiconductor layer 13 on the light-receiving surface side is not formed, and therefore, there is no damage to the intrinsic semiconductor layer 13 on the light-receiving surface side due to contact with a resist stripping solution (alkali solution) (the second problem is solved).
Next, both sides of the semiconductor substrate 11 are cleaned (first cleaning process). In the first cleaning step, for example, after ozone treatment, hydrofluoric acid treatment is performed. The hydrofluoric acid treatment also includes a treatment with a mixture containing other kinds of acids (for example, hydrochloric acid in the first cleaning step) in hydrofluoric acid, not only hydrofluoric acid. In this case, peeling of the peeling layer 41 can be suppressed by the upper layer having a low etching rate in the peeling layer 41.
In this case, since the intrinsic semiconductor layer 13 on the light-receiving surface side is not formed as will be described later, there is no damage to the intrinsic semiconductor layer 13 on the light-receiving surface side due to contact with a cleaning solution (hydrofluoric acid) (the second problem is solved).
Next, as shown in fig. 3E, an intrinsic semiconductor layer (third intrinsic semiconductor layer) 13 is laminated (formed) on the entire surface of the semiconductor substrate 11 on the light-receiving surface side by CVD, for example (third semiconductor layer forming step).
Further, for example, the intrinsic semiconductor layer material film 33Z and the n-type semiconductor layer material film 35Z are sequentially stacked (formed) on the entire surface of the back surface side of the semiconductor substrate 11, specifically, on the release layer 41 in the first region 7 and the second region 8 by using a CVD method (second semiconductor layer material film forming step).
Next, as shown in fig. 3F, the intrinsic semiconductor layer material film 33Z and the n-type semiconductor layer material film 35Z in the first region 7 are removed on the back surface side of the semiconductor substrate 11 by a lift-off method using a lift-off layer (sacrificial layer), whereby the patterned intrinsic semiconductor layer (second intrinsic semiconductor layer) 33 and the n-type semiconductor layer 35 are formed in the second region 8 (second semiconductor layer forming step).
Specifically, by removing the peeling layer 41, the intrinsic semiconductor layer material film 33Z and the n-type semiconductor layer material film 35Z on the peeling layer 41 are removed, and the intrinsic semiconductor layer 33 and the n-type semiconductor layer 35 are formed in the second region 8. As the removing solution of the peeling layer 41, for example, an acidic solution such as hydrofluoric acid can be used. In this case, the lower layer having a relatively high etching rate in the release layer 41 can improve the release property.
Next, as shown in fig. 3G, an optical adjustment layer 15 is formed on the entire light-receiving surface side of the semiconductor substrate 11 (optical adjustment layer forming step).
Next, as shown in fig. 3H and 3I, the first electrode layer 27 and the second electrode layer 37 are formed on the back surface side of the semiconductor substrate 11 (electrode layer forming step).
Specifically, for example, a PVD method such as a sputtering method is used, and a transparent electrode layer material film 28Z is laminated (formed) on the back surface side of the semiconductor substrate 11 so as to extend over the first conductive semiconductor layer 25 and the second conductive semiconductor layer 35 (transparent electrode layer material film forming step).
Thereafter, for example, a pattern printing method or a coating method is used to form the metal electrode layer 29 on the first conductivity type semiconductor layer 25 via the transparent electrode layer material film 28Z, and to form the metal electrode layer 39 on the second conductivity type semiconductor layer 35 via the transparent electrode layer material film 28Z (metal electrode layer forming step).
Thereafter, the transparent electrode layer material film 28Z is patterned using the metal electrode layer 29 and the metal electrode layer 39 as masks, thereby forming the first transparent electrode layer 28 and the second transparent electrode layer 38 which are separated from each other (transparent electrode layer forming step). As the etching solution for the transparent electrode layer material film 28Z, for example, hydrochloric acid or an aqueous solution of ferric chloride can be used. As described above, it is unnecessary to use a photolithography method using a mask or the like as in the prior art, and simplification and shortening of the formation of the transparent electrode layer can be achieved.
Through the above steps, the back electrode type solar cell 1 of the present embodiment shown in fig. 1 and 2 can be obtained.
As described above, according to the method for manufacturing a solar cell of the present embodiment, since the pattern-printed resist is not formed on the light-receiving surface side in the first semiconductor layer forming step (first patterning), the pattern-printed resist 90 on the back surface side is printed and fired (dried), and then the pattern-printed resist on the light-receiving surface side does not need to be printed and fired (dried), and the thermal history of the pattern-printed resist 90 on the back surface side becomes 1 time. This can reduce the thermal history of the back-side pattern printing resist 90, and can reduce the difficulty in stripping the back-side pattern printing resist 90. Therefore, the peeling residue of the pattern printing resist 90 on the back surface side can be reduced. In addition, no peeling residue of the pattern printing resist on the light receiving surface side was found.
In addition, according to the method of manufacturing a solar cell of the present embodiment, since the pattern printing resist is not formed on the light-receiving surface side in the first semiconductor layer forming step (first patterning), the temporary semiconductor layer 13Z on the light-receiving surface side formed before the first semiconductor layer forming step (first patterning) is removed. In the second semiconductor layer forming step (second patterning), the intrinsic semiconductor layer (third intrinsic semiconductor layer) 13 on the light-receiving surface side is newly formed. This can suppress damage to the intrinsic semiconductor layer 13 on the light-receiving surface side in the manufacturing process. Specifically, since there is no contact with the pattern printing resist, no contact with the resist stripping solution (alkali solution), and no contact with the cleaning solution (hydrofluoric acid), damage to the intrinsic semiconductor layer 13 on the light receiving surface side can be suppressed. As a result, the performance of the solar cell is improved.
The embodiments of the present invention have been described above, but the present invention is not limited to the above embodiments and various modifications and variations are possible. For example, in the above embodiment, the first conductive type semiconductor layer 25 is a p type semiconductor layer and the second conductive type semiconductor layer 35 is an n type semiconductor layer, but the first conductive type semiconductor layer 25 may be replaced with an n type semiconductor layer and the second conductive type semiconductor layer 35 may be replaced with a p type semiconductor layer.
In the above-described embodiment, the method of manufacturing the heterojunction solar cell 1 is illustrated as shown in fig. 2, but the features of the present invention are not limited to the heterojunction solar cell, and can be applied to various methods of manufacturing solar cells such as a homojunction solar cell.
In the above embodiment, the n-type semiconductor substrate is exemplified as the semiconductor substrate 11, but the semiconductor substrate 11 may be a p-type semiconductor substrate in which a p-type dopant (for example, boron (B) described above) is doped in a crystalline silicon material.
In the above embodiment, the solar cell having the crystalline silicon substrate was exemplified, but the present invention is not limited thereto. For example, the solar cell may also have a gallium arsenide (GaAs) substrate.
Description of the reference numerals
1. 1X … solar cell; 7 … first region; 7b, 8b … busbar portions; 7f, 8f … fingers; 8 … second region; 11. 11X … semiconductor substrate; 13. 13X … intrinsic semiconductor layer (third intrinsic semiconductor layer); 13Z … temporary semiconductor layer; 15. 15X … optical modifying layer; 23. 23X … intrinsic semiconductor layer (first intrinsic semiconductor layer); 23Z, 23ZX … intrinsic semiconductor layer material films (first intrinsic semiconductor layer material film); 25. 25X … p-type semiconductor layers (first-conductivity-type semiconductor layers); 25Z, 25ZX … p-type semiconductor layer material films (first-conductivity-type semiconductor layer material films); 27. 27X … first electrode layer; 28. 28X … first transparent electrode layer; 29. 29X … first metal electrode layer; 33. 33X … intrinsic semiconductor layer (second intrinsic semiconductor layer); 33Z, 33ZX … intrinsic semiconductor layer material films (second intrinsic semiconductor layer material film); 35. 35X … second conductive type semiconductor layers; 35Z, 35ZX … second conductive semiconductor layer material films; 37. 37X … second electrode layer; 38. 38X … second transparent electrode layer; 39. 39X … second metal electrode layer; 41. 41X … release layer; 90. 90X … pattern printing resist
Claims (4)
1. A method for manufacturing a back contact type solar cell, comprising: a semiconductor substrate; a first intrinsic semiconductor layer and a first conductivity type semiconductor layer sequentially stacked in a first region which is a part of one main surface side of the semiconductor substrate on the opposite side of the other main surface side; a second intrinsic semiconductor layer and a second conductivity type semiconductor layer sequentially stacked in a second region, the second region being another portion of the other main surface side of the semiconductor substrate; and a third intrinsic semiconductor layer laminated on the one principal surface side of the semiconductor substrate, wherein the method for manufacturing a solar cell is characterized by comprising, in order:
a first semiconductor layer material film forming step of forming a material film of the first intrinsic semiconductor layer and a material film of the first conductivity type semiconductor layer on the other main surface side of the semiconductor substrate;
a resist forming step of forming a pattern printing resist on a material film of the first conductive semiconductor layer in the first region on the other main surface side of the semiconductor substrate, the pattern printing resist not being formed on the one main surface side of the semiconductor substrate;
A first semiconductor layer forming step of removing the material film of the first intrinsic semiconductor layer and the material film of the first intrinsic semiconductor layer in the second region on the other main surface side of the semiconductor substrate by using the pattern printing resist, thereby forming the patterned first intrinsic semiconductor layer and the first conductivity type semiconductor layer in the first region on the other main surface side of the semiconductor substrate;
a resist removing step of removing the pattern printing resist; and
a third semiconductor layer forming step of forming the third intrinsic semiconductor layer on the one principal surface side of the semiconductor substrate,
a temporary semiconductor layer forming step of forming a temporary semiconductor layer on the one principal surface side of the semiconductor substrate before the resist forming step,
the temporary semiconductor layer is removed in the first semiconductor layer forming process.
2. The method for manufacturing a solar cell according to claim 1, wherein,
in the resist removing step, the pattern printing resist is peeled off using an alkali solution.
3. The method for manufacturing a solar cell according to claim 1 or 2, wherein,
The first semiconductor layer material film forming step further includes a peeling layer forming step,
the resist removing step further includes a second semiconductor layer material film forming step and a second semiconductor layer forming step,
in the peeling layer forming step, a peeling layer is formed over the material film of the first conductivity type semiconductor layer,
in the resist forming step, the pattern printing resist is formed on the release layer in the first region on the other main surface side of the semiconductor substrate,
in the first semiconductor layer forming step, the release layer, the material film of the first conductivity type semiconductor layer, and the material film of the first intrinsic semiconductor layer in the second region on the other main surface side of the semiconductor substrate are removed using the pattern printing resist, thereby forming the first intrinsic semiconductor layer, the first conductivity type semiconductor layer, and the release layer which have been patterned in the first region on the other main surface side of the semiconductor substrate,
in the second semiconductor layer material film forming step, a material film of the second intrinsic semiconductor layer and a material film of the second conductive semiconductor layer are formed on the peeling layer in the first region on the other main surface side of the semiconductor substrate and the second region on the other main surface side of the semiconductor substrate,
In the second semiconductor layer forming step, the peeling layer is removed, and the material film of the second intrinsic semiconductor layer and the material film of the second conductivity type semiconductor layer in the first region on the other main surface side of the semiconductor substrate are removed, and the patterned second intrinsic semiconductor layer and second conductivity type semiconductor layer are formed over the second region on the other main surface side of the semiconductor substrate.
4. The method for manufacturing a solar cell according to claim 3, wherein,
an electrode layer forming step of forming a first transparent electrode layer and a first metal electrode layer corresponding to the first conductive type semiconductor layer, and a second transparent electrode layer and a second metal electrode layer corresponding to the second conductive type semiconductor layer after the third semiconductor layer forming step and the second semiconductor layer forming step,
the electrode layer forming process sequentially includes:
a transparent electrode layer material film forming step of forming a transparent electrode layer material film on the first conductive semiconductor layer and the second conductive semiconductor layer so as to cross them;
A metal electrode layer forming step of forming the first metal electrode layer on the first conductive semiconductor layer through the material film of the transparent electrode layer, and forming the second metal electrode layer on the second conductive semiconductor layer through the material film of the transparent electrode layer; and
and a transparent electrode layer forming step of patterning a material film of the transparent electrode layer using the first metal electrode layer and the second metal electrode layer as masks, thereby forming the first transparent electrode layer and the second transparent electrode layer separated from each other.
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| WO2015189878A1 (en) * | 2014-06-13 | 2015-12-17 | 国立大学法人福島大学 | Solar cell and method for manufacturing same |
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