CN113632241B - Method for manufacturing solar cell - Google Patents

Method for manufacturing solar cell Download PDF

Info

Publication number
CN113632241B
CN113632241B CN202080023700.6A CN202080023700A CN113632241B CN 113632241 B CN113632241 B CN 113632241B CN 202080023700 A CN202080023700 A CN 202080023700A CN 113632241 B CN113632241 B CN 113632241B
Authority
CN
China
Prior art keywords
semiconductor layer
solar cell
layer
semiconductor substrate
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202080023700.6A
Other languages
Chinese (zh)
Other versions
CN113632241A (en
Inventor
中野邦裕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kaneka Corp
Original Assignee
Kaneka Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kaneka Corp filed Critical Kaneka Corp
Publication of CN113632241A publication Critical patent/CN113632241A/en
Application granted granted Critical
Publication of CN113632241B publication Critical patent/CN113632241B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Energy (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Photovoltaic Devices (AREA)

Abstract

The present invention relates to a method for manufacturing a solar cell. Even when the manufacturing process is simplified, degradation of the performance of the solar cell and deterioration of the appearance of the solar cell are suppressed. The method for manufacturing a solar cell is a method for manufacturing a back electrode type solar cell, and includes: a first semiconductor layer forming step of forming a patterned first conductivity type semiconductor layer and a release layer in a first region on the back surface side of the semiconductor substrate; a second semiconductor layer material film forming step of forming a material film of a second conductivity type semiconductor layer on the release layer of the first region and the second region on the back surface side of the semiconductor substrate; and a second semiconductor layer forming step of removing the peeling layer to thereby form a patterned second conductivity type semiconductor layer in the second region. In the second semiconductor layer forming step, the back surface side of the semiconductor substrate is brought into contact with the etching solution while being opposed to the liquid surface of the etching solution, and the semiconductor substrate is transported over the liquid surface of the etching solution.

Description

Method for manufacturing solar cell
Technical Field
The present invention relates to a method for manufacturing a back electrode type (back contact type) solar cell.
Background
As a solar cell using a semiconductor substrate, there are a two-sided electrode type solar cell in which electrodes are formed on both sides of a light receiving surface side and a back surface side, and a back surface electrode type solar cell in which electrodes are formed only on the back surface side. In a two-sided electrode type solar cell, since an electrode is formed on the light receiving surface side, sunlight is blocked by the electrode. On the other hand, in the back electrode type solar cell, since no electrode is formed on the light receiving surface side, the light receiving efficiency of sunlight is higher than that of the both-surface electrode type solar cell. Patent document 1 discloses a back electrode type solar cell.
The solar cell described in patent document 1 includes: a semiconductor substrate functioning as a photoelectric conversion layer, a first conductivity type semiconductor layer and a first electrode layer which are sequentially stacked on a part of a back surface side of the semiconductor substrate, and a second conductivity type semiconductor layer and a second electrode layer which are sequentially stacked on another part of the back surface side of the semiconductor substrate.
Patent document 1: japanese patent application laid-open No. 2014-75526
In general, etching methods using photolithography are used for the first conductive type semiconductor layer patterning (first patterning) and the second conductive type semiconductor layer patterning (second patterning). However, in the etching method using the photolithography technique, for example, a process of coating a photoresist by a spin coating method, drying the photoresist, exposing the photoresist, developing the photoresist, etching a semiconductor layer using the photoresist as a mask, and stripping the photoresist is required, and the process is complicated.
In this regard, patent document 1 describes a technique of simplifying a process of patterning by using a lift-off method using a lift-off layer (sacrificial layer) in the second patterning. In the peeling method, the peeled removed material is attached again to the light receiving surface of the solar cell. If the removed product after peeling is attached again to the light receiving surface of the solar cell, the performance of the solar cell is reduced and the appearance is impaired.
Disclosure of Invention
The invention aims to provide a method for manufacturing a solar cell, which can inhibit performance degradation of the solar cell and appearance damage of the solar cell even if manufacturing process is simplified.
The method for manufacturing a back electrode type solar cell includes a semiconductor substrate, a first conductive semiconductor layer and a first electrode layer sequentially stacked in a first region which is a part of the other main surface side of the semiconductor substrate opposite to the one main surface side, and a second conductive semiconductor layer and a second electrode layer sequentially stacked in a second region which is another part of the other main surface side of the semiconductor substrate, the method comprising the steps of: a first semiconductor layer material film forming step of forming a material film of the first conductivity type semiconductor layer on the other main surface side of the semiconductor substrate; a peeling layer forming step of forming a peeling layer on the material film of the first conductive semiconductor layer; a first semiconductor layer forming step of removing the material film of the release layer and the first conductivity type semiconductor layer in the second region, thereby forming the patterned first conductivity type semiconductor layer and release layer in the first region; a second semiconductor layer material film forming step of forming a material film of the second conductivity type semiconductor layer on the peeling layer in the first region and the second region; and a second semiconductor layer forming step of removing the release layer, thereby removing the material film of the second conductivity type semiconductor layer in the first region, forming the patterned second conductivity type semiconductor layer in the second region, and in the second semiconductor layer forming step, bringing the other main surface side of the semiconductor substrate into contact with the etching solution while facing the surface of the etching solution, and conveying the semiconductor substrate on the surface of the etching solution.
According to the present invention, even if the manufacturing process of the solar cell is simplified, the degradation of the performance of the solar cell and the deterioration of the external appearance of the solar cell can be suppressed.
Drawings
Fig. 1 is a view of the solar cell of the present embodiment as seen from the back side.
Fig. 2 is a cross-sectional view of the solar cell of fig. 1 taken along line II-II.
Fig. 3A is a diagram showing a first semiconductor layer material film forming step and a peeling layer forming step in the method for manufacturing a solar cell according to the present embodiment.
Fig. 3B is a diagram showing a first semiconductor layer forming step in the method for manufacturing a solar cell according to the present embodiment.
Fig. 3C is a diagram showing a first semiconductor layer forming step in the method for manufacturing a solar cell according to the present embodiment.
Fig. 3D is a diagram showing a first semiconductor layer forming step in the method for manufacturing a solar cell according to the present embodiment.
Fig. 3E is a diagram showing a second semiconductor layer material film forming process in the method for manufacturing a solar cell according to the present embodiment.
Fig. 3F is a diagram showing a second semiconductor layer forming step in the method for manufacturing a solar cell according to the present embodiment.
Fig. 4 is a diagram for explaining an etching process of the second semiconductor layer forming process shown in fig. 3F.
Fig. 5A is a diagram for explaining an etching process of the second semiconductor layer forming process shown in fig. 3F.
Fig. 5B is a diagram for explaining an etching process of the second semiconductor layer forming process shown in fig. 3F.
Fig. 6 is a diagram for explaining an etching process of the second semiconductor layer forming process shown in fig. 3F.
Detailed Description
An example of an embodiment of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same or corresponding portions are denoted by the same reference numerals. In addition, shading, component reference numerals, and the like are sometimes omitted for convenience, and in this case, reference is made to other drawings.
(solar cell)
Fig. 1 is a view of the solar cell of the present embodiment as seen from the back side. The solar cell 1 shown in fig. 1 is a back electrode type solar cell. The solar cell 1 includes a semiconductor substrate 11 having two main surfaces, and the semiconductor substrate 11 has a first region 7 and a second region 8 on the main surfaces.
The first region 7 has a so-called comb shape, and includes a plurality of finger portions 7f corresponding to the comb teeth and a bus portion 7b corresponding to the support portion of the comb teeth. The bus bar portion 7b extends along one edge portion of the semiconductor substrate 11 in a first direction (X direction), and the finger portion 7f extends from the bus bar portion 7b in a second direction (Y direction) intersecting the first direction (X direction).
Similarly, the second region 8 has a so-called comb shape, and includes a plurality of finger portions 8f corresponding to the comb teeth and a bus bar portion 8b corresponding to the support portion of the comb teeth. The bus bar portion 8b extends in the first direction (X direction) along one side portion of the semiconductor substrate 11, and the finger portion 8f extends in the second direction (Y direction) from the bus bar portion 8b.
The finger portions 7f and the finger portions 8f are alternately arranged in the first direction (X direction).
The first region 7 and the second region 8 may be formed in a stripe shape.
Fig. 2 is a cross-sectional view of the solar cell of fig. 1 taken along line II-II. As shown in fig. 2, the solar cell 1 includes: the semiconductor substrate 11, the intrinsic semiconductor layer 13 and the optical adjustment layer 15 are laminated in this order on the light receiving surface side, which is one of the main surfaces of the semiconductor substrate 11. The solar cell 1 further includes: a first intrinsic semiconductor layer 23, a first conductivity type semiconductor layer 25, and a first electrode layer 27 are sequentially stacked on a part (first region 7) of the back surface side, which is the other main surface opposite to the light receiving surface, of the main surface of the semiconductor substrate 11. The solar cell 1 further includes: a second intrinsic semiconductor layer 33, a second conductivity type semiconductor layer 35, and a second electrode layer 37 are sequentially stacked on the other portion (second region 8) of the back surface side of the semiconductor substrate 11.
The semiconductor substrate 11 is formed of a crystalline silicon material such as single crystal silicon or polycrystalline silicon. The semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which an n-type dopant is doped in a crystalline silicon material. Examples of the n-type dopant include phosphorus (P).
The semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light receiving surface side and generates photocarriers (electrons and holes).
By using crystalline silicon as a material of the semiconductor substrate 11, a relatively high output (stable output irrespective of illuminance) can be obtained even when the dark current is relatively small and the intensity of incident light is low.
The intrinsic semiconductor layer 13 is formed on the light receiving surface side of the semiconductor substrate 11. The first intrinsic semiconductor layer 23 is formed in the first region 7 on the back surface side of the semiconductor substrate 11. The second intrinsic semiconductor layer 33 is formed in the second region 8 on the back surface side of the semiconductor substrate 11. The intrinsic semiconductor layer 13, the first intrinsic semiconductor layer 23, and the second intrinsic semiconductor layer 33 are formed of, for example, a material containing intrinsic (i-type) amorphous silicon as a main component.
The intrinsic semiconductor layer 13, the first intrinsic semiconductor layer 23, and the second intrinsic semiconductor layer 33 function as so-called passivation layers, suppress recombination of carriers generated by the semiconductor substrate 11, and improve the recovery efficiency of carriers.
The optical adjustment layer 15 is formed on the intrinsic semiconductor layer 13 on the light receiving surface side of the semiconductor substrate 11. The optical adjustment layer 15 functions as an anti-reflection layer that prevents reflection of incident light, and also functions as a protective layer that protects the light-receiving surface side of the semiconductor substrate 11 and the intrinsic semiconductor layer 13. The optical adjustment layer 15 is formed of an insulator material such as a composite of silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON), for example.
The first conductivity type semiconductor layer 25 is formed on the first intrinsic semiconductor layer 23, i.e., the first region 7 on the back surface side of the semiconductor substrate 11. That is, the first conductivity type semiconductor layer 25 has a so-called comb shape, and includes a plurality of finger portions corresponding to the comb teeth and a bus bar portion corresponding to the support portion of the comb teeth and connected to one end of the plurality of finger portions. The bus bar portion corresponds to the bus bar portion 7b of the first region 7, and extends in the Y direction along the side portion on one end side in the X direction of the semiconductor substrate 11. The finger portion corresponds to the finger portion 7f of the first region 7, and extends from the bus bar portion in the X direction.
The second conductivity type semiconductor layer 35 is formed on the second intrinsic semiconductor layer 33, i.e., the second region 8 on the back surface side of the semiconductor substrate 11. That is, the second conductive semiconductor layer 35 has a so-called comb shape, and includes a plurality of finger portions corresponding to the comb teeth and a bus bar portion corresponding to the support portion of the comb teeth and connected to one end of the plurality of finger portions. The bus bar portion corresponds to the bus bar portion 8b of the second region 8, and extends in the Y direction along the side portion on the other end side in the X direction of the semiconductor substrate 11. The finger portion corresponds to the finger portion 8f of the second region 8, and extends from the bus bar portion in the X direction.
The first conductivity type semiconductor layer 25 is formed of, for example, an amorphous silicon material. The first conductivity type semiconductor layer 25 is, for example, a p-type semiconductor layer doped with a p-type dopant in an amorphous silicon material. Examples of the p-type dopant include boron (B).
The second conductivity type semiconductor layer 35 is formed of, for example, an amorphous silicon material. The second conductivity type semiconductor layer 35 is, for example, an n-type semiconductor layer in which an amorphous silicon material is doped with an n-type dopant (for example, phosphorus (P) described above).
The first conductivity type semiconductor layer 25 may be an n-type semiconductor layer, and the second conductivity type semiconductor layer 35 may be a p-type semiconductor layer.
The semiconductor substrate 11 may be a p-type semiconductor substrate in which a p-type dopant (e.g., boron (B) described above) is doped in a crystalline silicon material.
The first electrode layer 27 is formed on the first conductivity type semiconductor layer 25, i.e., the first region 7 on the back surface side of the semiconductor substrate 11. The second electrode layer 37 is formed on the second conductive semiconductor layer 35, that is, the second region 8 on the back surface side of the semiconductor substrate 11.
The first electrode layer 27 and the second electrode layer 37 may include a transparent electrode layer and a metal electrode layer, or may include only a metal electrode layer. In the present embodiment, the first electrode layer 27 has a transparent electrode layer 28 and a metal electrode layer 29 sequentially stacked on the first conductivity type semiconductor layer 25. The second electrode layer 37 has a transparent electrode layer 38 and a metal electrode layer 39 sequentially stacked on the second conductivity type semiconductor layer 35.
The transparent electrode layer 28 and the metal electrode layer 29 have a so-called comb-like shape, and include a plurality of finger portions corresponding to the comb teeth and a bus bar portion corresponding to the support portion of the comb teeth and connected to one end of the plurality of finger portions. The bus bar portion corresponds to the bus bar portion 7b of the first region 7, and extends in the Y direction along the side portion on one end side in the X direction of the semiconductor substrate 11. The finger portion corresponds to the finger portion 7f of the first region 7, and extends from the bus bar portion in the X direction.
The transparent electrode layer 38 and the metal electrode layer 39 have a so-called comb-like shape, and include a plurality of finger portions corresponding to the comb teeth and a bus bar portion corresponding to the support portion of the comb teeth and connected to one end of the plurality of finger portions. The bus bar portion corresponds to the bus bar portion 8b of the second region 8, and extends in the Y direction along the side portion on the other end side in the X direction of the semiconductor substrate 11. The finger portion corresponds to the finger portion 8f of the second region 8, and extends from the bus bar portion in the X direction.
The transparent electrode layers 28, 38 are formed of a transparent conductive material. Examples of the transparent conductive material include ITO (Indium Tin Oxide: composite Oxide of Indium Oxide and Tin Oxide) and ZnO (Zinc Oxide: zinc Oxide).
The metal electrode layers 29, 39 are formed of a metal material. As the metal material, cu, ag, al, or an alloy thereof can be used, for example. The metal electrode layers 29 and 39 may be formed of, for example, a conductive paste material containing a metal powder such as silver.
(method for manufacturing solar cell)
Next, a method for manufacturing the solar cell 1 according to the present embodiment shown in fig. 1 and 2 will be described with reference to fig. 3A to 3F. Fig. 3A is a diagram showing an intrinsic semiconductor layer forming step, an optical adjustment layer forming step, a first semiconductor layer material film forming step, and a release layer forming step in the method for manufacturing a solar cell according to the present embodiment, and fig. 3B to 3D are diagrams showing the first semiconductor layer forming step in the method for manufacturing a solar cell according to the present embodiment. Fig. 3E is a diagram showing a second semiconductor layer material film forming process in the method for manufacturing a solar cell according to the present embodiment, and fig. 3F is a diagram showing a second semiconductor layer forming process in the method for manufacturing a solar cell according to the present embodiment.
First, as shown in fig. 3A, an intrinsic semiconductor layer 13 is laminated (formed) on the entire surface of the semiconductor substrate 11 on the light-receiving surface side by, for example, CVD (chemical vapor deposition) method (intrinsic semiconductor layer forming step). Next, for example, an optical adjustment layer 15 is laminated (formed) on the entire surface of the intrinsic semiconductor layer 13 on the light receiving surface side of the semiconductor substrate 11 by CVD (optical adjustment layer forming step).
Further, for example, a CVD method is used to sequentially laminate (film) the first intrinsic semiconductor layer material film 23Z and the first conductivity type semiconductor layer material film 25Z on the back surface side of the semiconductor substrate 11 (first semiconductor layer material film forming step).
Next, for example, a CVD method is used to laminate (film) a release layer (sacrificial layer) 40 on the entire surface of the back surface side of the semiconductor substrate 11, specifically, on the entire surface of the first conductive semiconductor layer material film 25Z (release layer forming step).
The release layer 40 is formed of a material such as a composite of silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON).
Next, as shown in fig. 3B to 3D, the first intrinsic semiconductor layer material film 23Z, the first conductivity type semiconductor layer material film 25Z, and the peeling layer 40 of the second region 8 are removed on the back surface side of the semiconductor substrate 11 using, for example, a resist 90, whereby the patterned first intrinsic semiconductor layer 23, first conductivity type semiconductor layer 25, and peeling layer 40 are formed in the first region 7 (first semiconductor layer forming step).
Specifically, the photoresist is applied to the entire surface of the semiconductor substrate 11 on both sides by photolithography, and then the photoresist in the second region 8 on the back side is exposed to light and developed by using a mask. Thus, as shown in fig. 3B, a resist 90 is formed so as to cover the entire surface of the first region 7 on the back surface side and the light receiving surface side of the semiconductor substrate 11.
Then, as shown in fig. 3C, the lift-off layer 40, the first conductive semiconductor layer material film 25Z, and the first intrinsic semiconductor layer material film 23Z of the second region 8 are etched with the resist 90 as a mask, whereby the patterned first intrinsic semiconductor layer 23, first conductive semiconductor layer 25, and lift-off layer 40 are formed in the first region 7. As the etching solution for the peeling layer 40, the first conductive semiconductor layer material film 25Z, and the first intrinsic semiconductor layer material film 13Z, for example, an acidic solution such as a mixed solution of hydrofluoric acid and nitric acid is used.
Then, as shown in fig. 3D, the resist 90 is removed. As the stripping solution for the resist 90, for example, an organic solvent such as acetone is used in accordance with the type of resist.
Next, as shown in fig. 3E, a second intrinsic semiconductor layer material film 33Z and a second conductive semiconductor layer material film 35Z are sequentially stacked (formed) on the entire surface of the back surface side of the semiconductor substrate 11 using, for example, a CVD method (second semiconductor layer material film forming step).
Next, as shown in fig. 3F, the second intrinsic semiconductor layer material film 33Z and the second conductivity type semiconductor layer material film 35Z of the first region 7 are removed on the back surface side of the semiconductor substrate 11 by a lift-off method using a lift-off layer (sacrificial layer), whereby the patterned second intrinsic semiconductor layer 33 and second conductivity type semiconductor layer 35 are formed in the second region 8 (second semiconductor layer forming step).
Specifically, the lift-off layer 40 is removed, and thereby the second intrinsic semiconductor layer material film 33Z and the second conductivity type semiconductor layer material film 35Z on the lift-off layer 40 are removed, and the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 are formed in the second region 8. The release layer 40 is formed of an acidic solution such as hydrofluoric acid or hydrochloric acid, for example.
Next, the first electrode layer 27 and the second electrode layer 37 are formed on the back surface side of the semiconductor substrate 11 (electrode layer forming step).
Specifically, for example, a PVD method (physical vapor deposition method) such as sputtering is used to laminate (film) a transparent electrode layer material film on the entire surface of the back surface side of the semiconductor substrate 11. Then, a portion of the transparent electrode layer material film is removed, for example, by etching using an etching paste, thereby forming patterned transparent electrode layers 28, 38. As the etching solution for the transparent electrode layer material film, for example, hydrochloric acid or an aqueous solution of ferric chloride is used.
Then, for example, a pattern printing method or a coating method is used to form the metal electrode layer 29 on the transparent electrode layer 28 and the metal electrode layer 39 on the transparent electrode layer 38, thereby forming the first electrode layer 27 and the second electrode layer 37.
Through the above steps, the back electrode type solar cell 1 of the present embodiment shown in fig. 1 and 2 is completed.
As described above, according to the method for manufacturing a solar cell of the present embodiment, since the patterning of the second conductive semiconductor layer 35 is performed by the lift-off method using the lift-off layer (sacrificial layer) in the second semiconductor layer forming step, simplification, shortening, and cost reduction of the manufacturing process of the solar cell are possible.
Here, the peeling method has a problem that the peeled removed material is attached again to the light receiving surface and the back surface of the solar cell. If the removed product after peeling is attached again to the light receiving surface and the back surface of the solar cell, the performance of the solar cell is lowered or the appearance is impaired.
In this regard, in the present embodiment, the second semiconductor layer forming step includes an etching step and a rinsing step described below.
In the etching step, as shown in fig. 4, the back surface side of the semiconductor substrate 11 is brought into contact with the etching solution while facing the liquid surface of the etching solution, and the semiconductor substrate 11 is transported over the liquid surface of the etching solution. For example, a tube is disposed near the liquid surface of the etching solution, and the semiconductor substrate 11 is transported by rotating the tube. Thus, the semiconductor substrate 11 is transported by friction with the tube while floating in the etching solution (fig. 5A) or contacting the tube (fig. 5B). As described above, for example, an acidic solution such as hydrofluoric acid or hydrochloric acid is used as the etching solution.
In the rinsing step, the surface of the semiconductor substrate 11 is rinsed with a rinsing solution. As the rinse solution, water (H) 2 O) is a solution of the main component.
In this way, in the etching step, only one surface of the back surface side of the semiconductor substrate 11 is in contact with the etching solution, and the light receiving surface of the semiconductor substrate is not in contact with the etching solution, so that unnecessary exposure of the light receiving surface of the semiconductor substrate 11 to the etching solution can be avoided, and reattachment of the removed product after peeling to the light receiving surface of the semiconductor substrate can be avoided. Therefore, the removed product after peeling is attached again to the light-receiving surface of the semiconductor substrate, and the external appearance of the solar cell can be prevented from being impaired.
In this way, even if the process of manufacturing the solar cell is simplified by the lift-off method, degradation of the performance of the solar cell and deterioration of the appearance of the solar cell can be suppressed.
In the etching step, the semiconductor substrate 11 is preferably conveyed so that the longitudinal direction (Y direction in fig. 1) of the comb-shaped finger portions (patterns) of the first conductivity type semiconductor layer 25 is along the conveyance direction. By allowing the flow of the liquid to flow along the longitudinal direction due to overflow or conveyance, the etching liquid can be easily and uniformly permeated, and the stripping can be easily performed by the force from the flow of the liquid.
In the etching step, as shown in fig. 6, the etching solution may be overflowed. In the example of fig. 6, an inner tank filled with an etching solution and an outer tank receiving the overflow etching solution from the inner tank are provided. The overflowed etching solution returns to the central part of the inner tank, and is fed from the bottom to the top in the inner tank. Thus, the etching solution has a liquid flow. In the example of fig. 6, the etching solution has two streams that are directed away from each other from the center portion of the inner tank.
At this time, the flow direction of the etching solution is set to be along the transport direction of the semiconductor substrate 11. Thereby, the etching solution has two liquid flows facing away from each other in a direction along the conveying direction.
Thereby, the semiconductor substrate 11 is easily brought into contact with a new etching solution. As a result, the peeled removed material can be prevented from adhering to the back surface of the semiconductor substrate 11 again, and the performance of the solar cell can be prevented from being degraded due to the peeled removed material adhering to the back surface of the semiconductor substrate again.
In addition, a liquid-state adjusting agent for adjusting the liquid state may be added to at least one of the etching solution and the rinse solution. The liquid conditioner may also contain at least one surfactant. This makes it possible to disperse the peeled removed material in the solution, and to prevent the peeled removed material from adhering to the back surface of the semiconductor substrate 11 again. Therefore, the deterioration of the performance of the solar cell due to reattachment of the peeled removed material to the back surface of the semiconductor substrate can be suppressed.
The liquid-repellent agent may be contained in an etching solution or a rinse solution, and at least one of the removed release layer and the material film of the second conductive semiconductor layer may be coagulated. For example, in a rinse solution, if the specific gravity of the coagulated condensate is greater than that of water, the condensate precipitates. This can coagulate the peeled removed material, and can prevent the peeled removed material from adhering again to the back surface of the semiconductor substrate 11. Therefore, the deterioration of the performance of the solar cell due to reattachment of the peeled removed material to the back surface of the semiconductor substrate can be suppressed.
Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various changes and modifications are possible. For example, in the above-described embodiment, as shown in fig. 2, although the method of manufacturing the heterojunction-type solar cell 1 is illustrated, the features of the present invention are not limited to the heterojunction-type solar cell, and can be applied to various methods of manufacturing solar cells such as a homojunction-type solar cell.
In the above embodiment, the solar cell having the crystalline silicon substrate is exemplified, but the present invention is not limited thereto. For example, the solar cell may also have a gallium arsenide (GaAs) substrate.
Description of the reference numerals
1 … solar cell
7 … first region
7b, 8b … busbar portion
7f, 8f … fingers
8 … second region
11 … semiconductor substrate
13 … intrinsic semiconductor layer
15 … optical modifier layer
23 … first intrinsic semiconductor layer
23Z … first intrinsic semiconductor layer Material film
25 … first conductivity type semiconductor layer
25Z … first conductive semiconductor layer material film
27 … first electrode layer
28. 38 … transparent electrode layer
29. 39 … Metal electrode layer
33 … second intrinsic semiconductor layer
33Z … second intrinsic semiconductor layer Material film
35 … second conductivity type semiconductor layer
35Z … second conductive semiconductor layer material film
37 … second electrode layer
40 … release layer (sacrificial layer)
90 … mask.

Claims (7)

1. A method for manufacturing a back electrode type solar cell including a semiconductor substrate, a first conductive semiconductor layer and a first electrode layer sequentially stacked in a first region which is a part of the other main surface side of the semiconductor substrate opposite to the one main surface side, and a second conductive semiconductor layer and a second electrode layer sequentially stacked in a second region which is another part of the other main surface side of the semiconductor substrate, the method comprising the steps of:
a first semiconductor layer material film forming step of forming a material film of the first conductivity type semiconductor layer on the other main surface side of the semiconductor substrate;
a peeling layer forming step of forming a peeling layer on the material film of the first conductive semiconductor layer;
a first semiconductor layer forming step of removing the material film of the release layer and the first conductivity type semiconductor layer in the second region, thereby forming the patterned first conductivity type semiconductor layer and release layer in the first region;
a second semiconductor layer material film forming step of forming a material film of the second conductivity type semiconductor layer on the peeling layer in the first region and the second region; and
a second semiconductor layer forming step of removing the peeling layer to remove the material film of the second conductivity type semiconductor layer in the first region, forming the second conductivity type semiconductor layer patterned in the second region,
in the second semiconductor layer forming step, the semiconductor substrate is transported on the liquid surface of the etching solution by bringing the other main surface side of the semiconductor substrate into contact with the etching solution while facing the liquid surface of the etching solution,
the patterned first conductive semiconductor layer comprises comb-shaped patterns,
in the second semiconductor layer forming step, the semiconductor substrate is transported in a transport direction along a longitudinal direction of the comb-shaped pattern.
2. The method for manufacturing a solar cell according to claim 1, wherein,
the etching solution has a liquid flow and,
the flow direction of the etching solution is along the transport direction.
3. The method for manufacturing a solar cell according to claim 2, wherein,
the etching solution has two liquid flows facing away from each other in a direction along the conveying direction.
4. The method for manufacturing a solar cell according to any one of claim 1 to 3, wherein,
the second semiconductor layer forming step includes:
an etching step of transporting the semiconductor substrate over a surface of the etching solution; and
a rinsing step of rinsing the surface of the semiconductor substrate with a rinsing solution,
the above-mentioned rinse solution contains water as a main component,
at least one of the etching solution and the rinse solution is added with a liquid-state adjusting agent for adjusting liquid-state.
5. The method for manufacturing a solar cell according to claim 4, wherein,
the liquid conditioner contains at least one surfactant.
6. The method for manufacturing a solar cell according to claim 4, wherein,
at least one of the peeled layer after removal and the material film of the second conductive semiconductor layer is coagulated in the etching solution or the rinse solution to which the liquid-state adjusting agent is added.
7. The method for manufacturing a solar cell according to claim 4, wherein,
the specific gravity of the coagulated condensate is greater than that of water.
CN202080023700.6A 2019-03-28 2020-02-17 Method for manufacturing solar cell Active CN113632241B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2019-062652 2019-03-28
JP2019062652 2019-03-28
PCT/JP2020/006029 WO2020195324A1 (en) 2019-03-28 2020-02-17 Solar cell manufacturing method

Publications (2)

Publication Number Publication Date
CN113632241A CN113632241A (en) 2021-11-09
CN113632241B true CN113632241B (en) 2024-03-15

Family

ID=72608804

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202080023700.6A Active CN113632241B (en) 2019-03-28 2020-02-17 Method for manufacturing solar cell

Country Status (3)

Country Link
JP (1) JP7190555B2 (en)
CN (1) CN113632241B (en)
WO (1) WO2020195324A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014075526A (en) * 2012-10-05 2014-04-24 Sharp Corp Photoelectric conversion element and photoelectric conversion element manufacturing method
CN104037257A (en) * 2013-03-08 2014-09-10 北京北方微电子基地设备工艺研究中心有限责任公司 Solar energy battery and manufacture method thereof, and single-surface polishing device
CN108368636A (en) * 2015-12-11 2018-08-03 奈克斯沃夫有限公司 Device and method for unilateral etching semiconductor substrate

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3695932B2 (en) * 1998-02-12 2005-09-14 三洋電機株式会社 Manufacturing method of uneven substrate
JP2006286821A (en) * 2005-03-31 2006-10-19 Sanyo Electric Co Ltd Etching method of crystal system semiconductor device
CN201473591U (en) * 2009-07-22 2010-05-19 吴东升 Etch cleaning tank
JP2011077064A (en) * 2009-09-29 2011-04-14 Dainippon Screen Mfg Co Ltd Substrate treatment apparatus
JP2012178500A (en) * 2011-02-28 2012-09-13 Mitsubishi Electric Corp Wet etching method and wet etching apparatus
CN203846108U (en) * 2014-03-26 2014-09-24 上饶光电高科技有限公司 Device for solving circular bubbling of etching groove of wet process etching machine
JP2018163999A (en) 2017-03-27 2018-10-18 国立大学法人福島大学 Solar battery and production method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014075526A (en) * 2012-10-05 2014-04-24 Sharp Corp Photoelectric conversion element and photoelectric conversion element manufacturing method
CN104037257A (en) * 2013-03-08 2014-09-10 北京北方微电子基地设备工艺研究中心有限责任公司 Solar energy battery and manufacture method thereof, and single-surface polishing device
CN108368636A (en) * 2015-12-11 2018-08-03 奈克斯沃夫有限公司 Device and method for unilateral etching semiconductor substrate

Also Published As

Publication number Publication date
WO2020195324A1 (en) 2020-10-01
CN113632241A (en) 2021-11-09
JPWO2020195324A1 (en) 2020-10-01
JP7190555B2 (en) 2022-12-15

Similar Documents

Publication Publication Date Title
JP7356445B2 (en) Method of manufacturing solar cells, solar cells, and solar cell modules
CN113632241B (en) Method for manufacturing solar cell
WO2020149128A1 (en) Method for producing solar cells
US20220140162A1 (en) Solar cell and method for manufacturing solar cell
JP7458834B2 (en) Solar cells and solar cell manufacturing methods
JP7436299B2 (en) How to manufacture solar cells
JP7274899B2 (en) Solar cell manufacturing method
JP7202456B2 (en) SOLAR CELL AND SOLAR CELL MANUFACTURING METHOD
JP2014183073A (en) Photoelectric conversion element and method of manufacturing photoelectric conversion element
JP7146786B2 (en) Solar cell manufacturing method, solar cell and solar cell module
JP2013168605A (en) Manufacturing method of solar cell
JP7241173B2 (en) Element manufacturing method
WO2020138185A1 (en) Solar cell manufacturing method
CN114830357B (en) Method for manufacturing solar cell
JP7459059B2 (en) Method for manufacturing solar cell and solar cell
CN113632245B (en) Method for manufacturing solar cell
JP7169440B2 (en) SOLAR CELL MANUFACTURING METHOD AND SOLAR CELL
US20240021742A1 (en) Solar cell and method for manufacturing solar cell
WO2020195570A1 (en) Method for producing solar cell and in-process product of solar cell
CN114649442A (en) Method for manufacturing solar cell
JP5957102B2 (en) Manufacturing method of solar cell
JP2023111632A (en) Method for manufacturing solar cell and solar cell
JP2022103965A (en) Manufacturing method of solar cell and solar cell

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant