WO2020195570A1 - Method for producing solar cell and in-process product of solar cell - Google Patents

Method for producing solar cell and in-process product of solar cell Download PDF

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Publication number
WO2020195570A1
WO2020195570A1 PCT/JP2020/008626 JP2020008626W WO2020195570A1 WO 2020195570 A1 WO2020195570 A1 WO 2020195570A1 JP 2020008626 W JP2020008626 W JP 2020008626W WO 2020195570 A1 WO2020195570 A1 WO 2020195570A1
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Prior art keywords
solar cell
layer
resist pattern
resist
semiconductor substrate
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PCT/JP2020/008626
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French (fr)
Japanese (ja)
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邦裕 中野
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株式会社カネカ
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Priority to JP2021508878A priority Critical patent/JP7190556B2/en
Publication of WO2020195570A1 publication Critical patent/WO2020195570A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a method for manufacturing a solar cell and a work-in-process of a solar cell.
  • the solar cell includes a semiconductor substrate that functions as a photoelectric conversion layer, a semiconductor layer laminated on the main surface of the semiconductor substrate, a transparent conductive Oxide (TCO), and a metal electrode layer.
  • TCO transparent conductive Oxide
  • a metal electrode layer Generally, in patterning of these semiconductor layers, transparent electrode layers, or metal electrode layers, an etching method using, for example, a photolithography technique (photoresist) is used (see, for example, Patent Document 1).
  • the etching solution may accumulate in the vicinity of the resist. As a result, the etching becomes non-uniform, and the performance of the solar cell may deteriorate.
  • An object of the present invention is to provide a method for manufacturing a solar cell and a work-in-process of the solar cell, which suppresses deterioration of the performance of the solar cell due to a patterning process using an etching method.
  • the method for manufacturing a solar cell according to the present invention is a method for manufacturing a solar cell having a patterned layer on at least one main surface side of a semiconductor substrate, and serves as a base of the patterned layer on the main surface side of the semiconductor substrate.
  • a non-patterned layer forming step of forming a non-patterned layer before patterning a resist pattern forming step of forming a resist pattern which is a patterned resist film on the non-patterned layer, and an etching method.
  • a resist is used so as to separate by a predetermined interval by using a screen printing method.
  • the agent is printed, and the predetermined interval means that the separated resist agents are linked to each other to form a resist pattern due to the fluidity of the resist agent, and the thickness of the connecting portion in which the separated resist agents are connected in the resist pattern is linked. It is an interval that is thinner than the thickness other than the part.
  • the solar cell device is a solar cell device for forming a patterned layer on at least one main surface side of a semiconductor substrate, and is a pattern formed on the main surface side of the semiconductor substrate. It includes a non-patterned layer that is the basis of the chemical layer and a resist pattern that is a patterned resist film formed on the non-patterned layer, and the resist pattern is thicker than other parts. Has a thin groove portion.
  • the present invention it is possible to suppress the deterioration of the performance of the solar cell due to the patterning process using the etching method.
  • FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG. It is a figure which shows the passivation layer forming process and the optical adjustment layer forming process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the 1st semiconductor layer material film formation process (non-patterning layer formation process) in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the resist pattern forming process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the 1st semiconductor layer formation process (patterned layer formation process) in the manufacturing method of the solar cell which concerns on this embodiment.
  • FIG. 3C is a back view of the IV portion of the work-in-process of the solar cell in the resist pattern forming step shown in FIG. 3C, and a sectional view taken along line IVA-IVA (immediately after pattern printing).
  • 3C is a back view of the IV portion of the work-in-process of the solar cell in the resist pattern forming step shown in FIG. 3C, and a sectional view taken along line IVB-IVB (after a predetermined time has elapsed). It is the back view and VV line sectional view corresponding to the IV part of the work-in-process of the solar cell in the conventional resist pattern forming process.
  • FIG. 1 is a view of the solar cell according to the present embodiment as viewed from the back surface side.
  • the solar cell 1 shown in FIG. 1 is a back electrode type (back contact type) solar cell.
  • the solar cell 1 includes a semiconductor substrate 11 having two main surfaces, and has a first region 7 and a second region 8 on one main surface of the semiconductor substrate 11.
  • the first region 7 has a so-called comb-shaped shape, and has a plurality of finger portions 7f corresponding to the comb teeth and a bus bar portion 7b corresponding to the support portion of the comb teeth.
  • the bus bar portion 7b extends in the first direction (X direction) along one side of the semiconductor substrate 11, and the finger portion 7f intersects the bus bar portion 7b in the first direction (X direction). It extends in the direction (Y direction).
  • the second region 8 has a so-called comb-shaped shape, and has a plurality of finger portions 8f corresponding to the comb teeth and a bus bar portion 8b corresponding to the support portion of the comb teeth.
  • the bus bar portion 8b extends in the first direction (X direction) along the other side portion facing one side portion of the semiconductor substrate 11, and the finger portion 8f extends from the bus bar portion 8b in the second direction (Y). Extends in the direction).
  • the finger portions 7f and the finger portions 8f are alternately provided in the first direction (X direction).
  • FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG.
  • the solar cell 1 includes a semiconductor substrate 11, a passivation layer 13 which is sequentially laminated on a light receiving surface side which is one of the main surfaces of the semiconductor substrate 11 on the light receiving side, and optical adjustment.
  • the layer 15 is provided.
  • the passivation layers 23 and the first are sequentially laminated on a part (first region 7) of the back surface side which is the other main surface of the main surface of the semiconductor substrate 11 opposite to the light receiving surface.
  • a conductive semiconductor layer 25 and a first electrode layer 27 are provided.
  • the solar cell 1 includes a passivation layer 33, a second conductive semiconductor layer 35, and a second electrode layer 37, which are sequentially laminated on another part (second region 8) on the back surface side of the semiconductor substrate 11.
  • the semiconductor substrate 11 is formed of a crystalline silicon material such as single crystal silicon or polycrystalline silicon.
  • the semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which a crystalline silicon material is doped with an n-type dopant. Examples of the n-type dopant include phosphorus (P).
  • the semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light receiving surface side to generate optical carriers (electrons and holes).
  • the passivation layer 13 is formed on the light receiving surface side of the semiconductor substrate 11.
  • the passivation layer 23 is formed in the first region 7 on the back surface side of the semiconductor substrate 11.
  • the passivation layer 33 is formed in the second region 8 on the back surface side of the semiconductor substrate 11.
  • the passivation layers 13, 23, 33 are formed of, for example, a material containing intrinsic (i-type) amorphous silicon as a main component.
  • the passivation layers 13, 23, 33 suppress the recombination of carriers generated in the semiconductor substrate 11 and increase the carrier recovery efficiency.
  • the optical adjustment layer 15 is formed on the passivation layer 13 on the light receiving surface side of the semiconductor substrate 11.
  • the optical adjustment layer 15 functions as an antireflection layer that prevents reflection of incident light, and also functions as a protective layer that protects the light receiving surface side of the semiconductor substrate 11 and the passivation layer 13.
  • the optical adjustment layer 15 is formed of an insulating material such as a composite thereof such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON).
  • the first conductive semiconductor layer 25 is formed on the passivation layer 23, that is, in the first region 7 on the back surface side of the semiconductor substrate 11. That is, the first conductive semiconductor layer 25 has a so-called comb-shaped shape, and is a bus bar in which a plurality of finger portions corresponding to comb teeth and one end of the plurality of finger portions are connected, which corresponds to a support portion of the comb teeth. Has a part.
  • the bus bar portion corresponds to the bus bar portion 7b of the first region 7 and extends in the Y direction along the side portion on one end side of the semiconductor substrate 11 in the X direction.
  • the finger portion corresponds to the finger portion 7f of the first region 7 and extends in the X direction from the bus bar portion.
  • the second conductive semiconductor layer 35 is formed on the passivation layer 33, that is, in the second region 8 on the back surface side of the semiconductor substrate 11. That is, the second conductive semiconductor layer 35 has a so-called comb-shaped shape, and is a bus bar in which a plurality of finger portions corresponding to the comb teeth and one end of the plurality of finger portions are connected, which corresponds to the support portion of the comb teeth. Has a part.
  • the bus bar portion corresponds to the bus bar portion 8b of the second region 8 and extends in the Y direction along the side portion of the semiconductor substrate 11 on the other end side in the X direction.
  • the finger portion corresponds to the finger portion 8f of the second region 8 and extends in the X direction from the bus bar portion.
  • the first conductive semiconductor layer 25 is formed of, for example, an amorphous silicon material.
  • the first conductive semiconductor layer 25 is, for example, a p-type semiconductor layer in which an amorphous silicon material is doped with a p-type dopant.
  • Examples of the p-type dopant include boron (B).
  • the second conductive semiconductor layer 35 is formed of, for example, an amorphous silicon material.
  • the second conductive semiconductor layer 35 is, for example, an n-type semiconductor layer in which an amorphous silicon material is doped with an n-type dopant (for example, phosphorus (P) described above).
  • P phosphorus
  • the first conductive semiconductor layer 25 may be an n-type semiconductor layer
  • the second conductive semiconductor layer 35 may be a p-type semiconductor layer
  • the semiconductor substrate 11 may be a p-type semiconductor substrate in which a crystalline silicon material is doped with a p-type dopant (for example, the above-mentioned boron (B)).
  • the first electrode layer 27 is formed on the first conductive semiconductor layer 25, that is, in the first region 7 on the back surface side of the semiconductor substrate 11.
  • the second electrode layer 37 is formed on the second conductive semiconductor layer 35, that is, in the second region 8 on the back surface side of the semiconductor substrate 11.
  • the first electrode layer 27 has a transparent electrode layer 28 and a metal electrode layer 29, which are sequentially laminated on the first conductive semiconductor layer 25.
  • the second electrode layer 37 has a transparent electrode layer 38 and a metal electrode layer 39 that are sequentially laminated on the second conductive semiconductor layer 35.
  • the transparent electrode layer 28 and the metal electrode layer 29 have a so-called comb shape, and are a bus bar having a plurality of finger portions corresponding to comb teeth and a support portion of the comb teeth to which one ends of the plurality of finger portions are connected.
  • the bus bar portion corresponds to the bus bar portion 7b of the first region 7 and extends in the Y direction along the side portion on one end side of the semiconductor substrate 11 in the X direction.
  • the finger portion corresponds to the finger portion 7f of the first region 7 and extends in the X direction from the bus bar portion.
  • the transparent electrode layer 38 and the metal electrode layer 39 have a so-called comb shape, and are a bus bar having a plurality of finger portions corresponding to comb teeth and a support portion of the comb teeth to which one ends of the plurality of finger portions are connected.
  • the bus bar portion corresponds to the bus bar portion 8b of the second region 8 and extends in the Y direction along the side portion of the semiconductor substrate 11 on the other end side in the X direction.
  • the finger portion corresponds to the finger portion 8f of the second region 8 and extends in the X direction from the bus bar portion.
  • the transparent electrode layers 28 and 38 are formed of a transparent conductive material.
  • the transparent conductive material include ITO (Indium Tin Oxide: a composite oxide of indium tin oxide and tin oxide) and ZnO (Zinc Oxide: zinc oxide).
  • the metal electrode layers 28 and 38 are made of a metal material. As the metal material, for example, Cu, Ag, Al and alloys thereof are used.
  • the metal electrode layers 28 and 38 may be formed of, for example, a conductive paste material containing a metal powder such as silver.
  • FIG. 3A is a diagram showing a passivation layer forming step and an optical adjustment layer forming step in the solar cell manufacturing method according to the present embodiment
  • FIG. 3B is a diagram showing a first semiconductor layer in the solar cell manufacturing method according to the present embodiment. It is a figure which shows the material film formation process (non-patterned layer formation process).
  • FIG. 3C is a diagram showing a resist pattern forming step in the solar cell manufacturing method according to the present embodiment, and FIG.
  • FIG. 3D is a first semiconductor layer forming step (patterned layer) in the solar cell manufacturing method according to the present embodiment. It is a figure which shows the forming process).
  • FIG. 3E is a diagram showing a second semiconductor layer material film forming step (non-patterned layer forming step) in the method for manufacturing a solar cell according to the present embodiment
  • FIG. 3F is a diagram showing manufacturing of a solar cell according to the present embodiment. It is a figure which shows the resist pattern forming process in the method.
  • FIG. 3G is a diagram showing a second semiconductor layer forming step (patterned layer forming step) in the method for manufacturing a solar cell according to the present embodiment.
  • FIG. 4A is a back view of the IV portion of the work-in-process of the solar cell in the resist pattern forming step shown in FIG. 3C and a sectional view taken along line IVA-IVA (immediately after pattern printing), and FIG. 4B shows the resist pattern forming shown in FIG. 3C. It is a back view and IVB-IVB line sectional view of the IV part of the work-in-process of the solar cell in the process (after a predetermined time elapses). Further, FIG. 5 is a back view and a sectional view taken along line VV corresponding to the IV portion of the work-in-process of the solar cell in the conventional resist pattern forming step.
  • the substrate tray 3 a tray that covers the peripheral region on the side surface side of the semiconductor substrate 11 and the back surface side of the semiconductor substrate 11 is used, but the substrate tray is not limited to this, and various trays are used. You may.
  • the passivation layer 13 is laminated (film-formed) on the entire surface of the semiconductor substrate 11 on the light receiving surface side by, for example, a CVD method (chemical vapor deposition method) (passivation layer forming step). ..
  • the optical adjustment layer 15 is laminated (film-formed) on the entire surface of the passivation layer 13 on the light receiving surface side of the semiconductor substrate 11 (optical adjustment layer forming step).
  • the entire surface of the back surface side of the semiconductor substrate 11 is covered by, for example, the CVD method.
  • Passivation layer material film 23Z and first conductive semiconductor layer material film 25Z (non-patterned layer) are sequentially formed (film-formed) (first semiconductor layer material film forming step: non-patterned layer forming step).
  • a resist pattern which is a resist film patterned on the passivation layer material film 23Z and the first conductive semiconductor layer material film 25Z in the first region 7 on the back surface side of the semiconductor substrate 11.
  • a resist pattern 40X having a substantially uniform thickness was formed corresponding to the finger portion 7f and the bus bar portion 7b in the first region 7 by using a photolithography technique.
  • this conventional resist pattern 40X the following problems occur in the patterning layer forming step using the etching method described later.
  • the insertion (immersion) and removal directions of the semiconductor substrate 11 in the etching solution are the spread of the resist pattern 40X corresponding to the finger portion. Along the current direction (Y direction).
  • the etching solution collects in the blind alley, impasse A formed at the portion corresponding to the bus bar portion and the finger portion in the resist pattern 40X, and the portion of the blind alley A. Etching may proceed more than the part other than the dead end A. Therefore, the etching becomes non-uniform, and the performance of the solar cell may deteriorate.
  • the resist pattern 40 is formed by using a screen printing method. Specifically, as shown in FIG. 4A, the resist agent 40Z is printed so as to be separated by a predetermined interval using a printing plate.
  • the predetermined interval is the thickness of the connecting portion 41 in which the separated resist agents 40Z are connected to each other to form the resist pattern 40 due to the fluidity of the resist agent 40Z, and the resist agents 40Z separated in the resist pattern 40 are connected to each other.
  • the interval is thinner than the thickness other than the connecting portion 41.
  • the connecting portion (groove portion) 41 is formed in the portion of the resist pattern 40 that forms the dead end A.
  • the extending direction of the connecting portion 41 corresponds to the insertion and removal directions of the semiconductor substrate 11 with respect to the etching solution in the patterning layer forming step described later, in other words, the resist pattern 40 corresponding to the finger portion. It is formed along the extending direction (Y direction).
  • the etching solution is suppressed from accumulating in the dead end A. Therefore, the non-uniformity of etching is suppressed, and the deterioration of the performance of the solar cell is suppressed.
  • the connecting portion (groove portion) 41 only needs to be able to prevent the etching solution from accumulating in the dead end A, and the extending direction of the connecting portion 41 is relative to the insertion / removal direction (Y direction) of the semiconductor substrate 11 with respect to the etching solution. It may be formed along an angle. Further, the connecting portion (groove portion) 41 is formed not only in the portion corresponding to the bus bar portion in the resist pattern 40 forming the dead end A, but also in the portion corresponding to the finger portion in the resist pattern 40 forming the dead end A. You may.
  • the resist agent 40Z for forming the resist pattern 40 contains a material having thixotropy.
  • the viscosity of the resist agent 40Z decreases (the fluidity increases) due to the force received when passing through the printing plate for screen printing, and the resisting agents 40Z are connected at the portions separated by a predetermined interval.
  • the viscosity of the resist agent 40Z gradually increases (the fluidity decreases), and the viscosity of the resist agent 40Z returns before the surface becomes flat in the portions separated by a predetermined interval, and the thickness of the connecting portion 41 increases. It is thinner than the thickness other than the connecting portion 41, and a groove is formed in the connecting portion 41.
  • the thickness of the connecting portion 41 can be made thinner than the thickness other than the connecting portion 41, in other words, a groove can be formed in the connecting portion 41. It will be easy.
  • an example of the in-process product 1Z of the solar cell after the non-patterned layer forming step and the resist pattern forming step in the solar cell manufacturing method of the present embodiment and before the patterned layer forming step is
  • the passivation layer material film 23Z and the first conductive semiconductor layer material before patterning which are the basis of the passivation layer 23 and the first conductive semiconductor layer 25 (patterned layer), formed on the entire back surface side of the semiconductor substrate 11.
  • the resist pattern 40 has a connecting portion (groove portion) 41 that is thinner than the other portions.
  • the connecting portion (groove portion) 41 is arranged at a portion of the resist pattern 40 that forms the dead end A.
  • the passionation layer material film 23Z and the first conductive semiconductor layer material film 25Z (non-patterned layer) in the second region 8 on the back surface side of the semiconductor substrate 11 are formed by using an etching method. Remove.
  • the patterned passivation layer 23 and the first conductive semiconductor layer 25 (patterned layer) are formed in the first region 7 on the back surface side of the semiconductor substrate 11 (first semiconductor layer forming step: patterned layer). Formation process).
  • etching solution for example, an acidic solution such as a mixed solution of hydrofluoric acid and nitric acid is used. After that, a rinsing treatment is performed to peel off the resist pattern 40.
  • the passivation layer material film 33Z and the n-type semiconductor layer material film 35Z (non-patterned layer) before patterning which are the basis of the passivation layer 33 and the second conductive semiconductor layer 35 (patterned layer), are sequentially placed.
  • Forming (film formation) second semiconductor layer material film forming step: non-patterned layer forming step).
  • the passivation layer material film 23Z in the second region 8 on the back surface side of the semiconductor substrate 11 remains in the first semiconductor layer forming step, the passivation layer material film does not need to be laminated (film formation). Further, in the first semiconductor layer forming step, when a part of the passivation layer material film 23Z in the second region 8 on the back surface side of the semiconductor substrate 11 remains, the passivation layer material film is laminated (film-forming) by the amount removed. Just do it.
  • the passivation in the second region 8 on the back surface side of the semiconductor substrate 11 is performed by using the screen printing method in the same manner as the resist pattern forming step (FIGS. 3C, 4A and 4B) described above.
  • a resist pattern 40 which is a patterned resist film, is formed on the layer material film 33Z and the n-type semiconductor layer material film 35Z (resist pattern forming step).
  • the passionation layer material film 33Z and the second conductive semiconductor layer material film 35Z (non-patterned layer) in the first region 7 on the back surface side of the semiconductor substrate 11 are formed by using an etching method. Remove.
  • the patterned passivation layer 33 and the second conductive semiconductor layer 35 (patterned layer) are formed in the second region 8 on the back surface side of the semiconductor substrate 11 (second semiconductor layer forming step: patterned layer). Formation process).
  • etching solution for example, an acidic solution such as a mixed solution of hydrofluoric acid and nitric acid is used. After that, a rinsing treatment is performed to peel off the resist pattern 40.
  • the first electrode layer 27 and the second electrode layer 37 are formed on the back surface side of the semiconductor substrate 11 (electrode layer forming step).
  • a PVD method physical vapor deposition method
  • a sputtering method is used to laminate (form) a transparent electrode layer material film on the entire back surface side of the semiconductor substrate 11.
  • the transparent electrode layers 28 and 38 are patterned by removing a part of the transparent electrode layer material film by, for example, an etching method using an etching paste.
  • the etching solution for the transparent electrode layer material film for example, hydrochloric acid or an aqueous ferric chloride solution is used.
  • a metal electrode layer 29 is formed on the transparent electrode layer 28, and a metal electrode layer 39 is formed on the transparent electrode layer 38, whereby the first electrode layer 27 and The second electrode layer 37 is formed.
  • the resist agent 40Z is printed so as to be separated by a predetermined interval by using a screen printing method (FIG. 4A).
  • the predetermined interval is the thickness of the connecting portion 41 in which the separated resist agents 40Z are connected to each other to form the resist pattern 40 due to the fluidity of the resist agent 40Z, and the resist agents 40Z separated in the resist pattern 40 are connected to each other.
  • the interval is thinner than the thickness other than the connecting portion 41 (FIG. 4B).
  • a groove is formed in the connecting portion 41, for example, in the portion forming the dead end A.
  • the etching solution is suppressed from accumulating in the dead end A. Therefore, the non-uniformity of etching is suppressed, and the deterioration of the performance of the solar cell is suppressed. As a result, the decrease in the yield of the solar cell is suppressed.
  • the etching solution when the semiconductor substrate 11 is taken out from the etching solution, the etching solution is less likely to accumulate in the dead end, so that the amount of the etching solution brought into the subsequent rinsing treatment is reduced. Is reduced. Therefore, the processing time of the rinsing process can be shortened, the amount of the rinsing solution and the number of times the rinsing solution is replaced can be saved, and the cost can be reduced.
  • the present invention is not limited to the above-described embodiments, and various modifications and modifications can be made.
  • a method for manufacturing a solar cell to which the resist pattern forming step using the screen printing method, which is a feature of the present invention, is applied has been exemplified.
  • the features of the present invention are not limited to this, and can be applied to the case where the etching method is used in forming the patterned layer of the transparent electrode layer or the metal electrode layer.
  • the manufacturing method of the back electrode type solar cell is illustrated, but the feature of the present invention can also be applied to the manufacturing method of the double-sided electrode type solar cell.
  • the method for manufacturing the heterozygous solar cell 1 is illustrated as shown in FIG. 2, but the feature of the present invention is not limited to the heterozygous solar cell, but the homozygous solar cell. It can be applied to various methods for manufacturing solar cells such as batteries.
  • a solar cell having a crystalline silicon substrate has been exemplified, but the present invention is not limited to this.
  • a solar cell may have a gallium arsenide (GaAs) substrate.
  • GaAs gallium arsenide

Abstract

The present invention provides a method for producing a solar cell, which suppresses performance decrease of a solar cell caused by a patterning process that uses an etching method. A method for producing a solar cell according to the present invention comprises: a non-patterning layer formation step wherein a non-patterning layer, which serves as a base for a patterning layer, is formed on the main surface side of a semiconductor substrate; a resist pattern formation step wherein a patterned resist pattern is formed on the non-patterning layer; and a patterning layer formation step wherein a patterning layer, which is obtained by patterning the non-patterning layer based on the resist pattern, is formed with use of an etching method. In the resist pattern formation step, a resist agent is printed with use of a screen printing method, so that the printed resist agents are separated from each other at a predetermined interval; and the predetermined interval is such a distance that the separated resist agents are connected with each other due to the fluidity of the resist agents so as to form a resist pattern 40, and the thickness of a connection part 41, where the separated resist agents are connected with each other, is thinner than the thicknesses of portions other than the connection part 41 in the resist pattern 40.

Description

太陽電池の製造方法および太陽電池の仕掛品Manufacturing method of solar cells and work-in-process of solar cells
　本発明は、太陽電池の製造方法および太陽電池の仕掛品に関する。 The present invention relates to a method for manufacturing a solar cell and a work-in-process of a solar cell.
　太陽電池は、光電変換層として機能する半導体基板と、半導体基板の主面に積層された半導体層、透明電極層（Transparent Conductive Oxide：ＴＣＯ）および金属電極層とを備える。一般に、これらの半導体層、透明電極層または金属電極層のパターニングでは、例えばフォトリソグラフィ技術（フォトレジスト）を用いたエッチング法が用いられる（例えば、特許文献１参照）。 The solar cell includes a semiconductor substrate that functions as a photoelectric conversion layer, a semiconductor layer laminated on the main surface of the semiconductor substrate, a transparent conductive Oxide (TCO), and a metal electrode layer. Generally, in patterning of these semiconductor layers, transparent electrode layers, or metal electrode layers, an etching method using, for example, a photolithography technique (photoresist) is used (see, for example, Patent Document 1).
特開２０１８－１６４０５７号公報JP-A-2018-164857
　半導体層、透明電極層または金属電極層をエッチング法を用いて形成する場合、レジスト近傍にエッチング溶液が溜まることがある。その結果、エッチングが不均一となり、太陽電池の性能が低下することがある。 When the semiconductor layer, transparent electrode layer or metal electrode layer is formed by the etching method, the etching solution may accumulate in the vicinity of the resist. As a result, the etching becomes non-uniform, and the performance of the solar cell may deteriorate.
　本発明は、エッチング法を用いたパターニングプロセスに起因する太陽電池の性能低下を抑制する太陽電池の製造方法および太陽電池の仕掛品を提供することを目的とする。 An object of the present invention is to provide a method for manufacturing a solar cell and a work-in-process of the solar cell, which suppresses deterioration of the performance of the solar cell due to a patterning process using an etching method.
　本発明に係る太陽電池の製造方法は、半導体基板の少なくとも１つの主面側にパターン化層を備える太陽電池の製造方法であって、半導体基板の主面側に、パターン化層の基となるパターン化前の非パターン化層を形成する非パターン化層形成工程と、非パターン化層上に、パターン化されたレジスト膜であるレジストパターンを形成するレジストパターン形成工程と、エッチング法を用いて、レジストパターンに基づいて非パターン化層をパターン化したパターン化層を形成するパターン化層形成工程とを含み、レジストパターン形成工程では、スクリーン印刷法を用いて、所定間隔だけ分離するようにレジスト剤を印刷し、所定間隔とは、レジスト剤の流動性により、分離したレジスト剤同士が連結してレジストパターンを形成し、レジストパターンにおいて分離したレジスト剤同士が連結した連結部分の厚さが連結部分以外の厚さよりも薄くなる、間隔である。 The method for manufacturing a solar cell according to the present invention is a method for manufacturing a solar cell having a patterned layer on at least one main surface side of a semiconductor substrate, and serves as a base of the patterned layer on the main surface side of the semiconductor substrate. Using a non-patterned layer forming step of forming a non-patterned layer before patterning, a resist pattern forming step of forming a resist pattern which is a patterned resist film on the non-patterned layer, and an etching method. Including a patterning layer forming step of forming a patterned layer in which a non-patterning layer is patterned based on a resist pattern, in the resist pattern forming step, a resist is used so as to separate by a predetermined interval by using a screen printing method. The agent is printed, and the predetermined interval means that the separated resist agents are linked to each other to form a resist pattern due to the fluidity of the resist agent, and the thickness of the connecting portion in which the separated resist agents are connected in the resist pattern is linked. It is an interval that is thinner than the thickness other than the part.
　本発明に係る太陽電池の仕掛品は、半導体基板の少なくとも１つの主面側にパターン化層を形成するための太陽電池の仕掛品であって、半導体基板の主面側に形成された、パターン化層の基となるパターン化前の非パターン化層と、非パターン化層上に形成された、パターン化したレジスト膜であるレジストパターンとを備え、レジストパターンは、他の部分よりも厚さが薄い溝部分を有する。 The solar cell device according to the present invention is a solar cell device for forming a patterned layer on at least one main surface side of a semiconductor substrate, and is a pattern formed on the main surface side of the semiconductor substrate. It includes a non-patterned layer that is the basis of the chemical layer and a resist pattern that is a patterned resist film formed on the non-patterned layer, and the resist pattern is thicker than other parts. Has a thin groove portion.
　本発明によれば、エッチング法を用いたパターニングプロセスに起因する太陽電池の性能低下を抑制することができる。 According to the present invention, it is possible to suppress the deterioration of the performance of the solar cell due to the patterning process using the etching method.
本実施形態に係る太陽電池を裏面側からみた図である。It is the figure which looked at the solar cell which concerns on this embodiment from the back side. 図１の太陽電池におけるII-II線断面図である。FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG. 本実施形態に係る太陽電池の製造方法におけるパッシベーション層形成工程および光学調整層形成工程を示す図である。It is a figure which shows the passivation layer forming process and the optical adjustment layer forming process in the manufacturing method of the solar cell which concerns on this embodiment. 本実施形態に係る太陽電池の製造方法における第１半導体層材料膜形成工程（非パターン化層形成工程）を示す図である。It is a figure which shows the 1st semiconductor layer material film formation process (non-patterning layer formation process) in the manufacturing method of the solar cell which concerns on this embodiment. 本実施形態に係る太陽電池の製造方法におけるレジストパターン形成工程を示す図である。It is a figure which shows the resist pattern forming process in the manufacturing method of the solar cell which concerns on this embodiment. 本実施形態に係る太陽電池の製造方法における第１半導体層形成工程（パターン化層形成工程）を示す図である。It is a figure which shows the 1st semiconductor layer formation process (patterned layer formation process) in the manufacturing method of the solar cell which concerns on this embodiment. 本実施形態に係る太陽電池の製造方法における第２半導体層材料膜形成工程（非パターン化層形成工程）を示す図である。It is a figure which shows the 2nd semiconductor layer material film formation process (non-patterning layer formation process) in the manufacturing method of the solar cell which concerns on this embodiment. 本実施形態に係る太陽電池の製造方法におけるレジストパターン形成工程を示す図である。It is a figure which shows the resist pattern forming process in the manufacturing method of the solar cell which concerns on this embodiment. 本実施形態に係る太陽電池の製造方法における第２半導体層形成工程（パターン化層形成工程）を示す図である。It is a figure which shows the 2nd semiconductor layer formation process (patterned layer formation process) in the manufacturing method of the solar cell which concerns on this embodiment. 図３Ｃに示すレジストパターン形成工程における太陽電池の仕掛品のIV部分の裏面図およびIVA－IVA線断面図である（パターン印刷直後）。FIG. 3C is a back view of the IV portion of the work-in-process of the solar cell in the resist pattern forming step shown in FIG. 3C, and a sectional view taken along line IVA-IVA (immediately after pattern printing). 図３Ｃに示すレジストパターン形成工程における太陽電池の仕掛品のIV部分の裏面図およびIVB－IVB線断面図である（所定時間経過後）。FIG. 3C is a back view of the IV portion of the work-in-process of the solar cell in the resist pattern forming step shown in FIG. 3C, and a sectional view taken along line IVB-IVB (after a predetermined time has elapsed). 従来のレジストパターン形成工程における太陽電池の仕掛品のIV部分相当の裏面図およびV－V線断面図である。It is the back view and VV line sectional view corresponding to the IV part of the work-in-process of the solar cell in the conventional resist pattern forming process.
　以下、添付の図面を参照して本発明の実施形態の一例について説明する。なお、各図面において同一または相当の部分に対しては同一の符号を附すこととする。また、便宜上、ハッチングや部材符号等を省略する場合もあるが、かかる場合、他の図面を参照するものとする。 Hereinafter, an example of the embodiment of the present invention will be described with reference to the accompanying drawings. The same reference numerals are given to the same or corresponding parts in each drawing. Further, for convenience, hatching, member codes, etc. may be omitted, but in such cases, other drawings shall be referred to.
（太陽電池の一例）
　まず、本実施形態に係る太陽電池の製造方法で製造される太陽電池の一例について説明する。図１は、本実施形態に係る太陽電池を裏面側からみた図である。図１に示す太陽電池１は、裏面電極型（バックコンタクト型）の太陽電池である。太陽電池１は、２つの主面を備える半導体基板１１を備え、半導体基板１１の一方の主面において第１領域７と第２領域８とを有する。 (Example of solar cell)
First, an example of a solar cell manufactured by the method for manufacturing a solar cell according to the present embodiment will be described. FIG. 1 is a view of the solar cell according to the present embodiment as viewed from the back surface side. The solar cell 1 shown in FIG. 1 is a back electrode type (back contact type) solar cell. The solar cell 1 includes a semiconductor substrate 11 having two main surfaces, and has a first region 7 and a second region 8 on one main surface of the semiconductor substrate 11.
　第１領域７は、いわゆる櫛型の形状をなし、櫛歯に相当する複数のフィンガー部７ｆと、櫛歯の支持部に相当するバスバー部７ｂとを有する。バスバー部７ｂは、半導体基板１１の一方の辺部に沿って第１方向（Ｘ方向）に延在し、フィンガー部７ｆは、バスバー部７ｂから、第１方向（Ｘ方向）に交差する第２方向（Ｙ方向）に延在する。
　同様に、第２領域８は、いわゆる櫛型の形状であり、櫛歯に相当する複数のフィンガー部８ｆと、櫛歯の支持部に相当するバスバー部８ｂとを有する。バスバー部８ｂは、半導体基板１１の一方の辺部に対向する他方の辺部に沿って第１方向（Ｘ方向）に延在し、フィンガー部８ｆは、バスバー部８ｂから、第２方向（Ｙ方向）に延在する。
　フィンガー部７ｆとフィンガー部８ｆとは、第１方向（Ｘ方向）に交互に設けられている。 The first region 7 has a so-called comb-shaped shape, and has a plurality of finger portions 7f corresponding to the comb teeth and a bus bar portion 7b corresponding to the support portion of the comb teeth. The bus bar portion 7b extends in the first direction (X direction) along one side of the semiconductor substrate 11, and the finger portion 7f intersects the bus bar portion 7b in the first direction (X direction). It extends in the direction (Y direction).
Similarly, the second region 8 has a so-called comb-shaped shape, and has a plurality of finger portions 8f corresponding to the comb teeth and a bus bar portion 8b corresponding to the support portion of the comb teeth. The bus bar portion 8b extends in the first direction (X direction) along the other side portion facing one side portion of the semiconductor substrate 11, and the finger portion 8f extends from the bus bar portion 8b in the second direction (Y). Extends in the direction).
The finger portions 7f and the finger portions 8f are alternately provided in the first direction (X direction).
　図２は、図１の太陽電池におけるII－II線断面図である。図２に示すように、太陽電池１は、半導体基板１１と、半導体基板１１の主面のうちの受光する側の一方の主面である受光面側に順に積層されたパッシベーション層１３および光学調整層１５を備える。また、太陽電池１は、半導体基板１１の主面のうちの受光面の反対側の他方の主面である裏面側の一部（第１領域７）に順に積層されたパッシベーション層２３、第１導電型半導体層２５および第１電極層２７を備える。また、太陽電池１は、半導体基板１１の裏面側の他の一部（第２領域８）に順に積層されたパッシベーション層３３、第２導電型半導体層３５、および第２電極層３７を備える。 FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG. As shown in FIG. 2, the solar cell 1 includes a semiconductor substrate 11, a passivation layer 13 which is sequentially laminated on a light receiving surface side which is one of the main surfaces of the semiconductor substrate 11 on the light receiving side, and optical adjustment. The layer 15 is provided. Further, in the solar cell 1, the passivation layers 23 and the first are sequentially laminated on a part (first region 7) of the back surface side which is the other main surface of the main surface of the semiconductor substrate 11 opposite to the light receiving surface. A conductive semiconductor layer 25 and a first electrode layer 27 are provided. Further, the solar cell 1 includes a passivation layer 33, a second conductive semiconductor layer 35, and a second electrode layer 37, which are sequentially laminated on another part (second region 8) on the back surface side of the semiconductor substrate 11.
　半導体基板１１は、単結晶シリコンまたは多結晶シリコン等の結晶シリコン材料で形成される。半導体基板１１は、例えば結晶シリコン材料にｎ型ドーパントがドープされたｎ型の半導体基板である。ｎ型ドーパントとしては、例えばリン（Ｐ）が挙げられる。
　半導体基板１１は、受光面側からの入射光を吸収して光キャリア（電子および正孔）を生成する光電変換基板として機能する。 The semiconductor substrate 11 is formed of a crystalline silicon material such as single crystal silicon or polycrystalline silicon. The semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which a crystalline silicon material is doped with an n-type dopant. Examples of the n-type dopant include phosphorus (P).
The semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light receiving surface side to generate optical carriers (electrons and holes).
　パッシベーション層１３は、半導体基板１１の受光面側に形成されている。パッシベーション層２３は、半導体基板１１の裏面側の第１領域７に形成されている。パッシベーション層３３は、半導体基板１１の裏面側の第２領域８に形成されている。パッシベーション層１３，２３，３３は、例えば真性（ｉ型）アモルファスシリコンを主成分とする材料で形成される。
　パッシベーション層１３，２３，３３は、半導体基板１１で生成されたキャリアの再結合を抑制し、キャリアの回収効率を高める。 The passivation layer 13 is formed on the light receiving surface side of the semiconductor substrate 11. The passivation layer 23 is formed in the first region 7 on the back surface side of the semiconductor substrate 11. The passivation layer 33 is formed in the second region 8 on the back surface side of the semiconductor substrate 11. The passivation layers 13, 23, 33 are formed of, for example, a material containing intrinsic (i-type) amorphous silicon as a main component.
The passivation layers 13, 23, 33 suppress the recombination of carriers generated in the semiconductor substrate 11 and increase the carrier recovery efficiency.
　光学調整層１５は、半導体基板１１の受光面側のパッシベーション層１３上に形成されている。光学調整層１５は、入射光の反射を防止する反射防止層として機能するとともに、半導体基板１１の受光面側およびパッシベーション層１３を保護する保護層として機能する。光学調整層１５は、例えば酸化珪素（ＳｉＯ）、窒化珪素（ＳｉＮ）、または酸窒化珪素（ＳｉＯＮ）のようなそれらの複合物等の絶縁体材料で形成される。 The optical adjustment layer 15 is formed on the passivation layer 13 on the light receiving surface side of the semiconductor substrate 11. The optical adjustment layer 15 functions as an antireflection layer that prevents reflection of incident light, and also functions as a protective layer that protects the light receiving surface side of the semiconductor substrate 11 and the passivation layer 13. The optical adjustment layer 15 is formed of an insulating material such as a composite thereof such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON).
　第１導電型半導体層２５は、パッシベーション層２３上に、すなわち半導体基板１１の裏面側の第１領域７に形成されている。すなわち、第１導電型半導体層２５は、いわゆる櫛型の形状をなし、櫛歯に相当する複数のフィンガー部と、櫛歯の支持部に相当し、複数のフィンガー部の一端が接続されたバスバー部とを有する。バスバー部は、第１領域７のバスバー部７ｂに対応し、半導体基板１１のＸ方向の一方端側の辺部に沿ってＹ方向に延在する。フィンガー部は、第１領域７のフィンガー部７ｆに対応し、バスバー部からＸ方向に延在する。 The first conductive semiconductor layer 25 is formed on the passivation layer 23, that is, in the first region 7 on the back surface side of the semiconductor substrate 11. That is, the first conductive semiconductor layer 25 has a so-called comb-shaped shape, and is a bus bar in which a plurality of finger portions corresponding to comb teeth and one end of the plurality of finger portions are connected, which corresponds to a support portion of the comb teeth. Has a part. The bus bar portion corresponds to the bus bar portion 7b of the first region 7 and extends in the Y direction along the side portion on one end side of the semiconductor substrate 11 in the X direction. The finger portion corresponds to the finger portion 7f of the first region 7 and extends in the X direction from the bus bar portion.
　第２導電型半導体層３５は、パッシベーション層３３上に、すなわち半導体基板１１の裏面側の第２領域８に形成されている。すなわち、第２導電型半導体層３５は、いわゆる櫛型の形状をなし、櫛歯に相当する複数のフィンガー部と、櫛歯の支持部に相当し、複数のフィンガー部の一端が接続されたバスバー部とを有する。バスバー部は、第２領域８のバスバー部８ｂに対応し、半導体基板１１のＸ方向の他方端側の辺部に沿ってＹ方向に延在する。フィンガー部は、第２領域８のフィンガー部８ｆに対応し、バスバー部からＸ方向に延在する。 The second conductive semiconductor layer 35 is formed on the passivation layer 33, that is, in the second region 8 on the back surface side of the semiconductor substrate 11. That is, the second conductive semiconductor layer 35 has a so-called comb-shaped shape, and is a bus bar in which a plurality of finger portions corresponding to the comb teeth and one end of the plurality of finger portions are connected, which corresponds to the support portion of the comb teeth. Has a part. The bus bar portion corresponds to the bus bar portion 8b of the second region 8 and extends in the Y direction along the side portion of the semiconductor substrate 11 on the other end side in the X direction. The finger portion corresponds to the finger portion 8f of the second region 8 and extends in the X direction from the bus bar portion.
　第１導電型半導体層２５は、例えばアモルファスシリコン材料で形成される。第１導電型半導体層２５は、例えばアモルファスシリコン材料にｐ型ドーパントがドープされたｐ型半導体層である。ｐ型ドーパントとしては、例えばホウ素（Ｂ）が挙げられる。
　第２導電型半導体層３５は、例えばアモルファスシリコン材料で形成される。第２導電型半導体層３５は、例えばアモルファスシリコン材料にｎ型ドーパント（例えば、上述したリン（Ｐ））がドープされたｎ型の半導体層である。 The first conductive semiconductor layer 25 is formed of, for example, an amorphous silicon material. The first conductive semiconductor layer 25 is, for example, a p-type semiconductor layer in which an amorphous silicon material is doped with a p-type dopant. Examples of the p-type dopant include boron (B).
The second conductive semiconductor layer 35 is formed of, for example, an amorphous silicon material. The second conductive semiconductor layer 35 is, for example, an n-type semiconductor layer in which an amorphous silicon material is doped with an n-type dopant (for example, phosphorus (P) described above).
　なお、第１導電型半導体層２５がｎ型半導体層であり、第２導電型半導体層３５がｐ型半導体層であってもよい。
　また、半導体基板１１は、結晶シリコン材料にｐ型ドーパント（例えば、上述したホウ素（Ｂ））がドープされたｐ型半導体基板であってもよい。 The first conductive semiconductor layer 25 may be an n-type semiconductor layer, and the second conductive semiconductor layer 35 may be a p-type semiconductor layer.
Further, the semiconductor substrate 11 may be a p-type semiconductor substrate in which a crystalline silicon material is doped with a p-type dopant (for example, the above-mentioned boron (B)).
　第１電極層２７は、第１導電型半導体層２５上に、すなわち半導体基板１１の裏面側の第１領域７に形成されている。第２電極層３７は、第２導電型半導体層３５上に、すなわち半導体基板１１の裏面側の第２領域８に形成されている。
　第１電極層２７は、第１導電型半導体層２５上に順に積層された透明電極層２８と金属電極層２９とを有する。第２電極層３７は、第２導電型半導体層３５上に順に積層された透明電極層３８と金属電極層３９とを有する。 The first electrode layer 27 is formed on the first conductive semiconductor layer 25, that is, in the first region 7 on the back surface side of the semiconductor substrate 11. The second electrode layer 37 is formed on the second conductive semiconductor layer 35, that is, in the second region 8 on the back surface side of the semiconductor substrate 11.
The first electrode layer 27 has a transparent electrode layer 28 and a metal electrode layer 29, which are sequentially laminated on the first conductive semiconductor layer 25. The second electrode layer 37 has a transparent electrode layer 38 and a metal electrode layer 39 that are sequentially laminated on the second conductive semiconductor layer 35.
　透明電極層２８および金属電極層２９は、いわゆる櫛型の形状をなし、櫛歯に相当する複数のフィンガー部と、櫛歯の支持部に相当し、複数のフィンガー部の一端が接続されたバスバー部とを有する。バスバー部は、第１領域７のバスバー部７ｂに対応し、半導体基板１１のＸ方向の一方端側の辺部に沿ってＹ方向に延在する。フィンガー部は、第１領域７のフィンガー部７ｆに対応し、バスバー部からＸ方向に延在する。 The transparent electrode layer 28 and the metal electrode layer 29 have a so-called comb shape, and are a bus bar having a plurality of finger portions corresponding to comb teeth and a support portion of the comb teeth to which one ends of the plurality of finger portions are connected. Has a part. The bus bar portion corresponds to the bus bar portion 7b of the first region 7 and extends in the Y direction along the side portion on one end side of the semiconductor substrate 11 in the X direction. The finger portion corresponds to the finger portion 7f of the first region 7 and extends in the X direction from the bus bar portion.
　透明電極層３８および金属電極層３９は、いわゆる櫛型の形状をなし、櫛歯に相当する複数のフィンガー部と、櫛歯の支持部に相当し、複数のフィンガー部の一端が接続されたバスバー部とを有する。バスバー部は、第２領域８のバスバー部８ｂに対応し、半導体基板１１のＸ方向の他方端側の辺部に沿ってＹ方向に延在する。フィンガー部は、第２領域８のフィンガー部８ｆに対応し、バスバー部からＸ方向に延在する。 The transparent electrode layer 38 and the metal electrode layer 39 have a so-called comb shape, and are a bus bar having a plurality of finger portions corresponding to comb teeth and a support portion of the comb teeth to which one ends of the plurality of finger portions are connected. Has a part. The bus bar portion corresponds to the bus bar portion 8b of the second region 8 and extends in the Y direction along the side portion of the semiconductor substrate 11 on the other end side in the X direction. The finger portion corresponds to the finger portion 8f of the second region 8 and extends in the X direction from the bus bar portion.
　透明電極層２８，３８は、透明な導電性材料で形成される。透明導電性材料としては、ＩＴＯ（Indium Tin Oxide：酸化インジウムおよび酸化スズの複合酸化物）、ＺｎＯ（Zinc Oxide：酸化亜鉛）が挙げられる。
　金属電極層２８，３８は、金属材料で形成される。金属材料としては、例えば、Ｃｕ、Ａｇ、Ａｌおよびこれらの合金が用いられる。金属電極層２８，３８は、例えば、銀等の金属粉末を含有する導電性ペースト材料で形成されてもよい。 The transparent electrode layers 28 and 38 are formed of a transparent conductive material. Examples of the transparent conductive material include ITO (Indium Tin Oxide: a composite oxide of indium tin oxide and tin oxide) and ZnO (Zinc Oxide: zinc oxide).
The metal electrode layers 28 and 38 are made of a metal material. As the metal material, for example, Cu, Ag, Al and alloys thereof are used. The metal electrode layers 28 and 38 may be formed of, for example, a conductive paste material containing a metal powder such as silver.
（太陽電池の製造方法の一例）
　次に、図３Ａ～図３Ｇ，図４Ａおよび図４Ｂを参照して、図１および図２に示す本実施形態の太陽電池１の製造方法について説明する。図３Ａは、本実施形態に係る太陽電池の製造方法におけるパッシベーション層形成工程および光学調整層形成工程を示す図であり、図３Ｂは、本実施形態に係る太陽電池の製造方法における第１半導体層材料膜形成工程（非パターン化層形成工程）を示す図である。図３Ｃは、本実施形態に係る太陽電池の製造方法におけるレジストパターン形成工程を示す図であり、図３Ｄは、本実施形態に係る太陽電池の製造方法における第１半導体層形成工程（パターン化層形成工程）を示す図である。図３Ｅは、本実施形態に係る太陽電池の製造方法における第２半導体層材料膜形成工程（非パターン化層形成工程）を示す図であり、図３Ｆは、本実施形態に係る太陽電池の製造方法におけるレジストパターン形成工程を示す図である。図３Ｇは、本実施形態に係る太陽電池の製造方法における第２半導体層形成工程（パターン化層形成工程）を示す図である。図４Ａは、図３Ｃに示すレジストパターン形成工程における太陽電池の仕掛品のIV部分の裏面図およびIVA－IVA線断面図であり（パターン印刷直後）、図４Ｂは、図３Ｃに示すレジストパターン形成工程における太陽電池の仕掛品のIV部分の裏面図およびIVB－IVB線断面図である（所定時間経過後）。また、図５は、従来のレジストパターン形成工程における太陽電池の仕掛品のIV部分相当の裏面図およびV－V線断面図である。 (Example of solar cell manufacturing method)
Next, a method for manufacturing the solar cell 1 of the present embodiment shown in FIGS. 1 and 2 will be described with reference to FIGS. 3A to 3G, 4A and 4B. FIG. 3A is a diagram showing a passivation layer forming step and an optical adjustment layer forming step in the solar cell manufacturing method according to the present embodiment, and FIG. 3B is a diagram showing a first semiconductor layer in the solar cell manufacturing method according to the present embodiment. It is a figure which shows the material film formation process (non-patterned layer formation process). FIG. 3C is a diagram showing a resist pattern forming step in the solar cell manufacturing method according to the present embodiment, and FIG. 3D is a first semiconductor layer forming step (patterned layer) in the solar cell manufacturing method according to the present embodiment. It is a figure which shows the forming process). FIG. 3E is a diagram showing a second semiconductor layer material film forming step (non-patterned layer forming step) in the method for manufacturing a solar cell according to the present embodiment, and FIG. 3F is a diagram showing manufacturing of a solar cell according to the present embodiment. It is a figure which shows the resist pattern forming process in the method. FIG. 3G is a diagram showing a second semiconductor layer forming step (patterned layer forming step) in the method for manufacturing a solar cell according to the present embodiment. FIG. 4A is a back view of the IV portion of the work-in-process of the solar cell in the resist pattern forming step shown in FIG. 3C and a sectional view taken along line IVA-IVA (immediately after pattern printing), and FIG. 4B shows the resist pattern forming shown in FIG. 3C. It is a back view and IVB-IVB line sectional view of the IV part of the work-in-process of the solar cell in the process (after a predetermined time elapses). Further, FIG. 5 is a back view and a sectional view taken along line VV corresponding to the IV portion of the work-in-process of the solar cell in the conventional resist pattern forming step.
　本実施形態では、基板トレイ３として、半導体基板１１の側面側、および半導体基板１１の裏面側の周縁領域を被覆するトレイを用いるが、基板トレイはこれに限定されず、種々のトレイが用いられてもよい。 In the present embodiment, as the substrate tray 3, a tray that covers the peripheral region on the side surface side of the semiconductor substrate 11 and the back surface side of the semiconductor substrate 11 is used, but the substrate tray is not limited to this, and various trays are used. You may.
　まず、図３Ａに示すように、例えばＣＶＤ法（化学気相堆積法）を用いて、半導体基板１１の受光面側の全面に、パッシベーション層１３を積層（製膜）する（パッシベーション層形成工程）。次に、例えばＣＶＤ法を用いて、半導体基板１１の受光面側のパッシベーション層１３上の全面に、光学調整層１５を積層（製膜）する（光学調整層形成工程）。 First, as shown in FIG. 3A, the passivation layer 13 is laminated (film-formed) on the entire surface of the semiconductor substrate 11 on the light receiving surface side by, for example, a CVD method (chemical vapor deposition method) (passivation layer forming step). .. Next, for example, using a CVD method, the optical adjustment layer 15 is laminated (film-formed) on the entire surface of the passivation layer 13 on the light receiving surface side of the semiconductor substrate 11 (optical adjustment layer forming step).
　次に、図３Ｂに示すように、例えばＣＶＤ法を用いて、半導体基板１１の裏面側の全面に、パッシベーション層２３および第１導電型半導体層２５（パターン化層）の基となるパターン化前のパッシベーション層材料膜２３Ｚおよび第１導電型半導体層材料膜２５Ｚ（非パターン化層）を順に形成（製膜）する（第１半導体層材料膜形成工程：非パターン化層形成工程）。 Next, as shown in FIG. 3B, before patterning, which is the basis of the passivation layer 23 and the first conductive semiconductor layer 25 (patterning layer), the entire surface of the back surface side of the semiconductor substrate 11 is covered by, for example, the CVD method. Passivation layer material film 23Z and first conductive semiconductor layer material film 25Z (non-patterned layer) are sequentially formed (film-formed) (first semiconductor layer material film forming step: non-patterned layer forming step).
　次に、図３Ｃに示すように、半導体基板１１の裏面側の第１領域７におけるパッシベーション層材料膜２３Ｚおよび第１導電型半導体層材料膜２５Ｚ上に、パターン化されたレジスト膜であるレジストパターンを形成する（レジストパターン形成工程）。 Next, as shown in FIG. 3C, a resist pattern, which is a resist film patterned on the passivation layer material film 23Z and the first conductive semiconductor layer material film 25Z in the first region 7 on the back surface side of the semiconductor substrate 11. (Resist pattern forming step).
　ここで、従来、フォトリソグラフィ―技術を用いて、図５に示すように、第１領域７におけるフィンガー部７ｆおよびバスバー部７ｂに対応し、略均一な厚さを有するレジストパターン４０Ｘを形成した。この従来のレジストパターン４０Ｘでは、後述するエッチング法を用いたパターン化層形成工程において、以下の問題が生じる。
　パターン化層形成工程では、半導体基板１１の表面に気泡が発生することを抑制するために、エッチング溶液に対する半導体基板１１の挿入（浸漬）および取出方向は、フィンガー部に対応するレジストパターン４０Ｘの延在方向（Ｙ方向）に沿う。
　この場合、エッチング溶液から半導体基板１１を取り出す際に、レジストパターン４０Ｘにおけるバスバー部とフィンガー部とに対応する部分で形成される袋小路（blind alley，impasse）Ａにエッチング溶液が溜まり、袋小路Ａの部分のエッチングが袋小路Ａ以外の部分よりも進行し過ぎることがある。そのため、エッチングが不均一となり、太陽電池の性能が低下することがある。 Here, conventionally, as shown in FIG. 5, a resist pattern 40X having a substantially uniform thickness was formed corresponding to the finger portion 7f and the bus bar portion 7b in the first region 7 by using a photolithography technique. In this conventional resist pattern 40X, the following problems occur in the patterning layer forming step using the etching method described later.
In the patterning layer forming step, in order to suppress the generation of bubbles on the surface of the semiconductor substrate 11, the insertion (immersion) and removal directions of the semiconductor substrate 11 in the etching solution are the spread of the resist pattern 40X corresponding to the finger portion. Along the current direction (Y direction).
In this case, when the semiconductor substrate 11 is taken out from the etching solution, the etching solution collects in the blind alley, impasse A formed at the portion corresponding to the bus bar portion and the finger portion in the resist pattern 40X, and the portion of the blind alley A. Etching may proceed more than the part other than the dead end A. Therefore, the etching becomes non-uniform, and the performance of the solar cell may deteriorate.
　この点に関し、本実施形態では、スクリーン印刷法を用いて、レジストパターン４０を形成する。具体的には、図４Ａに示すように、印刷版を用いて、所定間隔だけ分離するようにレジスト剤４０Ｚを印刷する。所定間隔とは、レジスト剤４０Ｚの流動性により、分離したレジスト剤４０Ｚ同士が連結してレジストパターン４０を形成し、レジストパターン４０において分離したレジスト剤４０Ｚ同士が連結した連結部分４１の厚さが連結部分４１以外の厚さよりも薄くなる、間隔である。
　このように、印刷版を通過させた直後のレジスト剤４０Ｚを分離配置させると、一定時間経過後、図４Ｂに示すように、分離していたレジスト剤４０Ｚ同士が連結し、連結部分４１の厚さが連結部分４１以外の厚さよりも薄くなる。これにより、連結部分４１に溝が形成される。 In this regard, in this embodiment, the resist pattern 40 is formed by using a screen printing method. Specifically, as shown in FIG. 4A, the resist agent 40Z is printed so as to be separated by a predetermined interval using a printing plate. The predetermined interval is the thickness of the connecting portion 41 in which the separated resist agents 40Z are connected to each other to form the resist pattern 40 due to the fluidity of the resist agent 40Z, and the resist agents 40Z separated in the resist pattern 40 are connected to each other. The interval is thinner than the thickness other than the connecting portion 41.
When the resisting agent 40Z immediately after passing through the printing plate is separated and arranged in this way, after a certain period of time, as shown in FIG. 4B, the separated resisting agents 40Z are connected to each other and the thickness of the connecting portion 41 is increased. Is thinner than the thickness other than the connecting portion 41. As a result, a groove is formed in the connecting portion 41.
　連結部分（溝部分）４１は、レジストパターン４０における、袋小路Ａを形成する部分に形成される。連結部分（溝部分）４１は、連結部分４１の延在方向が、後述するパターン化層形成工程におけるエッチング溶液に対する半導体基板１１の挿入および取出方向、換言すればフィンガー部に対応するレジストパターン４０の延在方向（Ｙ方向）に沿うように、形成される。 The connecting portion (groove portion) 41 is formed in the portion of the resist pattern 40 that forms the dead end A. In the connecting portion (groove portion) 41, the extending direction of the connecting portion 41 corresponds to the insertion and removal directions of the semiconductor substrate 11 with respect to the etching solution in the patterning layer forming step described later, in other words, the resist pattern 40 corresponding to the finger portion. It is formed along the extending direction (Y direction).
　これにより、後述するエッチング法を用いたパターン化層形成工程において、エッチング溶液から半導体基板１１を取り出す際に、袋小路Ａにエッチング溶液が溜まることが抑制される。そのため、エッチングの不均一が抑制され、太陽電池の性能低下が抑制される。 As a result, in the patterning layer forming step using the etching method described later, when the semiconductor substrate 11 is taken out from the etching solution, the etching solution is suppressed from accumulating in the dead end A. Therefore, the non-uniformity of etching is suppressed, and the deterioration of the performance of the solar cell is suppressed.
　なお、連結部分（溝部分）４１は袋小路Ａにエッチング溶液が溜まることを抑制できればよく、連結部分４１の延在方向は、エッチング溶液に対する半導体基板１１の挿入および取出方向（Ｙ方向）に対して斜めに沿うように形成されてもよい。また、連結部分（溝部分）４１は、袋小路Ａを形成する、レジストパターン４０におけるバスバー部に対応する部分のみならず、袋小路Ａを形成する、レジストパターン４０におけるフィンガー部に対応する部分に形成されてもよい。 The connecting portion (groove portion) 41 only needs to be able to prevent the etching solution from accumulating in the dead end A, and the extending direction of the connecting portion 41 is relative to the insertion / removal direction (Y direction) of the semiconductor substrate 11 with respect to the etching solution. It may be formed along an angle. Further, the connecting portion (groove portion) 41 is formed not only in the portion corresponding to the bus bar portion in the resist pattern 40 forming the dead end A, but also in the portion corresponding to the finger portion in the resist pattern 40 forming the dead end A. You may.
　レジストパターン４０を形成するためのレジスト剤４０Ｚは、チキソトロピー性を有する材料を含む。これにより、スクリーン印刷の印刷版を通過する際に受ける力によってレジスト剤４０Ｚの粘度が低下し（流動性が上昇し）、所定間隔だけ分離した部分において連結する。その際、次第にレジスト剤４０Ｚの粘度が上昇し（流動性が低下し）、所定間隔だけ分離した部分において表面が平坦になる前に、レジスト剤４０Ｚの粘度が戻り、連結部分４１の厚さが連結部分４１以外の厚さよりも薄くなり、連結部分４１に溝が形成される。このように、スクリーン印刷において、チキソトロピー性を有するレジスト剤を用いると、連結部分４１の厚さを連結部分４１以外の厚さよりも薄くすること、換言すれば連結部分４１に溝を形成することが容易となる。 The resist agent 40Z for forming the resist pattern 40 contains a material having thixotropy. As a result, the viscosity of the resist agent 40Z decreases (the fluidity increases) due to the force received when passing through the printing plate for screen printing, and the resisting agents 40Z are connected at the portions separated by a predetermined interval. At that time, the viscosity of the resist agent 40Z gradually increases (the fluidity decreases), and the viscosity of the resist agent 40Z returns before the surface becomes flat in the portions separated by a predetermined interval, and the thickness of the connecting portion 41 increases. It is thinner than the thickness other than the connecting portion 41, and a groove is formed in the connecting portion 41. As described above, in screen printing, when a resist agent having thixotropy property is used, the thickness of the connecting portion 41 can be made thinner than the thickness other than the connecting portion 41, in other words, a groove can be formed in the connecting portion 41. It will be easy.
　図４Ｂに示すように、本実施形態の太陽電池の製造方法における非パターン化層形成工程およびレジストパターン形成工程後であって、パターン化層形成工程前の太陽電池の仕掛品１Ｚの一例は、半導体基板１１の裏面側の全面に形成された、パッシベーション層２３および第１導電型半導体層２５（パターン化層）の基となるパターン化前のパッシベーション層材料膜２３Ｚおよび第１導電型半導体層材料膜２５Ｚ（非パターン化層）と、半導体基板１１の裏面側の第１領域７におけるパッシベーション層材料膜２３Ｚおよび第１導電型半導体層材料膜２５Ｚ上に形成された、パターン化されたレジスト膜であるレジストパターン４０とを備える。レジストパターン４０は、他の部分よりも厚さが薄い連結部分（溝部分）４１を有する。連結部分（溝部分）４１は、レジストパターン４０における、袋小路Ａを形成する部分に配置される。 As shown in FIG. 4B, an example of the in-process product 1Z of the solar cell after the non-patterned layer forming step and the resist pattern forming step in the solar cell manufacturing method of the present embodiment and before the patterned layer forming step is The passivation layer material film 23Z and the first conductive semiconductor layer material before patterning, which are the basis of the passivation layer 23 and the first conductive semiconductor layer 25 (patterned layer), formed on the entire back surface side of the semiconductor substrate 11. A patterned resist film formed on the film 25Z (non-patterned layer), the passivation layer material film 23Z in the first region 7 on the back surface side of the semiconductor substrate 11, and the first conductive semiconductor layer material film 25Z. It includes a certain resist pattern 40. The resist pattern 40 has a connecting portion (groove portion) 41 that is thinner than the other portions. The connecting portion (groove portion) 41 is arranged at a portion of the resist pattern 40 that forms the dead end A.
　次に、図３Ｄに示すように、エッチング法を用いて、半導体基板１１の裏面側の第２領域８におけるパッシベーション層材料膜２３Ｚおよび第１導電型半導体層材料膜２５Ｚ（非パターン化層）を除去する。これにより、半導体基板１１の裏面側の第１領域７に、パターン化されたパッシベーション層２３および第１導電型半導体層２５（パターン化層）を形成する（第１半導体層形成工程：パターン化層形成工程）。 Next, as shown in FIG. 3D, the passionation layer material film 23Z and the first conductive semiconductor layer material film 25Z (non-patterned layer) in the second region 8 on the back surface side of the semiconductor substrate 11 are formed by using an etching method. Remove. As a result, the patterned passivation layer 23 and the first conductive semiconductor layer 25 (patterned layer) are formed in the first region 7 on the back surface side of the semiconductor substrate 11 (first semiconductor layer forming step: patterned layer). Formation process).
　エッチング溶液としては、例えばフッ酸と硝酸との混合液等の酸性溶液が用いられる。
　その後、リンス処理が行われ、レジストパターン４０を剥離する。 As the etching solution, for example, an acidic solution such as a mixed solution of hydrofluoric acid and nitric acid is used.
After that, a rinsing treatment is performed to peel off the resist pattern 40.
　次に、図３Ｅに示すように、例えばＣＶＤ法を用いて、半導体基板１１の裏面側の全面に、すなわち第２領域８における露出した半導体基板１１上および第１領域７における第１導電型半導体層２５上に、パッシベーション層３３および第２導電型半導体層３５（パターン化層）の基となるパターン化前のパッシベーション層材料膜３３Ｚおよびｎ型半導体層材料膜３５Ｚ（非パターン化層）を順に形成（製膜）する（第２半導体層材料膜形成工程：非パターン化層形成工程）。 Next, as shown in FIG. 3E, for example, using the CVD method, the first conductive type semiconductor on the entire back surface side of the semiconductor substrate 11, that is, on the exposed semiconductor substrate 11 in the second region 8 and in the first region 7. On the layer 25, the passivation layer material film 33Z and the n-type semiconductor layer material film 35Z (non-patterned layer) before patterning, which are the basis of the passivation layer 33 and the second conductive semiconductor layer 35 (patterned layer), are sequentially placed. Forming (film formation) (second semiconductor layer material film forming step: non-patterned layer forming step).
　なお、第１半導体層形成工程において、半導体基板１１の裏面側の第２領域８におけるパッシベーション層材料膜２３Ｚの全部が残る場合、パッシベーション層材料膜の積層（製膜）を行わなくてもよい。また、第１半導体層形成工程において、半導体基板１１の裏面側の第２領域８におけるパッシベーション層材料膜２３Ｚの一部が残る場合、除去された分だけパッシベーション層材料膜の積層（製膜）を行えばよい。 If the entire passivation layer material film 23Z in the second region 8 on the back surface side of the semiconductor substrate 11 remains in the first semiconductor layer forming step, the passivation layer material film does not need to be laminated (film formation). Further, in the first semiconductor layer forming step, when a part of the passivation layer material film 23Z in the second region 8 on the back surface side of the semiconductor substrate 11 remains, the passivation layer material film is laminated (film-forming) by the amount removed. Just do it.
　次に、図３Ｆに示すように、上述したレジストパターン形成工程（図３Ｃ，図４Ａおよび図４Ｂ）と同様に、スクリーン印刷法を用いて、半導体基板１１の裏面側の第２領域８におけるパッシベーション層材料膜３３Ｚおよびｎ型半導体層材料膜３５Ｚ上に、パターン化されたレジスト膜であるレジストパターン４０を形成する（レジストパターン形成工程）。 Next, as shown in FIG. 3F, the passivation in the second region 8 on the back surface side of the semiconductor substrate 11 is performed by using the screen printing method in the same manner as the resist pattern forming step (FIGS. 3C, 4A and 4B) described above. A resist pattern 40, which is a patterned resist film, is formed on the layer material film 33Z and the n-type semiconductor layer material film 35Z (resist pattern forming step).
　次に、図３Ｇに示すように、エッチング法を用いて、半導体基板１１の裏面側の第１領域７におけるパッシベーション層材料膜３３Ｚおよび第２導電型半導体層材料膜３５Ｚ（非パターン化層）を除去する。これにより、半導体基板１１の裏面側の第２領域８に、パターン化されたパッシベーション層３３および第２導電型半導体層３５（パターン化層）を形成する（第２半導体層形成工程：パターン化層形成工程）。 Next, as shown in FIG. 3G, the passionation layer material film 33Z and the second conductive semiconductor layer material film 35Z (non-patterned layer) in the first region 7 on the back surface side of the semiconductor substrate 11 are formed by using an etching method. Remove. As a result, the patterned passivation layer 33 and the second conductive semiconductor layer 35 (patterned layer) are formed in the second region 8 on the back surface side of the semiconductor substrate 11 (second semiconductor layer forming step: patterned layer). Formation process).
　エッチング溶液としては、例えばフッ酸と硝酸との混合液等の酸性溶液が用いられる。
　その後、リンス処理が行われ、レジストパターン４０を剥離する。 As the etching solution, for example, an acidic solution such as a mixed solution of hydrofluoric acid and nitric acid is used.
After that, a rinsing treatment is performed to peel off the resist pattern 40.
　次に、半導体基板１１の裏面側に、第１電極層２７および第２電極層３７を形成する（電極層形成工程）。
　具体的には、例えばスパッタリング法等のＰＶＤ法（物理気相成長法）を用いて、半導体基板１１の裏面側の全面に、透明電極層材料膜を積層（製膜）する。その後、例えばエッチングペーストを用いたエッチング法を用いて、透明電極層材料膜の一部を除去することにより、透明電極層２８，３８のパターニングを行う。透明電極層材料膜に対するエッチング溶液としては、例えば塩酸または塩化第二鉄水溶液が用いられる。
　その後、例えばパターン印刷法または塗布法を用いて、透明電極層２８上に金属電極層２９を形成し、透明電極層３８の上に金属電極層３９を形成することにより、第１電極層２７および第２電極層３７を形成する。 Next, the first electrode layer 27 and the second electrode layer 37 are formed on the back surface side of the semiconductor substrate 11 (electrode layer forming step).
Specifically, for example, a PVD method (physical vapor deposition method) such as a sputtering method is used to laminate (form) a transparent electrode layer material film on the entire back surface side of the semiconductor substrate 11. After that, the transparent electrode layers 28 and 38 are patterned by removing a part of the transparent electrode layer material film by, for example, an etching method using an etching paste. As the etching solution for the transparent electrode layer material film, for example, hydrochloric acid or an aqueous ferric chloride solution is used.
Then, for example, by using a pattern printing method or a coating method, a metal electrode layer 29 is formed on the transparent electrode layer 28, and a metal electrode layer 39 is formed on the transparent electrode layer 38, whereby the first electrode layer 27 and The second electrode layer 37 is formed.
　以上の工程により、図１および図２に示す本実施形態の裏面電極型の太陽電池１が完成する。 Through the above steps, the back electrode type solar cell 1 of the present embodiment shown in FIGS. 1 and 2 is completed.
　以上説明したように、本実施形態の太陽電池の製造方法によれば、レジストパターン形成工程において、スクリーン印刷法を用いて、所定間隔だけ分離するようにレジスト剤４０Ｚを印刷し（図４Ａ）、所定間隔とは、レジスト剤４０Ｚの流動性により、分離したレジスト剤４０Ｚ同士が連結してレジストパターン４０を形成し、レジストパターン４０において分離したレジスト剤４０Ｚ同士が連結した連結部分４１の厚さが連結部分４１以外の厚さよりも薄くなる、間隔である（図４Ｂ）。これにより、連結部分４１に、例えば袋小路Ａを形成する部分に溝が形成される。これにより、エッチング法を用いたパターン化層形成工程において、エッチング溶液から半導体基板１１を取り出す際に、袋小路Ａにエッチング溶液が溜まることが抑制される。そのため、エッチングの不均一が抑制され、太陽電池の性能低下が抑制される。その結果、太陽電池の歩留りの低下が抑制される。 As described above, according to the method for manufacturing a solar cell of the present embodiment, in the resist pattern forming step, the resist agent 40Z is printed so as to be separated by a predetermined interval by using a screen printing method (FIG. 4A). The predetermined interval is the thickness of the connecting portion 41 in which the separated resist agents 40Z are connected to each other to form the resist pattern 40 due to the fluidity of the resist agent 40Z, and the resist agents 40Z separated in the resist pattern 40 are connected to each other. The interval is thinner than the thickness other than the connecting portion 41 (FIG. 4B). As a result, a groove is formed in the connecting portion 41, for example, in the portion forming the dead end A. As a result, in the patterning layer forming step using the etching method, when the semiconductor substrate 11 is taken out from the etching solution, the etching solution is suppressed from accumulating in the dead end A. Therefore, the non-uniformity of etching is suppressed, and the deterioration of the performance of the solar cell is suppressed. As a result, the decrease in the yield of the solar cell is suppressed.
　また、本実施形態の太陽電池の製造方法によれば、エッチング溶液から半導体基板１１を取り出す際に、エッチング溶液が袋小路に溜まることが軽減されるので、その後のリンス処理へのエッチング溶液の持ち込み量が軽減される。そのため、リンス処理の処理時間の短縮、およびリンス溶液量およびリンス液交換回数の省力化ができ、コストダウンが可能となる。 Further, according to the method for manufacturing a solar cell of the present embodiment, when the semiconductor substrate 11 is taken out from the etching solution, the etching solution is less likely to accumulate in the dead end, so that the amount of the etching solution brought into the subsequent rinsing treatment is reduced. Is reduced. Therefore, the processing time of the rinsing process can be shortened, the amount of the rinsing solution and the number of times the rinsing solution is replaced can be saved, and the cost can be reduced.
　以上、本発明の実施形態について説明したが、本発明は上述した実施形態に限定されることなく、種々の変更および変形が可能である。例えば、上述した実施形態では、エッチング法を用いた半導体層のパターン化層形成において、本発明の特徴のスクリーン印刷法を用いたレジストパターン形成工程を適用した太陽電池の製造方法を例示したが、本発明の特徴はこれに限定されず、透明電極層または金属電極層のパターン化層形成においてエッチング法を用いる場合にも適用可能である。 Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications and modifications can be made. For example, in the above-described embodiment, in the patterning layer formation of the semiconductor layer using the etching method, a method for manufacturing a solar cell to which the resist pattern forming step using the screen printing method, which is a feature of the present invention, is applied has been exemplified. The features of the present invention are not limited to this, and can be applied to the case where the etching method is used in forming the patterned layer of the transparent electrode layer or the metal electrode layer.
　また、上述した実施形態では、裏面電極型の太陽電池の製造方法を例示したが、本発明の特徴は、両面電極型の太陽電池の製造方法にも適用可能である。 Further, in the above-described embodiment, the manufacturing method of the back electrode type solar cell is illustrated, but the feature of the present invention can also be applied to the manufacturing method of the double-sided electrode type solar cell.
　また、上述した実施形態では、図２に示すようにヘテロ接合型の太陽電池１の製造方法を例示したが、本発明の特徴は、ヘテロ接合型の太陽電池に限らず、ホモ接合型の太陽電池等の種々の太陽電池の製造方法に適用可能である。 Further, in the above-described embodiment, the method for manufacturing the heterozygous solar cell 1 is illustrated as shown in FIG. 2, but the feature of the present invention is not limited to the heterozygous solar cell, but the homozygous solar cell. It can be applied to various methods for manufacturing solar cells such as batteries.
　また、上述した実施形態では、結晶シリコン基板を有する太陽電池を例示したが、これに限定されない。例えば、太陽電池は、ガリウムヒ素（ＧａＡｓ）基板を有していてもよい。 Further, in the above-described embodiment, a solar cell having a crystalline silicon substrate has been exemplified, but the present invention is not limited to this. For example, a solar cell may have a gallium arsenide (GaAs) substrate.
　１　太陽電池
　７　第１領域
　７ｂ，８ｂ　バスバー部
　７ｆ，８ｆ　フィンガー部
　８　第２領域
　１１　半導体基板
　１３　パッシベーション層
　１５　光学調整層
　２３　パッシベーション層
　２３Ｚ，３３Ｚ　パッシベーション層材料膜
　２５　第１導電型半導体層（パターン化層）
　２５Ｚ　第１導電型半導体層材料膜（非パターン化層）
　２７　第１電極層
　２８，３８　透明電極層（パターン化層）
　２９，３９　金属電極層（パターン化層）
　３３　パッシベーション層
　３５　第２導電型半導体層（パターン化層）
　３５Ｚ　第２導電型半導体層材料膜（非パターン化層）
　３７　第２電極層
　４０，４０Ｘ　レジストパターン
　４０Ｚ　レジスト剤
　４１　連結部分（溝部分） 1 Solar cell 7 1st area 7b, 8b Bus bar part 7f, 8f Finger part 8 2nd area 11 Semiconductor substrate 13 Passivation layer 15 Passivation layer 23 Passivation layer 23Z, 33Z Passivation layer Material film 25 First conductive semiconductor layer (pattern) Passivation)
25Z 1st Conductive Semiconductor Layer Material Film (Non-Patterned Layer)
27 First electrode layer 28,38 Transparent electrode layer (patterned layer)
29,39 Metal electrode layer (patterned layer)
33 Passivation layer 35 Second conductive semiconductor layer (patterned layer)
35Z Second Conductive Semiconductor Layer Material Membrane (Non-Patterned Layer)
37 Second electrode layer 40, 40X Resist pattern 40Z Resist agent 41 Connecting part (groove part)

Claims (8)

  1. 　半導体基板の少なくとも１つの主面側にパターン化層を備える太陽電池の製造方法であって、
    　前記半導体基板の前記主面側に、前記パターン化層の基となるパターン化前の非パターン化層を形成する非パターン化層形成工程と、
    　前記非パターン化層上に、パターン化されたレジスト膜であるレジストパターンを形成するレジストパターン形成工程と、
    　エッチング法を用いて、前記レジストパターンに基づいて前記非パターン化層をパターン化した前記パターン化層を形成するパターン化層形成工程と、
    を含み、
    　前記レジストパターン形成工程では、スクリーン印刷法を用いて、所定間隔だけ分離するようにレジスト剤を印刷し、
    　前記所定間隔とは、前記レジスト剤の流動性により、分離した前記レジスト剤同士が連結して前記レジストパターンを形成し、前記レジストパターンにおいて分離した前記レジスト剤同士が連結した連結部分の厚さが前記連結部分以外の厚さよりも薄くなる、間隔である、
    太陽電池の製造方法。     A method for manufacturing a solar cell having a patterned layer on at least one main surface side of a semiconductor substrate.
    A non-patterned layer forming step of forming a pre-patterned non-patterned layer which is a base of the patterned layer on the main surface side of the semiconductor substrate.
    A resist pattern forming step of forming a resist pattern, which is a patterned resist film, on the non-patterned layer.
    A patterned layer forming step of forming the patterned layer in which the non-patterned layer is patterned based on the resist pattern by using an etching method.
    Including
    In the resist pattern forming step, a resist agent is printed so as to separate by a predetermined interval by using a screen printing method.
    The predetermined interval is the thickness of the connecting portion in which the separated resist agents are linked to each other to form the resist pattern due to the fluidity of the resist agent, and the resist agents separated in the resist pattern are connected to each other. It is an interval that is thinner than the thickness other than the connecting portion.
    How to manufacture solar cells.
  2. 　前記レジストパターン形成工程では、前記レジストパターンにおける、袋小路を形成する部分に前記連結部分を形成する、請求項１に記載の太陽電池の製造方法。 The method for manufacturing a solar cell according to claim 1, wherein in the resist pattern forming step, the connecting portion is formed in a portion of the resist pattern that forms a dead end.
  3. 　前記レジストパターン形成工程では、前記連結部分の延在方向が、前記パターン化層形成工程におけるエッチング溶液に対する前記半導体基板の挿入および取出方向に沿うように、前記連結部分を形成する、請求項１または２に記載の太陽電池の製造方法。 In the resist pattern forming step, the connecting portion is formed so that the extending direction of the connecting portion is along the insertion / removal direction of the semiconductor substrate with respect to the etching solution in the patterning layer forming step. 2. The method for manufacturing a solar cell according to 2.
  4. 　前記パターン化層は、半導体層、透明電極層または金属電極層である、請求項１～３のいずれか１項に記載の太陽電池の製造方法。 The method for manufacturing a solar cell according to any one of claims 1 to 3, wherein the patterned layer is a semiconductor layer, a transparent electrode layer, or a metal electrode layer.
  5. 　前記太陽電池は、前記半導体基板の２つの主面の両方に電極層を備える両面電極型、または、前記半導体基板の２つの主面の一方に電極層を備える裏面電極型である、請求項１～４のいずれか１項に記載の太陽電池の製造方法。 The solar cell is a double-sided electrode type having electrode layers on both of the two main surfaces of the semiconductor substrate, or a back electrode type having an electrode layer on one of the two main surfaces of the semiconductor substrate. The method for manufacturing a solar cell according to any one of 4 to 4.
  6. 　前記レジストパターンを形成するための前記レジスト剤は、チキソトロピー性を有する材料を含む、請求項１～５のいずれか１項に記載の太陽電池の製造方法。 The method for manufacturing a solar cell according to any one of claims 1 to 5, wherein the resist agent for forming the resist pattern contains a material having thixotropy.
  7. 　半導体基板の少なくとも１つの主面側にパターン化層を形成するための太陽電池の仕掛品であって、
    　前記半導体基板の前記主面側に形成された、前記パターン化層の基となるパターン化前の非パターン化層と、
    　前記非パターン化層上に形成された、パターン化したレジスト膜であるレジストパターンと、
    を備え、
    　前記レジストパターンは、他の部分よりも厚さが薄い溝部分を有する、
    太陽電池の仕掛品。     A work-in-process product of a solar cell for forming a patterned layer on at least one main surface side of a semiconductor substrate.
    An unpatterned layer before patterning, which is a base of the patterned layer, formed on the main surface side of the semiconductor substrate, and
    A resist pattern, which is a patterned resist film formed on the non-patterned layer,
    With
    The resist pattern has a groove portion that is thinner than the other portions.
    Work in process of solar cells.
  8. 　前記溝部分は、前記レジストパターンにおける、袋小路を形成する部分に配置される、請求項７に記載の太陽電池の仕掛品。 The work-in-process of the solar cell according to claim 7, wherein the groove portion is arranged in a portion of the resist pattern that forms a dead end.
PCT/JP2020/008626 2019-03-22 2020-03-02 Method for producing solar cell and in-process product of solar cell WO2020195570A1 (en)

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Citations (3)

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JP4168413B2 (en) * 1998-07-27 2008-10-22 シチズンホールディングス株式会社 Manufacturing method of solar cell
US20100047721A1 (en) * 2007-01-31 2010-02-25 Stuart Ross Wenham Method of forming openings in selected material
CN104681641A (en) * 2013-11-29 2015-06-03 比亚迪股份有限公司 Etching resisting agent and preparation method thereof as well as SE (selective emitter) crystalline silicon solar cell and preparation method thereof

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* Cited by examiner, † Cited by third party
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JP2004168413A (en) * 2002-11-18 2004-06-17 Akihide Kanazawa Envelope allowing check of contents

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4168413B2 (en) * 1998-07-27 2008-10-22 シチズンホールディングス株式会社 Manufacturing method of solar cell
US20100047721A1 (en) * 2007-01-31 2010-02-25 Stuart Ross Wenham Method of forming openings in selected material
CN104681641A (en) * 2013-11-29 2015-06-03 比亚迪股份有限公司 Etching resisting agent and preparation method thereof as well as SE (selective emitter) crystalline silicon solar cell and preparation method thereof

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