WO2020218000A1 - Solar cell and method for manufacturing solar cell - Google Patents

Solar cell and method for manufacturing solar cell Download PDF

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WO2020218000A1
WO2020218000A1 PCT/JP2020/015916 JP2020015916W WO2020218000A1 WO 2020218000 A1 WO2020218000 A1 WO 2020218000A1 JP 2020015916 W JP2020015916 W JP 2020015916W WO 2020218000 A1 WO2020218000 A1 WO 2020218000A1
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semiconductor layer
conductive
solar cell
region
type
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PCT/JP2020/015916
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French (fr)
Japanese (ja)
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訓太 吉河
暢 入江
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株式会社カネカ
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Priority to JP2021515970A priority Critical patent/JP7202456B2/en
Publication of WO2020218000A1 publication Critical patent/WO2020218000A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a back surface bonding type (also referred to as a back contact type or a back surface electrode type) solar cell and a method for manufacturing the solar cell.
  • a back surface bonding type also referred to as a back contact type or a back surface electrode type
  • a solar cell using a semiconductor substrate for example, a heterojunction type in which semiconductor layers are formed on both the light receiving surface side and the back surface side (hereinafter, referred to as a double-sided bonding type as opposed to a back surface bonding type, also referred to as a double-sided electrode type).
  • a double-sided bonding type as opposed to a back surface bonding type
  • a double-sided electrode type there are two types of solar cells: a back-side bonded solar cell in which a semiconductor layer is formed only on the back side.
  • an electrode is formed on the light receiving surface side, so that the electrode shields sunlight.
  • the back surface bonded type solar cell since the electrode is not formed on the light receiving surface side, the light receiving rate of sunlight is higher than that of the double-sided bonded type solar cell.
  • Patent Documents 1 and 2 disclose a back surface bonded type solar cell.
  • the solar cells described in Patent Documents 1 and 2 include a semiconductor substrate that functions as a photoelectric conversion layer, a first conductive semiconductor layer formed in a first region that is a part of the back surface side of the semiconductor substrate, and a semiconductor substrate. It includes a second region which is another part on the back surface side, and a second conductive semiconductor layer formed on the first conductive semiconductor layer in the first region. According to such a solar cell, after patterning the first conductive semiconductor layer, the second conductive semiconductor layer may be formed on the entire back surface side of the semiconductor substrate, so that the manufacturing process can be simplified. is there.
  • a method for manufacturing a solar cell there is a method using a CVD (chemical vapor deposition) process and a wet process.
  • CVD chemical vapor deposition
  • CVD process and A first semiconductor layer forming step (patterning) in which the material film of the first conductive semiconductor layer in the second region is removed by using an etching method to form a patterned first conductive semiconductor layer in the first region.
  • a second semiconductor layer forming step (second CVD process) of forming a second conductive semiconductor layer on the first conductive semiconductor layer in the first region and on the intrinsic semiconductor layer in the second region by using the CVD method.
  • second CVD process A second semiconductor layer forming step of forming a second conductive semiconductor layer on the first conductive semiconductor layer in the first region and on the intrinsic semiconductor layer in the second region by using the CVD method.
  • An object of the present invention is to provide a solar cell and a method for manufacturing a solar cell, which can further simplify the manufacturing process and improve the output.
  • the solar cell according to the present invention is a back surface bonded type solar cell, which is a semiconductor substrate, a first region which is a part of one main surface side of the semiconductor substrate, and the one main surface side of the semiconductor substrate.
  • the first conductive type semiconductor layer formed in the second region which is a part of the other, and formed on the first conductive type semiconductor layer which is the first conductive type and the first conductive type semiconductor layer in the second region.
  • a second electrode layer formed on the conductive semiconductor layer is provided.
  • the method for manufacturing a solar cell according to the present invention is a method for manufacturing a back-bonded type solar cell, in which a first region which is a part of one main surface side of the semiconductor substrate and the one main surface side of the semiconductor substrate.
  • the second semiconductor layer forming step of forming the patterned second conductive semiconductor layer in the second region by removing the material film of the conductive semiconductor layer is included.
  • FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG. It is a figure which shows the intrinsic semiconductor layer forming step, the 1st conductive type semiconductor layer forming step, and the 2nd conductive type semiconductor layer material film forming step in the manufacturing method of the solar cell which concerns on this embodiment (CVD process). It is a figure which shows the 2nd semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment (patterning: wet process). It is a figure which shows the 2nd semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment (patterning: wet process). It is a figure which shows the 2nd semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment (patterning: wet process). It is a figure which shows the 2nd semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment (patterning: wet process).
  • FIG. 1 is a view of the solar cell according to the present embodiment as viewed from the back surface side.
  • the solar cell 1 shown in FIG. 1 is a back surface bonded type solar cell.
  • the solar cell 1 includes a semiconductor substrate 11 having two main surfaces, and has a first region 7 and a second region 8 on the main surface of the semiconductor substrate 11.
  • the first region 7 has a so-called comb-shaped shape, and has a plurality of finger portions 7f corresponding to comb teeth and a bus bar portion 7b corresponding to a support portion of the comb teeth.
  • the bus bar portion 7b extends in the first direction (X direction) along one side of the semiconductor substrate 11, and the finger portion 7f extends from the bus bar portion 7b in the second direction (Y direction) intersecting the first direction. ) Extends.
  • the second region 8 has a so-called comb-shaped shape, and has a plurality of finger portions 8f corresponding to the comb teeth and a bus bar portion 8b corresponding to the support portion of the comb teeth.
  • the bus bar portion 8b extends in the first direction (X direction) along the other side portion facing one side portion of the semiconductor substrate 11, and the finger portion 8f extends from the bus bar portion 8b in the second direction (Y). Extends in the direction).
  • the finger portions 7f and the finger portions 8f are alternately provided in the first direction (X direction).
  • the first region 7 and the second region 8 may be formed in a striped shape.
  • FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG.
  • the solar cell 1 is an intrinsic semiconductor layer laminated in order on the semiconductor substrate 11 and the light receiving surface side, which is the main surface (the other main surface) of the semiconductor substrate 11 on the light receiving side. It includes (second intrinsic semiconductor layer) 13 and an optical adjustment layer 15. Further, the solar cell 1 includes a part (first region 7) on the back surface side, which is the main surface (one main surface) on the opposite side of the light receiving surface of the main surface of the semiconductor substrate 11, and another part (second).
  • the solar cell 1 includes a first electrode layer 27 formed in the first region 7 and a second electrode layer 37 formed in the second region 8.
  • the semiconductor substrate 11 is formed of a crystalline silicon material such as single crystal silicon or polycrystalline silicon.
  • the semiconductor substrate 11 is, for example, a p-type semiconductor substrate in which a crystalline silicon material is doped with a p-type dopant. Examples of the p-type dopant include boron (B).
  • the semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light receiving surface side to generate optical carriers (electrons and holes). By using crystalline silicon as the material of the semiconductor substrate 11, a relatively high output (stable output regardless of the illuminance) can be obtained even when the dark current is relatively small and the intensity of the incident light is low.
  • the intrinsic semiconductor layer 13 is formed on the light receiving surface side of the semiconductor substrate 11.
  • the intrinsic semiconductor layer 23 is continuously formed in the first region 7 and the second region 8 on the back surface side of the semiconductor substrate 11, that is, on the entire surface on the back surface side of the semiconductor substrate 11.
  • the intrinsic semiconductor layers 13 and 23 are formed of, for example, a material mainly composed of substantially intrinsic (i-type) amorphous (amorphous) silicon.
  • substantially intrinsic i-type amorphous (amorphous) silicon.
  • substantially true is not limited to a completely true layer that does not contain conductive impurities, but a weak p-type or n-type impurity that contains trace amounts of p-type or n-type impurities to the extent that the silicon-based layer can function as a true layer. It also includes a weak n-type substantially true layer.
  • an aluminum oxide layer may be formed on the light receiving surface side of the semiconductor substrate 11 instead of the intrinsic semiconductor layer 13 (so-called PERK structure).
  • the intrinsic semiconductor layers 13 and 23 function as so-called passivation layers, suppress the recombination of carriers generated in the semiconductor substrate 11, and increase the carrier recovery efficiency.
  • the optical adjustment layer 15 is formed on the intrinsic semiconductor layer 13 (or aluminum oxide layer) on the light receiving surface side of the semiconductor substrate 11.
  • the optical adjustment layer 15 functions as an antireflection layer that prevents reflection of incident light, and also functions as a protective layer that protects the light receiving surface side of the semiconductor substrate 11 and the intrinsic semiconductor layer 13 (or the aluminum oxide layer).
  • the optical adjustment layer 15 is formed of an insulating material such as a composite thereof such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON).
  • the first conductive semiconductor layer 25 is continuously formed in the first region 7 and the second region 8 on the back surface side of the semiconductor substrate 11, that is, so as to cover the entire surface on the back surface side of the semiconductor substrate 11. Specifically, the first conductive semiconductor layer 25 is formed on the intrinsic semiconductor layer 23.
  • the first conductive semiconductor layer 25 is formed of, for example, an amorphous silicon material.
  • the first conductive semiconductor layer 25 may include a microcrystalline silicon layer. Further, the crystallinity of the first conductive semiconductor layer 25 may increase toward the interface on the second conductive semiconductor layer 35 side. That is, the semiconductor substrate 11 side of the first conductive semiconductor layer 25 is an amorphous silicon layer, but in the first conductive semiconductor layer 25, the semiconductor substrate 11 side is directed toward the second conductive semiconductor layer 35 side. The degree of crystallization gradually increases, and the second conductive semiconductor layer 35 side of the first conductive semiconductor layer 25 may be a microcrystalline silicon layer. As a result, the interfacial resistance between the first conductive semiconductor layer 25 and the second conductive semiconductor layer 35 is reduced.
  • the first conductive semiconductor layer 25 is, for example, a p-type semiconductor layer in which an amorphous silicon material (and a microcrystalline silicon layer) is doped with a p-type dopant (for example, the above-mentioned boron (B)).
  • a p-type dopant for example, the above-mentioned boron (B)
  • the second conductive semiconductor layer 35 is formed in the second region 8 on the back surface side of the semiconductor substrate 11. Specifically, the second conductive semiconductor layer 35 is formed on the first conductive semiconductor layer 25 in the second region 8.
  • the second conductive semiconductor layer 35 is formed of, for example, an amorphous silicon material.
  • the second conductive semiconductor layer 35 may include a microcrystalline silicon layer. As a result, the interfacial resistance in the second conductive semiconductor layer 35 is reduced.
  • the second conductive semiconductor layer 35 is, for example, an n-type semiconductor layer in which an amorphous silicon material (and a microcrystalline silicon layer) is doped with an n-type dopant.
  • the n-type dopant include phosphorus (P).
  • the film thickness of the first conductive semiconductor layer 25 is 0.7 nm or more and 6 nm or less, and the film thickness of the second conductive semiconductor layer 35 is 8 nm or more and 60 nm or less.
  • the film thickness is the thickness of the semiconductor layer in the stacking direction (direction intersecting the XY plane).
  • the second conductive semiconductor layer 35 is formed on the semiconductor substrate 11 via the first conductive semiconductor layer 25, and the first conductive semiconductor layer 25 is the semiconductor substrate 11. If the first conductive semiconductor layer 25 is of the same conductive type and the thickness of the first conductive semiconductor layer 25 is sufficiently thin, the minority carriers generated in the semiconductor substrate 11 due to the tunnel effect (tunnel current) are transferred to the second conductive semiconductor layer 35. Can be recovered.
  • the etching rate of the first conductive semiconductor layer 25 with respect to the etching solution may be smaller than the etching rate of the second conductive semiconductor layer 35 with respect to the etching solution (for example, alkaline solution).
  • the first conductive semiconductor layer 25 may be an n-type semiconductor layer
  • the second conductive semiconductor layer 35 may be a p-type semiconductor layer.
  • the etching solution that realizes the above-mentioned etching rate relationship Easy to choose eg, alkaline solution.
  • the semiconductor substrate 11 is the same first conductive type semiconductor substrate as the conductive type of the first conductive type semiconductor layer 25 is illustrated, but the semiconductor substrate 11 is the first conductive type semiconductor layer. It may be a second conductive type semiconductor substrate different from the conductive type 25.
  • the first electrode layer 27 is formed on the first conductive semiconductor layer 25 in the first region 7, and the second electrode layer 37 is formed on the second conductive semiconductor layer 35 in the second region 8. There is.
  • the first electrode layer 27 and the second electrode layer 37 may include a transparent electrode layer and a metal electrode layer, or may include only a metal electrode layer.
  • the transparent electrode layer is formed of a transparent conductive material. Examples of the transparent conductive material include ITO (Indium Tin Oxide: a composite oxide of indium tin oxide and tin oxide) and ZnO (Zinc Oxide: zinc oxide).
  • the metal electrode layer is formed of a conductive paste material containing a metal powder such as silver.
  • FIG. 3A is a diagram showing an intrinsic semiconductor layer forming step, a first conductive type semiconductor layer forming step, and a second conductive type semiconductor layer material film forming step in the method for manufacturing a solar cell according to the present embodiment (CVD process).
  • 3B to 3D are diagrams showing a second semiconductor layer forming step in the method for manufacturing a solar cell according to the present embodiment (patterning: wet process).
  • the intrinsic semiconductor layer 23 is formed on the entire surface of the back surface side of the semiconductor substrate 11, that is, on the first region 7 and the second region 8.
  • Lamination (film formation) intrinsic semiconductor layer forming process.
  • the intrinsic semiconductor layer 13 (or the aluminum oxide layer) and the optical adjustment layer 15 are laminated (film-formed) on the entire surface of the semiconductor substrate 11 on the light receiving surface side.
  • the first conductive semiconductor layer 25 is laminated (film-forming) on the entire surface of the back surface side of the semiconductor substrate 11, that is, on the intrinsic semiconductor layer 23 in the first region 7 and the second region 8. ) (First semiconductor layer forming step).
  • the second conductive semiconductor layer material film 35Z is placed on the entire surface of the back surface side of the semiconductor substrate 11, that is, on the first conductive semiconductor layer 25 in the first region 7 and the second region 8. Is laminated (film-formed) (second semiconductor layer material film forming step).
  • the intrinsic semiconductor layer 23, the first conductive semiconductor layer 25, and the second conductive semiconductor layer material film 35Z are collectively formed on the back surface side of the semiconductor substrate 11 by the CVD process.
  • the semiconductor substrate 11 is removed by removing the second conductive semiconductor layer material film 35Z in the first region 7 on the back surface side of the semiconductor substrate 11, for example, using a resist 90.
  • a patterned second conductive semiconductor layer 35 is formed in the second region 8 on the back surface side of the above (second semiconductor layer forming step).
  • a resist 90 is formed on the second region 8 on the back surface side of the semiconductor substrate 11 and the entire surface on the light receiving surface side by using a photolithography method, a screen printing method, an inkjet coating method, or the like. To do.
  • the second conductive semiconductor layer material film 35Z in the first region 7 on the back surface side of the semiconductor substrate 11 is etched using the resist 90 as a mask, and the second region on the back surface side of the semiconductor substrate 11 is etched.
  • a patterned second conductive semiconductor layer 35 is formed.
  • an alkaline solution is used as the etching solution for the first conductive semiconductor layer material film.
  • the resist 90 is removed.
  • an organic solvent such as acetone is used as the removal solution for the resist 90.
  • the alkaline solution has a higher etching rate than the n-type semiconductor layer and a lower etching rate than the p-type semiconductor layer.
  • the etching rate of the first conductive semiconductor layer 25 with respect to the etching solution becomes smaller than the etching rate of the second conductive semiconductor layer 35 with respect to the etching solution.
  • the first electrode layer 27 and the second electrode layer 37 are formed on the back surface side of the semiconductor substrate 11 (electrode layer forming step).
  • a PVD method physical vapor deposition method
  • a sputtering method is used to laminate (film) a transparent electrode layer material film on the entire back surface side of the semiconductor substrate 11.
  • the transparent electrode layer is patterned by removing a part of the transparent electrode layer material film by, for example, an etching method using an etching paste.
  • the etching solution for the transparent electrode layer material film for example, hydrochloric acid or an aqueous ferric chloride solution is used.
  • the first electrode layer 27 and the second electrode layer 37 are formed by forming the metal electrode layer on the transparent electrode layer by using, for example, a pattern printing method or a coating method.
  • the first conductive semiconductor layer 25 and the second conductive semiconductor layer material film are collectively formed by the CVD process, and then wet.
  • the process only the second conductive semiconductor layer material film in the first region 7 can be selectively etched to leave the first conductive semiconductor layer 25 in the first region 7.
  • the number of CVD processes required twice in the solar cell configurations described in Patent Documents 1 and 2 is reduced to one, and the manufacturing process can be further simplified and the cost can be reduced.
  • the film is continuously formed by the CVD process, the interfacial resistance in the first conductive semiconductor layer 25 and the second conductive semiconductor layer 35 is reduced, and the output of the solar cell is improved.
  • the present invention is not limited to the above-described embodiments, and various modifications and modifications can be made.
  • the method for manufacturing the heterozygous solar cell 1 is illustrated as shown in FIG. 2, but the feature of the present invention is not limited to the heterozygous solar cell, but the homozygous solar cell. It can be applied to various methods for manufacturing solar cells such as batteries.
  • a solar cell having a crystalline silicon substrate has been exemplified, but the present invention is not limited to this.
  • a solar cell may have a gallium arsenide (GaAs) substrate.
  • GaAs gallium arsenide

Abstract

Provided is a solar cell which enables simplification of manufacturing process and an increase in output. A solar cell 1, which is a back junction solar cell, comprises: a semiconductor substrate 11; a first conductivity-type semiconductor layer 25 of a first conductivity type which is formed in a first region 7, which is a part of a back side of the semiconductor substrate 11, and in a second region 8, which is another part of the back side of the semiconductor substrate 11; a second conductivity-type semiconductor layer 35 of a second conductivity type opposite to the first conductivity type which is formed on the first conductivity-type semiconductor layer 25 in the second region 8; a first electrode layer 27 formed on the first conductivity-type semiconductor layer 25 in the first region 7; and a second electrode layer 37 formed on the second conductivity-type semiconductor layer 35 in the second region 8.

Description

太陽電池および太陽電池の製造方法Solar cells and methods of manufacturing solar cells
　本発明は、裏面接合型（バックコンタクト型、裏面電極型ともいう。）の太陽電池および太陽電池の製造方法に関する。 The present invention relates to a back surface bonding type (also referred to as a back contact type or a back surface electrode type) solar cell and a method for manufacturing the solar cell.
　半導体基板を用いた太陽電池として、受光面側および裏面側の両面に半導体層が形成された例えばヘテロ接合型（以下、裏面接合型に対して両面接合型と称する。両面電極型ともいう。）の太陽電池と、裏面側のみに半導体層が形成された裏面接合型の太陽電池とがある。両面接合型の太陽電池では、受光面側に電極が形成されるため、この電極により太陽光が遮蔽されてしまう。一方、裏面接合型の太陽電池では、受光面側に電極が形成されないため、両面接合型の太陽電池と比較して太陽光の受光率が高い。特許文献１および２には、裏面接合型の太陽電池が開示されている。 As a solar cell using a semiconductor substrate, for example, a heterojunction type in which semiconductor layers are formed on both the light receiving surface side and the back surface side (hereinafter, referred to as a double-sided bonding type as opposed to a back surface bonding type, also referred to as a double-sided electrode type). There are two types of solar cells: a back-side bonded solar cell in which a semiconductor layer is formed only on the back side. In a double-sided solar cell, an electrode is formed on the light receiving surface side, so that the electrode shields sunlight. On the other hand, in the back surface bonded type solar cell, since the electrode is not formed on the light receiving surface side, the light receiving rate of sunlight is higher than that of the double-sided bonded type solar cell. Patent Documents 1 and 2 disclose a back surface bonded type solar cell.
　特許文献１および２に記載の太陽電池は、光電変換層として機能する半導体基板と、半導体基板の裏面側の一部である第１領域に形成された第１導電型半導体層と、半導体基板の裏面側の他の一部である第２領域、および第１領域の第１導電型半導体層上に形成された第２導電型半導体層とを備える。このような太陽電池によれば、第１導電型半導体層をパターニングした後、第２導電型半導体層を半導体基板の裏面側の全面に製膜すればよいので、製造プロセスの簡略化が可能である。 The solar cells described in Patent Documents 1 and 2 include a semiconductor substrate that functions as a photoelectric conversion layer, a first conductive semiconductor layer formed in a first region that is a part of the back surface side of the semiconductor substrate, and a semiconductor substrate. It includes a second region which is another part on the back surface side, and a second conductive semiconductor layer formed on the first conductive semiconductor layer in the first region. According to such a solar cell, after patterning the first conductive semiconductor layer, the second conductive semiconductor layer may be formed on the entire back surface side of the semiconductor substrate, so that the manufacturing process can be simplified. is there.
特開２００５－１０１１５１号公報Japanese Unexamined Patent Publication No. 2005-101151 国際公開第２０１４／００２２５７号International Publication No. 2014/002257
　このような太陽電池の製造方法の一例として、ＣＶＤ（化学気相堆積法）プロセスとウエットプロセスとを用いる方法がある。このような方法では、
・ＣＶＤ法を用いて、半導体基板の裏面側の第１領域および第２領域に、真性半導体層および第１導電型半導体層の材料膜を形成する第１半導体層材料膜形成工程（１回目のＣＶＤプロセス）と、
・エッチング法を用いて、第２領域における第１導電型半導体層の材料膜を除去し、第１領域に、パターン化された第１導電型半導体層を形成する第１半導体層形成工程（パターニング：ウエットプロセス）と、
・ＣＶＤ法を用いて、第１領域における第１導電型半導体層上および第２領域における真性半導体層上に、第２導電型半導体層を形成する第２半導体層形成工程（２回目ＣＶＤプロセス）と、
を含む。このような太陽電池の製造方法では、２回のＣＶＤプロセスとウエットプロセスとを交互に行う必要があり、太陽電池の出力低下が予想される。 As an example of such a method for manufacturing a solar cell, there is a method using a CVD (chemical vapor deposition) process and a wet process. In this way,
A first semiconductor layer material film forming step of forming a material film of an intrinsic semiconductor layer and a first conductive semiconductor layer in the first region and the second region on the back surface side of a semiconductor substrate by using a CVD method (first time). CVD process) and
A first semiconductor layer forming step (patterning) in which the material film of the first conductive semiconductor layer in the second region is removed by using an etching method to form a patterned first conductive semiconductor layer in the first region. : Wet process) and
A second semiconductor layer forming step (second CVD process) of forming a second conductive semiconductor layer on the first conductive semiconductor layer in the first region and on the intrinsic semiconductor layer in the second region by using the CVD method. When,
including. In such a method for manufacturing a solar cell, it is necessary to alternately perform two CVD processes and a wet process, and it is expected that the output of the solar cell will decrease.
　本発明は、更なる製造プロセスの簡略化と出力の向上が可能である太陽電池および太陽電池の製造方法を提供することを目的とする。 An object of the present invention is to provide a solar cell and a method for manufacturing a solar cell, which can further simplify the manufacturing process and improve the output.
　本発明に係る太陽電池は、裏面接合型の太陽電池であって、半導体基板と、前記半導体基板の一方主面側の一部である第１領域、および前記半導体基板の前記一方主面側の他の一部である第２領域に形成され、第１導電型である第１導電型半導体層と、前記第２領域における前記第１導電型半導体層の上に形成され、前記第１導電型とは逆の第２導電型である第２導電型半導体層と、前記第１領域における前記第１導電型半導体層の上に形成された第１電極層と、前記第２領域における前記第２導電型半導体層の上に形成された第２電極層と、を備える。 The solar cell according to the present invention is a back surface bonded type solar cell, which is a semiconductor substrate, a first region which is a part of one main surface side of the semiconductor substrate, and the one main surface side of the semiconductor substrate. The first conductive type semiconductor layer formed in the second region which is a part of the other, and formed on the first conductive type semiconductor layer which is the first conductive type and the first conductive type semiconductor layer in the second region. A second conductive semiconductor layer which is the opposite of the second conductive type, a first electrode layer formed on the first conductive semiconductor layer in the first region, and the second electrode layer in the second region. A second electrode layer formed on the conductive semiconductor layer is provided.
　本発明に係る太陽電池の製造方法は、裏面接合型の太陽電池の製造方法であって、半導体基板の一方主面側の一部である第１領域、および前記半導体基板の前記一方主面側の他の一部である第２領域に、第１導電型である第１導電型半導体層を形成する第１半導体層形成工程と、前記第１領域および前記第２領域における前記第１導電型半導体層の上に、前記第１導電型とは逆の第２導電型である第２導電型半導体層の材料膜を形成する第２半導体層材料膜形成工程と、前記第１領域における前記第２導電型半導体層の材料膜を除去することにより、前記第２領域に、パターン化された前記第２導電型半導体層を形成する第２半導体層形成工程と、を含む。 The method for manufacturing a solar cell according to the present invention is a method for manufacturing a back-bonded type solar cell, in which a first region which is a part of one main surface side of the semiconductor substrate and the one main surface side of the semiconductor substrate. A first semiconductor layer forming step of forming a first conductive type semiconductor layer which is a first conductive type in a second region which is another part, and the first conductive type in the first region and the second region. A second semiconductor layer material film forming step of forming a material film of a second conductive type semiconductor layer, which is a second conductive type opposite to the first conductive type, on the semiconductor layer, and the first in the first region. 2. The second semiconductor layer forming step of forming the patterned second conductive semiconductor layer in the second region by removing the material film of the conductive semiconductor layer is included.
　本発明によれば、太陽電池の製造プロセスの簡略化および太陽電池の出力の向上が可能である。 According to the present invention, it is possible to simplify the manufacturing process of the solar cell and improve the output of the solar cell.
本実施形態に係る太陽電池を裏面側からみた図である。It is the figure which looked at the solar cell which concerns on this embodiment from the back side. 図１の太陽電池におけるII－II線断面図である。FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG. 本実施形態に係る太陽電池の製造方法における真性半導体層形成工程、第１導電型半導体層形成工程、および第２導電型半導体層材料膜形成工程を示す図である（ＣＶＤプロセス）。It is a figure which shows the intrinsic semiconductor layer forming step, the 1st conductive type semiconductor layer forming step, and the 2nd conductive type semiconductor layer material film forming step in the manufacturing method of the solar cell which concerns on this embodiment (CVD process). 本実施形態に係る太陽電池の製造方法における第２半導体層形成工程を示す図である（パターニング：ウエットプロセス）。It is a figure which shows the 2nd semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment (patterning: wet process). 本実施形態に係る太陽電池の製造方法における第２半導体層形成工程を示す図である（パターニング：ウエットプロセス）。It is a figure which shows the 2nd semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment (patterning: wet process). 本実施形態に係る太陽電池の製造方法における第２半導体層形成工程を示す図である（パターニング：ウエットプロセス）。It is a figure which shows the 2nd semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment (patterning: wet process).
　以下、添付の図面を参照して本発明の実施形態の一例について説明する。なお、各図面において同一または相当の部分に対しては同一の符号を附すこととする。また、便宜上、ハッチングや部材符号等を省略する場合もあるが、かかる場合、他の図面を参照するものとする。 Hereinafter, an example of the embodiment of the present invention will be described with reference to the accompanying drawings. In addition, the same reference numerals are given to the same or corresponding parts in each drawing. Further, for convenience, hatching, member codes, etc. may be omitted, but in such cases, other drawings shall be referred to.
（太陽電池）
　図１は、本実施形態に係る太陽電池を裏面側からみた図である。図１に示す太陽電池１は、裏面接合型の太陽電池である。太陽電池１は、２つの主面を備える半導体基板１１を備え、半導体基板１１の主面において第１領域７と第２領域８とを有する。 (Solar cell)
FIG. 1 is a view of the solar cell according to the present embodiment as viewed from the back surface side. The solar cell 1 shown in FIG. 1 is a back surface bonded type solar cell. The solar cell 1 includes a semiconductor substrate 11 having two main surfaces, and has a first region 7 and a second region 8 on the main surface of the semiconductor substrate 11.
　第１領域７は、いわゆる櫛型の形状をなし、櫛歯に相当する複数のフィンガー部７ｆと、櫛歯の支持部に相当するバスバー部７ｂとを有する。バスバー部７ｂは、半導体基板１１の一方の辺部に沿って第１方向（Ｘ方向）に延在し、フィンガー部７ｆは、バスバー部７ｂから、第１方向に交差する第２方向（Ｙ方向）に延在する。
　同様に、第２領域８は、いわゆる櫛型の形状であり、櫛歯に相当する複数のフィンガー部８ｆと、櫛歯の支持部に相当するバスバー部８ｂとを有する。バスバー部８ｂは、半導体基板１１の一方の辺部に対向する他方の辺部に沿って第１方向（Ｘ方向）に延在し、フィンガー部８ｆは、バスバー部８ｂから、第２方向（Ｙ方向）に延在する。
　フィンガー部７ｆとフィンガー部８ｆとは、第１方向（Ｘ方向）に交互に設けられている。
　なお、第１領域７および第２領域８は、ストライプ状に形成されてもよい。 The first region 7 has a so-called comb-shaped shape, and has a plurality of finger portions 7f corresponding to comb teeth and a bus bar portion 7b corresponding to a support portion of the comb teeth. The bus bar portion 7b extends in the first direction (X direction) along one side of the semiconductor substrate 11, and the finger portion 7f extends from the bus bar portion 7b in the second direction (Y direction) intersecting the first direction. ) Extends.
Similarly, the second region 8 has a so-called comb-shaped shape, and has a plurality of finger portions 8f corresponding to the comb teeth and a bus bar portion 8b corresponding to the support portion of the comb teeth. The bus bar portion 8b extends in the first direction (X direction) along the other side portion facing one side portion of the semiconductor substrate 11, and the finger portion 8f extends from the bus bar portion 8b in the second direction (Y). Extends in the direction).
The finger portions 7f and the finger portions 8f are alternately provided in the first direction (X direction).
The first region 7 and the second region 8 may be formed in a striped shape.
　図２は、図１の太陽電池におけるII－II線断面図である。図２に示すように、太陽電池１は、半導体基板１１と、半導体基板１１の主面のうちの受光する側の主面（他方主面）である受光面側に順に積層された真性半導体層（第２真性半導体層）１３および光学調整層１５を備える。また、太陽電池１は、半導体基板１１の主面のうちの受光面の反対側の主面（一方主面）である裏面側の一部（第１領域７）および他の一部（第２領域８）に順に積層された真性半導体層（第１真性半導体層）２３および第１導電型半導体層２５と、半導体基板１１の裏面側の第２領域８の第１導電型半導体層２５上に積層された第２導電型半導体層３５とを備える。また、太陽電池１は、第１領域７に形成された第１電極層２７と、第２領域８に形成された第２電極層３７とを備える。 FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG. As shown in FIG. 2, the solar cell 1 is an intrinsic semiconductor layer laminated in order on the semiconductor substrate 11 and the light receiving surface side, which is the main surface (the other main surface) of the semiconductor substrate 11 on the light receiving side. It includes (second intrinsic semiconductor layer) 13 and an optical adjustment layer 15. Further, the solar cell 1 includes a part (first region 7) on the back surface side, which is the main surface (one main surface) on the opposite side of the light receiving surface of the main surface of the semiconductor substrate 11, and another part (second). On the intrinsic semiconductor layer (first intrinsic semiconductor layer) 23 and the first conductive semiconductor layer 25 laminated in order in the region 8), and on the first conductive semiconductor layer 25 of the second region 8 on the back surface side of the semiconductor substrate 11. It includes a laminated second conductive semiconductor layer 35. Further, the solar cell 1 includes a first electrode layer 27 formed in the first region 7 and a second electrode layer 37 formed in the second region 8.
　半導体基板１１は、単結晶シリコンまたは多結晶シリコン等の結晶シリコン材料で形成される。半導体基板１１は、例えば結晶シリコン材料にｐ型ドーパントがドープされたｐ型の半導体基板である。ｐ型ドーパントとしては、例えばホウ素（Ｂ）が挙げられる。
　半導体基板１１は、受光面側からの入射光を吸収して光キャリア（電子および正孔）を生成する光電変換基板として機能する。
　半導体基板１１の材料として結晶シリコンが用いられることにより、暗電流が比較的に小さく、入射光の強度が低い場合であっても比較的高出力（照度によらず安定した出力）が得られる。 The semiconductor substrate 11 is formed of a crystalline silicon material such as single crystal silicon or polycrystalline silicon. The semiconductor substrate 11 is, for example, a p-type semiconductor substrate in which a crystalline silicon material is doped with a p-type dopant. Examples of the p-type dopant include boron (B).
The semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light receiving surface side to generate optical carriers (electrons and holes).
By using crystalline silicon as the material of the semiconductor substrate 11, a relatively high output (stable output regardless of the illuminance) can be obtained even when the dark current is relatively small and the intensity of the incident light is low.
　真性半導体層１３は、半導体基板１１の受光面側に形成されている。真性半導体層２３は、半導体基板１１の裏面側の第１領域７および第２領域８に、すなわち半導体基板１１の裏面側の全面に連続して形成されている。真性半導体層１３，２３は、例えば実質的に真性（ｉ型）なアモルファス（非晶質）シリコンを主成分とする材料で形成される。実質的に真性とは、導電型不純物を含まない完全に真性である層に限られず、シリコン系層が真性層として機能し得る範囲で微量のｐ型不純物またはｎ型不純物を含む弱ｐ型または弱ｎ型の実質的に真性な層も包含する。 The intrinsic semiconductor layer 13 is formed on the light receiving surface side of the semiconductor substrate 11. The intrinsic semiconductor layer 23 is continuously formed in the first region 7 and the second region 8 on the back surface side of the semiconductor substrate 11, that is, on the entire surface on the back surface side of the semiconductor substrate 11. The intrinsic semiconductor layers 13 and 23 are formed of, for example, a material mainly composed of substantially intrinsic (i-type) amorphous (amorphous) silicon. Substantially true is not limited to a completely true layer that does not contain conductive impurities, but a weak p-type or n-type impurity that contains trace amounts of p-type or n-type impurities to the extent that the silicon-based layer can function as a true layer. It also includes a weak n-type substantially true layer.
　なお、半導体基板１１がｐ型半導体基板である場合、半導体基板１１の受光面側には、真性半導体層１３に代えて酸化アルミニウム層が形成されてもよい（所謂、ＰＥＲＫ構造）。 When the semiconductor substrate 11 is a p-type semiconductor substrate, an aluminum oxide layer may be formed on the light receiving surface side of the semiconductor substrate 11 instead of the intrinsic semiconductor layer 13 (so-called PERK structure).
　真性半導体層１３，２３（および、酸化アルミニウム層）は、いわゆるパッシベーション層として機能し、半導体基板１１で生成されたキャリアの再結合を抑制し、キャリアの回収効率を高める。 The intrinsic semiconductor layers 13 and 23 (and the aluminum oxide layer) function as so-called passivation layers, suppress the recombination of carriers generated in the semiconductor substrate 11, and increase the carrier recovery efficiency.
　光学調整層１５は、半導体基板１１の受光面側の真性半導体層１３（または、酸化アルミニウム層）上に形成されている。光学調整層１５は、入射光の反射を防止する反射防止層として機能するとともに、半導体基板１１の受光面側および真性半導体層１３（または、酸化アルミニウム層）を保護する保護層として機能する。光学調整層１５は、例えば酸化珪素（ＳｉＯ）、窒化珪素（ＳｉＮ）、または酸窒化珪素（ＳｉＯＮ）のようなそれらの複合物等の絶縁体材料で形成される。 The optical adjustment layer 15 is formed on the intrinsic semiconductor layer 13 (or aluminum oxide layer) on the light receiving surface side of the semiconductor substrate 11. The optical adjustment layer 15 functions as an antireflection layer that prevents reflection of incident light, and also functions as a protective layer that protects the light receiving surface side of the semiconductor substrate 11 and the intrinsic semiconductor layer 13 (or the aluminum oxide layer). The optical adjustment layer 15 is formed of an insulating material such as a composite thereof such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON).
　第１導電型半導体層２５は、半導体基板１１の裏面側の第１領域７および第２領域８に、すなわち半導体基板１１の裏面側の全面を覆うように連続して形成されている。具体的には、第１導電型半導体層２５は、真性半導体層２３上に形成されている。第１導電型半導体層２５は、例えばアモルファス（非晶質）シリコン材料で形成される。 The first conductive semiconductor layer 25 is continuously formed in the first region 7 and the second region 8 on the back surface side of the semiconductor substrate 11, that is, so as to cover the entire surface on the back surface side of the semiconductor substrate 11. Specifically, the first conductive semiconductor layer 25 is formed on the intrinsic semiconductor layer 23. The first conductive semiconductor layer 25 is formed of, for example, an amorphous silicon material.
　第１導電型半導体層２５は、微結晶シリコン層を含んでいてもよい。また、第１導電型半導体層２５の結晶化度は、第２導電型半導体層３５側の界面に向けて、増大していてもよい。すなわち、第１導電型半導体層２５の半導体基板１１側はアモルファス（非晶質）シリコン層であるが、第１導電型半導体層２５において半導体基板１１側から第２導電型半導体層３５側へ向けて次第に結晶化度が増大し、第１導電型半導体層２５の第２導電型半導体層３５側は微結晶シリコン層であってもよい。これにより、第１導電型半導体層２５と第２導電型半導体層３５との間の界面抵抗が小さくなる。 The first conductive semiconductor layer 25 may include a microcrystalline silicon layer. Further, the crystallinity of the first conductive semiconductor layer 25 may increase toward the interface on the second conductive semiconductor layer 35 side. That is, the semiconductor substrate 11 side of the first conductive semiconductor layer 25 is an amorphous silicon layer, but in the first conductive semiconductor layer 25, the semiconductor substrate 11 side is directed toward the second conductive semiconductor layer 35 side. The degree of crystallization gradually increases, and the second conductive semiconductor layer 35 side of the first conductive semiconductor layer 25 may be a microcrystalline silicon layer. As a result, the interfacial resistance between the first conductive semiconductor layer 25 and the second conductive semiconductor layer 35 is reduced.
　第１導電型半導体層２５は、例えばアモルファスシリコン材料（および、微結晶シリコン層）にｐ型ドーパント（例えば、上述したホウ素（Ｂ））がドープされたｐ型半導体層である。 The first conductive semiconductor layer 25 is, for example, a p-type semiconductor layer in which an amorphous silicon material (and a microcrystalline silicon layer) is doped with a p-type dopant (for example, the above-mentioned boron (B)).
　第２導電型半導体層３５は、半導体基板１１の裏面側の第２領域８に形成されている。具体的には、第２導電型半導体層３５は、第２領域８における第１導電型半導体層２５上に形成されている。第２導電型半導体層３５は、例えばアモルファスシリコン材料で形成される。 The second conductive semiconductor layer 35 is formed in the second region 8 on the back surface side of the semiconductor substrate 11. Specifically, the second conductive semiconductor layer 35 is formed on the first conductive semiconductor layer 25 in the second region 8. The second conductive semiconductor layer 35 is formed of, for example, an amorphous silicon material.
　第２導電型半導体層３５は微結晶シリコン層を含んでもよい。これにより、第２導電型半導体層３５における界面抵抗が小さくなる。 The second conductive semiconductor layer 35 may include a microcrystalline silicon layer. As a result, the interfacial resistance in the second conductive semiconductor layer 35 is reduced.
　第２導電型半導体層３５は、例えばアモルファスシリコン材料（および、微結晶シリコン層）にｎ型ドーパントがドープされたｎ型の半導体層である。ｎ型ドーパントとしては、例えばリン（Ｐ）が挙げられる。 The second conductive semiconductor layer 35 is, for example, an n-type semiconductor layer in which an amorphous silicon material (and a microcrystalline silicon layer) is doped with an n-type dopant. Examples of the n-type dopant include phosphorus (P).
　第１導電型半導体層２５の膜厚は、０．７ｎｍ以上６ｎｍ以下であり、第２導電型半導体層３５の膜厚は、８ｎｍ以上６０ｎｍ以下である。膜厚とは、半導体層の積層方向（ＸＹ平面に交差する方向）の厚さである。 The film thickness of the first conductive semiconductor layer 25 is 0.7 nm or more and 6 nm or less, and the film thickness of the second conductive semiconductor layer 35 is 8 nm or more and 60 nm or less. The film thickness is the thickness of the semiconductor layer in the stacking direction (direction intersecting the XY plane).
　ここで、第２領域８において、第２導電型半導体層３５は、第１導電型半導体層２５を介して半導体基板１１上に形成されるが、第１導電型半導体層２５が半導体基板１１と同一の導電型であり、かつ、第１導電型半導体層２５の膜厚が十分に薄いと、トンネル効果（トンネル電流）により、半導体基板１１で生じた少数キャリアを第２導電型半導体層３５で回収することができる。 Here, in the second region 8, the second conductive semiconductor layer 35 is formed on the semiconductor substrate 11 via the first conductive semiconductor layer 25, and the first conductive semiconductor layer 25 is the semiconductor substrate 11. If the first conductive semiconductor layer 25 is of the same conductive type and the thickness of the first conductive semiconductor layer 25 is sufficiently thin, the minority carriers generated in the semiconductor substrate 11 due to the tunnel effect (tunnel current) are transferred to the second conductive semiconductor layer 35. Can be recovered.
　第１導電型半導体層２５のエッチング溶液（例えば、アルカリ溶液）に対するエッチングレートは、第２導電型半導体層３５のエッチング溶液（例えば、アルカリ溶液）に対するエッチングレートよりも小さくてもよい。これにより、ＣＶＤプロセスによって第１導電型半導体層２５および第２導電型半導体層材料膜を一括製膜した後、ウエットプロセスにおいて、第１領域７における第２導電型半導体層材料膜のみを選択的にエッチングし、第１領域７に第１導電型半導体層２５を残すことができる（詳細は後述する）。 The etching rate of the first conductive semiconductor layer 25 with respect to the etching solution (for example, alkaline solution) may be smaller than the etching rate of the second conductive semiconductor layer 35 with respect to the etching solution (for example, alkaline solution). As a result, after the first conductive semiconductor layer 25 and the second conductive semiconductor layer material film are collectively formed by the CVD process, only the second conductive semiconductor layer material film in the first region 7 is selectively selected in the wet process. The first conductive semiconductor layer 25 can be left in the first region 7 (details will be described later).
　なお、第１導電型半導体層２５がｎ型半導体層であり、第２導電型半導体層３５がｐ型半導体層であってもよい。なお、上述したように、第１導電型半導体層２５がｐ型半導体層であり、第２導電型半導体層３５がｎ型半導体層であると、上述したエッチングレートの関係を実現するエッチング溶液の選択が容易である（例えば、アルカリ溶液）。 The first conductive semiconductor layer 25 may be an n-type semiconductor layer, and the second conductive semiconductor layer 35 may be a p-type semiconductor layer. As described above, when the first conductive type semiconductor layer 25 is a p-type semiconductor layer and the second conductive type semiconductor layer 35 is an n-type semiconductor layer, the etching solution that realizes the above-mentioned etching rate relationship Easy to choose (eg, alkaline solution).
　また、上述した実施形態では、半導体基板１１が第１導電型半導体層２５の導電型と同一の第１導電型の半導体基板である形態を例示したが、半導体基板１１は第１導電型半導体層２５の導電型と異なる第２導電型の半導体基板であってもよい。 Further, in the above-described embodiment, the embodiment in which the semiconductor substrate 11 is the same first conductive type semiconductor substrate as the conductive type of the first conductive type semiconductor layer 25 is illustrated, but the semiconductor substrate 11 is the first conductive type semiconductor layer. It may be a second conductive type semiconductor substrate different from the conductive type 25.
　第１電極層２７は、第１領域７における第１導電型半導体層２５上に形成されており、第２電極層３７は、第２領域８における第２導電型半導体層３５上に形成されている。
　第１電極層２７および第２電極層３７は、透明電極層と金属電極層とを含んでもよいし、金属電極層のみを含んでもよい。透明電極層は、透明な導電性材料で形成される。透明導電性材料としては、ＩＴＯ（Indium Tin Oxide：酸化インジウムおよび酸化スズの複合酸化物）、ＺｎＯ（Zinc Oxide：酸化亜鉛）が挙げられる。金属電極層は、銀等の金属粉末を含有する導電性ペースト材料で形成される。 The first electrode layer 27 is formed on the first conductive semiconductor layer 25 in the first region 7, and the second electrode layer 37 is formed on the second conductive semiconductor layer 35 in the second region 8. There is.
The first electrode layer 27 and the second electrode layer 37 may include a transparent electrode layer and a metal electrode layer, or may include only a metal electrode layer. The transparent electrode layer is formed of a transparent conductive material. Examples of the transparent conductive material include ITO (Indium Tin Oxide: a composite oxide of indium tin oxide and tin oxide) and ZnO (Zinc Oxide: zinc oxide). The metal electrode layer is formed of a conductive paste material containing a metal powder such as silver.
（太陽電池の製造方法）
　以下、図３Ａ～図３Ｄを参照して、図１および図２に示す本実施形態の太陽電池１の製造方法について説明する。図３Ａは、本実施形態に係る太陽電池の製造方法における真性半導体層形成工程、第１導電型半導体層形成工程、および第２導電型半導体層材料膜形成工程を示す図であり（ＣＶＤプロセス）、図３Ｂ～図３Ｄは、本実施形態に係る太陽電池の製造方法における第２半導体層形成工程を示す図である（パターニング：ウエットプロセス）。 (Solar cell manufacturing method)
Hereinafter, the method for manufacturing the solar cell 1 of the present embodiment shown in FIGS. 1 and 2 will be described with reference to FIGS. 3A to 3D. FIG. 3A is a diagram showing an intrinsic semiconductor layer forming step, a first conductive type semiconductor layer forming step, and a second conductive type semiconductor layer material film forming step in the method for manufacturing a solar cell according to the present embodiment (CVD process). 3B to 3D are diagrams showing a second semiconductor layer forming step in the method for manufacturing a solar cell according to the present embodiment (patterning: wet process).
　まず、図３Ａに示すように、例えばＣＶＤ法（化学気相堆積法）を用いて、半導体基板１１の裏面側の全面に、すなわち第１領域７および第２領域８に、真性半導体層２３を積層（製膜）する（真性半導体層形成工程）。
　また、例えばＣＶＤ法を用いて、半導体基板１１の受光面側の全面に、真性半導体層１３（または、酸化アルミニウム層）、および光学調整層１５を積層（製膜）する。 First, as shown in FIG. 3A, for example, by using a CVD method (chemical vapor deposition method), the intrinsic semiconductor layer 23 is formed on the entire surface of the back surface side of the semiconductor substrate 11, that is, on the first region 7 and the second region 8. Lamination (film formation) (intrinsic semiconductor layer forming process).
Further, for example, by using a CVD method, the intrinsic semiconductor layer 13 (or the aluminum oxide layer) and the optical adjustment layer 15 are laminated (film-formed) on the entire surface of the semiconductor substrate 11 on the light receiving surface side.
　次に、例えばＣＶＤ法を用いて、半導体基板１１の裏面側の全面に、すなわち第１領域７および第２領域８における真性半導体層２３上に、第１導電型半導体層２５を積層（製膜）する（第１半導体層形成工程）。 Next, for example, using a CVD method, the first conductive semiconductor layer 25 is laminated (film-forming) on the entire surface of the back surface side of the semiconductor substrate 11, that is, on the intrinsic semiconductor layer 23 in the first region 7 and the second region 8. ) (First semiconductor layer forming step).
　次に、例えばＣＶＤ法を用いて、半導体基板１１の裏面側の全面に、すなわち第１領域７および第２領域８における第１導電型半導体層２５上に、第２導電型半導体層材料膜３５Ｚを積層（製膜）する（第２半導体層材料膜形成工程）。 Next, for example, using the CVD method, the second conductive semiconductor layer material film 35Z is placed on the entire surface of the back surface side of the semiconductor substrate 11, that is, on the first conductive semiconductor layer 25 in the first region 7 and the second region 8. Is laminated (film-formed) (second semiconductor layer material film forming step).
　このように、ＣＶＤプロセスによって、半導体基板１１の裏面側に、真性半導体層２３、第１導電型半導体層２５、および第２導電型半導体層材料膜３５Ｚを一括製膜する。 In this way, the intrinsic semiconductor layer 23, the first conductive semiconductor layer 25, and the second conductive semiconductor layer material film 35Z are collectively formed on the back surface side of the semiconductor substrate 11 by the CVD process.
　次に、図３Ｂ～図３Ｄに示すように、例えばレジスト９０を用いて、半導体基板１１の裏面側の第１領域７における第２導電型半導体層材料膜３５Ｚを除去することにより、半導体基板１１の裏面側の第２領域８に、パターン化された第２導電型半導体層３５を形成する（第２半導体層形成工程）。 Next, as shown in FIGS. 3B to 3D, the semiconductor substrate 11 is removed by removing the second conductive semiconductor layer material film 35Z in the first region 7 on the back surface side of the semiconductor substrate 11, for example, using a resist 90. A patterned second conductive semiconductor layer 35 is formed in the second region 8 on the back surface side of the above (second semiconductor layer forming step).
　具体的には、図３Ｂに示すように、フォトリソグラフィ法、スクリーン印刷法、インクジェット塗布法等を用いて、半導体基板１１の裏面側の第２領域８および受光面側の全面にレジスト９０を形成する。 Specifically, as shown in FIG. 3B, a resist 90 is formed on the second region 8 on the back surface side of the semiconductor substrate 11 and the entire surface on the light receiving surface side by using a photolithography method, a screen printing method, an inkjet coating method, or the like. To do.
　その後、図３Ｃに示すように、レジスト９０をマスクとして、半導体基板１１の裏面側の第１領域７における第２導電型半導体層材料膜３５Ｚをエッチングし、半導体基板１１の裏面側の第２領域８に、パターン化された第２導電型半導体層３５を形成する。第１導電型半導体層材料膜に対するエッチング溶液としては、例えばアルカリ溶液が用いられる。 Then, as shown in FIG. 3C, the second conductive semiconductor layer material film 35Z in the first region 7 on the back surface side of the semiconductor substrate 11 is etched using the resist 90 as a mask, and the second region on the back surface side of the semiconductor substrate 11 is etched. In 8, a patterned second conductive semiconductor layer 35 is formed. As the etching solution for the first conductive semiconductor layer material film, for example, an alkaline solution is used.
　その後、図３Ｄに示すように、レジスト９０を除去する。レジスト９０に対する除去溶液としては、例えばアセトン等の有機溶剤が用いられる。 After that, as shown in FIG. 3D, the resist 90 is removed. As the removal solution for the resist 90, for example, an organic solvent such as acetone is used.
　ここで、アルカリ溶液は、ｎ型半導体層に対してエッチングレートが大きく、ｐ型半導体層に対してエッチングレートが小さい。これにより、第１導電型半導体層２５のエッチング溶液に対するエッチングレートが、第２導電型半導体層３５のエッチング溶液に対するエッチングレートよりも小さくなる。 Here, the alkaline solution has a higher etching rate than the n-type semiconductor layer and a lower etching rate than the p-type semiconductor layer. As a result, the etching rate of the first conductive semiconductor layer 25 with respect to the etching solution becomes smaller than the etching rate of the second conductive semiconductor layer 35 with respect to the etching solution.
　このように、ウエットプロセスにおいて、第１領域７における第２導電型半導体層材料膜のみを選択的にエッチングし、第１領域７に第１導電型半導体層２５を残す。 As described above, in the wet process, only the second conductive semiconductor layer material film in the first region 7 is selectively etched, and the first conductive semiconductor layer 25 is left in the first region 7.
　次に、半導体基板１１の裏面側に、第１電極層２７および第２電極層３７を形成する（電極層形成工程）。
　具体的には、例えばスパッタリング法等のＰＶＤ法（物理気相成長法）を用いて、半導体基板１１の裏面側の全面に、透明電極層材料膜を積層（製膜）する。その後、例えばエッチングペーストを用いたエッチング法を用いて、透明電極層材料膜の一部を除去することにより、透明電極層のパターニングを行う。透明電極層材料膜に対するエッチング溶液としては、例えば塩酸または塩化第二鉄水溶液が用いられる。
　その後、例えばパターン印刷法または塗布法を用いて、透明電極層上に金属電極層を形成することにより、第１電極層２７および第２電極層３７を形成する。 Next, the first electrode layer 27 and the second electrode layer 37 are formed on the back surface side of the semiconductor substrate 11 (electrode layer forming step).
Specifically, for example, a PVD method (physical vapor deposition method) such as a sputtering method is used to laminate (film) a transparent electrode layer material film on the entire back surface side of the semiconductor substrate 11. After that, the transparent electrode layer is patterned by removing a part of the transparent electrode layer material film by, for example, an etching method using an etching paste. As the etching solution for the transparent electrode layer material film, for example, hydrochloric acid or an aqueous ferric chloride solution is used.
Then, the first electrode layer 27 and the second electrode layer 37 are formed by forming the metal electrode layer on the transparent electrode layer by using, for example, a pattern printing method or a coating method.
　以上の工程により、図１および図２に示す本実施形態の裏面接合型の太陽電池１が得られる。 Through the above steps, the back surface bonded type solar cell 1 of the present embodiment shown in FIGS. 1 and 2 can be obtained.
　以上説明したように、本実施形態の太陽電池１および太陽電池の製造方法によれば、ＣＶＤプロセスによって第１導電型半導体層２５および第２導電型半導体層材料膜を一括製膜した後、ウエットプロセスにおいて、第１領域７における第２導電型半導体層材料膜のみを選択的にエッチングし、第１領域７に第１導電型半導体層２５を残すことができる。これにより、特許文献１および２に記載の太陽電池の構成では２回必要であったＣＶＤプロセス回数が１回になり、更なる製造プロセスの簡略化、低コスト化が可能である。 As described above, according to the solar cell 1 and the method for manufacturing the solar cell of the present embodiment, the first conductive semiconductor layer 25 and the second conductive semiconductor layer material film are collectively formed by the CVD process, and then wet. In the process, only the second conductive semiconductor layer material film in the first region 7 can be selectively etched to leave the first conductive semiconductor layer 25 in the first region 7. As a result, the number of CVD processes required twice in the solar cell configurations described in Patent Documents 1 and 2 is reduced to one, and the manufacturing process can be further simplified and the cost can be reduced.
　また、ＣＶＤプロセスによる連続製膜であるので、第１導電型半導体層２５および第２導電型半導体層３５における界面抵抗が低減し、太陽電池の出力が向上する。 Further, since the film is continuously formed by the CVD process, the interfacial resistance in the first conductive semiconductor layer 25 and the second conductive semiconductor layer 35 is reduced, and the output of the solar cell is improved.
　以上、本発明の実施形態について説明したが、本発明は上述した実施形態に限定されることなく、種々の変更および変形が可能である。例えば、上述した実施形態では、図２に示すようにヘテロ接合型の太陽電池１の製造方法を例示したが、本発明の特徴は、ヘテロ接合型の太陽電池に限らず、ホモ接合型の太陽電池等の種々の太陽電池の製造方法に適用可能である。 Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications and modifications can be made. For example, in the above-described embodiment, the method for manufacturing the heterozygous solar cell 1 is illustrated as shown in FIG. 2, but the feature of the present invention is not limited to the heterozygous solar cell, but the homozygous solar cell. It can be applied to various methods for manufacturing solar cells such as batteries.
　また、上述した実施形態では、結晶シリコン基板を有する太陽電池を例示したが、これに限定されない。例えば、太陽電池は、ガリウムヒ素（ＧａＡｓ）基板を有していてもよい。 Further, in the above-described embodiment, a solar cell having a crystalline silicon substrate has been exemplified, but the present invention is not limited to this. For example, a solar cell may have a gallium arsenide (GaAs) substrate.
　１　太陽電池
　７　第１領域
　７ｂ，８ｂ　バスバー部
　７ｆ，８ｆ　フィンガー部
　８　第２領域
　１１　半導体基板
　１３　真性半導体層（第２真性半導体層）
　１５　光学調整層
　２３　真性半導体層（第１真性半導体層）
　２５　第１導電型半導体層
　２７　第１電極層
　３５　第２導電型半導体層
　２５Ｚ　第２導電型半導体層材料膜
　３７　第２電極層
　９０　レジスト 1 Solar cell 7 1st area 7b, 8b Bus bar part 7f, 8f Finger part 8 2nd area 11 Semiconductor substrate 13 Intrinsic semiconductor layer (2nd intrinsic semiconductor layer)
15 Optical adjustment layer 23 Intrinsic semiconductor layer (first intrinsic semiconductor layer)
25 First Conductive Semiconductor Layer 27 First Electrode Layer 35 Second Conductive Semiconductor Layer 25Z Second Conductive Semiconductor Layer Material Film 37 Second Electrode Layer 90 Resist

Claims (14)

  1. 　裏面接合型の太陽電池であって、
    　半導体基板と、
    　前記半導体基板の一方主面側の一部である第１領域、および前記半導体基板の前記一方主面側の他の一部である第２領域に形成され、第１導電型である第１導電型半導体層と、
    　前記第２領域における前記第１導電型半導体層の上に形成され、前記第１導電型とは逆の第２導電型である第２導電型半導体層と、
    　前記第１領域における前記第１導電型半導体層の上に形成された第１電極層と、
    　前記第２領域における前記第２導電型半導体層の上に形成された第２電極層と、
    を備える、太陽電池。     It is a back-bonded solar cell
    With a semiconductor substrate
    A first conductive type, which is formed in a first region which is a part of one main surface side of the semiconductor substrate and a second region which is another part of the one main surface side of the semiconductor substrate and is a first conductive type. Type semiconductor layer and
    A second conductive semiconductor layer formed on the first conductive semiconductor layer in the second region and which is a second conductive type opposite to the first conductive type,
    A first electrode layer formed on the first conductive semiconductor layer in the first region,
    A second electrode layer formed on the second conductive semiconductor layer in the second region,
    With a solar cell.
  2. 　前記第１導電型はｐ型であり、前記第２導電型はｎ型である、請求項１に記載の太陽電池。 The solar cell according to claim 1, wherein the first conductive type is a p-type and the second conductive type is an n-type.
  3. 　前記半導体基板は前記第１導電型の半導体基板である、請求項１または２に記載の太陽電池。 The solar cell according to claim 1 or 2, wherein the semiconductor substrate is the first conductive type semiconductor substrate.
  4. 　前記半導体基板と前記第１導電型半導体層との間に形成され、実質的に真性な第１真性半導体層を更に備える、請求項１～３のいずれかに記載の太陽電池。 The solar cell according to any one of claims 1 to 3, further comprising a substantially intrinsic first intrinsic semiconductor layer formed between the semiconductor substrate and the first conductive type semiconductor layer.
  5. 　前記第１導電型半導体層のエッチング溶液に対するエッチングレートは、前記第２導電型半導体層のエッチング溶液に対するエッチングレートよりも小さい、請求項１～４のいずれか１項に記載の太陽電池。 The solar cell according to any one of claims 1 to 4, wherein the etching rate of the first conductive semiconductor layer with respect to the etching solution is smaller than the etching rate of the second conductive semiconductor layer with respect to the etching solution.
  6. 　前記第１導電型半導体層は微結晶シリコン層を含む、請求項１～５のいずれか１項に記載の太陽電池。 The solar cell according to any one of claims 1 to 5, wherein the first conductive semiconductor layer includes a microcrystalline silicon layer.
  7. 　前記第２導電型半導体層は微結晶シリコン層を含む、請求項１～６のいずれか１項に記載の太陽電池。 The solar cell according to any one of claims 1 to 6, wherein the second conductive semiconductor layer includes a microcrystalline silicon layer.
  8. 　前記第１導電型半導体層の結晶化度は、前記第２導電型半導体層側の界面に向けて、増大している、請求項６に記載の太陽電池。 The solar cell according to claim 6, wherein the crystallinity of the first conductive semiconductor layer increases toward the interface on the second conductive semiconductor layer side.
  9. 　前記半導体基板の前記一方主面側と反対側の他方主面側に形成され、実質的に真性な第２真性半導体層を更に備える、請求項１～８のいずれか１項に記載の太陽電池。 The solar cell according to any one of claims 1 to 8, further comprising a second intrinsic semiconductor layer formed on the other main surface side opposite to the one main surface side of the semiconductor substrate and further comprising a substantially intrinsic second intrinsic semiconductor layer. ..
  10. 　前記半導体基板の前記一方主面側と反対側の他方主面側に形成された酸化アルミニウム層を更に備える、請求項１～８のいずれか１項に記載の太陽電池。 The solar cell according to any one of claims 1 to 8, further comprising an aluminum oxide layer formed on the other main surface side opposite to the one main surface side of the semiconductor substrate.
  11. 　前記第１導電型半導体層は、前記半導体基板の前記一方主面側の全面を覆っている、請求項１～１０のいずれか１項に記載の太陽電池。 The solar cell according to any one of claims 1 to 10, wherein the first conductive type semiconductor layer covers the entire surface of the semiconductor substrate on one main surface side.
  12. 　裏面接合型の太陽電池の製造方法であって、
    　半導体基板の一方主面側の一部である第１領域、および前記半導体基板の前記一方主面側の他の一部である第２領域に、第１導電型である第１導電型半導体層を形成する第１半導体層形成工程と、
    　前記第１領域および前記第２領域における前記第１導電型半導体層の上に、前記第１導電型とは逆の第２導電型である第２導電型半導体層の材料膜を形成する第２半導体層材料膜形成工程と、
    　前記第１領域における前記第２導電型半導体層の材料膜を除去することにより、前記第２領域に、パターン化された前記第２導電型半導体層を形成する第２半導体層形成工程と、
    を含む、太陽電池の製造方法。     This is a method for manufacturing a back-bonded solar cell.
    A first conductive semiconductor layer that is a first conductive type in a first region that is a part of one main surface side of a semiconductor substrate and a second region that is another part of the one main surface side of the semiconductor substrate. The first semiconductor layer forming step of forming
    A second material film of a second conductive type semiconductor layer, which is a second conductive type opposite to the first conductive type, is formed on the first conductive type semiconductor layer in the first region and the second region. Semiconductor layer material film formation process and
    A second semiconductor layer forming step of forming the patterned second conductive semiconductor layer in the second region by removing the material film of the second conductive semiconductor layer in the first region.
    Manufacturing methods for solar cells, including.
  13. 　前記第２半導体層形成工程では、エッチング溶液を用いて、前記第１領域における前記第２導電型半導体層の材料膜を除去し、
    　前記第１導電型半導体層の前記エッチング溶液に対するエッチングレートは、前記第２導電型半導体層の前記エッチング溶液に対するエッチングレートよりも小さい、請求項１２に記載の太陽電池の製造方法。     In the second semiconductor layer forming step, the material film of the second conductive semiconductor layer in the first region is removed by using an etching solution.
    The method for manufacturing a solar cell according to claim 12, wherein the etching rate of the first conductive semiconductor layer with respect to the etching solution is smaller than the etching rate of the second conductive semiconductor layer with respect to the etching solution.
  14. 　前記第１導電型はｐ型であり、
    　前記第２導電型はｎ型であり、
    　前記エッチング溶液はアルカリ溶液である、
    請求項１３に記載の太陽電池の製造方法。     The first conductive type is a p type.
    The second conductive type is n type.
    The etching solution is an alkaline solution.
    The method for manufacturing a solar cell according to claim 13.
PCT/JP2020/015916 2019-04-23 2020-04-09 Solar cell and method for manufacturing solar cell WO2020218000A1 (en)

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