JP2021145056A - Solar cell and manufacturing method for solar cell - Google Patents

Abstract

To provide a manufacturing method for a solar cell whose manufacturing process can be simplified.SOLUTION: A manufacturing method for a solar cell 1 includes the steps of forming an intrinsic semiconductor layer 23 in a first region 7 and a second region 8 on a back surface side of a semiconductor substrate 11, forming a lift-off layer on the intrinsic semiconductor layer 23 and then removing the lift-off layer in the first region 7, thereby forming the patterned lift-off layer in the second region 8, forming a first conductivity type semiconductor layer material film on the intrinsic semiconductor layer 23 in the first region 7 and on the lift-off layer in the second region 8, removing the lift-off layer in the second region 8 to remove the first conductivity type semiconductor layer material film in the second region 8 and while leaving the intrinsic semiconductor layer 23 in the second region 8, forming a first conductivity type semiconductor layer 25 patterned in the first region 7, and forming a second conductivity type semiconductor layer 35 on the first conductivity type semiconductor layer 25 in the first region 7 and on the intrinsic semiconductor layer 23 in the second region 8.SELECTED DRAWING: Figure 2

Description

The present invention relates to a back contact type (also referred to as a back contact type or a back electrode type) solar cell and a method for manufacturing the solar cell.

As a solar cell using a semiconductor substrate, for example, a heterojunction type in which semiconductor layers are formed on both the light receiving surface side and the back surface side (hereinafter, referred to as a double-sided bonding type as opposed to a back surface bonding type, also referred to as a double-sided electrode type). There are two types of solar cells: a back-side bonded type solar cell in which a semiconductor layer is formed only on the back side. In a double-sided solar cell, an electrode is formed on the light receiving surface side, so that the electrode shields sunlight. On the other hand, in the back surface bonded type solar cell, since the electrode is not formed on the light receiving surface side, the light receiving rate of sunlight is higher than that of the double-sided bonded type solar cell. Patent Document 1 discloses a back surface bonded type solar cell.

The solar cell described in Patent Document 1 includes a semiconductor substrate that functions as a photoelectric conversion layer, a first conductive semiconductor layer formed in a first region that is a part of the back surface side of the semiconductor substrate, and a back surface side of the semiconductor substrate. It includes a second region which is another part thereof, and a second conductive semiconductor layer formed on the first conductive semiconductor layer of the first region. According to such a solar cell, after patterning the first conductive semiconductor layer, the second conductive semiconductor layer may be formed on the entire back surface side of the semiconductor substrate, so that the manufacturing process can be simplified. be.

Japanese Unexamined Patent Publication No. 2005-101151

Generally, in the patterning of the first conductive semiconductor layer, an etching method using a photolithography technique is used. However, in the etching method using the photolithography technique, for example, photoresist coating by the spin coating method, photoresist drying, photoresist exposure, photoresist development, etching of a semiconductor layer using a photoresist as a mask, and photoresist peeling can be performed. A process was required and the process was complicated.

An object of the present invention is to provide a method for manufacturing a solar cell and a solar cell capable of simplifying the manufacturing process.

The method for manufacturing a solar cell according to the present invention comprises a first conductive semiconductor layer formed in a first region formed in a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and the semiconductor substrate. Manufacture of a back surface bonded type solar cell including a second region which is another part on the other main surface side and a second conductive semiconductor layer formed on the first conductive semiconductor layer of the first region. The method is a step of forming an intrinsic semiconductor layer in which an intrinsic semiconductor layer is formed in the first region and the second region on the other main surface side of the semiconductor substrate, and a lift-off layer is formed on the intrinsic semiconductor layer. Then, the lift-off layer forming step of forming the patterned lift-off layer in the second region by removing the lift-off layer in the first region using an etching solution, and the lift-off layer forming step in the first region. A first semiconductor layer material film forming step of forming a material film of the first conductive semiconductor layer on the intrinsic semiconductor layer and on the lift-off layer in the second region, and the lift-off layer in the second region. By removing the material film of the first conductive semiconductor layer in the second region, the first region is patterned while leaving the intrinsic semiconductor layer in the second region. The first semiconductor layer forming step of forming the first conductive semiconductor layer, the second conductive type on the first conductive semiconductor layer in the first region, and on the intrinsic semiconductor layer in the second region. It includes a second semiconductor layer forming step of forming a semiconductor layer.

The solar cell according to the present invention has a first conductive semiconductor layer formed in a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and the other main surface of the semiconductor substrate. A back surface bonding type solar cell including a second region which is another part on the surface side and a second conductive semiconductor layer formed on the first conductive semiconductor layer in the first region. In the first region, the first conductive semiconductor layer and the second conductive semiconductor layer are sequentially laminated on the other main surface side of the semiconductor substrate via an intrinsic semiconductor layer, and the second region is formed. The second conductive semiconductor layer is laminated on the other main surface side of the semiconductor substrate via the intrinsic semiconductor layer, and the intrinsic semiconductor layer in the first region and the second region The intrinsic semiconductor layer is continuous, and the second conductive semiconductor layer in the first region and the second conductive semiconductor layer in the second region are continuous, and the first in the first region. The particles of the first conductive semiconductor layer are attached to the surface side of the first conductive semiconductor layer.

According to the present invention, it is possible to simplify the manufacturing process of a solar cell.

It is the figure which looked at the solar cell which concerns on this embodiment from the back side. FIG. 2 is a cross-sectional view taken along the line II-II of the solar cell of FIG. It is a figure which shows the intrinsic semiconductor layer forming process and the lift-off layer forming process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the lift-off layer forming process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the 1st semiconductor layer material film formation process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the 1st semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment. It is a figure which shows the 2nd semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment.

Hereinafter, an example of the embodiment of the present invention will be described with reference to the accompanying drawings. In addition, the same reference numerals are given to the same or corresponding parts in each drawing. In addition, for convenience, hatching, member codes, and the like may be omitted, but in such cases, other drawings shall be referred to.

(Solar cell)
FIG. 1 is a view of the solar cell according to the present embodiment as viewed from the back surface side. The solar cell 1 shown in FIG. 1 is a back surface bonded type solar cell. The solar cell 1 includes a semiconductor substrate 11 having two main surfaces, and has a first region 7 and a second region 8 on the main surface of the semiconductor substrate 11.

The first region 7 has a so-called comb-shaped shape, and has a plurality of finger portions 7f corresponding to the comb teeth and a bus bar portion 7b corresponding to the support portion of the comb teeth. The bus bar portion 7b extends in the first direction (X direction) along one side of the semiconductor substrate 11, and the finger portion 7f intersects the bus bar portion 7b in the first direction (X direction). It extends in the direction (Y direction).
Similarly, the second region 8 has a so-called comb-shaped shape, and has a plurality of finger portions 8f corresponding to the comb teeth and a bus bar portion 8b corresponding to the support portion of the comb teeth. The bus bar portion 8b extends in the first direction (X direction) along the other side portion facing one side portion of the semiconductor substrate 11, and the finger portion 8f extends from the bus bar portion 8b in the second direction (Y). Extends in the direction).
The finger portions 7f and the finger portions 8f are alternately provided in the first direction (X direction).
The first region 7 and the second region 8 may be formed in a striped shape.

FIG. 2 is a sectional view taken along line II-II of the solar cell of FIG. As shown in FIG. 2, the solar cell 1 includes a semiconductor substrate 11, an intrinsic semiconductor layer 13 and optics, which are sequentially laminated on the light receiving surface side, which is one of the main surfaces of the semiconductor substrate 11 on the light receiving side. The adjusting layer 15 is provided. Further, the solar cell 1 includes an intrinsic semiconductor layer 23 laminated on the back surface side, which is the other main surface of the main surface of the semiconductor substrate 11 opposite to the light receiving surface, and a part of the back surface side of the semiconductor substrate 11. The first conductive semiconductor layer 25 laminated on the intrinsic semiconductor layer 23 of the first region 7), the other part (second region 8) on the back surface side of the semiconductor substrate 11 on the intrinsic semiconductor layer 23, and the semiconductor. A second conductive semiconductor layer 35 laminated on the first conductive semiconductor layer 25 of a part (first region 7) on the back surface side of the substrate 11 is provided. Further, the solar cell 1 includes a first electrode layer 27 formed in the first region 7 and a second electrode layer 37 formed in the second region 8.

The semiconductor substrate 11 is formed of a crystalline silicon material such as single crystal silicon or polycrystalline silicon. The semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which a crystalline silicon material is doped with an n-type dopant. Examples of the n-type dopant include phosphorus (P).
The semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light receiving surface side to generate optical carriers (electrons and holes).
By using crystalline silicon as the material of the semiconductor substrate 11, a relatively high output (stable output regardless of the illuminance) can be obtained even when the dark current is relatively small and the intensity of the incident light is low.

The semiconductor substrate 11 may have a pyramid-shaped fine uneven structure called a texture structure on the back surface side. As a result, the recovery efficiency of light that has passed through without being absorbed by the semiconductor substrate 11 is increased.
Further, the semiconductor substrate 11 may have a pyramid-shaped fine uneven structure called a texture structure on the light receiving surface side. As a result, the reflection of incident light on the light receiving surface is reduced, and the light confinement effect on the semiconductor substrate 11 is improved.

The intrinsic semiconductor layer 13 is formed on the light receiving surface side of the semiconductor substrate 11. The intrinsic semiconductor layer 23 is formed so as to be connected to the first region 7 and the second region 8 on the back surface side of the semiconductor substrate 11. The intrinsic semiconductor layers 13 and 23 are formed of, for example, a material containing intrinsic (i-type) amorphous silicon as a main component.
The intrinsic semiconductor layers 13 and 23 function as so-called passivation layers, suppress recombination of carriers generated in the semiconductor substrate 11, and improve carrier recovery efficiency.

The optical adjustment layer 15 is formed on the intrinsic semiconductor layer 13 on the light receiving surface side of the semiconductor substrate 11. The optical adjustment layer 15 functions as an antireflection layer that prevents reflection of incident light, and also functions as a protective layer that protects the light receiving surface side of the semiconductor substrate 11 and the intrinsic semiconductor layer 13. The optical adjustment layer 15 is formed of an insulating material such as a composite thereof such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON).

The first conductive semiconductor layer 25 is formed in the first region 7 on the back surface side of the semiconductor substrate 11. Specifically, the first conductive semiconductor layer 25 is formed on the intrinsic semiconductor layer 23 in the first region 7. The first conductive semiconductor layer 25 is formed of, for example, an amorphous silicon material. The first conductive semiconductor layer 25 is, for example, an n-type semiconductor layer in which an amorphous silicon material is doped with an n-type dopant (for example, phosphorus (P) described above).

The second conductive semiconductor layer 35 is formed so as to be connected to the first region 7 and the second region 8 on the back surface side of the semiconductor substrate 11. Specifically, the second conductive semiconductor layer 35 is formed on the first conductive semiconductor layer 25 in the first region 7 and on the intrinsic semiconductor layer 23 in the second region 8. The second conductive semiconductor layer 35 is formed of, for example, an amorphous silicon material. The second conductive semiconductor layer 35 is, for example, a p-type semiconductor layer in which an amorphous silicon material is doped with a p-type dopant. Examples of the p-type dopant include boron (B).

The film thickness of the second conductive semiconductor layer 35 is preferably 3.5 nm or more. The film thickness of the second conductive semiconductor layer 35 is the thickness of the first conductive semiconductor layer 25, the second conductive semiconductor layer 35, etc. in the stacking direction, and is the thickness in the first direction (X direction) and the second direction. It is the thickness in the direction intersecting (Y direction).
Further, the particles 25A of the first conductive semiconductor layer 25 are attached to the surface side of the first conductive semiconductor layer 25 in the first region 7 (details will be described later).

The first conductive semiconductor layer 25 may be a p-type semiconductor layer, and the second conductive semiconductor layer 35 may be an n-type semiconductor layer. In this case, the semiconductor substrate 11 may be a p-type semiconductor substrate in which a crystalline silicon material is doped with a p-type dopant (for example, the above-mentioned boron (B)).

In other words, in the first region 7, the first conductive semiconductor layer 25 and the second conductive semiconductor layer 35 are sequentially laminated on the back surface side of the semiconductor substrate 11 via the intrinsic semiconductor layer 23. In the second region 8, the second conductive semiconductor layer 35 is laminated on the back surface side of the semiconductor substrate 11 via the intrinsic semiconductor layer 23.

The first electrode layer 27 is formed on the second conductive semiconductor layer 35 in the first region 7, and the second electrode layer 37 is formed on the second conductive semiconductor layer 35 in the second region 8. There is.
The first electrode layer 27 has a transparent electrode layer 28 and a metal electrode layer 29 that are sequentially laminated on the second conductive semiconductor layer 35. The second electrode layer 37 has a transparent electrode layer 38 and a metal electrode layer 39 which are sequentially laminated on the second conductive semiconductor layer 35.
The transparent electrode layers 28 and 38 are formed of a transparent conductive material. Examples of the transparent conductive material include ITO (Indium Tin Oxide: a composite oxide of indium tin oxide and tin oxide) and ZnO (Zinc Oxide: zinc oxide). The metal electrode layers 29 and 39 are formed of a conductive paste material containing a metal powder such as silver.

(Solar cell manufacturing method)
Hereinafter, the method for manufacturing the solar cell 1 of the present embodiment shown in FIGS. 1 and 2 will be described with reference to FIGS. 3A to 3E. FIG. 3A is a diagram showing an intrinsic semiconductor layer forming step and a lift-off layer forming step in the solar cell manufacturing method according to the present embodiment, and FIG. 3B is a lift-off layer forming step in the solar cell manufacturing method according to the present embodiment. It is a figure which shows. FIG. 3C is a diagram showing a first semiconductor layer material film forming step in the solar cell manufacturing method according to the present embodiment, and FIG. 3D is a diagram showing a first semiconductor layer forming step in the solar cell manufacturing method according to the present embodiment. It is a figure which shows. Further, FIG. 3E is a diagram showing a second semiconductor layer forming step in the method for manufacturing a solar cell according to the present embodiment.

First, as shown in FIG. 3A, for example, by using a CVD method (chemical vapor deposition method), the intrinsic semiconductor layer 23 is formed on the entire surface of the back surface side of the semiconductor substrate 11, that is, on the first region 7 and the second region 8. Lamination (film formation) (intrinsic semiconductor layer forming step).
Further, for example, by using a CVD method, the intrinsic semiconductor layer 13 and the optical adjustment layer 15 are laminated (film-formed) on the entire surface of the semiconductor substrate 11 on the light receiving surface side.

Next, for example, using a CVD method, the lift-off layer 40 is laminated (film-formed) on the entire surface of the semiconductor substrate 11 on the back surface side, that is, on the entire surface of the intrinsic semiconductor layer 23 (lift-off layer forming step).

Next, as shown in FIG. 3B, the lift-off layer 40 in the first region 7 is removed from the back surface side of the semiconductor substrate 11 by using an etching solution, so that the lift-off layer patterned in the second region 8 is formed. 40 is formed (lift-off layer forming step). As the etching solution for the lift-off layer 40, for example, hydrofluoric acid or a mixture of hydrofluoric acid and another kind of acid is used.

Next, as shown in FIG. 3C, the first conductive semiconductor layer is placed on the entire surface of the semiconductor substrate 11 on the back surface side, that is, on the intrinsic semiconductor layer 23 in the first region 7 and on the lift-off layer 40 in the second region 8. The material film 25Z is laminated (film-formed) (first semiconductor layer material film forming step).

Next, as shown in FIG. 3D, the first conductive type semiconductor layer material film 25Z in the second region 8 on the back surface side of the semiconductor substrate 11 is removed by using the lift-off method using the lift-off layer 40, and the second A patterned first conductive semiconductor layer 25 is formed in the first region 7 while leaving the intrinsic semiconductor layer 23 in the region 8 (first semiconductor layer forming step).

Specifically, the lift-off layer 40 in the second region 8 on the back surface side of the semiconductor substrate 11 is etched (removed) with an etching solution to obtain the first conductive semiconductor layer material film 25Z on the lift-off layer 40. The first conductive semiconductor layer 25 is formed in the first region 7 while removing the intrinsic semiconductor layer 23 in the second region 8. As the etching solution for the lift-off layer 40, for example, an acidic solution such as hydrofluoric acid is used.

At this time, the particles 25A of the first conductive semiconductor layer in the second region 8 peeled off by the lift-off adhere to the surface side of the first conductive semiconductor layer 25 in the first region 7. In order to control the adhesion of the particles, an aqueous solution containing a surfactant is used as the rinsing solution after etching. Examples of the surfactant include anionic surfactants, cationic surfactants, amphoteric ionic surfactants, nonionic surfactants, and mixtures thereof.
The surfactant may be an organic acid containing an aromatic structure and a long chain linear alkyl structure. This improves the affinity between the high surface active action and the solvent having a large surface free energy (for example, water).
Further, as the particle adhesion inhibitor, in addition to the surfactant, a stabilizer, an emulsifier, a buffer solution of an organic acid ion and an organic acid salt, and / or a pH adjuster may be contained.

Next, as shown in FIG. 3E, for example, using the CVD method, the intrinsic semiconductor on the entire back surface side of the semiconductor substrate 11, that is, on the first conductive semiconductor layer 25 in the first region 7, and in the second region 8. A second conductive semiconductor layer 35 is formed on the layer 23 (second semiconductor layer forming step).

Next, the first electrode layer 27 and the second electrode layer 37 are formed on the back surface side of the semiconductor substrate 11 (electrode layer forming step).
Specifically, for example, a PVD method (physical vapor deposition method) such as a sputtering method is used to laminate (form) a transparent electrode layer material film on the entire back surface side of the semiconductor substrate 11. After that, the transparent electrode layers 28 and 38 are patterned by removing a part of the transparent electrode layer material film by, for example, an etching method using an etching paste. As the etching solution for the transparent electrode layer material film, for example, hydrochloric acid or an aqueous ferric chloride solution is used.
Then, for example, by forming a metal electrode layer 29 on the transparent electrode layer 28 and forming a metal electrode layer 39 on the transparent electrode layer 38 by using, for example, a pattern printing method or a coating method, the first electrode layer 27 and The second electrode layer 37 is formed.

Through the above steps, the back surface bonded type solar cell 1 of the present embodiment shown in FIGS. 1 and 2 can be obtained.

As described above, according to the solar cell 1 and the method for manufacturing the solar cell of the present embodiment, after the first conductive semiconductor layer 25 is patterned, the second conductive semiconductor layer 35 is placed on the back surface side of the semiconductor substrate 11. Since the film may be formed on the entire surface, the manufacturing process can be simplified, shortened, and reduced in cost.
Further, according to the method for manufacturing a solar cell of the present embodiment, the main surface of the semiconductor substrate 11 is formed during the manufacturing process, particularly when the first conductive semiconductor layer 25 and the second conductive semiconductor layer 35 are formed. Since it is not exposed, the high lifetime of the solar cell can be maintained.

Further, according to the method for manufacturing a solar cell of the present embodiment, the first conductive semiconductor layer 25 is patterned by using the lift-off method using the lift-off layer 40, so that the manufacturing process of the solar cell is simplified and shortened. It is possible to reduce the cost and cost.

Further, according to the method for manufacturing a solar cell of the present embodiment, in the first semiconductor layer forming step, the lift-off is performed while leaving the intrinsic semiconductor layer 23, so that the etching solution (HF) for removing the lift-off layer 40 is simultaneously lifted off. The surface of the intrinsic semiconductor layer 23 is cleaned to improve the performance of the solar cell.

Here, in order to prevent the performance of the second conductive semiconductor layer (for example, P-type semiconductor layer) 35 in the second region 8 from deteriorating, it is necessary to increase the film thickness of the second conductive semiconductor layer 35 (for example,). 3.5 nm or more). However, when the thickness of the second conductive semiconductor layer 35 is increased, the first conductive semiconductor layer (for example, N-type semiconductor layer) 25 and the second conductive semiconductor layer (for example, P-type semiconductor layer) in the first region 7 are increased. ) 35, the tunneling efficiency is reduced, and the resistance in the film thickness direction is increased.

On the other hand, according to the method for manufacturing a solar cell of the present embodiment, since the lift-off method is used in the first semiconductor layer forming step, the particles of the first conductive semiconductor layer in the second region 8 peeled off by the lift-off. 25A adheres to the surface side of the first conductive semiconductor layer 25 in the first region 7. As a result, the particles 25A of the first conductive semiconductor layer are interposed between the first conductive semiconductor layer 25 and the second conductive semiconductor layer 35 in the first region 7, and the first conductive semiconductor layer in the first region 7 is interposed. The tunnel conductivity between the (for example, N-type semiconductor layer) 25 and the second conductive type semiconductor layer (for example, P-type semiconductor layer) 35 is improved, and the interface resistance and the increase in resistance in the film thickness direction are reduced. As a result, the FF characteristics of the solar cell are improved.
As described above, by utilizing the lift-off method in the first semiconductor layer forming step and setting the thickness of the second conductive semiconductor layer 35 to 3.5 nm or more, the second conductive semiconductor layer (for example, the second conductive semiconductor layer) in the second region 8 is formed. , P-type semiconductor layer) 35 can be prevented from deteriorating, and the increase in resistance of the second conductive semiconductor layer (for example, P-type semiconductor layer) 35 in the first region 7 in the film thickness direction can be reduced. As a result, a high-performance solar cell can be realized.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications and modifications can be made. For example, in the above-described embodiment, the method for manufacturing the heterozygous solar cell 1 is illustrated as shown in FIG. 2, but the feature of the present invention is not limited to the heterozygous solar cell, but the homojunction solar cell. It can be applied to various methods for manufacturing solar cells such as batteries.

Further, in the above-described embodiment, a solar cell having a crystalline silicon substrate has been exemplified, but the present invention is not limited thereto. For example, a solar cell may have a gallium arsenide (GaAs) substrate.

Hereinafter, the present invention will be specifically described based on Examples, but the present invention is not limited to the following Examples.

(Example 1)
The solar cell 1 shown in FIGS. 1 and 2 was manufactured by the method for manufacturing the solar cell shown in FIGS. 3A to 3E. The main features of the solar cell of Example 1 and the method for manufacturing the solar cell are as follows and Table 1.
First conductive semiconductor layer 25: N-type semiconductor layer Second conductive semiconductor layer 35: P-type semiconductor layer, thickness 3.5 nm
Particles 25A of the first conductive semiconductor layer interposed between the first conductive semiconductor layer 25 and the second conductive semiconductor layer 35 in the first region 7: Coverage 3%
Here, the coverage is the coverage of the particles 25A in the first region 7, that is, on the first conductive semiconductor layer 25.

The coverage was adjusted by setting the surfactant concentration of the rinse liquid after etching to 1.5 vol% in the first semiconductor layer forming step using the lift-off method. Anionic mama lemon (manufactured by Lion Corporation) (registered trademark) was used as the surfactant.

When the surface of the first conductive semiconductor layer 25 in the first region 7 after the first semiconductor layer forming step using the lift-off method is observed with an optical microscope, the first conductive type semiconductor layer 25 is on the first conductive type semiconductor layer 25. The particles 25A of the semiconductor layer were diffused and adhered. The size of the particles 25A was 1 μm or more and 50 μm or less, and most of the particles were 10 μm or more and 20 μm or less.

The coverage and particle size were measured using an optical microscope device (model number: DSX510, manufactured by Olympus Corporation).

(Example 2)
In the first embodiment, the coverage of the particles 25A of the first conductive semiconductor layer on the first conductive semiconductor layer 25 is different. The main features of the solar cell of Example 2 and the method for manufacturing the solar cell are as follows and Table 1.
Particles 25A of the first conductive semiconductor layer interposed between the first conductive semiconductor layer 25 and the second conductive semiconductor layer 35 in the first region 7: Coverage 5%
The coverage was adjusted by setting the surfactant concentration of the rinse liquid after etching to 1.0 vol% in the first semiconductor layer forming step using the lift-off method. Anionic mama lemon was used as the surfactant.

(Example 3)
In the first embodiment, the coverage of the particles 25A of the first conductive semiconductor layer on the first conductive semiconductor layer 25 is different. The main features of the solar cell of Example 3 and the method for manufacturing the solar cell are as follows and Table 1.
Particles 25A of the first conductive semiconductor layer interposed between the first conductive semiconductor layer 25 and the second conductive semiconductor layer 35 in the first region 7: Coverage 10%
The coverage was adjusted by setting the surfactant concentration of the rinse liquid after etching to 0.5 vol% in the first semiconductor layer forming step using the lift-off method. Anionic mama lemon was used as the surfactant.

(Example 4)
In the first embodiment, the coverage of the particles 25A of the first conductive semiconductor layer on the first conductive semiconductor layer 25 is different. The main features of the solar cell of Example 4 and the method for manufacturing the solar cell are as follows and Table 1.
Particles 25A of the first conductive semiconductor layer interposed between the first conductive semiconductor layer 25 and the second conductive semiconductor layer 35 in the first region 7: Coverage 20%
The coverage was adjusted by setting the surfactant concentration of the rinse liquid after etching to 0.1 vol% in the first semiconductor layer forming step using the lift-off method. Anionic mama lemon was used as the surfactant.

(Example 5)
In the first embodiment, the coverage of the particles 25A of the first conductive semiconductor layer on the first conductive semiconductor layer 25 is different. The main features of the solar cell of Example 5 and the method for manufacturing the solar cell are as follows and Table 1.
Particles 25A of the first conductive semiconductor layer interposed between the first conductive semiconductor layer 25 and the second conductive semiconductor layer 35 in the first region 7: Coverage 30%
The coverage was adjusted by setting the surfactant concentration of the rinse liquid after etching to 0.02 vol% in the first semiconductor layer forming step using the lift-off method. Anionic mama lemon was used as the surfactant.

(Comparative Example 1)
The first embodiment is different in that the particles 25A of the first conductive semiconductor layer do not intervene on the first conductive semiconductor layer 25. The main features of the solar cell of Comparative Example 1 and its manufacturing method are as follows and Table 1.
Particles 25A of the first conductive semiconductor layer interposed between the first conductive semiconductor layer 25 and the second conductive semiconductor layer 35 in the first region 7: 0% coverage.
The coverage was adjusted by setting the surfactant concentration of the rinse liquid after etching to 2.5 vol% in the first semiconductor layer forming step using the lift-off method. Anionic mama lemon was used as the surfactant.

Using a pulsed solar simulator having a spectral distribution of AM1.5, simulated sunlight was ^{irradiated at an energy density of 100 mW / cm 2} at 25 ° C., and the performance characteristics of the solar cells of the above Examples and Comparative Examples ( The open circuit voltage Voc, the short circuit current Isc, the curve factor FF, and the conversion efficiency Eff) were measured. The measurement results are shown in Table 1.
In Table 1, the output correlation was evaluated by comparing the evaluation results of each example with the output characteristic result of Comparative Example 1 as a reference (1.00).

According to Table 1, when the particles 25A of the first conductive semiconductor layer are interposed between the first conductive semiconductor layer 25 and the second conductive semiconductor layer 35 in the first region 7, the FF characteristics of the solar cell are improved. You can see that it does. In particular, when the coverage of the particles 25A was 3% or more and 10% or less, the increase in FF characteristics was remarkable.

1 Solar cell 7 1st region 7b, 8b Bus bar part 7f, 8f Finger part 8 2nd area 11 Semiconductor substrate 13,23 Intrinsic semiconductor layer 15 Optical adjustment layer 25 1st conductive semiconductor layer 25Z 1st conductive semiconductor layer Material film 27 1st electrode layer 28,38 Transparent electrode layer 29,39 Metal electrode layer 35 2nd conductive semiconductor layer 37 2nd electrode layer

Claims (3)

A first conductive semiconductor layer formed in a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and another part of the semiconductor substrate on the other main surface side. A method for manufacturing a back-bonded solar cell including a second region and a second conductive semiconductor layer formed on the first conductive semiconductor layer in the first region.
An intrinsic semiconductor layer forming step of forming an intrinsic semiconductor layer in the first region and the second region on the other main surface side of the semiconductor substrate.
After forming the lift-off layer on the intrinsic semiconductor layer, the lift-off layer in the first region is removed by using an etching solution to form the patterned lift-off layer in the second region. Layer formation process and
A first semiconductor layer material film forming step of forming a material film of the first conductive type semiconductor layer on the intrinsic semiconductor layer in the first region and on the lift-off layer in the second region.
By removing the lift-off layer in the second region, the material film of the first conductive semiconductor layer in the second region is removed, leaving the intrinsic semiconductor layer in the second region, and the first region. In addition, a first semiconductor layer forming step of forming the patterned first conductive semiconductor layer, and
A second semiconductor layer forming step of forming the second conductive semiconductor layer on the first conductive semiconductor layer in the first region and on the intrinsic semiconductor layer in the second region.
A method of manufacturing a solar cell, including. A first conductive semiconductor layer formed in a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and another part of the semiconductor substrate on the other main surface side. A back-bonded solar cell including a second region and a second conductive semiconductor layer formed on the first conductive semiconductor layer in the first region.
In the first region, the first conductive semiconductor layer and the second conductive semiconductor layer are sequentially laminated on the other main surface side of the semiconductor substrate via an intrinsic semiconductor layer.
In the second region, the second conductive semiconductor layer is laminated on the other main surface side of the semiconductor substrate via the intrinsic semiconductor layer.
The intrinsic semiconductor layer in the first region and the intrinsic semiconductor layer in the second region are connected to each other.
The second conductive semiconductor layer in the first region and the second conductive semiconductor layer in the second region are connected to each other.
The particles of the first conductive semiconductor layer are attached to the surface side of the first conductive semiconductor layer in the first region.
Solar cell. The solar cell according to claim 2, wherein the thickness of the second conductive semiconductor layer is 3.5 nm or more.

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