KR20140021730A - Solar cell and manufacturing method thereof - Google Patents

Abstract

The present invention relates to solar cell and a manufacturing method thereof. An embodiment according to the present invention comprises: a substrate containing the impurities of a first conductivity type and a silicon; an emitter part containing impurities of a second conductivity type opposite the first conductivity type located on the rear surface of the substrate; a rear side field part located on the rear surface of the substrate and containing a high concentration of impurities of the first conductivity type than the substrate; a first electrode connecting to the emitter part; and a second electrode connecting the rear side field part, wherein the emitter part consists of an amorphous silicon and the rear side field part consists of crystalline silicon.

Description

SOLAR CELL AND MANUFACTURING METHOD THEREOF

The present invention relates to a solar cell and a manufacturing method thereof.

Recently, as energy resources such as oil and coal are expected to be depleted, interest in alternative energy to replace them is increasing, and solar cells that produce electric energy from solar energy are attracting attention.

Typical solar cells have a semiconductor portion that forms a p-n junction by different conductive types, such as p-type and n-type, and electrodes connected to semiconductor portions of different conductivity types, respectively.

When light is incident on the solar cell, a plurality of electron-hole pairs are generated in the semiconductor, and the generated electron-hole pairs are separated into electrons and holes, which are electric charges, and the electrons move toward the n-type semiconductor portion, and the holes are p-type. Move toward the semiconductor portion. The transferred electrons and holes are collected by the different electrodes connected to the p-type semiconductor portion and the n-type semiconductor portion, respectively, and the electrodes are connected by a wire to obtain electric power.

The present invention provides a solar cell and a method for manufacturing the same, which can simplify the manufacturing process more.

One example of a solar cell according to the present invention includes a substrate containing impurities of a first conductivity type and containing crystalline silicon; An emitter portion disposed on the rear surface of the substrate and containing impurities of a second conductivity type opposite to the first conductivity type; A rear electric field unit positioned on a rear surface of the substrate and containing a higher concentration of impurities of a first conductivity type than the substrate; A first electrode connected to the emitter portion; And a second electrode connected to the rear electric field part, wherein the emitter part includes amorphous silicon, and the back electric field part includes crystalline silicon.

Here, the rear electric field portion may be formed inside the substrate, and the emitter portion may be formed outside the substrate. In one example, the substrate may include a depression in the rear surface, the rear electric field may be located in the depression.

In addition, the solar cell according to the present invention may further include a conductive layer positioned on the emitter portion, and the conductive layer may include a transparent conductive oxide (TCO).

In addition, the first electrode may directly contact the conductive layer, and the second electrode may directly contact the rear electric field part.

In addition, an example of the solar cell manufacturing method according to the present invention comprises the steps of forming an emitter portion containing an impurity of the second conductivity type opposite to the first conductivity type on the rear surface of the substrate containing the impurity of the first conductivity type; Forming a backside electric field containing an impurity of a first conductivity type inside a backside of the substrate; Forming a first electrode electrically connected to the emitter portion; And forming a second electrode electrically connected to the backside electric field, wherein the emitter portion is formed by depositing amorphous silicon containing impurities of a second conductivity type on the backside of the substrate, and the backside electric field of the substrate It is formed by diffusing impurities of the first conductive phase type on the back surface.

Here, the step of forming a conductive layer on the emitter portion between the step of forming the emitter portion and the back side electric field portion; Etching a portion of the conductive layer to expose a portion of the emitter portion; And forming a first passivation layer on the exposed emitter portion and the conductive layer.

Also, between the step of forming the emitter portion and the back side electric field portion, forming a conductive layer on the emitter portion; Etching a portion of the conductive layer and the emitter portion to expose a portion of the rear surface of the substrate; And forming a first passivation layer on a portion of the exposed back surface of the substrate and the conductive layer.

In addition, after applying the first etching paste on a portion of the conductive layer, heat treatment may be performed to etch a portion of the conductive layer, or a portion of the conductive layer and the emitter portion.

Here, the heat treatment temperature of the heat treatment process may be between about 150 ℃ to 250 ℃.

The forming of the backside electric field may include applying a dopant paste containing an impurity of a first conductivity type on the first passivation layer; And irradiating a laser beam on the dopant paste to diffuse impurities of the dopant paste onto the rear surface of the substrate.

In addition, in the step of applying the dopant paste, the dopant paste may be applied on the first protective film formed on the back surface or the emitter portion of the substrate exposed by etching.

In addition, a portion of the first passivation layer coated with the dopant paste may be removed by a laser beam.

In addition, the forming of the first electrode may include applying a second etching paste on the first passivation layer disposed on the conductive layer; And performing a heat treatment to etch a part of the first passivation layer.

In addition, by using a plating method, a first electrode electrically connected to the conductive layer and a second electrode electrically connected to the rear field part may be formed.

The solar cell and the method of manufacturing the same according to the present invention are formed by depositing an emitter portion on a rear surface of a substrate and forming a diffused electric field on a rear surface, thereby simplifying the manufacturing process of the solar cell, thereby reducing manufacturing costs. .

1 to 2 are diagrams for explaining a first embodiment of a solar cell according to the present invention.
3A to 3K are diagrams for explaining an example of a method of manufacturing the solar cell shown in FIG. 1.
4 is a view for explaining a second embodiment of a solar cell according to the present invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. When a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case directly above another portion but also the case where there is another portion in between. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle. Also, when a part is formed as "whole" on the other part, it means not only that it is formed on the entire surface (or the front surface) of the other part but also not on the edge part.

Hereinafter, a solar cell according to the present invention will be described with reference to the accompanying drawings.

1 to 2 are diagrams for explaining a first embodiment of a solar cell according to the present invention.

1 is a partial perspective view of a solar cell according to the present invention, and FIG. 2 is a cross-sectional view taken along a line II-II of the solar cell shown in FIG.

1 and 2, a solar cell 1 according to an example of the present invention includes a front surface electric field unit 171 (front surface) which is positioned on a substrate 110, a first surface of the substrate 110, that is, on a front surface thereof. field, FSF) 171, the anti-reflection film 130 positioned on the front electric field unit 171, the second surface opposite to the first surface of the substrate 110, that is, the plurality of emitter units 121 positioned on the rear surface. ), A plurality of back surface fields 172 (back surface field, BSF) 172 and a plurality of emitter portions 121 which are positioned on the rear surface of the substrate 110 and extend in parallel with the plurality of emitter portions 121. A plurality of first electrodes 141 and a plurality of second electrodes 142 positioned on the plurality of rear electric field parts 172 may be included.

1 and 2, the solar cell according to the present invention, in addition to the above-described configuration, the conductive layer 150 on the emitter portion 121, the first passivation layer 191 and the substrate (on the emitter portion 121). A second passivation layer 192 may be further included between the 110 and the emitter unit 121.

As described above, in FIGS. 1 and 2, the solar cell 1 according to the present invention includes the anti-reflection film 130, the front electric field part 171, the conductive layer 150, the first protective film 191, and the first protective film 191. 2, the anti-reflective film 130, the front electric field part 171, the conductive layer 150, the first passivation film 191 and the second passivation film 192 may be formed. It may be omitted.

However, when the anti-reflection film 130, the front electric field part 171, the conductive layer 150, the first passivation layer 191 and the second passivation layer 192 are formed, the photoelectric efficiency of the solar cell may be further improved. Hereinafter, an example in which the anti-reflection film 130, the front electric field part 171, the conductive layer 150, the first passivation layer 191 and the second passivation layer 192 are included in the solar cell 1 will be described.

The substrate 110 may be a crystalline substrate 110 of a first conductivity type, for example, silicon of n-type conductivity type. At this time, the silicon may be crystalline silicon such as single crystal silicon or polycrystalline silicon. Impurities of pentavalent elements such as phosphorus (P), arsenic (As), and antimony (Sb) are doped to the substrate 110 when the substrate 110 has an n-type conductivity type. Alternatively, however, the substrate 110 may be of the p-type conductivity type and may be made of a semiconductor material other than silicon. When the substrate 110 has a p-type conductivity type, the substrate 110 is doped with an impurity of a trivalent element such as boron (B), gallium (Ga), indium (In)

The substrate 110 has a front surface textured to have an uneven surface. For convenience, in FIG. 1, only the edge portion of the substrate 110 is illustrated as an uneven surface, but substantially the entire front surface of the substrate 110 has an uneven surface, which causes the anti-reflection film 130 positioned on the front surface of the substrate 110. And the front electric field portion 171 may also have an uneven surface.

In addition, in FIGS. 1 and 2, only the front surface of the substrate 110 is illustrated as having a concave-convex surface. Alternatively, the solar cell according to the present invention may not only have a front surface of the substrate 110 but also a rear surface of the substrate 110. A concave-convex surface can also be provided.

Next, the front electric field unit 171 may be located on the front surface of the substrate 110, as shown in FIGS. 1 and 2.

The front field 171 may have a potential barrier due to a difference in impurity concentration between the substrate 110 and the front field 171 to prevent electric charges (eg, holes) from moving toward the front of the substrate 110. There is.

Accordingly, the front electric field 171 has a front electric field effect for returning holes moving toward the front of the substrate 110 toward the back of the substrate 110 by the potential barrier, and thus, the front electric field 171 is The amount of charge output to the external device is increased, and the amount of charge lost by recombination or defects at the front of the substrate 110 is reduced.

The front electric field unit 171 may include hydrogen, and in the case of containing hydrogen, it is possible to stabilize defects such as dangling bonds mainly present on and near the surface of the substrate 110. Switching to a bond may perform a passivation function that reduces the dissipation of charges on the front surface of the substrate 110 due to defects.

The front electric field unit 171 may be formed of one layer, but may also be formed of a plurality of layers.

For example, the front electric field part 171 may include an amorphous silicon layer 171b containing impurities of a first conductivity type on the intrinsic amorphous silicon layer 171a and the intrinsic amorphous silicon layer 171a directly contacting the entire surface of the substrate 110. ) May be included.

In addition, the front electric field unit 171 may include hydrogen, and in this case, the passivation function may also be performed.

Next, the anti-reflection film 130 may be positioned on the front electric field part 171 and may reduce the reflectivity of light incident on the solar cell 1 and increase selectivity of a specific wavelength region, thereby improving efficiency of the solar cell 1. Increase The anti-reflection film 130 may include at least one of a silicon nitride film (SiNx), a zinc oxide (ZnO), or an aluminum zinc oxide (AZO).

As described above, although the anti-reflection film 130 has a single film structure in FIGS. 1 and 2, the anti-reflection film 130 may be formed in a double film structure or a multilayer film structure.

The plurality of emitter parts 121 extend in a direction parallel to the rear electric field part 172 on a rear surface of the substrate 110.

As shown in FIGS. 1 and 2, the rear electric field part 172 and the emitter part 121 are alternately positioned on the substrate 110.

Each emitter portion 121 is formed on the rear surface of the substrate 110, and has a second conductivity type, for example, a p-type conductivity type, which is opposite to the conductivity type of the substrate 110, and thus emitter portion 121 is formed. Forms a pn junction with the substrate 110.

Hole pairs formed by the light incident on the substrate 110 are separated into electrons and holes by the pn junction formed between the substrate 110 and the plurality of emitter sections 121 so that the electrons are moved toward the n- And the holes move toward the p-type. Therefore, when the substrate 110 is n-type and the plurality of emitter portions 121 are p-type, the separated holes move toward the respective emitter portions 121, and the separated electrons are separated into a plurality of And moves toward the rear electric power 172 side.

Each emitter section 121 forms a pn junction with the substrate 110. Thus, unlike the present embodiment, when the substrate 110 has a p-type conductivity type, the emitter section 121 is an n-type conductivity type I have. In this case, the separated electrons move toward the plurality of emitter parts 121, and the separated holes move toward the plurality of rear electric field parts 172.

When the emitter portion 121 has a p-type conductivity type The emitter portion 121 may be doped with an impurity of a trivalent element. On the contrary, when the emitter portion 121 has an n-type conductivity type. The emitter unit 121 may be doped with impurities of a pentavalent element.

In the solar cell according to the present invention, since the substrate 110 includes crystalline silicon and the emitter portion 121 includes amorphous silicon, and the emitter portion 121 forms a pn junction with the rear surface of the substrate 110, As well as forming hetero junctions. As described above, when the substrate 110 and the emitter portion 121 form heterojunctions, the open voltage Voc of the solar cell may be further improved.

The thickness of the emitter unit 121 may be formed between 10 nm and 30 nm in consideration of the power generation efficiency and manufacturing cost of the solar cell.

The plurality of backside electric fields 172 is a region containing impurities of the same first conductivity type as the substrate 110 at a higher concentration than the substrate 110. For example, when the substrate 110 includes an n-type impurity, the plurality of rear electric field parts 172 may be n + impurity regions.

The plurality of rear electric field parts 172 are disposed on the rear surface of the substrate 110 and extend in a predetermined direction in parallel with the emitter part 121. Here, the rear electric field unit 172 may be formed to be spaced apart from each other, as shown in Fig. 1 and 2, the emitter unit 121, it may be formed in contact with each other. Hereinafter, as shown in FIGS. 1 and 2, a case in which the rear electric field part 172 and the emitter part 121 are formed to be spaced apart from each other will be described as an example.

This rear electric field 172 prevents the hole movement toward the rear electric field 172, which is the direction of movement of the electrons, due to the potential barrier due to the difference in impurity concentration between the substrate 110 and the rear electric field 172, (E. G., Electrons) to the electrical system 172. The < / RTI > Thus, the amount of charge lost by recombination of electrons and holes in the rear electric field 172 and in the vicinity thereof or at the first and second electrodes 141 and 142 is reduced and the electron movement is accelerated to the rear electric field 172 The electron transfer amount can be increased.

Each of the plurality of first electrodes 141 is located on the plurality of emitter sections 121 and extends along the plurality of emitter sections 121 and is electrically and physically connected to the plurality of emitter sections 121. Each first electrode 141 collects charges, for example, holes, which have migrated toward the corresponding emitter section 121.

A plurality of second electrodes 142 extend over the plurality of rear electrical components 172 and are electrically and physically connected to the plurality of rear electrical components 172 have. Each second electrode 142 collects a charge, e. G., Electrons, that travels toward the corresponding rear electric field 172.

 The plurality of first and second electrodes 141 and 142 may be formed of a conductive metal material. For example, nickel (Ni), copper (Cu), silver (Ag), aluminum (Al), tin (Sn), zinc (Zn), indium (In), titanium (Ti), gold (Au) and these It may be made of at least one conductive material selected from the group consisting of, or alternatively, it may be formed including a transparent conductive metal, for example TCO.

Since the first electrode 141 and the second electrode 142 are positioned on the emitter unit 121 and the rear electric field unit 172, respectively, the pattern of the emitter unit 121 and the rear electric field unit 172 is the same. They may alternate in parallel with one another and extend in a constant direction.

The operation of the solar cell 1 according to this embodiment having such a structure is as follows.

When light is irradiated onto the solar cell 1 and incident on the substrate 110, electron-hole pairs are generated in the substrate 110 by light energy. These electron-hole pairs are separated from each other by the pn junction of the substrate 110 and the emitter section 121, and the holes move toward the emitter section 121 having the p-type conductivity type, and electrons move to the n- And are transferred to the first electrode 141 and the second electrode 142, respectively, and are collected by the first and second electrodes 141 and 142, respectively. When the first electrode 141 and the second electrode 142 are connected to each other by a conductor, a current flows and the external power is utilized.

Meanwhile, in the solar cell according to the present invention, the emitter part 121 is formed by depositing amorphous silicon containing impurities of the second conductivity type on the rear surface of the substrate 110, and the rear electric field part 172 is the substrate 110. It is formed by diffusing impurities of the first conductivity type on the rear surface of the substrate.

Accordingly, the emitter part 121 includes amorphous silicon containing the second conductive impurity, and the back surface field part 172 includes crystalline silicon containing the first conductive impurity. The structure of such a solar cell is to implement a back-heterojunction solar cell that relatively improves the power generation efficiency, there is an effect that can simplify the manufacturing process more.

More specifically, when implementing a back heterojunction solar cell, in contrast to the present invention, when the emitter portion 121 and the rear electric field portion 172 are formed by depositing amorphous silicon on the rear surface of the substrate 110, it is relatively Since a complex patterning process is required, and the amorphous silicon included in the emitter unit 121 and the rear electric field unit 172 must contain impurities of different conductivity types, the process must be deposited in different deposition chambers. It is relatively complicated.

For example, when the emitter portion 121 is formed on the rear surface of the substrate 110, in the emitter portion 121 deposition chamber, amorphous silicon containing impurities of the second conductivity type is formed on the entire rear surface of the substrate 110. After forming the emitter unit 121 including, the portion of the emitter unit 121 needs to be etched in order to provide the region on which the rear field unit 172 is to be formed on the rear surface of the substrate 110.

In this case, in order to etch a part of the emitter part 121, after etching a part of the emitter part 121 using an etch stop mask, the mask is applied only to the emitter part 121 remaining on the rear surface of the substrate 110. After the formation, the back field 172 including amorphous silicon containing impurities of the first conductivity type must be formed on the back of the substrate 110 exposed by etching in the back field 172 deposition chamber. .

In such a case, the manufacturing process of a solar cell becomes complicated, and the price of a solar cell can rise relatively.

However, the solar cell according to the present invention is formed by depositing only the emitter portion 121 with amorphous silicon, and the rear electric field portion 172 is formed of a substrate (using a dopant paste DP containing a first conductive impurity and a laser beam). Since the structure can be formed by diffusing the first conductive impurity on the rear surface of the 110, a chamber is not required when forming the rear electric field portion 172, and dopant paste (DP) when the rear electric field portion 172 is formed. ) And the laser beam, there is no need to use a separate etch mask. Therefore, the manufacturing process of a solar cell can be made simpler.

In this case, the solar cell according to the present invention, due to the features of the manufacturing process, as shown in Figure 2, the substrate 110 includes a recessed portion in the remaining region other than the region where the emitter portion 121 is formed in the rear surface; The rear electric field unit 172 may be located in a recess formed in the rear of the substrate 110.

In addition, as illustrated in FIG. 2, the conductive layer 150 formed on the emitter portion 121 may include a transparent conductive oxide (TCO), for example, ITO. The conductive layer 150 serves to minimize the contact resistance between the emitter portion 121 and the first electrode 141, and further includes the first electrode 141 electrically connected to the emitter portion 121. It is possible to prevent the emitter portion 121 from being damaged during the process of forming the emitter portion 121.

The conductive layer 150 may be formed to be thicker than the thickness of the emitter portion 121. For example, the thickness of the conductive layer 150 may be formed between 40 nm and 80 nm.

The thickness of the conductive layer 150 is 40 nm or more in order to have a minimum thickness in order to prevent damage to the emitter portion 121. The thickness of the conductive layer 150 is 80 nm or less. This is to minimize battery manufacturing costs.

Next, the first passivation layer 191 may be formed on the emitter portion 121 and on the rear surface of the substrate 110.

More specifically, as shown in FIG. 2, when the conductive layer 150 is on the emitter portion 121, a portion of the first passivation layer 191 is formed on the conductive layer 150 on the emitter portion 121. The remaining portion of the first passivation layer 191 may be formed on a region where the emitter portion 121 is not formed on the rear surface of the substrate 110.

The first passivation layer 191 may include a plurality of layers.

For example, the first passivation layer 191 may further include a lower passivation layer 191a directly contacting the conductive layer 150 and the substrate 110 and an upper passivation layer 191b formed on the lower passivation layer 191a. In this case, the lower passivation layer 191a may include intrinsic amorphous silicon, and the upper passivation layer 191b may include at least one of silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide.

The first passivation layer 191 prevents the carrier, which is moved to the rear surface of the substrate 110, from being lost by the defect, thereby increasing the short circuit current of the solar cell.

In addition, the solar cell according to the present invention may further include a second passivation layer 192 between the emitter unit 121 and the substrate 110 as shown in FIG. 2.

The second passivation layer 192 may include intrinsic amorphous silicon, and like the first passivation layer 191, the carrier which is moved to the rear surface of the substrate 110 may be prevented from being lost by a defect. It serves to increase the short circuit current of the battery.

When the second passivation layer 192 is excessively thick, when the carrier generated in the substrate 110 moves to the emitter part 121, it may be disturbed. Therefore, the thickness of the second passivation layer 192 may be thinner than the emitter portion 121, and may be formed, for example, between 1 nm and 5 nm.

In addition, the first electrode 141 and the second electrode 142 of the solar cell according to the present invention may be formed by a plating method.

Thus, although not shown in FIG. 2, each of the first electrode 141 and the second electrode 142 may include a seed layer and a conductive metal layer.

Here, the seed layer may be in contact with the surface of the emitter portion 121 or the rear electric field portion 172, the conductive metal layer may be formed on the seed layer.

As such, the seed layer may include a nickel silicon compound (Ni silicide), and the conductive metal layer may include at least one of copper (Cu), tin (Sn), and silver (Ag).

1 and 2 have been described only for the structure of a solar cell according to an example of the present invention, the following will be described in detail for the process of manufacturing such a solar cell.

3A to 3K are diagrams for explaining an example of a method of manufacturing the solar cell shown in FIG. 1.

First, as shown in FIG. 3A, a substrate 110 containing impurities of a first conductivity type is prepared.

The substrate 110 may have an uneven surface by texturing the entire surface by saw damage etching. In addition, unlike FIG. 3A, the substrate 110 may have a back check uneven surface of the substrate 110.

Next, as shown in FIG. 3B, the front surface electric field 171 may be formed on the entire front surface of the substrate 110, and then the anti-reflection film 130 may be formed on the front surface electric field 171. The anti-reflection film 130 and the front electric field unit 171 may be formed by being deposited in a CVD chamber or a PECVD chamber.

1 and 2, since the intrinsic amorphous silicon layer 171a is formed directly on the entire surface of the substrate 110, the front electric field part 171 may be formed of the first conductive type on the intrinsic amorphous silicon layer. An amorphous silicon layer 171b containing an impurity may be formed to be composed of a plurality of layers.

In addition, the second protective layer 192 containing amorphous silicon is first formed on the entire rear surface of the substrate 110, and then the emitter unit 121 including the second conductive impurity and amorphous silicon is formed on the entire second protective layer 192. The conductive layer 150 including the transparent conductive oxide (TCO) may be sequentially formed on the entire surface of the emitter unit 121. Here, the second passivation layer 192 and the emitter unit 121 may be formed by being deposited in the CVD chamber or the PECVD chamber.

Next, a portion of the second passivation layer 192, the emitter portion 121, and the conductive layer 150 formed on the entire rear surface of the substrate 110 is etched.

To this end, as shown in FIG. 3C, a part of the emitter part 121 and the conductive layer 150 may apply the first etching paste EP1 on the part of the emitter part 121 and the conductive layer 150.

Thereafter, as illustrated in FIG. 3D, heat is applied to the first etching paste EP1 to remove a portion of the emitter portion 121, the conductive layer 150, and the second passivation layer 192 disposed on the rear surface of the substrate 110. Etching may expose the rear surface of the substrate 110. In this case, in FIG. 3D, not only part of the emitter part 121 but also part of the conductive layer 150 is etched. For example, the emitter part 121 may not be etched. Partial etching is also possible. The structure of the solar cell according to this will be described later with reference to FIG. 4.

As such, the heat treatment temperature in the process of etching the emitter portion 121 and the portion of the conductive layer 150 using the first etching paste EP1 may be approximately 150 ° C to 250 ° C.

As such, the limit of the heat treatment temperature is to minimize the damage caused by the heat of the substrate 110 while the etching process of the emitter portion 121 and the conductive layer 150 is performed as desired.

Next, as shown in FIG. 3E, the first passivation layer 191 may be formed on the emitter unit 121 and on the rear surface of the substrate 110 exposed by etching. In this case, the first passivation layer 191 may be formed of a plurality of layers.

For example, as illustrated in FIG. 3E, the first passivation layer 191 may be formed on the lower passivation layer 191a and the lower passivation layer 191a directly contacting the conductive layer 150 and the substrate 110. In this case, the lower passivation layer 191a may include intrinsic amorphous silicon, and the upper passivation layer 191b may include at least one of silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. .

Subsequently, impurities of the first conductive phase type may be diffused in the rear surface of the substrate 110 to form the rear surface electric field part 172 containing the impurities of the first conductive type.

To this end, a dopant paste DP containing an impurity of the first conductivity type may be coated on the rear surface of the substrate 110.

For example, as illustrated in FIG. 3F, the dopant paste DP may be coated on the first passivation layer 191 formed in contact with the rear surface of the substrate 110 exposed by being etched by the first etching paste EP1. .

Thereafter, as illustrated in FIG. 3G, by irradiating a laser beam to the dopant paste DP by using the laser gun LB, impurities of the dopant paste DP are diffused to the rear surface of the substrate 110 and then the front surface of the rear surface is spread. The system unit 172 may be formed.

As such, when the laser beam is irradiated onto the dopant paste DP, the first passivation layer 191 may be etched by the laser beam, and a portion of the rear surface of the substrate 110 may be etched together.

Accordingly, a recess is formed on the rear surface of the substrate 110, and the first conductive impurity contained in the dopant paste DP is diffused into the recess by heat of the laser beam.

Accordingly, the backside electric field 172 may be formed in the recessed portion formed on the backside of the substrate 110 at a higher concentration than the substrate 110.

Thereafter, as shown in FIG. 3H, after forming the rear electric field 172 on the rear surface of the substrate 110, the dopant paste DP remaining on the rear surface of the substrate 110 is removed.

Next, a first electrode 141 electrically connected to the emitter unit 121 and a second electrode 142 electrically connected to the rear electric field unit 172 may be formed.

For example, as illustrated in FIG. 3I, first, a second etching paste EP2 may be applied onto the first passivation layer 191 disposed on the conductive layer 150 to form the first electrode 141. have.

Next, as illustrated in FIG. 3J, the first protective layer 191 disposed on the conductive layer 150 may be etched by applying heat to the second etching paste EP2. At this time, the temperature of the heat applied to the second etching paste EP2 may be approximately 150 ° C to 250 ° C.

In this case, the conductive layer 150 positioned between the emitter unit 121 and the first passivation layer 191 may prevent the emitter unit 121 from being etched or damaged by the second etching paste EP2. . If the thickness of the emitter portion 121 is relatively very thin, the role of the conductive layer 150 becomes particularly important.

Thereafter, as illustrated in FIG. 3K, a first electrode 141 electrically connected to the emitter unit 121 is formed on the conductive layer 150 exposed by etching, and is connected to the rear electric field unit 172. The second electrode 142 may be formed.

In this case, the first electrode 141 and the second electrode 142 may be formed by a plating method. As such, when the first electrode 141 and the second electrode 142 are formed by the plating method, a separate patterning process for forming the first electrode 141 and the second electrode 142 is not required. The manufacturing process can be further simplified.

For example, the first electrode 141 and the second electrode 142 may be formed by mixing an electroless plating method and an electrolytic plating method.

For example, when forming each seed layer of the first electrode 141 and the second electrode 142, an electroless plating method such as light induced plating (LIP) is used, and then a conductive metal layer is formed on the seed layer. In this case, an electrolytic plating method may be used.

As such, by using an electroless plating method, contact resistance between the first electrode 141 and the emitter portion 121 and the second electrode 142 and the rear electric field portion 172 can be reduced, and electrolytic plating By using the method, the electrode formation rate can be further improved by supplementing the electroless plating method, which is relatively slow in forming the electrode.

As such, one example of the solar cell manufacturing method according to the present invention is to simplify the solar cell manufacturing process by using a mixture of the deposition method and the diffusion method when forming the emitter portion 121 and the back electric field portion 172. This can further reduce manufacturing time and cost.

Next, Figure 4 is a view for explaining a second embodiment of a solar cell according to the present invention.

In FIG. 4, descriptions of parts overlapping with those described in FIG. 2 will be omitted, and only parts different from those of FIG. 2 will be described.

As shown in FIG. 4, in the solar cell according to the second embodiment, the emitter portion 121 may be formed on the rear surface of the substrate 110 to be wider than the conductive layer 150.

As described above with reference to FIG. 3D, when the etching is performed using the first etching paste EP1, only a part of the conductive layer 150 is etched without etching the emitter portion 121, and the dopant paste DP is etched. When the back field unit 172 is formed using the laser beam and the laser beam, a portion of the emitter unit 121 may be etched.

As described above, unlike in FIG. 3D, when etching using the first etching paste EP1, only a part of the conductive layer 150 is etched and the emitter portion 121 is left without being etched. It is possible to minimize the influence of the back surface of the substrate 110 by the EP1, thereby preventing the factors that can reduce the carrier life time generated in the substrate (110).

Therefore, the solar cell according to the second embodiment can extend the life of the carrier more than the solar cell according to the first embodiment, thereby further improving the power generation efficiency of the solar cell.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, Of the right.

Claims (16)

A substrate containing impurities of the first conductivity type and containing crystalline silicon;
An emitter portion disposed on a rear surface of the substrate and containing impurities of a second conductivity type opposite to the first conductivity type;
A rear electric field unit positioned on a rear surface of the substrate and containing a higher concentration of impurities of the first conductivity type than the substrate;
A first electrode connected to the emitter; And
And a second electrode connected to the rear electric field portion,
And the emitter portion comprises amorphous silicon and the back field portion comprises crystalline silicon. The method according to claim 1,
The rear electric field portion is formed inside the substrate, and the emitter portion is formed outside the substrate. The method of claim 2,
The substrate includes a recess on the back side,
The back field is a solar cell located in the depression. The method according to claim 1,
The solar cell further comprises a conductive layer positioned on the emitter portion. 5. The method of claim 4,
The conductive layer includes a transparent conductive oxide (TCO). 5. The method of claim 4,
The first electrode is in direct contact with the conductive layer, and the second electrode is in direct contact with the back field. Forming an emitter portion containing an impurity of a second conductivity type opposite to the first conductivity type on a back surface of the substrate containing an impurity of a first conductivity type;
Forming a backside electric field portion containing impurities of the first conductivity type in a backside of the substrate;
Forming a first electrode electrically connected to the emitter portion; And
And forming a second electrode electrically connected to the rear field part.
The emitter part is formed by depositing amorphous silicon containing impurities of the second conductivity type on the rear surface of the substrate,
And the rear electric field part is formed by diffusing impurities of the first conductive phase type on a rear surface of the substrate. The method of claim 7, wherein
Between forming the emitter portion and forming the rear electric field portion,
Forming a conductive layer on the emitter portion;
Etching a portion of the conductive layer to expose a portion of the emitter portion; And
Forming a first passivation layer on the exposed emitter portion and the conductive layer
Solar cell manufacturing method comprising a more. The method of claim 7, wherein
Between forming the emitter portion and forming the rear electric field portion,
Forming a conductive layer on the emitter portion;
Etching a portion of the conductive layer and the emitter to expose a portion of the rear surface of the substrate; And
Forming a first passivation layer on a portion of the exposed back surface of the substrate and the conductive layer;
Solar cell manufacturing method comprising a more. 10. The method according to claim 8 or 9,
Applying a first etching paste on a portion of the conductive layer and then performing heat treatment to etch a portion of the conductive layer or a portion of the conductive layer and the emitter portion. 11. The method of claim 10,
The heat treatment temperature of the heat treatment step is about 150 ℃ to 250 ℃ manufacturing method of a solar cell. 11. The method of claim 10,
The step of forming the rear surface electric field portion
Applying a dopant paste containing an impurity of the first conductivity type on the first passivation layer; And
Irradiating the dopant paste with a laser beam to diffuse impurities from the dopant paste onto the rear surface of the substrate;
Solar cell manufacturing method comprising a. 13. The method of claim 12,
In the step of applying the dopant paste,
The dopant paste is applied to the first protective film formed on the back of the substrate or the emitter portion exposed by etching. 13. The method of claim 12,
And removing a portion of the first passivation layer coated with the dopant paste by the laser beam. 15. The method of claim 14,
The step of forming the first electrode
Applying a second etching paste on the first passivation layer disposed on the conductive layer; And
Etching a portion of the first passivation layer by performing a heat treatment. 16. The method of claim 15,
Forming a first electrode electrically connected to the conductive layer and the second electrode electrically connected to the rear electric field part by using a plating method.

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