WO2020182017A1 - 像素电路、显示面板、显示装置和像素驱动方法 - Google Patents

像素电路、显示面板、显示装置和像素驱动方法 Download PDF

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Publication number
WO2020182017A1
WO2020182017A1 PCT/CN2020/077571 CN2020077571W WO2020182017A1 WO 2020182017 A1 WO2020182017 A1 WO 2020182017A1 CN 2020077571 W CN2020077571 W CN 2020077571W WO 2020182017 A1 WO2020182017 A1 WO 2020182017A1
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Prior art keywords
transistor
control signal
compensation
circuit
voltage
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PCT/CN2020/077571
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English (en)
French (fr)
Inventor
胡祖权
江鹏
戴珂
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京东方科技集团股份有限公司
合肥京东方显示技术有限公司
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Priority to US17/052,558 priority Critical patent/US11295668B2/en
Publication of WO2020182017A1 publication Critical patent/WO2020182017A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation

Definitions

  • the present invention relates to the field of display technology, and in particular to a pixel circuit, a display panel, a display device and a pixel driving method.
  • OLED Organic Light-Emitting Diode
  • the ability to emit light is driven by the current generated by the driving transistor in the saturation state.
  • different threshold voltages will generate different driving currents, which causes current inconsistency.
  • An embodiment of the present disclosure provides a pixel circuit, including: a data compensation circuit, a storage circuit, a driving transistor, and a replica transistor, the replica transistor and the driving transistor have the same structure;
  • the gate of the replica transistor, the gate of the drive transistor, the data compensation circuit, and the storage circuit are connected to a first node, and the first pole of the replica transistor and the second pole of the replica transistor are both Connected to the data compensation circuit, the first electrode of the driving transistor is connected to the first electrode of the light emitting device, and the second electrode of the driving transistor is connected to the second power terminal;
  • the data compensation circuit is connected to the first power terminal, the data line, the first control signal line, the second control signal line, and the third control signal line for responding to the second control signal line in the initialization phase
  • the second control signal provided and the third control signal provided by the third control signal line are controlled to write the first voltage provided by the first power terminal to the first node; and, for In the data writing and compensation phase, in response to the control of the third control signal and the first control signal provided by the first control signal line, the data voltage provided by the data line is written to the copy
  • the first pole of the transistor detects the threshold voltage of the replica transistor, and writes a compensation voltage to the first node for storage by the storage circuit.
  • the compensation voltage is equal to the data voltage and the replica transistor's Sum of threshold voltage;
  • the storage circuit is also connected to the second power terminal, and is used to provide the compensation voltage to the first node during the light-emitting phase;
  • the driving transistor is configured to output a corresponding driving current according to the compensation voltage during the light-emitting phase to drive the light-emitting device to emit light.
  • the data compensation circuit includes: a data writing sub-circuit and an initialization and compensation sub-circuit;
  • the data writing sub-circuit is connected to the first control signal line, and is used to write the data voltage to the first control signal in response to the control of the first control signal during the data writing and compensation phase.
  • the first pole of the replica transistor is connected to the first control signal line, and is used to write the data voltage to the first control signal in response to the control of the first control signal during the data writing and compensation phase.
  • the initialization and compensation sub-circuit is connected to the second control signal line and the third control signal line, and is used to respond to the control of the second control signal and the third control signal during the initialization phase,
  • the first voltage is written to the first node to initialize the first node; and used to respond to the control of the third control signal during the data writing and compensation phase, according to
  • the signal output from the second electrode of the replica transistor writes the compensation voltage to the first node.
  • the data writing sub-circuit includes: a first transistor
  • the control electrode of the first transistor is connected to the first control signal line, the first electrode of the first transistor is connected to the data line, and the second electrode of the first transistor is connected to the second electrode of the replica transistor.
  • One pole connection is provided.
  • the initialization and compensation sub-circuit includes: a second transistor and a third transistor;
  • the control electrode of the second transistor is connected to the second control signal line, the first electrode of the second transistor is connected to the first power supply terminal, and the second electrode of the second transistor is connected to the replica transistor The second pole connection;
  • the control electrode of the third transistor is connected to the third control signal line, the first electrode of the third transistor is connected to the second electrode of the replica transistor, and the second electrode of the third transistor is connected to the The first node is connected.
  • the storage circuit includes: a storage capacitor
  • the first end of the storage capacitor is connected to the first node, and the second end of the storage capacitor is connected to the second power terminal.
  • it further includes: a light emission control circuit connected to the first pole of the driving transistor;
  • the light-emitting control circuit is connected to a fourth control signal line, and is used to respond to the control of the fourth control signal provided by the fourth control signal line during the light-emitting phase, so that the driving output of the driving transistor is Current can flow through the light emitting device; and at other stages, the current output by the driving transistor cannot flow through the light emitting device.
  • the light emission control circuit includes: a fourth transistor
  • the control electrode of the fourth transistor is connected to the fourth control signal line, the first electrode of the fourth transistor is connected to the first power supply terminal, and the second electrode of the fourth transistor is connected to the driving transistor.
  • the fourth control signal line and the third control signal line are the same control signal line.
  • the gate of the replica transistor and the gate of the drive transistor are arranged in the same layer;
  • the active layer of the replica transistor and the active layer of the replica transistor are arranged in the same layer.
  • all transistors in the pixel circuit are N-type transistors or P-type transistors at the same time.
  • an embodiment of the present disclosure further provides a display panel, including: the above-mentioned pixel circuit.
  • an embodiment of the present disclosure further provides a display device, including: the above-mentioned display panel.
  • an embodiment of the present disclosure also provides a pixel driving method based on the above-mentioned pixel circuit, and the pixel driving method includes:
  • the data compensation circuit writes the first voltage to the first node in response to the control of the second control signal and the third control signal;
  • the data compensation circuit responds to the control of the first control signal and the third control signal to write the data voltage to the first pole of the replica transistor to detect Copying the threshold voltage of the transistor, and writing a compensation voltage to the first node for storage by the storage circuit;
  • the storage circuit provides the compensation voltage to the first node, and the driving transistor outputs a corresponding driving current according to the compensation voltage to drive the light-emitting device to emit light.
  • FIG. 1 is a schematic diagram of the circuit structure of a pixel circuit provided in the related art
  • FIG. 2 is a working timing diagram of the pixel circuit shown in FIG. 1;
  • FIG. 3 is a schematic diagram of the circuit structure of a pixel circuit provided by an embodiment of the disclosure.
  • FIG. 4 is a schematic diagram of a circuit structure of another pixel circuit provided by an embodiment of the disclosure.
  • FIG. 5 is a working timing diagram of the pixel circuit shown in FIG. 4;
  • FIG. 6 is a flowchart of a pixel driving method provided by an embodiment of the disclosure.
  • the compensation principle of the pixel circuit with threshold compensation function is as follows: first, use the compensation circuit to obtain the threshold voltage of the driving transistor and write it to the storage capacitor; then, write the data voltage to one end of the storage capacitor, based on The bootstrap function of the capacitor is to pull up the voltage at the other end of the storage capacitor (the end is connected to the gate of the drive transistor) to obtain a compensation voltage; finally, the compensation voltage is used to control the output drive current of the drive transistor to actually The driving transistor performs threshold compensation.
  • FIG. 1 is a schematic diagram of a circuit structure of a pixel circuit in the related art
  • FIG. 2 is a working timing diagram of the pixel circuit shown in FIG. 1.
  • description will be made with reference to FIGS. 1 and 2 and taking as an example that all the transistors in FIG. 1 are N-type transistors at the same time.
  • the working process of the pixel circuit shown in FIG. 1 includes the following four stages p1 to p4.
  • the scan signal line Scan provides a high level signal
  • the control signal line S1 provides a high level signal
  • the control signal line S2 provides a high level signal
  • the data line Data provides a reference voltage Vref;
  • the transistor T1 , T2, T3, and T4 are all turned on, the reference voltage Vref is written to the node a through the transistor T1, the first voltage Vdd is written to the node c through the transistor T2 and the transistor T3, and then to the node b through the transistor T4.
  • the voltage of node a is Vref
  • the voltages of node b and node c are Vdd.
  • the scan signal line Scan provides a high level signal
  • the control signal line S1 provides a low level signal
  • the control signal line S2 provides a high level signal
  • the data line Data provides a reference voltage Vref.
  • the transistor T3 is turned off.
  • Vdd no longer charges the node b and the node c. Therefore, the node b and the node c are discharged through the driving transistor DTFT, and the voltage between the two nodes begins to drop.
  • the driving transistor DTFT is turned off.
  • the voltage of node a maintains Vref
  • the voltage difference between the two ends of the storage capacitor C1 is Vref-Vss-Vth, where Vth is the threshold voltage of the driving transistor DTFT.
  • the scan signal line Scan provides a high level signal
  • the control signal line S1 provides a low level signal
  • the control signal line S2 provides a low level signal
  • the data line Data provides a data voltage Vdata.
  • the transistors T1 and T2 are turned on, and the transistors S3 and S4 are turned off. Since the transistor T4 is turned off, the node b is in a floating state.
  • the storage capacitor C1 maintains the voltage difference between the two terminals through the bootstrap function. Without considering the parasitic capacitances Cgd and Cgs of the driving transistor DTFT itself, At this time, the voltage of node b jumps to Vss+Vth+Vdata-Vref.
  • the scan signal line Scan provides a low level signal
  • the control signal line S1 provides a high level signal
  • the control signal line S2 provides a low level signal
  • the data line Data provides a reference voltage Vref.
  • the transistor T1 , T2 and T4 are off, and transistor T3 is on.
  • I is the driving current output by the driving transistor DTFT
  • K is a constant. It can be seen from the above formula that the drive current output by the drive transistor is related to the data voltage Vdata and the reference voltage Vref, and has nothing to do with the threshold voltage of the drive transistor DTFT, thereby achieving threshold compensation.
  • the driving current output by the driving transistor DTFT has nothing to do with the threshold voltage of the driving transistor, it is related to the storage capacitor C1, the parasitic capacitances Cgd and Cgs.
  • the present disclosure provides a pixel circuit, which can realize accurate compensation of the threshold voltage of the driving transistor.
  • the light-emitting device in the present disclosure may be a current-driven light-emitting device including LED (Light Emitting Diode) or OLED (Organic Light Emitting Diode) in the related art, which is implemented in the following
  • the light-emitting device is an OLED as an example.
  • the transistors in the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • a transistor generally includes three electrodes: a gate, a source, and a drain.
  • the source and drain in the transistor are structurally symmetrical, and the two can be interchanged as needed.
  • the control electrode refers to the gate of the transistor, and one of the first electrode and the second electrode is the source and the other is the drain.
  • FIG. 3 is a schematic diagram of a circuit structure of a pixel circuit according to an embodiment of the disclosure.
  • the pixel circuit includes: a data compensation circuit 1, a storage circuit 2, a driving transistor DTFT, and a copy transistor CTFT.
  • the copy transistor CTFT and the driving transistor DTFT have the same structure.
  • the gate of the copy transistor CTFT, the gate of the drive transistor DTFT, the data compensation circuit 1 and the storage circuit 2 are connected to the first node N1, and the first pole of the copy transistor CTFT and the second pole of the copy transistor CTFT are both connected to the data compensation circuit 1.
  • the first electrode of the driving transistor DTFT is connected to the first electrode of the light emitting device OLED
  • the second electrode of the light emitting device OLED is connected to the first power terminal
  • the second electrode of the driving transistor DTFT is connected to the second power terminal.
  • the data compensation circuit 1 is connected to the first power terminal, the data line Data, the first control signal line CL1, the second control signal line CL2, and the third control signal line CL3.
  • the data compensation circuit 1 is used to respond to the second The second control signal provided by the control signal line CL2 and the third control signal provided by the third control signal line CL3 are controlled to write the first voltage provided by the first power terminal to the first node N1; and, for In the data writing and compensation stage, in response to the control of the third control signal and the first control signal provided by the first control signal line CL1, the data voltage provided by the data line Data is written to the first pole of the copy transistor CTFT To detect the threshold voltage of the copy transistor CTFT, and write a compensation voltage to the first node N1 for storage by the storage circuit 2, the compensation voltage is equal to the sum of the data voltage and the threshold voltage of the copy transistor CTFT.
  • the storage circuit 2 is connected to the second power supply terminal, and the storage circuit 2 is used to provide a compensation voltage to the first node N1 during the light-emitting phase.
  • the driving transistor DTFT is used for outputting a corresponding driving current according to the compensation voltage during the light-emitting stage to drive the light-emitting device OLED to emit light.
  • the structure of the duplicate transistor CTFT and the drive transistor DTFT are the same, which specifically means that the shape, size, and materials used for the two transistors are approximately the same, so as to ensure the threshold voltage of the two transistors when they are completed. the same.
  • the replication transistor CTFT and the driving transistor DTFT can be prepared by using the same manufacturing process and at the same time, so as to ensure the same structure of the two.
  • the gate of the copy transistor CTFT is connected to the gate of the drive transistor DTFT, and the distance between the two is relatively close (located in the same pixel), so the threshold voltage drift of the two at the same time is also the same. That is, the threshold voltages of the copy transistor CTFT and the drive transistor DTFT are the same at any time.
  • the replica transistor CTFT and the driving transistor DTFT in the same pixel circuit are relatively close, so it is easy to realize the same structure of the two in the manufacturing process.
  • the positions of the two can be made as close as possible.
  • the gate of the replication transistor CTFT and the gate of the drive transistor DTFT are arranged in the same layer; the first pole of the replication transistor CTFT, the second pole of the replication transistor CTFT, the first pole of the drive transistor DTFT, and the drive transistor DTFT
  • the second pole of the four is arranged in the same layer; the active layer of the replication transistor CTFT and the active layer of the driving transistor DTFT are arranged in the same layer. That is to say, the same transistor preparation process can be used to prepare the replica transistor CTFT and the driving transistor DTFT at the same time. At this time, the process error in the preparation process can be reduced as much as possible to ensure that the prepared replica transistor CTFT and the driving transistor DTFT are prepared.
  • the positions are different, the structure is exactly the same.
  • the "same layer arrangement" in the present disclosure refers to being located in the same functional film layer structure; among them, the preparation materials of different structures arranged in the same layer are the same, so they can be prepared simultaneously by using a patterning process; The distance between the different structures of the layer arrangement and the substrate can be the same or different.
  • the first power terminal provides the first voltage Vdd and the second power terminal provides the second voltage Vss as an example for description.
  • the working process of the pixel circuit shown in FIG. 3 includes an initialization phase, a data writing and compensation phase, and a light-emitting phase.
  • the data compensation circuit 1 writes the first voltage to the first node N1 in response to the control of the second control signal and the third control signal to reset the voltage at the first node N1.
  • the data line Data provides the data voltage Vdata to the data compensation circuit 1.
  • the data compensation circuit 1 responds to the control of the first control signal and the third control signal to write the data voltage Vdata to the copy transistor CTFT.
  • a first electrode to detect replica transistor threshold voltage CTFT Vth_ CTFT, and offset voltage of the first node N1 is written to the memory circuit 2 for storing.
  • the storage circuit 2 provides a compensation voltage to the first node N1, and the driving transistor DTFT outputs a corresponding driving current according to the compensation voltage to drive the light-emitting device OLED to emit light.
  • the gate-source voltage of the driving transistor DTFT Vgs Vdata+ Vth_CTFT -Vss, according to the saturation driving current formula of the driving transistor DTFT, it can be obtained:
  • the driving current of the driving transistor DTFT related data voltage Vdata outputted, regardless of the threshold voltage of the driving transistor of the DTFT Vth_ DTFT, thus realizing the drive transistor DTFT threshold compensation.
  • the present disclosure aspect can achieve a size equal to the compensation voltage and the data voltage Vdata CTFT replica transistor and the threshold voltage of the precise Vth_ CTFT written to the first node N1, according to the compensation voltage when emission phase
  • the threshold voltage of the driving transistor DTFT can be accurately compensated.
  • the pixel circuit further includes: a light-emitting control circuit 3, which is connected to the first pole of the driving transistor DTFT; and the light-emitting control circuit 3 is also connected to a fourth control signal line CL4 for use in the light-emitting phase.
  • the driving current output by the driving transistor DTFT can flow through the light emitting device OLED; and at other stages, the current output by the driving transistor DTFT cannot flow through the light emitting device.
  • Device OLED is another stage, the current output by the driving transistor DTFT cannot flow through the light emitting device.
  • the light emission control circuit 3 by setting the light emission control circuit 3 to control the flow direction of the current output by the driving transistor DTFT, it is possible to prevent the light emitting device OLED from erroneously emitting light in other stages except the light emitting stage.
  • the light-emitting control circuit 3 and the light-emitting device OLED are connected in parallel shown in the drawings is merely illustrative, and it does not limit the technical solutions of the present disclosure.
  • the light-emitting control circuit 3 may also be arranged between the first pole of the driving transistor DTFT and the first pole of the light-emitting device OLED, and the detailed description may refer to the subsequent content.
  • FIG. 4 is a schematic diagram of a circuit structure of another pixel circuit provided by an embodiment of the disclosure. As shown in FIG. 4, the pixel circuit shown in FIG. 4 is a specific solution based on the pixel circuit shown in FIG.
  • the data compensation circuit 1 includes: a data writing sub-circuit 101 and an initialization and compensation sub-circuit 102.
  • the data writing sub-circuit 101 is connected to the first control signal line CL1, and the data writing sub-circuit 101 is used to write the data voltage to the copy transistor CTFT in response to the control of the first control signal during the data writing and compensation phase.
  • the first pole The first pole.
  • the initialization and compensation sub-circuit 102 is connected to the second control signal line CL2 and the third control signal line CL3.
  • the initialization and compensation sub-circuit 102 is used to respond to the control of the second control signal and the third control signal during the initialization phase, A voltage is written to the first node N1 to initialize the first node N1; and used to respond to the control of the third control signal during the data writing and compensation phase, according to the second pole of the replica transistor CTFT output The signal of writes the compensation voltage to the first node N1.
  • the data writing sub-circuit 101 includes a first transistor T1, a control electrode of the first transistor T1 is connected to the first control signal line CL1, a first electrode of the first transistor T1 is connected to the data line Data, and The second pole of a transistor T1 is connected to the first pole of the replica transistor CTFT.
  • the initialization and compensation sub-circuit 102 includes: a second transistor T2 and a third transistor T3; the control electrode of the second transistor T2 is connected to the second control signal line CL2, and the first electrode of the second transistor T2 is connected to the A power supply terminal is connected, the second electrode of the second transistor T2 is connected to the second electrode of the copy transistor CTFT; the control electrode of the third transistor T3 is connected to the third control signal line CL3, and the first electrode of the third transistor T3 is connected to the copy transistor The second electrode of the CTFT is connected, and the second electrode of the third transistor T3 is connected to the first node N1.
  • the storage circuit 2 includes: a storage capacitor C2; a first end of the storage capacitor C2 is connected to the first node N1, and a second end of the storage capacitor C2 is connected to a second power supply end.
  • the light emission control circuit 3 includes: a fourth transistor T4; the control electrode of the fourth transistor T4 is connected to the fourth control signal line, the first electrode of the fourth transistor T4 is connected to the first power terminal, and the fourth transistor T4
  • the second electrode of the DTFT is connected to the first electrode of the driving transistor DTFT, and the fourth control signal line and the third control signal line CL3 are the same control signal line (unified as the third control signal line CL3).
  • transistors can be divided into N-type transistors and P-type transistors; when the transistor is an N-type transistor, its turn-on voltage is a high-level voltage, and its cut-off voltage is a low-level voltage; when the transistor is a P-type transistor , Its turn-on voltage is a low-level voltage, and its cut-off voltage is a high-level voltage.
  • all transistors in the pixel circuit are simultaneously N-type transistors as an example for exemplary description.
  • the first power terminal provides a first voltage Vdd
  • the second power terminal provides a second voltage Vss (the value of Vss is approximately 0V).
  • FIG. 5 is a working timing diagram of the pixel circuit shown in FIG. 4. As shown in FIG. 5, the working process of the pixel circuit includes three stages: an initialization stage, a data writing and compensation stage, and a light-emitting stage.
  • the first control signal provided by the first control signal line CL1 is in a low level state
  • the second control signal provided by the second control signal line CL2 is in a high level state
  • the third control signal line CL3 provides The third control signal is at a high level.
  • the second transistor M2, the third transistor M3, and the fourth transistor M4 are all turned on, and the first transistor M1 is turned off.
  • the first voltage Vdd can be written to the first node N1 through the second transistor M2 and the third transistor M3, and the voltages of the first node N1 and the second node N2 are both Vdd.
  • the driving transistor DTFT will be in the on state and output current at this time, since the fourth transistor M4 is turned on (the light-emitting device OLED is short-circuited), the current output by the driving transistor DTFT will pass through the fourth transistor M4 flows to the first power terminal, but does not flow through the light-emitting device OLED, and the driving transistor DTFT does not emit light by mistake.
  • the first control signal provided by the first control signal line CL1 is at a high level
  • the second control signal provided by the second control signal line CL2 is at a low level
  • the third control signal provided by CL3 is at a high level
  • the data line Data provides a data voltage Vdata; at this time, the first transistor M1, the third transistor M3, and the fourth transistor M4 are all turned on, and the second transistor M2 is turned off.
  • the copy transistor CTFT Since the voltage at the first node N1 is Vdd at the end of the initialization phase t1, at the initial moment of the data writing and compensation phase, the copy transistor CTFT is in a conducting state. Since the first transistor M1 is turned on, the third transistor M3 is turned on, and the second transistor M2 is turned off, the first node N1 forms a path between the third transistor M3, the copy transistor CTFT, and the first transistor M1 and the data line Data. the first node N1 may be carried out by the discharge passage, the voltage at the first node N1 starts to decrease; when the voltage at the first node N1 drops to Vdata + Vth_ CTFT, CTFT replica transistor is turned off, the discharge end. Among them, the above discharging process will not be affected by the parasitic capacitances Cgd and Cgs of the driving transistor DTFT itself.
  • the above-mentioned process of the voltage at the first node N1 falling from Vdd to Vdata+Vth_CTFT can be regarded as the initialization and compensation sub-circuit 102 sensing the threshold voltage Vth_CTFT of the replica transistor CTFT according to the signal output from the second pole of the replica transistor CTFT , And the process of accurately writing the compensation voltage Vdata+Vth_CTFT to the first node N1.
  • the voltage difference between the two ends of the storage capacitor C2 is Vdata+ Vth_CTFT -Vss, that is, the storage capacitor C2 finishes storing the compensation voltage.
  • the first control signal provided by the first control signal line CL1 is in a low level state
  • the second control signal provided by the second control signal line CL2 is in a low level state
  • the second control signal provided by the third control signal line CL3 is in a low level state.
  • the three control signals are in a low level state; at this time, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all turned off.
  • the storage capacitor C2 maintains the voltage at the first node N1 as Vdata+ Vth_CTFT , that is, the storage capacitor C2 provides a compensation voltage to the first node N1.
  • the gate-source voltage of the driving transistor DTFT Vgs Vdata+ Vth_CTFT -Vss, according to the saturation driving current formula of the driving transistor DTFT, it can be obtained:
  • the driving current of the driving transistor DTFT related data voltage Vdata outputted, regardless of the threshold voltage of the driving transistor of the DTFT Vth_ DTFT, thus realizing the drive transistor DTFT threshold compensation.
  • control electrode of the fourth transistor M4 is connected to the fourth control signal line
  • first electrode of the fourth transistor M4 is connected to the first power terminal
  • second electrode of the fourth transistor M4 is connected to the first electrode of the driving transistor DTFT.
  • Polar connection, the fourth control signal line and the third control signal line CL3 are the same control signal line, which is an implementation in this disclosure, which can reduce the types of control signal lines that need to be configured in the pixel circuit , Reduce the complexity of the drive control process.
  • the fourth transistor M4 may also be arranged between the first electrode of the driving transistor DTFT and the first electrode of the light emitting device OLED (in this case, the corresponding drawings are not given). Specifically, the first electrode of the fourth transistor M4 is connected to the first electrode of the light-emitting device OLED, the second electrode of the fourth transistor M4 is connected to the first electrode of the driving transistor DTFT, and the control electrode of the fourth transistor M4 is connected to the fourth electrode.
  • the control signal line is a control signal line different from the first control signal line CL1 to the third control signal line CL3. At this time, the fourth transistor M4 is controlled by the fourth control signal provided by the fourth control signal line.
  • the fourth transistor M4 is turned on only in the light-emitting phase to transmit the driving current output by the driving transistor DTFT to the light-emitting device OLED, and the fourth transistor M4 is turned off in the initialization phase and the data writing and compensation phase to make the first pole of the driving transistor DTFT and the light-emitting device OLED The first pole is disconnected, thereby preventing the light-emitting device OLED from emitting light by mistake.
  • all the transistors in the pixel circuit are N-type transistors at the same time is a preferred embodiment in this disclosure.
  • all the transistors in the pixel circuit can be manufactured at the same time using the same manufacturing process, thereby shortening the manufacturing cycle .
  • all the transistors in the pixel circuit can also be P-type transistors at the same time.
  • the same preparation process can also be used to prepare all the transistors at the same time.
  • the transistors in the present disclosure can be independently selected from N-type transistors or P-type transistors. According to the type of transistor, the state of each transistor is controlled by configuring corresponding control signals to achieve the above-mentioned working process. It also belongs to the protection scope of the present disclosure.
  • FIG. 6 is a flowchart of a pixel driving method provided by an embodiment of the disclosure. As shown in FIG. 6, the pixel driving method is based on the pixel circuit provided in the foregoing embodiment, and the pixel driving method includes:
  • Step S1 In the initialization phase, the data compensation circuit writes the first voltage to the first node in response to the control of the second control signal and the third control signal;
  • Step S2 the data compensation circuit responds to the control of the first control signal and the third control signal to write the data voltage to the first pole of the replica transistor to detect the threshold voltage of the replica transistor, and to The first node writes the compensation voltage for storage by the storage circuit;
  • Step S3 In the light-emitting phase, the storage circuit provides a compensation voltage to the first node, and the driving transistor outputs a corresponding driving current according to the compensation voltage to drive the light-emitting device to emit light.
  • the technical solution of the present disclosure can accurately write a compensation voltage equal to the sum of the data voltage and the threshold voltage of the replica transistor to the first node.
  • the writing process is not affected by the parasitic capacitance of the driving transistor.
  • the compensation voltage controls the driving transistor to emit light, which can realize accurate compensation of the threshold voltage of the driving transistor.
  • An embodiment of the present disclosure also provides a display panel, which includes: a pixel circuit; wherein the pixel circuit adopts the pixel circuit provided in the foregoing embodiment.
  • the embodiments of the present disclosure also provide a display device, which includes a display panel; wherein the display panel adopts the display panel provided in the foregoing embodiment.
  • the display device in the present invention may specifically include: electronic paper, OLED panels, mobile phones, tablet computers, televisions, displays, notebook computers, digital photo frames, navigators and other products or components with display functions.

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Abstract

本公开提供了一种像素电路，包括：数据补偿电路、存储电路、驱动晶体管和复制晶体管，复制晶体管与驱动晶体管的结构相同；数据补偿电路用于在初始化阶段时响应于第二控制信号线所提供的第二控制信号和第三控制信号线所提供的第三控制信号的控制，将第一电源端提供的第一电压写入至第一节点；以及，用于在数据写入及补偿阶段时响应于第三控制信号和第一控制信号线所提供的第一控制信号的控制，将数据线所提供的数据电压写入至复制晶体管的第一极以探测复制晶体管的阈值电压，并向第一节点写入补偿电压以供存储电路进行存储，补偿电压等于数据电压与复制晶体管的阈值电压之和。本公开还提供了一种显示面板、显示装置和像素驱动方法。

Description

像素电路、显示面板、显示装置和像素驱动方法
相关公开的交叉引用
本公开要求于2019年3月11日提交的中国专利公开No.201910180239.4的优先权，所公开的内容以引用的方式合并于此。
技术领域
本发明涉及显示技术领域，特别涉及像素电路、显示面板、显示装置和像素驱动方法。
背景技术
有机发光二极管(Organic Light-Emitting Diode，简称OLED)
能够发光是由驱动晶体管在饱和状态时产生的电流所驱动，当输入相同的灰阶电压时，不同的阈值电压会产生不同的驱动电流，则造成电流的不一致性。
发明内容
本公开的一个实施例提供了一种像素电路，包括：数据补偿电路、存储电路、驱动晶体管和复制晶体管，所述复制晶体管与所述驱动晶体管的结构相同；
所述复制晶体管的栅极、所述驱动晶体管的栅极、所述数据补偿电路和所述存储电路连接于第一节点，所述复制晶体管的第一极和所述复制晶体管的第二极均与所述数据补偿电路连接，所述驱动晶体管的第一极与发光器件的第一极连接，所述驱动晶体管的第二极与第二电源端连接；
所述数据补偿电路与所述第一电源端、数据线、第一控制信号线、第二控制信号线、第三控制信号线连接，用于在初始化阶段时响应于所述第二控制信号线所提供的第二控制信号和所述第三控制信号线所提供的第三控制信号的控制，将所述第一电源端提供的第一电 压写入至所述第一节点；以及，用于在数据写入及补偿阶段时响应于所述第三控制信号和所述第一控制信号线所提供的第一控制信号的控制，将所述数据线所提供的数据电压写入至所述复制晶体管的第一极以探测所述复制晶体管的阈值电压，并向所述第一节点写入补偿电压以供所述存储电路进行存储，所述补偿电压等于所述数据电压与所述复制晶体管的阈值电压之和；
所述存储电路还与所述第二电源端连接，用于在发光阶段时向所述第一节点提供所述补偿电压；
所述驱动晶体管配置用于在所述发光阶段时根据所述补偿电压输出相应的驱动电流，以驱动发光器件发光。
在一些实施例中，所述数据补偿电路包括：数据写入子电路和初始化及补偿子电路；
所述数据写入子电路，与所述第一控制信号线连接，用于在所述数据写入及补偿阶段时响应于所述第一控制信号的控制，将所述数据电压写入至所述复制晶体管的第一极；
所述初始化及补偿子电路，与所述第二控制信号线和第三控制信号线连接，用于在初始化阶段时响应于所述第二控制信号和所述第三控制信号的控制，将所述第一电压写入至所述第一节点，以对所述第一节点处进行初始化；以及用于在所述数据写入及补偿阶段时，响应于所述第三控制信号的控制，根据所述复制晶体管的第二极输出的信号向所述第一节点写入所述补偿电压。
在一些实施例中，所述数据写入子电路包括：第一晶体管；
所述第一晶体管的控制极与所述第一控制信号线连接，所述第一晶体管的第一极与所述数据线连接，所述第一晶体管的第二极与所述复制晶体管的第一极连接。
在一些实施例中，所述初始化及补偿子电路包括：第二晶体管和第三晶体管；
所述第二晶体管的控制极与所述第二控制信号线连接，所述第二晶体管的第一极与所述第一电源端连接，所述第二晶体管的第二极与所述复制晶体管的第二极连接；
所述第三晶体管的控制极与所述第三控制信号线连接，所述第三晶体管的第一极与所述复制晶体管的第二极连接，所述第三晶体管的第二极与所述第一节点连接。
在一些实施例中，所述存储电路包括：存储电容；
所述存储电容的第一端与所述第一节点连接，所述存储电容的第二端与所述第二电源端连接。
在一些实施例中，还包括：发光控制电路，所述发光控制电路与所述驱动晶体管的第一极连接；
所述发光控制电路与第四控制信号线连接，用于在所述发光阶段时响应于所述第四控制信号线所提供的第四控制信号的控制，使得所述驱动晶体管输出的所述驱动电流能够流过所述发光器件；以及在其他阶段时，使得所述驱动晶体管输出的电流无法流过所述发光器件。
在一些实施例中，所述发光控制电路包括：第四晶体管；
所述第四晶体管控制极与所述第四控制信号线连接，所述第四晶体管的第一极与所述第一电源端连接，所述第四晶体管的第二极与所述驱动晶体管的第一极连接；
所述第四控制信号线和所述第三控制信号线为同一控制信号线。
在一些实施例中，所述复制晶体管的栅极与所述驱动晶体管的栅极同层设置；
所述复制晶体管的第一极、所述复制晶体管的第二极、所述驱动晶体管的第一极、所述驱动晶体管的第二极，四者同层设置；
所述复制晶体管的有源层与所述复制晶体管的有源层同层设置。
在一些实施例中，所述像素电路中的全部晶体管同时为N型晶体管或同时为P型晶体管。
第二方面，本公开的一个实施例还提供了一种显示面板，包括：如上述的像素电路。
第三方面，本公开的一个实施例还提供了一种显示装置，包括： 如上述的显示面板。
第四方面，本公开的一个实施例还提供了一种像素驱动方法，所述像素驱动方法基于上述的像素电路，所述像素驱动方法包括：
在初始化阶段，所述数据补偿电路响应于所述第二控制信号和所述第三控制信号的控制，将所述第一电压写入至所述第一节点；
在数据写入及补偿阶段，所述数据补偿电路响应于所述第一控制信号和所述第三控制信号的控制，将所述数据电压写入至所述复制晶体管的第一极以探测所述复制晶体管的阈值电压，并向所述第一节点写入补偿电压以供所述存储电路进行存储；
在发光阶段，所述存储电路向所述第一节点提供所述补偿电压，所述驱动晶体管根据所述补偿电压输出相应的驱动电流，以驱动所述发光器件发光。
附图说明
图1为相关技术中提供的一种像素电路的电路结构示意图；
图2为图1所示像素电路的工作时序图；
图3为本公开实施例提供的一种像素电路的电路结构示意图；
图4为本公开实施例提供的另一种像素电路的电路结构示意图；
图5为图4所示像素电路的一种工作时序图；
图6为本公开实施例所提供的一种像素驱动方法的流程图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图对本发明提供的像素电路、显示面板、显示装置和像素驱动方法进行详细描述。
相关技术中的2T1C像素电路亮度均匀性一直很差，为解决该问题，目前比较好的解决的方法就是在像素内加入补偿电路，通过补偿电路消除驱动晶体管的阈值电压对驱动电流的影响。目前，具有阈值补偿功能的像素电路，其补偿原理如下：首先，利用补偿电路获取驱动晶体管的阈值电压，并将其写入至存储电容；然后，向存储电容的 一端写入数据电压，并基于电容的自举作用以将存储电容的另一端(该端与驱动晶体管的栅极连接)的电压上拉以得到一个补偿电压；最后，利用该补偿电压来控制驱动晶体管输出驱动电流，以实对驱动晶体管进行阈值补偿。
然而，在实际应用中发现，在基于电容的自举作用将存储电容的另一端上拉至补偿电压时，由于存储电容与驱动晶体管自身的寄生电容构成串联，因此存储电容通过自举所得到的补偿电压会受到存储电容和驱动晶体管自身的寄生电容的影响，实际得到的补偿电压与理想的补偿电压存在偏差，从而导致无法进行精准补偿。
图1为相关技术中的一种像素电路的电路结构示意图，图2为图1所示像素电路的工作时序图。下面将参考图1和图2、并以图1中全部的晶体管均同时为N型晶体管为例进行说明。
图1所示的像素电路的工作过程包括如下四个阶段p1至p4。
在第一阶段p1时，扫描信号线Scan提供高电平信号，控制信号线S1提供高电平信号，控制信号线S2提供高电平信号，数据线Data提供参考电压Vref；此时，晶体管T1、T2、T3和T4均导通，参考电压Vref通过晶体管T1写入至节点a，第一电压Vdd通过晶体管T2和晶体管T3写入至节点c，并再通过晶体管T4写入至节点b。此时，节点a的电压为Vref，节点b和节点c的电压为Vdd。
在第二阶段p2时，扫描信号线Scan提供高电平信号，控制信号线S1提供低电平信号，控制信号线S2提供高电平信号，数据线Data提供参考电压Vref。此时，晶体管T3截止，此时Vdd不再向节点b和节点c进行充电，因此节点b和节点c通过驱动晶体管DTFT进行放电，两节点间的电压开始下降，当节点b和节点c的电压下降至Vss+Vth时，驱动晶体管DTFT截止。此时，节点a的电压维持Vref，存储电容C1两端电压差(节点a与节点b的电压差)为Vref-Vss-Vth，其中Vth为驱动晶体管DTFT的阈值电压。
在第三阶段p3时，扫描信号线Scan提供高电平信号，控制信号线S1提供低电平信号，控制信号线S2提供低电平信号，数据线 Data提供数据电压Vdata。此时，晶体管T1和T2导通，晶体管S3和S4截止。由于晶体管T4截止，因此节点b处于浮接(Floating)状态。在数据线将数据电压Vdata通过晶体管T1写入至节点a时，存储电容C1通过自举作用以维持两端电压差不变，在不考虑驱动晶体管DTFT自身的寄生电容Cgd和Cgs的情况下，此时节点b的电压跳变为Vss+Vth+Vdata-Vref。
在第四阶段p4时，扫描信号线Scan提供低电平信号，控制信号线S1提供高电平信号，控制信号线S2提供低电平信号，数据线Data提供参考电压Vref，此时，晶体管T1、T2和T4截止，晶体管T3导通。
此时，驱动晶体管DTFT的栅源电压Vgs＝Vth+Vdata-Vref，根据驱动晶体管DTFT的饱和驱动电流公式可得：
I＝K*(Vgs-Vth) 2
＝K*(Vth+Vdata-Vref-Vth) 2
＝K*(Vdata-Vref) 2
其中，I为驱动晶体管DTFT输出的驱动电流，K为一常量。通过上式可见，驱动晶体管输出的驱动电流与数据电压Vdata和参考电压Vref相关，与驱动晶体管DTFT的阈值电压无关，从而实现了阈值补偿。
然而，在实际补偿过程中，在第三阶段P3，当数据线Data向节点a写入数据电压时，节点b处的电压会因存储电容C1的自举而上升，但是由于驱动晶体管的寄生电容Cgd和Cgs与存储电容C1串联，寄生电容Cgd和Cgs会产生分压作用，使得节点b处的电压Vb仅能上升至
Figure PCTCN2020077571-appb-000001
因此，在第四阶段p4时，驱动晶体管DTFT的栅源电压Vgs＝Vb-Vss
Figure PCTCN2020077571-appb-000002
根据驱动晶体管DTFT的饱和驱动电流公式可得：
Figure PCTCN2020077571-appb-000003
此时，通过上式可见，驱动晶体管DTFT输出的驱动电流虽然与驱动晶体管的阈值电压无关，但是与存储电容C1、寄生电容Cgd和Cgs相关。
因此，当存在工艺偏差，使得显示面板中不同像素区域内的存储电容C1、寄生电容Cgd和Cgs不同时，此时即使给出相同的数据电压Vdata和参考电压Vref，不同像素区域内的驱动晶体管仍会产生不同的驱动电流，即现有的像素电路无法进行精准补偿。
为解决相关技术中存在的上述技术问题，本公开提供了一种像素电路，可实现对驱动晶体管的阈值电压进行精准补偿。
需要说明的是，本公开中的发光器件可以是相关技术中包括LED(Light Emitting Diode，发光二极管)或OLED(Organic Light Emitting Diode，有机发光二极管)在内的电流驱动型发光器件，在下述实施例中是以发光器件为OLED为例进行的说明。
另外，本公开中的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件。晶体管一般包括三个极：栅极、源极和漏极，晶体管中的源极和漏极在结构上是对称的，根据需要两者是可以互换的。在本发明中，控制极是指晶体管的栅极，第一极和第二极中的一者为源极，另一者为漏极。
图3为本公开的一个实施例提供的一种像素电路的电路结构的示意图。如图3所示，该像素电路包括：数据补偿电路1、存储电路2、驱动晶体管DTFT和复制晶体管CTFT，复制晶体管CTFT与驱动晶体管DTFT的结构相同。
复制晶体管CTFT的栅极、驱动晶体管DTFT的栅极、数据补偿电路1和存储电路2连接于第一节点N1，复制晶体管CTFT的第一极和复制晶体管CTFT的第二极均与数据补偿电路1连接，驱动晶体管DTFT的第一极与发光器件OLED的第一极连接，发光器件OLED的第 二极与第一电源端连接，驱动晶体管DTFT的第二极与第二电源端连接。
数据补偿电路1与第一电源端、数据线Data、第一控制信号线CL1、第二控制信号线CL2、第三控制信号线CL3连接，数据补偿电路1用于在初始化阶段时响应于第二控制信号线CL2所提供的第二控制信号和第三控制信号线CL3所提供的第三控制信号的控制，将第一电源端提供的第一电压写入至第一节点N1；以及，用于在数据写入及补偿阶段时响应于第三控制信号和第一控制信号线CL1所提供的第一控制信号的控制，将数据线Data所提供的数据电压写入至复制晶体管CTFT的第一极以探测复制晶体管CTFT的阈值电压，并向第一节点N1写入补偿电压以供存储电路2进行存储，补偿电压等于数据电压与复制晶体管CTFT的阈值电压之和。
存储电路2与第二电源端连接，存储电路2用于在发光阶段时向第一节点N1提供补偿电压。
驱动晶体管DTFT用于在发光阶段时根据补偿电压输出相应的驱动电流，以驱动发光器件OLED发光。
在本公开的实施例中，复制晶体管CTFT与驱动晶体管DTFT的结构相同具体是指两个晶体管的形状、尺寸以及所使用的材料均大致相同，从而保证该两个晶体管在完成制备时的阈值电压相同。作为一种实施方式，复制晶体管CTFT和驱动晶体管DTFT可采用相同的制备工艺且同时进行制备，以能保证两者结构相同。另外，在后续使用过程中，复制晶体管CTFT的栅极与驱动晶体管DTFT的栅极相连，且两者距离较近(位于同一像素中)，因此在同一时刻两者的阈值电压漂移量也是相同，即在任意时刻复制晶体管CTFT与驱动晶体管DTFT的阈值电压均相同。
实际生产过程中，同一像素电路内的复制晶体管CTFT和驱动晶体管DTFT距离较近，因此在制备工艺上很容易实现两者结构完全相同。另外，为保证复制晶体管CTFT和驱动晶体管DTFT在使用过程中阈值电压漂移量始终相同，可使得两者的位置尽量靠近。
在一些实施例中，复制晶体管CTFT的栅极与驱动晶体管DTFT 的栅极同层设置；复制晶体管CTFT的第一极、复制晶体管CTFT的第二极、驱动晶体管DTFT的第一极、驱动晶体管DTFT的第二极，四者同层设置；复制晶体管CTFT的有源层与驱动晶体管DTFT的有源层同层设置。即可采用相同的晶体管制备工艺以同时制备出复制晶体管CTFT和驱动晶体管DTFT，此时能尽可能的减小制备过程中的工艺误差，以保证所制备出的复制晶体管CTFT和驱动晶体管DTFT，两者虽位置不同，但结构完全相同。
需要说明的是，本公开中的“同层设置”是指位于同一功能膜层结构中；其中，同层设置的不同结构的制备材料是相同的，因而可采用一次构图工艺得以同时制备；同层设置的不同结构与衬底之间的距离可以相同，也可以不同。
在本公开的实施例中，以第一电源端提供第一电压Vdd，第二电源端提供第二电压Vss为例进行说明。
图3所示像素电路的工作过程包括初始化阶段、数据写入及补偿阶段和在发光阶段。
在初始化阶段，数据补偿电路1响应于第二控制信号和第三控制信号的控制，将第一电压写入至第一节点N1，以对第一节点N1处的电压进行重置处理。
在数据写入及补偿阶段，数据线Data向数据补偿电路1提供数据电压Vdata，数据补偿电路1响应于第一控制信号和第三控制信号的控制，将数据电压Vdata写入至复制晶体管CTFT的第一极以探测复制晶体管CTFT的阈值电压Vth_ CTFT，并向第一节点N1写入补偿电压以供存储电路2进行存储。
与相关技术中不同的是，在本实施例中基于数据电压来探测复制晶体管CTFT的阈值电压Vth_ CTFT，并将大小等于数据电压Vdata与复制晶体管CTFT的阈值电压Vth_ CTFT之和的补偿电压写入至第一节点N1，以供存储电路2进行存储。在向第一节点N1写入补偿电压的过程中，即便驱动晶体管DTFT自身存在寄生电容Cgd和Cgs，但该寄生电容Cgd和Cgs也不会对补偿电压的写入过程产生影响，因此补偿电压可以精准写入至第一节点N1。
在发光阶段，存储电路2向第一节点N1提供补偿电压，驱动晶体管DTFT根据补偿电压输出相应的驱动电流，以驱动发光器件OLED发光。
此时，驱动晶体管DTFT的栅源电压Vgs＝Vdata+Vth_ CTFT-Vss，根据驱动晶体管DTFT的饱和驱动电流公式可得：
I＝K*(Vgs-Vth_ DTFT) 2
＝K*(Vdata+Vth_ CTFT-Vss-Vth_ DTFT) 2
其中，Vth_ DTFT为驱动晶体管DTFT的阈值电压，根据前述分析可见，Vth_ DTFT＝Vth_ CTFT；因此，驱动电流I＝K*(Vdata-Vss) 2。
根据上式可见，驱动晶体管DTFT输出的驱动电流与数据电压Vdata相关，与驱动晶体管DTFT的阈值电压Vth_ DTFT无关，从而实现了对驱动晶体管DTFT进行阈值补偿。
基于上述内容可见，本公开的技术方案可实现将大小等于数据电压Vdata与复制晶体管CTFT的阈值电压Vth_ CTFT之和的补偿电压精准写入至第一节点N1，在发光阶段时根据该补偿电压来控制驱动晶体管DTFT发光，可实现对驱动晶体管DTFT的阈值电压进行精准补偿。
在一些实施例中，像素电路还包括：发光控制电路3，发光控制电路3与驱动晶体管DTFT的第一极连接；发光控制电路3还与第四控制信号线CL4连接，用于在发光阶段时响应于第四控制信号线CL4所提供的第四控制信号的控制，使得驱动晶体管DTFT输出的驱动电流能够流过发光器件OLED；以及在其他阶段时，使得驱动晶体管DTFT输出的电流无法流过发光器件OLED。
在本公开中，通过设置发光控制电路3以控制驱动晶体管DTFT所输出电流的流向，可防止发光器件OLED在除发光阶段之外的其他阶段出现误发光的现象。
需要说明的是，附图中所示发光控制电路3与发光器件OLED构成并联的情况，仅起到示意性作用，其不会对本公开的技术方案产生限制。在本公开中，发光控制电路3还可设置于驱动晶体管DTFT的第一极与发光器件OLED的第一极之间，具体描述可参见后续内容。
图4为本公开实施例提供的另一种像素电路的电路结构示意图， 如图4所示，图4所示像素电路为基于图3所示像素电路的一种具体化方案。
其中，数据补偿电路1包括：数据写入子电路101和初始化及补偿子电路102。
数据写入子电路101与第一控制信号线CL1连接，数据写入子电路101用于在数据写入及补偿阶段时响应于第一控制信号的控制，将数据电压写入至复制晶体管CTFT的第一极。
初始化及补偿子电路102与第二控制信号线CL2和第三控制信号线CL3连接，初始化及补偿子电路102用于在初始化阶段时响应于第二控制信号和第三控制信号的控制，将第一电压写入至第一节点N1，以对第一节点N1处进行初始化；以及用于在数据写入及补偿阶段时，响应于第三控制信号的控制，根据复制晶体管CTFT的第二极输出的信号向第一节点N1写入补偿电压。
在一些实施例中，数据写入子电路101包括：第一晶体管T1，第一晶体管T1的控制极与第一控制信号线CL1连接，第一晶体管T1的第一极与数据线Data连接，第一晶体管T1的第二极与复制晶体管CTFT的第一极连接。
在一些实施例中，初始化及补偿子电路102包括：第二晶体管T2和第三晶体管T3；第二晶体管T2的控制极与第二控制信号线CL2连接，第二晶体管T2的第一极与第一电源端连接，第二晶体管T2的第二极与复制晶体管CTFT的第二极连接；第三晶体管T3的控制极与第三控制信号线CL3连接，第三晶体管T3的第一极与复制晶体管CTFT的第二极连接，第三晶体管T3的第二极与第一节点N1连接。
在一些实施例中，存储电路2包括：存储电容C2；存储电容C2的第一端与第一节点N1连接，存储电容C2的第二端与第二电源端连接。
在一些实施例中，发光控制电路3包括：第四晶体管T4；第四晶体管T4控制极与第四控制信号线连接，第四晶体管T4的第一极与第一电源端连接，第四晶体管T4的第二极与驱动晶体管DTFT的第一极连接,第四控制信号线和第三控制信号线CL3为同一控制信号线 (统一为第三控制信号线CL3)。
按照晶体管特性，可将晶体管分为N型晶体管和P型晶体管；当晶体管为N型晶体管时，其导通电压为高电平电压，截止电压为低电平电压；当晶体管为P型晶体管时，其导通电压为低电平电压，截止电压为高电平电压。为便于本领域技术人员理解，在下面描述中，将以像素电路中的全部晶体管同时为N型晶体管为例，进行示例性描述。其中，第一电源端提供第一电压Vdd，第二电源端提供第二电压Vss(Vss取值约为0V)。
图5为图4所示像素电路的一种工作时序图，如图5所示，该像素电路的工作过程包括三个阶段：初始化阶段、数据写入及补偿阶段和发光阶段。
其中，在初始化阶段t1，第一控制信号线CL1提供的第一控制信号处于低电平状态，第二控制信号线CL2提供的第二控制信号处于高电平状态，第三控制信号线CL3提供的第三控制信号处于高电平状态。此时，第二晶体管M2、第三晶体管M3和第四晶体管M4均导通，第一晶体管M1截止。
由于第二晶体管T2和第三晶体管T3导通，因此第一电压Vdd可通过第二晶体管M2和第三晶体管M3写入至第一节点N1，第一节点N1和第二节点N2的电压均为Vdd。
需要说明的是，虽然此时驱动晶体管DTFT会处于导通状态且输出有电流，但是由于第四晶体管M4导通(发光器件OLED被短路)，因此驱动晶体管DTFT所输出的电流会通过第四晶体管M4流向第一电源端，而不会流过发光器件OLED，驱动晶体管DTFT不会出现误发光。
在数据写入及补偿阶段t2，第一控制信号线CL1提供的第一控制信号处于高电平状态，第二控制信号线CL2提供的第二控制信号处于低电平状态，第三控制信号线CL3提供的第三控制信号处于高电平状态，数据线Data提供数据电压Vdata；此时，第一晶体管M1、第三晶体管M3和第四晶体管M4均导通，第二晶体管M2截止。
由于在初始化阶段结束t1时，第一节点N1处的电压为Vdd，因此在在数据写入及补偿阶段的初始时刻，复制晶体管CTFT处于导通 状态。又由于第一晶体管M1导通、第三晶体管M3导通且第二晶体管M2截止，因此第一节点N1通过第三晶体管M3、复制晶体管CTFT和第一晶体管M1与数据线Data之间形成通路，第一节点N1可通过该通路进行放电，第一节点N1处的电压开始下降；当第一节点N1处的电压下降至Vdata+Vth_ CTFT时，复制晶体管CTFT截止，放电结束。其中，上述放电过程不会受到驱动晶体管DTFT自身的寄生电容Cgd和Cgs的影响。
上述第一节点N1处的电压从Vdd下降至Vdata+Vth_ CTFT的过程，可看作为初始化及补偿子电路102根据复制晶体管CTFT的第二极所输出的信号感测复制晶体管CTFT的阈值电压Vth_ CTFT，以及向第一节点N1精准写入补偿电压Vdata+Vth_ CTFT的过程。
此时，存储电容C2两端的电压差为Vdata+Vth_ CTFT-Vss，即存储电容C2完成对补偿电压进行存储。
在发光阶段t3，第一控制信号线CL1提供的第一控制信号处于低电平状态，第二控制信号线CL2提供的第二控制信号处于低电平状态，第三控制信号线CL3提供的第三控制信号处于低电平状态；此时，第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4均截止。
此时，存储电容C2维持第一节点N1处的电压为Vdata+Vth_ CTFT，即存储电容C2向第一节点N1提供补偿电压。
此时，驱动晶体管DTFT的栅源电压Vgs＝Vdata+Vth_ CTFT-Vss，根据驱动晶体管DTFT的饱和驱动电流公式可得：
I＝K*(Vgs-Vth_ DTFT) 2
＝K*(Vdata+Vth_ CTFT-Vss-Vth_ DTFT) 2
＝K*(Vdata-Vss) 2
根据上式可见，驱动晶体管DTFT输出的驱动电流与数据电压Vdata相关，与驱动晶体管DTFT的阈值电压Vth_ DTFT无关，从而实现了对驱动晶体管DTFT进行阈值补偿。
需要说明的是，上述第四晶体管M4控制极与第四控制信号线连接，第四晶体管M4的第一极与第一电源端连接，第四晶体管M4的第 二极与驱动晶体管DTFT的第一极连接，第四控制信号线和第三控制信号线CL3为同一控制信号线的情况，其为本公开中的一种实施方案，其可使得像素电路中所需配置的控制信号线的种类减少，降低驱动控制过程的复杂度。
在本公开中，第四晶体管M4也可设置于驱动晶体管DTFT的第一极与发光器件OLED的第一极之间(此种情况未给出相应附图)。具体地，第四晶体管M4的第一极与发光器件OLED的第一极，第四晶体管M4的第二极与驱动晶体管DTFT的第一极连接，第四晶体管M4的控制极所连接的第四控制信号线为与第一控制信号线CL1～第三控制信号线CL3不同的一个控制信号线，此时第四晶体管M4受控于第四控制信号线所提供的第四控制信号，第四晶体管M4仅在发光阶段导通以将驱动晶体管DTFT输出的驱动电流传输给发光器件OLED，第四晶体管M4在初始化阶段和数据写入及补偿阶段截止以使得驱动晶体管DTFT的第一极与发光器件OLED的第一极之间断路，从而防止发光器件OLED误发光。
另外，上述像素电路中的全部晶体管同时为N型晶体管的情况，其为本公开中的优选实施方案，此时像素电路中的全部晶体管可采用相同的制备工艺得以同时制备，从而能缩短制备周期。当然，在本公开中，像素电路中的全部晶体管也可同时为P型晶体管，此时也可采用相同的制备工艺以同时制备全部晶体管。
需要说明的是，本公开中的各晶体管可以分别独立选自N型晶体管或P型晶体管，根据晶体管的类型，通过配置相应的控制信号来控制各晶体管的状态以实现如上述的工作过程，其也属于本公开的保护范围。
图6为本公开实施例所提供的一种像素驱动方法的流程图，如图6所示，该像素驱动方法基于前述实施例所提供的像素电路，该像素驱动方法包括：
步骤S1、在初始化阶段，数据补偿电路响应于第二控制信号和第三控制信号的控制，将第一电压写入至第一节点；
步骤S2、在数据写入及补偿阶段，数据补偿电路响应于第一控 制信号和第三控制信号的控制，将数据电压写入至复制晶体管的第一极以探测复制晶体管的阈值电压，并向第一节点写入补偿电压以供存储电路进行存储；以及
步骤S3、在发光阶段，存储电路向第一节点提供补偿电压，驱动晶体管根据补偿电压输出相应的驱动电流，以驱动发光器件发光。
对于上述步骤S1～步骤S3的具体描述，可参见前述实施例中相应内容，此处不再赘述。
本公开的技术方案可实现将大小等于数据电压与复制晶体管的阈值电压之和的补偿电压精准写入至第一节点，该写入过程不受驱动晶体管的寄生电容的影响，在发光阶段时根据该补偿电压来控制驱动晶体管发光，可实现对驱动晶体管的阈值电压进行精准补偿。
本公开实施例还提供了一种显示面板，该显示面板包括：像素电路；其中，该像素电路采用前述实施例所提供的像素电路。
本公开实施例还提供了一种显示装置，该显示装置包括：显示面板；其中，该显示面板采用前述实施例所提供的显示面板。
需要说明的是，本发明中的显示装置具体可以包括：电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (12)

  1. 一种像素电路，包括：数据补偿电路、存储电路、驱动晶体管和复制晶体管，所述复制晶体管与所述驱动晶体管的结构相同；
    所述复制晶体管的栅极、所述驱动晶体管的栅极、所述数据补偿电路和所述存储电路连接于第一节点，所述复制晶体管的第一极和所述复制晶体管的第二极均与所述数据补偿电路连接，所述驱动晶体管的第一极与发光器件的第一极连接，所述驱动晶体管的第二极与第二电源端连接；
    所述数据补偿电路与所述第一电源端、数据线、第一控制信号线、第二控制信号线、第三控制信号线连接，用于在初始化阶段时响应于所述第二控制信号线所提供的第二控制信号和所述第三控制信号线所提供的第三控制信号的控制，将所述第一电源端提供的第一电压写入至所述第一节点；以及，用于在数据写入及补偿阶段时响应于所述第三控制信号和所述第一控制信号线所提供的第一控制信号的控制，将所述数据线所提供的数据电压写入至所述复制晶体管的第一极以探测所述复制晶体管的阈值电压，并向所述第一节点写入补偿电压以供所述存储电路进行存储，所述补偿电压等于所述数据电压与所述复制晶体管的阈值电压之和；
    所述存储电路还与所述第二电源端连接，用于在发光阶段时向所述第一节点提供所述补偿电压；
    所述驱动晶体管配置用于在所述发光阶段时根据所述补偿电压输出相应的驱动电流，以驱动发光器件发光。
  2. 根据权利要求1所述的像素电路，其中，所述数据补偿电路包括：数据写入子电路和初始化及补偿子电路；
    所述数据写入子电路与所述第一控制信号线连接，用于在所述数据写入及补偿阶段时响应于所述第一控制信号的控制，将所述数据电压写入至所述复制晶体管的第一极；
    所述初始化及补偿子电路与所述第二控制信号线和第三控制信 号线连接，用于在初始化阶段时响应于所述第二控制信号和所述第三控制信号的控制，将所述第一电压写入至所述第一节点，以对所述第一节点处进行初始化；以及用于在所述数据写入及补偿阶段时，响应于所述第三控制信号的控制，根据所述复制晶体管的第二极输出的信号向所述第一节点写入所述补偿电压。
  3. 根据权利要求2所述的像素电路，其中，所述数据写入子电路包括：第一晶体管；
    所述第一晶体管的控制极与所述第一控制信号线连接，所述第一晶体管的第一极与所述数据线连接，所述第一晶体管的第二极与所述复制晶体管的第一极连接。
  4. 根据权利要求2或3所述的像素电路，其中，所述初始化及补偿子电路包括：第二晶体管和第三晶体管；
    所述第二晶体管的控制极与所述第二控制信号线连接，所述第二晶体管的第一极与所述第一电源端连接，所述第二晶体管的第二极与所述复制晶体管的第二极连接；
    所述第三晶体管的控制极与所述第三控制信号线连接，所述第三晶体管的第一极与所述复制晶体管的第二极连接，所述第三晶体管的第二极与所述第一节点连接。
  5. 根据权利要求1之3中任一项所述的像素电路，其中，所述存储电路包括：存储电容；
    所述存储电容的第一端与所述第一节点连接，所述存储电容的第二端与所述第二电源端连接。
  6. 根据权利要求1之4中任一项所述的像素电路，其中，还包括：发光控制电路，所述发光控制电路与所述驱动晶体管的第一极连接；
    所述发光控制电路与第四控制信号线连接，用于在所述发光阶 段时响应于所述第四控制信号线所提供的第四控制信号的控制，使得所述驱动晶体管输出的所述驱动电流能够流过所述发光器件；以及在其他阶段时，使得所述驱动晶体管输出的电流无法流过所述发光器件。
  7. 根据权利要求6所述的像素电路，其中，所述发光控制电路包括：第四晶体管；
    所述第四晶体管控制极与所述第四控制信号线连接，所述第四晶体管的第一极与所述第一电源端连接，所述第四晶体管的第二极与所述驱动晶体管的第一极连接；
    所述第四控制信号线和所述第三控制信号线为同一控制信号线。
  8. 根据权利要求1所述的像素电路，其中，所述复制晶体管的栅极与所述驱动晶体管的栅极同层设置；
    所述复制晶体管的第一极、所述复制晶体管的第二极、所述驱动晶体管的第一极和所述驱动晶体管的第二极同层设置；
    所述复制晶体管的有源层与所述复制晶体管的有源层同层设置。
  9. 根据权利要求1-8中任一所述的像素电路，其中，所述像素电路中的全部晶体管同时为N型晶体管或同时为P型晶体管。
  10. 一种显示面板，包括：如上述权利要求1-9中任一所述的像素电路。
  11. 一种显示装置，其中，包括：如上述权利要求10所述的显示面板。
  12. 一种像素驱动方法，其中，所述像素驱动方法基于上述权利 要求1-9中任一所述的像素电路，所述像素驱动方法包括：
    在初始化阶段，所述数据补偿电路响应于所述第二控制信号和所述第三控制信号的控制，将所述第一电压写入至所述第一节点；
    在数据写入及补偿阶段，所述数据补偿电路响应于所述第一控制信号和所述第三控制信号的控制，将所述数据电压写入至所述复制晶体管的第一极以探测所述复制晶体管的阈值电压，并向所述第一节点写入补偿电压以供所述存储电路进行存储；
    在发光阶段，所述存储电路向所述第一节点提供所述补偿电压，所述驱动晶体管根据所述补偿电压输出相应的驱动电流，以驱动所述发光器件发光。
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