WO2020177056A1 - 薄膜晶体管及薄膜晶体管的制造方法 - Google Patents

薄膜晶体管及薄膜晶体管的制造方法 Download PDF

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WO2020177056A1
WO2020177056A1 PCT/CN2019/076870 CN2019076870W WO2020177056A1 WO 2020177056 A1 WO2020177056 A1 WO 2020177056A1 CN 2019076870 W CN2019076870 W CN 2019076870W WO 2020177056 A1 WO2020177056 A1 WO 2020177056A1
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semiconductor layer
thin film
film transistor
source
semiconductor material
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PCT/CN2019/076870
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English (en)
French (fr)
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王治
袁广才
关峰
许晨
王学勇
杜建华
李超
陈蕾
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京东方科技集团股份有限公司
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Priority to US16/642,638 priority Critical patent/US11309427B2/en
Priority to CN201980000226.2A priority patent/CN110972508B/zh
Priority to PCT/CN2019/076870 priority patent/WO2020177056A1/zh
Publication of WO2020177056A1 publication Critical patent/WO2020177056A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors

Definitions

  • the present disclosure relates to the field of display technology. Specifically, it relates to a thin film transistor and a manufacturing method of the thin film transistor.
  • Thin film transistors are widely used in the field of display technology. Thin film transistors can drive pixels of a display device.
  • the display device provided with thin film transistors can have advantages such as high speed, high brightness, and high contrast.
  • the embodiment of the present disclosure provides a thin film transistor.
  • the thin film transistor includes: a substrate;
  • a first semiconductor layer, a gate dielectric layer, and a gate electrode are sequentially stacked on the substrate, wherein the first semiconductor layer has a first portion located in the channel region of the thin film transistor and located on the thin film In the source/drain region of the transistor and located on both sides of the first part, the second part, and wherein, the second part and the first sub-part of the first part adjacent to the second part include an amorphous semiconductor Material, the second sub-portion of the first portion located between the first sub-portions includes a polycrystalline semiconductor material;
  • the second semiconductor layer located in the source/drain region and in contact with the second portion, wherein the conductivity of the second semiconductor layer is higher than the conductivity of the amorphous semiconductor material.
  • the second semiconductor layer is in contact with a surface of the second portion facing the substrate.
  • the second part contacts a surface of the second part away from the substrate at the second semiconductor layer.
  • the doping type of the first semiconductor layer and the second semiconductor layer is N-type, and the N-type carrier concentration of the second semiconductor layer is greater than that of the first semiconductor layer. Carrier concentration.
  • the doping type of the first semiconductor layer and the second semiconductor layer is P-type, and the P-type carrier concentration of the second semiconductor layer is greater than that of the first semiconductor layer. Carrier concentration.
  • the doping concentration of the first semiconductor layer is between 10 17 ions/cm 3 and 10 19 ions/cm 3
  • the doping concentration of the second semiconductor layer is between 10 19 ions/cm 3 Between 3 ⁇ 10 21 ions/cm 3 .
  • the polycrystalline semiconductor material includes polycrystalline silicon
  • the amorphous semiconductor material includes amorphous silicon
  • the thin film transistor further includes source/drain electrodes on a side of the second semiconductor layer facing away from the second portion.
  • the embodiment of the present disclosure also provides a method for manufacturing a thin film transistor.
  • the manufacturing method of the thin film transistor includes: sequentially forming a first semiconductor layer, a gate dielectric layer, and a gate electrode on a substrate, wherein the first semiconductor layer has a first semiconductor layer located in a channel region of the thin film transistor.
  • a part and a second part located in the source/drain region of the thin film transistor and located on both sides of the first part, and wherein the second part and the first part adjacent to the second part of the first part
  • a sub-portion includes an amorphous semiconductor material, and a second sub-portion of the first portion located between the first sub-portions includes a polycrystalline semiconductor material;
  • a second semiconductor layer located in the source/drain region and in contact with the second portion is formed, wherein the conductivity of the second semiconductor layer is higher than the conductivity of the amorphous semiconductor material.
  • forming the first semiconductor layer includes:
  • first semiconductor material layer including the amorphous semiconductor material, the first semiconductor material layer including a middle part as the first part and edge parts on both sides of the middle part as the second part;
  • the portion of the middle portion of the first semiconductor material layer corresponding to the first sub-portion is converted into the polycrystalline semiconductor material.
  • the conversion includes laser annealing the amorphous semiconductor material.
  • the laser annealing includes using a microlens array mask.
  • the method of manufacturing the thin film transistor further includes forming source/drain electrodes on a side of the second semiconductor layer away from the second portion.
  • forming the first semiconductor layer, the second semiconductor layer, and the source/drain electrode includes:
  • the first semiconductor layer is formed on the second semiconductor layer.
  • forming the first semiconductor layer, the second semiconductor layer, and the source/drain electrode includes:
  • the source/drain electrodes are formed on the second semiconductor layer.
  • forming the first semiconductor layer and the second semiconductor layer includes using CVD.
  • the polycrystalline semiconductor material includes polycrystalline silicon
  • the amorphous semiconductor material includes amorphous silicon
  • FIG. 1 is a schematic diagram of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a thin film transistor according to an embodiment of the present disclosure
  • 3A-3B are schematic diagrams of a method of forming a first semiconductor layer according to an embodiment of the present disclosure
  • 4A-4C are schematic diagrams of a method of forming a first semiconductor layer, a second semiconductor layer, and source/drain electrodes according to an embodiment of the present disclosure
  • 5A-5C are schematic diagrams of a method of forming a first semiconductor layer, a second semiconductor layer, and source/drain electrodes according to an embodiment of the present disclosure.
  • the terms “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom” and the directions indicated in the drawings The derivative word should involve public.
  • the terms “overlying”, “on top of”, “positioned on top” or “positioned on top” mean that a first element such as a first structure is present on a second element such as a second structure Above, where there may be an intermediate element such as an interface structure between the first element and the second element.
  • the term “contact” means to connect a first element such as a first structure and a second element such as a second structure, and there may or may not be other elements at the interface of the two elements.
  • FIG. 1 is a schematic diagram of a thin film transistor according to an embodiment of the present disclosure.
  • a thin film transistor according to an embodiment of the present disclosure includes: a substrate 10; a first semiconductor layer 11, a gate dielectric layer 12 and a gate electrode 13 are sequentially stacked on the substrate 10.
  • the first semiconductor layer 11 has a first portion P1 located in the channel region R1 of the thin film transistor and a second portion P2 located in the source/drain region R2 of the thin film transistor and located on both sides of the first portion P1.
  • the second portion P2 and the first sub-portion P11 of the first portion P1 adjacent to the second portion P2 include an amorphous semiconductor material.
  • the second sub-portion P12 of the first portion P1 located between the first sub-portion P11 includes a polycrystalline semiconductor material.
  • the thin film transistor also includes a second semiconductor layer 14 located in the source/drain region R2 and in contact with the second portion P2.
  • the conductivity of the second semiconductor layer 14 is higher than that of the amorphous semiconductor material.
  • the first semiconductor layer may be unintentionally doped, and the second semiconductor layer may be N-type or P-type doped.
  • the first semiconductor layer may have the same doping type as the second semiconductor layer but with a lower doping concentration.
  • the second semiconductor layer 14 is not in direct contact with the first portion P1 of the first semiconductor layer 11, which can reduce the hot carrier effect and reduce the leakage current of the transistor.
  • the second semiconductor layer 14 may be in contact with the surface S1 of the second portion P2 of the first semiconductor layer 11 away from the substrate.
  • FIG. 2 is a schematic diagram of a thin film transistor according to an embodiment of the present disclosure.
  • the second semiconductor layer 14 may be in contact with the surface S2 of the second portion P2 of the first semiconductor layer 11 facing the substrate.
  • the thin film transistor may further include a source/drain electrode 15 located on a side of the second semiconductor layer 14 facing away from the second portion P2 of the first semiconductor layer 11.
  • the doping type of the first semiconductor layer 11 and the second semiconductor layer 14 may be N-type, and the N-type carrier concentration of the second semiconductor layer 14 is greater than the N-type carrier concentration of the first semiconductor layer 11.
  • the doping concentration of the first semiconductor layer 11 is between 10 17 ions/cm 3 and 10 19 ions/cm 3 .
  • the doping concentration of the second semiconductor layer may be between 10 19 ions/cm 3 and 10 21 ions/cm 3 .
  • the N-type dopant may be a pentavalent impurity element such as phosphorus.
  • the doping type of the first semiconductor layer 11 and the second semiconductor layer 14 is P-type, and the P-type carrier concentration of the second semiconductor layer 14 is greater than the P-type carrier concentration of the first semiconductor layer 11.
  • the doping concentration of the first semiconductor layer 11 may be between 10 17 ions/cm 3 and 10 19 ions/cm 3 .
  • the doping concentration of the second semiconductor layer may be between 10 19 ions/cm 3 and 10 21 ions/cm 3 .
  • the P-type dopant may be a trivalent impurity element such as boron.
  • the polycrystalline semiconductor material may include polycrystalline silicon, and the amorphous semiconductor material may include amorphous silicon.
  • the embodiment of the present disclosure also provides a method for manufacturing a thin film transistor.
  • a method of manufacturing a thin film transistor according to an embodiment of the present disclosure includes: sequentially forming a first semiconductor layer 11, a gate dielectric layer 12, and a gate electrode 13 on a substrate 10, wherein the first semiconductor layer 11 has a thin film transistor The first portion P1 in the channel region R1 and the second portion P2 located in the source/drain region R2 of the thin film transistor and located on both sides of the first portion P1; forming R2 located in the source/drain region and contacting the second portion P2 The second semiconductor layer 14.
  • the second part P2 and the first sub-part P11 of the first part P1 adjacent to the second part P2 comprise amorphous semiconductor material
  • the second sub-part P12 of the first part P2 located between the first sub-parts P2 comprises polycrystalline semiconductors.
  • the conductivity of the second semiconductor layer 14 is higher than that of the amorphous semiconductor material.
  • the second semiconductor layer 14 is not in direct contact with the first portion P1 of the first semiconductor layer 11, which can reduce the hot carrier effect and reduce the leakage current of the transistor.
  • 3A-3B are schematic diagrams of a method of forming a first semiconductor layer according to an embodiment of the present disclosure. As shown in FIGS. 3A-3B, forming the first semiconductor layer may include:
  • a first semiconductor material layer 11' including an amorphous semiconductor material is formed.
  • the first semiconductor material layer 11' includes a middle part P1' as a first part P1 and a middle part as a second part P2. Edge parts P2' on both sides of P1';
  • laser annealing may be used to convert an amorphous semiconductor material into a polycrystalline semiconductor material (ie, perform a polycrystallization process).
  • a Micro Lens Array (MLA) mask can be used for laser annealing.
  • the method of manufacturing a thin film transistor according to an embodiment of the present disclosure further includes forming a source/drain electrode 15 on a side of the second semiconductor layer 14 facing away from the second portion P2 of the first semiconductor layer.
  • 4A-4C are schematic diagrams of a method of forming a first semiconductor layer, a second semiconductor layer, and source/drain electrodes according to an embodiment of the present disclosure. In the embodiment shown in FIGS. 4A-4C, forming the first semiconductor layer, the second semiconductor layer and the source/drain electrodes includes:
  • source/drain electrodes 15 are formed on the substrate 10.
  • a conductive layer can be deposited on the substrate, and then the conductive layer can be patterned to form source/drain electrodes.
  • the source/drain electrodes may include metal, for example, molybdenum. It is also possible to form the buffer layer 16 on the substrate before forming the source/drain electrodes.
  • a second semiconductor layer 14 is formed on the source/drain electrodes 15.
  • a non-crystalline silicon material may be deposited and doped on the source/drain electrodes, and then the amorphous silicon material may be patterned to remove the part located in the channel region, thereby forming the second semiconductor layer.
  • the doping may be in-situ doping performed during deposition, or doping separately after deposition.
  • the first semiconductor layer 11 is formed on the second semiconductor layer 14.
  • an amorphous silicon material may be deposited on the second semiconductor layer 14 to form the first semiconductor layer.
  • FIGS. 5A-5C are schematic diagrams of a method of forming a first semiconductor layer, a second semiconductor layer, and source/drain electrodes according to an embodiment of the present disclosure.
  • forming the first semiconductor layer, the second semiconductor layer and the source/drain electrodes includes:
  • a first semiconductor layer 11 is formed on the substrate 10.
  • an amorphous silicon material may be deposited on the substrate to form the first semiconductor layer. It is also possible to form a buffer layer on the substrate before forming the first semiconductor layer 11.
  • a second semiconductor layer 14 is formed on the first semiconductor layer 11.
  • an amorphous silicon material may be deposited and doped on the first semiconductor layer, and then the amorphous silicon material may be patterned to remove the part located in the channel region, thereby forming the second semiconductor layer.
  • source/drain electrodes 15 are formed on the second semiconductor layer 14.
  • a conductive layer may be deposited on the second semiconductor layer, and then the conductive layer may be patterned to form source/drain electrodes.
  • a method such as chemical vapor deposition (CVD) may be used to form the semiconductor layer.
  • CVD chemical vapor deposition

Abstract

一种薄膜晶体管及其制造方法。该薄膜晶体管包括：衬底；在衬底上依次层叠的第一半导体层、栅极介质层和栅极电极；其中，第一半导体层具有位于该薄膜晶体管的沟道区域中的第一部分和位于薄膜晶体管的源/漏极区域中且位于第一部分两侧的第二部分，并且其中，第二部分和第一部分的与第二部分邻接的第一子部分包括非晶半导体材料，第一部分的位于第一子部分之间的第二子部分包括多晶半导体材料；位于源/漏极区域的且与第二部分接触的第二半导体层，其中，该第二半导体层的导电性高于非晶半导体材料的导电性。

Description

薄膜晶体管及薄膜晶体管的制造方法 技术领域
本公开涉及显示技术领域。具体地，涉及一种薄膜晶体管及薄膜晶体管的制造方法。
背景技术
薄膜晶体管被广泛应用于显示技术领域。薄膜晶体管可以驱动显示装置的像素。设置有薄膜晶体管的显示装置可以具有高速度、高亮度和高对比度等优势。
发明内容
本公开的实施例提供了一种薄膜晶体管。所述薄膜晶体管包括：衬底；
在所述衬底上依次层叠的第一半导体层、栅极介质层和栅极电极，其中，所述第一半导体层具有位于所述薄膜晶体管的沟道区域中的第一部分和位于所述薄膜晶体管的源/漏极区域中且位于所述第一部分两侧第二部分，并且其中，所述第二部分和所述第一部分的与所述第二部分邻接的第一子部分包括非晶半导体材料，所述第一部分的位于所述第一子部分之间的第二子部分包括多晶半导体材料；
位于所述源/漏极区域的且与所述第二部分接触的第二半导体层，其中，所述第二半导体层的导电性高于所述非晶半导体材料的导电性。
在一些实施例中，所述第二半导体层与所述第二部分的朝向所述衬底的表面接触。
在一些实施例中，所述第二部分在所述第二半导体层与所述第二部分的远离所述衬底的表面接触。
在一些实施例中，所述第一半导体层和所述第二半导体层的掺杂类型为N型，所述第二半导体层的N型载流子浓度大于所述第一半导体层的N型载流子浓度。
在一些实施例中，所述第一半导体层和所述第二半导体层的掺杂类型为P型，所述第二半导体层的P型载流子浓度大于所述第一半导体层的P型载流子浓度。
在一些实施例中，所述第一半导体层的掺杂浓度在10 17ions/cm 3～10 19ions/cm 3之间，所述第二半导体层的掺杂浓度在在10 19ions/cm 3～10 21ions/cm 3之间。
在一些实施例中，所述多晶半导体材料包括多晶硅，所述非晶半导体材料包括非晶硅。
在一些实施例中，所述薄膜晶体管还包括位于所述第二半导体层的背离所述第二部分的一侧上的源/漏极电极。
本公开的实施例还提供了一种薄膜晶体管的制造方法。所述薄膜晶体管的制造方法包括：在衬底上依次形成第一半导体层、栅极介质层和栅极电极，其中，所述第一半导体层具有位于所述薄膜晶体管的沟道区域中的第一部分和位于所述薄膜晶体管的源/漏极区域中且位于所述第一部分两侧的第二部分，并且其中，所述第二部分和所述第一部分的与所述第二部分邻接的第一子部分包括非晶半导体材料，所述第一部分的位于所述第一子部分之间的第二子部分包括多晶半导体材料；
形成位于所述源/漏极区域中且与所述第二部分接触的第二半导体层，其中，所述第二半导体层的导电性高于所述非晶半导体材料的导电性。
在一些实施例中，形成所述第一半导体层包括：
形成包括所述非晶半导体材料的第一半导体材料层，所述第一半导体材料层包括作为所述第一部分的中间部分以及作为所述第二部分的位于所述中间部分两侧的边缘部分；
将所述第一半导体材料层的所述中间部分的与所述第一子部分对应的部分转变为所述多晶半导体材料。
在一些实施例中，所述转换包括对所述非晶半导体材料进行激光退火。
在一些实施例中，所述激光退火包括采用微透镜阵列掩模。
在一些实施例中，所述薄膜晶体管的制造方法还包括在所述第二半导 体层的背离所述第二部分的一侧上形成源/漏极电极。
在一些实施例中，形成所述第一半导体层、所述第二半导体层和所述源/漏极电极包括：
在所述衬底上形成源/漏极电极；
在所述源/漏极电极上形成所述第二半导体层；
在所述第二半导体层上形成所述第一半导体层。
在一些实施例中，形成所述第一半导体层、所述第二半导体层和所述源/漏极电极包括：
在所述衬底上形成所述第一半导体层；
在所述第一半导体层上形成所述第二半导体层；
在所述第二半导体层上形成所述源/漏极电极。
在一些实施例中，形成所述第一半导体层、所述第二半导体层包括采用CVD。
在一些实施例中，所述多晶半导体材料包括多晶硅，所述非晶半导体材料包括非晶硅。
附图说明
为了更清楚地说明本公开的实施例的技术方案，下面将对实施例的附图进行简要说明，应当知道，以下描述的附图仅仅涉及本公开的一些实施例，而非对本公开的限制，其中：
图1为根据本公开的实施例的薄膜晶体管的示意图；
图2为根据本公开的实施例的薄膜晶体管的示意图；
图3A-3B为根据本公开的实施例的形成第一半导体层的方法的示意图；
图4A-4C为根据本公开的实施例的形成第一半导体层、第二半导体层和源/漏极电极的方法的示意图；
图5A-5C为根据本公开的实施例的形成第一半导体层、第二半导体层和源/漏极电极的方法的示意图。
具体实施方式
为了使本公开的实施例的目的、技术方案和优点更加清楚，下面将接合附图，对本公开的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域技术人员在无需创造性劳动的前提下所获得的所有其他实施例，也都属于本公开保护的范围。
当介绍本公开的元素及其实施例时，冠词“一”、“一个”、“该”和“所述”旨在表示存在一个或者多个要素。用语“包含”、“包括”、“含有”和“具有”旨在包括性的并且表示可以存在除所列要素之外的另外的要素。
出于下文表面描述的目的，如其在附图中被标定方向那样，术语“上”、“下”、“左”、“右”“垂直”、“水平”、“顶”、“底”及其派生词应涉及公开。术语“上覆”、“在……顶上”、“定位在……上”或者“定位在……顶上”意味着诸如第一结构的第一要素存在于诸如第二结构的第二要素上，其中，在第一要素和第二要素之间可存在诸如界面结构的中间要素。术语“接触”意味着连接诸如第一结构的第一要素和诸如第二结构的第二要素，而在两个要素的界面处可以有或者没有其它要素。
图1为根据本公开的实施例的薄膜晶体管的示意图。如图1所示，根据本公开的实施例的薄膜晶体管包括：衬底10；在衬底10上依次层叠的第一半导体层11、栅极介质层12和栅极电极13。第一半导体层11具有位于薄膜晶体管的沟道区域R1中的第一部分P1和位于薄膜晶体管的源/漏极区域R2中且位于第一部分P1两侧第二部分P2。第二部分P2和第一部分P1的与第二部分P2邻接的第一子部分P11包括非晶半导体材料。第一部分P1的位于第一子部分P11之间的第二子部分P12包括多晶半导体材料。薄膜晶体管还包括位于源/漏极区域R2且与第二部分P2接触的第二半导体层14。第二半导体层14的导电性高于非晶半导体材料的导电性。例如，根据本公开的实施例，第一半导体层可以为非故意掺杂的，第二半导体层为N型或P型掺杂的。根据本公开的另一实施例，第一半导体层可 以具有与第二半导体层相同的掺杂类型但具有较低的掺杂浓度。
对于本公开的实施例的薄膜晶体管，第二半导体层14与第一半导体层11的第一部分P1不直接接触，这样可以减弱热载流子效应，降低晶体管的漏电流。
如图1所示，在本公开的实施例中，第二半导体层14可以与第一半导体层11的第二部分P2的远离衬底的表面S1接触。
图2为根据本公开的实施例的薄膜晶体管的示意图。如图2所示，在本公开的实施例中，第二半导体层14可以与第一半导体层11的第二部分P2的朝向衬底的表面S2接触。
薄膜晶体管还可以包括位于第二半导体层14的背离第一半导体层11的第二部分P2的一侧上的源/漏极电极15。
第一半导体层11和第二半导体层14的掺杂类型可以为N型，第二半导体层14的N型载流子浓度大于第一半导体层11的N型载流子浓度。例如，第一半导体层11的掺杂浓度在10 17ions/cm 3～10 19ions/cm 3之间。例如，第二半导体层的掺杂浓度可以在10 19ions/cm 3～10 21ions/cm 3之间。例如，当第一和第二半导体层的材料为诸如硅的四价元素半导体材料时，N型掺杂剂可以为诸如磷的五价杂质元素。
第一半导体层11和第二半导体层14的掺杂类型为P型，第二半导体层14的P型载流子浓度大于第一半导体层11的P型载流子浓度。例如，第一半导体层11的掺杂浓度可以在10 17ions/cm 3～10 19ions/cm 3之间。例如，第二半导体层的掺杂浓度可以在10 19ions/cm 3～10 21ions/cm 3之间。例如，当第一和第二半导体层的材料为诸如硅的四价元素半导体材料时，P型掺杂剂可以为诸如硼的三价杂质元素。
根据本公开的实施例，多晶半导体材料可以包括多晶硅，非晶半导体材料可以包括非晶硅。
本公开的实施例还提供了一种薄膜晶体管的制造方法。根据本公开的实施例的薄膜晶体管的制造方法包括：在衬底10上依次形成第一半导体层11、栅极介质层12和栅极电极13，其中，第一半导体层11具有位于薄膜 晶体管的沟道区域R1中的第一部分P1和位于薄膜晶体管的源/漏极区域R2中且位于第一部分P1两侧的第二部分P2；形成位于源/漏极区域中R2且与第二部分P2接触的第二半导体层14。其中，第二部分P2和第一部分P1的与第二部分P2邻接的第一子部分P11包括非晶半导体材料，第一部分P2的位于第一子部分P2之间的第二子部分P12包括多晶半导体材料。第二半导体层14的导电性高于非晶半导体材料的导电性。
本公开的实施例的薄膜晶体管的制造方法，使得第二半导体层14与第一半导体层11的第一部分P1不直接接触，这样可以减弱热载流子效应，降低晶体管的漏电流。图3A-3B为根据本公开的实施例的形成第一半导体层的方法的示意图。如图3A-3B所示，形成所述第一半导体层可以包括：
S31、如图3A所示，形成包括非晶半导体材料的第一半导体材料层11’，第一半导体材料层11’包括作为第一部分P1的中间部分P1’以及作为第二部分P2的位于中间部分P1’两侧的边缘部分P2’；
S33、如图3B所示，将第一半导体材料层11’的中间部分P1’的与第一子部分P11对应的部分P11’转变为多晶半导体材料。
根据本公开的实施例，可以采用激光退火来将非晶半导体材料来转换成多晶半导体材料(即，进行多晶化处理)。例如，可以采用微透镜阵列(Micro Lens Array，MLA)掩模来进行激光退火。
根据本公开的实施例的薄膜晶体管的制造方法还包括在第二半导体层14的背离第一半导体层的第二部分P2的一侧上形成源/漏极电极15。图4A-4C为根据本公开的实施例的形成第一半导体层、第二半导体层和源/漏极电极的方法的示意图。在图4A-4C所示出的实施例中，形成第一半导体层、第二半导体层和源/漏极电极包括：
S41、如图4A所示，在衬底10上形成源/漏极电极15。例如，可以在衬底上沉积导电层，然后对导电层进行构图来形成源/漏极电极。源/漏极电极可以包括金属，例如，钼。也可以在形成源/漏极电极之前在衬底上形成缓冲层16。
S43、如图4B所示，在源/漏极电极15上形成第二半导体层14。例如， 可以在源/漏极电极上沉积并非晶硅材料并进行掺杂，然后对非晶硅材料进行构图以去除位于沟道区域内的部分，从而形成第二半导体层。根据本公开的实施例，掺杂可以为在沉积时进行的原位掺杂，也可以在沉积后单独进行掺杂。
S45、如图4C所示，在第二半导体层14上形成所述第一半导体层11。例如，可以在第二半导体层14上沉积非晶硅材料以形成第一半导体层。
图5A-5C为根据本公开的实施例的形成第一半导体层、第二半导体层和源/漏极电极的方法的示意图。在图5A-5C所示出的实施例中，形成第一半导体层、第二半导体层和源/漏极电极包括：
S51、如图5A所示，在衬底10上形成第一半导体层11。例如，可以在衬底上沉积非晶硅材料以形成第一半导体层。也可以在形成第一半导体层11之前，在衬底上形成缓冲层。
S53、如图5B所示，在第一半导体层11上形成第二半导体层14。例如，可以在第一半导体层上沉积非晶硅材料并进行掺杂，然后对非晶硅材料进构图以去除位于沟道区域内的部分，从而形成第二半导体层。
S55、如图5C所示，在第二半导体层14上形成源/漏极电极15。例如，可以在第二半导体层上沉积导电层，然后对导电层进行构图来形成源/漏极电极。
根据本公开的实施例，可以采用诸如化学气相沉积(CVD)的方法来形成半导体层。
已经描述了某特定实施例，这些实施例仅通过举例的方式展现，而且不旨在限制本公开的范围。事实上，本文所描述的新颖实施例可以以各种其它形式来实施；此外，可在不脱离本公开的精神下，做出以本文所描述的实施例的形式的各种省略、替代和改变。所附权利要求以及它们的等价物旨在覆盖落在本公开范围和精神内的此类形式或者修改。

Claims (17)

  1. 一种薄膜晶体管，包括：衬底；
    在所述衬底上依次层叠的第一半导体层、栅极介质层和栅极电极，其中，所述第一半导体层具有位于所述薄膜晶体管的沟道区域中的第一部分和位于所述薄膜晶体管的源/漏极区域中且位于所述第一部分两侧的第二部分，并且其中，所述第二部分和所述第一部分的与所述第二部分邻接的第一子部分包括非晶半导体材料，所述第一部分的位于所述第一子部分之间的第二子部分包括多晶半导体材料；
    位于所述源/漏极区域的且与所述第二部分接触的第二半导体层，其中，所述第二半导体层的导电性高于所述非晶半导体材料的导电性。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述第二半导体层与所述第二部分的朝向所述衬底的表面接触。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述第二部分在所述第二半导体层与所述第二部分的远离所述衬底的表面接触。
  4. 根据权利要求2或3所述的薄膜晶体管，其中，所述第一半导体层和所述第二半导体层的掺杂类型为N型，所述第二半导体层的N型载流子浓度大于所述第一半导体层的N型载流子浓度。
  5. 根据权利要求2或3所述的薄膜晶体管，其中，所述第一半导体层和所述第二半导体层的掺杂类型为P型，所述第二半导体层的P型载流子浓度大于所述第一半导体层的P型载流子浓度。
  6. 根据权利要求2或3所述的薄膜晶体管，其中，所述第一半导体层的掺杂浓度在10 17ions/cm 3～10 19ions/cm 3之间，所述第二半导体层的掺杂浓度在在10 19ions/cm 3～10 21ions/cm 3之间。
  7. 根据权利要求1所述的薄膜晶体管，其中，所述多晶半导体材料包括多晶硅，所述非晶半导体材料包括非晶硅。
  8. 根据权利要求1所述的薄膜晶体管，还包括位于所述第二半导体层的背离所述第二部分的一侧上的源/漏极电极。
  9. 一种薄膜晶体管的制造方法，包括：
    在衬底上依次形成第一半导体层、栅极介质层和栅极电极，其中，所述第一半导体层具有位于所述薄膜晶体管的沟道区域中的第一部分和位于所述薄膜晶体管的源/漏极区域中且位于所述第一部分两侧的第二部分，并且其中，所述第二部分和所述第一部分的与所述第二部分邻接的第一子部分包括非晶半导体材料，所述第一部分的位于所述第一子部分之间的第二子部分包括多晶半导体材料；
    形成位于所述源/漏极区域中且与所述第二部分接触的第二半导体层，其中，所述第二半导体层的导电性高于所述非晶半导体材料的导电性。
  10. 根据权利要求9所述的薄膜晶体管的制造方法，其中，形成所述第一半导体层包括：
    形成包括所述非晶半导体材料的第一半导体材料层，所述第一半导体材料层包括作为所述第一部分的中间部分以及作为所述第二部分的位于所述中间部分两侧的边缘部分；
    将所述第一半导体材料层的所述中间部分的与所述第一子部分对应的部分转变为所述多晶半导体材料。
  11. 根据权利要求10所述的薄膜晶体管的制造方法，其中，所述转换包括对所述非晶半导体材料进行激光退火。
  12. 根据权利要求11所述的薄膜晶体管的制造方法，其中，所述激光退火包括采用微透镜阵列掩模。
  13. 根据权利要求9-12中任一项所述的薄膜晶体管的制造方法，还包括在所述第二半导体层的背离所述第二部分的一侧上形成源/漏极电极。
  14. 根据权利要求13所述的薄膜晶体管的制造方法，形成所述第一半导体层、所述第二半导体层和所述源/漏极电极包括：
    在所述衬底上形成源/漏极电极；
    在所述源/漏极电极上形成所述第二半导体层；
    在所述第二半导体层上形成所述第一半导体层。
  15. 根据权利要求13所述的薄膜晶体管的制造方法，形成所述第一半导体层、所述第二半导体层和所述源/漏极电极包括：
    在所述衬底上形成所述第一半导体层；
    在所述第一半导体层上形成所述第二半导体层；
    在所述第二半导体层上形成所述源/漏极电极。
  16. 根据权利要求14或15所述的薄膜晶体管的制造方法，其中，形成所述第一半导体层、所述第二半导体层包括采用CVD。
  17. 根据权利要求9-12和14-15中任一项所述的薄膜晶体管的制造方法，其中，所述多晶半导体材料包括多晶硅，所述非晶半导体材料包括非晶硅。
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