WO2020135378A1 - 一种沟槽型vdmos的元胞版图结构 - Google Patents

一种沟槽型vdmos的元胞版图结构 Download PDF

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WO2020135378A1
WO2020135378A1 PCT/CN2019/127710 CN2019127710W WO2020135378A1 WO 2020135378 A1 WO2020135378 A1 WO 2020135378A1 CN 2019127710 W CN2019127710 W CN 2019127710W WO 2020135378 A1 WO2020135378 A1 WO 2020135378A1
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source
trench
region
cell
source region
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PCT/CN2019/127710
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English (en)
French (fr)
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肖魁
方冬
卞铮
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无锡华润上华科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0869—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out

Definitions

  • the present application relates to the field of semiconductor technology, specifically to a cell layout structure of a trench-type VDMOS.
  • VDMOS vertical double-diffused metal oxide semiconductor field effect transistor
  • Vertical Double-diffuse MOS vertical Double-diffuse MOS
  • Trench VDMOS products are more widely used power devices.
  • the maturity of the trench process further reduces the size of a single cell.
  • the trench area passes through the bottom of the P-type base region, the trench is formed.
  • the channel is located between the source region and the drift region.
  • the JFET region can be eliminated, and the on-resistance is greatly reduced, so the trench VDMOS greatly improves the performance of the MOS power device.
  • the present application provides a cell layout structure of a trench-type VDMOS and a manufacturing method thereof to further increase the channel density so that the chip area can be further reduced under the same current.
  • the present application provides a cell layout structure of a trench-type VDMOS, including at least one cell, and the cell includes:
  • a protrusion structure extending in the direction of the trench is provided on the boundary of the source region to increase the perimeter of the channel of the cell.
  • the source region is improved, a convex structure is added on the boundary of the source region, and the length of the channel defined by the boundary of the trench is increased , It can increase the channel density, so that under the same current situation, further reduce the chip area.
  • FIG. 1 is a schematic diagram of a cell layout structure of a trench-type VDMOS according to an embodiment of the present application
  • 2A-2C are cross-sectional views of the cell layout structure of the trench VDMOS shown in FIG. 1 along A1-A2, B1-B2, and C1-C2, respectively;
  • 3A-3H are schematic diagrams of the deformation of the cell layout structure of the trench-type VDMOS according to an embodiment of the present application.
  • the channel width of the device In order to increase the operating current of the device, the channel width of the device needs to be increased as much as possible. In order to obtain the largest channel width within a certain silicon area, multiple cells are generally connected in parallel, and the more cells in parallel , The greater the device current, the greater the channel width of each cell, the greater the device current, or the greater the cell channel density (cell channel perimeter/cell area), the greater the device current.
  • the present application proposes a cell layout structure of a trench-type VDMOS, in which the cell layout structure is used in addition to VDMOS In addition to the device, it can also be applied to other similar structures.
  • the structure of the trench VDMOS will be described first, and then the cell layout structure of the trench VDMOS will be further described.
  • FIG. 2C The general structure of the trench-type VDMOS is shown in FIG. 2C, where FIG. 2C is a cross-sectional view of the cell layout structure of the trench-type VDMOS shown in FIG. 1 along C1-C2.
  • the trench-type VDMOS includes :
  • a semiconductor substrate 201, the semiconductor substrate 201 includes a body layer 2011 and an epitaxial layer 2012 on the body layer 2011;
  • the trench 202 is located in the epitaxial layer 2012;
  • the body region 203 is located in the epitaxial layer 2012 on both sides of the trench 202;
  • a first source-drain region 2041 is located in the body region 203, and the doping ion conductivity type of the first source-drain region 2041 is the same as the doping ion conductivity type of the body region 203;
  • a second source-drain region 2042 located on the body region 203 on both sides of the trench 202, a doped ion conductivity type of the second source drain region 2042 and a doped ion conductivity type of the body region 203 in contrast;
  • the gate structure 205 is located inside the trench 202;
  • An interlayer dielectric layer 206 is located on the second source-drain region 2042 and the gate structure 205;
  • the contact hole 207 is located in the interlayer dielectric layer 206 and extends to the second source-drain region 2042 and part of the first source-drain region 2041.
  • the doping ions of the body region 203 are P-type, such as boron or other trivalent elements; the doping ions of the first source-drain region 2041 are P-type, such as boron or other trivalent elements; the first The doping ions of the second source-drain region 2042 are N-type, such as phosphorus or other pentavalent elements.
  • the gate structure 205 includes a gate oxide layer 2051 at the bottom and sidewalls of the trench 202 and a polysilicon layer 2052 over the gate oxide layer 2051.
  • the gate structure 205 of the device described in this application is located inside the trench 202 and is formed after filling the gate material in the trench. Therefore, the shape of the trench is the same as the shape of the gate structure.
  • the structure after the trench is formed and before the gate material is not filled will describe the cell layout structure of the present application.
  • FIG. 1 is a cross-sectional view of the upper surface of the gate structure 205 in FIG. 2A cut along a horizontal plane.
  • the cell layout structure includes: a cell region 101, surrounding the cell A transition zone (not shown) of zone 101 and a terminal zone (not shown) provided at the periphery of the transition zone,
  • the cell region 101 includes several source regions 102 arranged in parallel, and several of the source regions 102 are separated by trenches 103, and the trenches are used to form a gate structure in a subsequent step, so
  • the boundary of the trench is the boundary of the gate structure, and at the same time, the boundary of the trench coincides with the boundary of the source region 102, so the channel is the position of the adjacent interface between the trench and the source region.
  • the boundary of 103 or the boundary of the source region 102 may be used to define the channel 104 in the cell.
  • the cell layout structure of the trench VDMOS includes at least one cell, and the cell includes:
  • a protrusion structure extending in the direction of the trench is provided on the boundary of the source region to increase the circumference of the channel.
  • the cell refers to a repeating minimum unit arranged in parallel in the cell layout structure, that is, the cell includes both the trench 103 and the source region 102 (ie, non-trench Area), wherein the protruding structure is provided on the boundary of the source area.
  • the more source regions in parallel in the cell structure described in this application the greater the device current, the larger the channel width of each source region, and the greater the device current. Therefore, the source regions included in the cell structure
  • the number of 102 is not limited, and it can be added as a repeating unit according to actual needs.
  • the trench is a trench before filling the gate material, which is used to form a gate structure and then form a trench-type VDMOS.
  • the profile of the channel in the cell is improved to increase the channel perimeter in the cell.
  • a convex structure is provided on the boundary of the source region in the cell, and the length of the boundary of the source region can be extended by the arrangement of the convex structure , Thereby increasing the circumference of the channel defined by the source region.
  • the boundary of the trench completely coincides with the boundary of the source region, so when the shape of the source region After the improvement, the shape of the groove will be correspondingly improved, and the two are in a matching relationship.
  • a protrusion structure is provided on the source region
  • FIGS. 3A-3H are cross-sectional views of various embodiments of the upper surface of the gate structure 205 in FIG. 2A cut along a horizontal plane.
  • At least one boundary of the source region is provided with a plurality of mutually spaced convex structures and the convex structures do not penetrate the trench, so that the boundary of the source region is uneven
  • the length of the channel in the cell is increased by setting the side wall of the source region to an uneven shape.
  • the notch is provided on the inner side wall and/or the outer side wall of the groove, and the notch does not penetrate the groove, and the groove is a closed structure with uneven side walls.
  • the perimeter of the channel can be increased by the arrangement.
  • At least one boundary of the source region is provided with the protruding structure penetrating the trench to remove the trench Partitioning and connecting the source region with at least another source region adjacent thereto through the protruding structure.
  • the notch penetrates the groove to partition the groove.
  • the protruding structure penetrates the trenches to break the trenches, so that the trenches are discontinuous and unsealed on the plane.
  • the side wall of the protruding structure increases the perimeter of the boundary of the source region, thereby increasing the perimeter of the channel.
  • the protruding structure includes at least the above two ways of penetrating and not penetrating the trench, and the common parts of the two ways will be described below.
  • the projected shape of the source region on the horizontal plane in this application that is, the shape of the plan view of the source region, is not limited herein, and can be any polygon, such as a triangle, a square, or a hexagon. Wait.
  • the squares shown in FIGS. 3A-3E, 3F, and 3G, or the hexagons shown in FIG. 3H are not limited to the above example, and may be any other suitable shapes. I will not list them one by one here.
  • the source region has multiple sides, wherein the protruding structure is provided on at least one side of the polygonal structure.
  • At least one protruding structure is provided on two opposite sides of the source region.
  • the protruding structure may be provided at any position on a boundary of the source region, for example, at a middle position of a boundary of the source region, as shown in FIGS. 3A and 3E; it may also be located at the source The location of one end of a boundary of the zone is shown in Figures 3B-3F.
  • the protruding structure when located at one end of a boundary of the source region, it further includes at least the following types:
  • the source region is a square structure
  • the cell (basic repeating unit) of the cell layout structure includes four source regions, wherein the protruding structure is located in each source region At a diagonal line, and one of the protruding structures of the four source regions overlaps to form the repeating unit.
  • the source region is a square structure
  • the cell (basic repeating unit) of the cell layout structure includes two source regions, wherein the protruding structure is located at each source region Diagonally, and one of the two source regions protruding structures are overlapped, and then multiple repeat units are provided, for example, as shown in FIG. 3C, two repeat units described above are provided to form four The structure of the source region, and the repeating unit shares a trench.
  • FIG. 3F is a modification of FIG. 3C, the difference is only in the position of the protruding structure, for example, the protruding structure in FIG. 3C is located on the right side of the source region, and the protruding in FIG. 3F The structure is located on the left side of the source area.
  • the source region is a square structure
  • the cell (basic repeating unit) of the cell layout structure includes four source regions, wherein the protruding structure is located in each source region After combining the four source regions to form a repeating unit at both ends of a side, the protruding structure is located at the four top corners of the repeating unit.
  • each of the source regions is surrounded by the trench alone, or adjacent source regions share part of the trench.
  • adjacent source regions may share one trench.
  • the source regions may also have separate trenches, but adjacent trenches communicate with each other, that is, the width of the trench is twice the normal width, as shown in FIG. 3H, which is not limited herein.
  • the sidewall profile of the source region is a vertical plane or a curved surface.
  • the cross section of the notch is flat or curved.
  • the sidewall of the source region is a vertical plane, and the projection of the sidewall on the horizontal plane is a straight line.
  • the side wall of the source area is a curved surface, and the projection of the side wall on the horizontal plane is a curve with a certain arc.
  • the side wall of the source area may also have other shapes As long as the groove length can be increased, it can be applied to this application.
  • the outline of the side wall of the protruding structure is a vertical plane, or the outline of at least one side wall of the protruding structure is a curved surface.
  • the outline of the side wall of the protruding structure is a vertical plane, and the projection of the side wall on the horizontal plane is square, and the outline of the side wall of the protruding structure may be a cubic structure.
  • the outline of the side wall of the protruding structure may be a cubic structure.
  • cuboid structure for example, cuboid structure.
  • the profile of the side wall of the protruding structure may also be gradual, for example, the width gradually decreases in the direction extending toward the groove, for example, the projected shape of the protruding structure on the horizontal plane is a stepped structure, such as As shown in Figure 3E.
  • the projected shape of the protruding structure on the horizontal plane is a stepped structure, such as As shown in Figure 3E.
  • it may be other shapes with a reduced width gradient, which is not limited herein.
  • FIG. 2A-2C are cross-sectional views of the cell structure shown in FIG. 1, wherein FIG. 2A is a straight line parallel to the source surface 102 of FIG.
  • A1-A2 a cross-sectional view of A1-A2
  • a semiconductor substrate 201 including a body layer 2011 and an epitaxial layer 2012 located above the body layer 2011; a trench 202 located at the epitaxial layer 2012; the body region 203 and the source-drain region 204 provided from bottom to top, located in the epitaxial layer 2012 on both sides of the trench 202, the source-drain region 204 is doped with the ion conductivity type and the body
  • the region 203 has the opposite doping ion conductivity type;
  • the gate structure 205 is located inside the trench 202; and the interlayer dielectric layer 206 is located above the source-drain region 204 and the gate structure 205.
  • the body layer 2011 of the semiconductor substrate may be at least one of the materials mentioned below: silicon, silicon on insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator ( S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.
  • An active region may be defined on the semiconductor substrate 201.
  • the semiconductor substrate is N-type doped, that is, the doping ions of the body layer 2011 and the epitaxial layer 2012 are N-type, such as phosphorus or other pentavalent elements.
  • the doping ions of the body region 203 are P-type, such as boron or other trivalent elements, and the doping ions of the source-drain region 204 are N-type, such as phosphorus or other pentavalent elements.
  • the gate structure 205 includes a gate oxide layer 2051 at the bottom and sidewalls of the trench 202 and a polysilicon layer 2052 over the gate oxide layer 2051.
  • the gate structure 205 may also be any separate gate structure in the prior art.
  • 2B is a cross-sectional view of the source region 102 along a straight line (B1-B2) that does not pass through the contact hole 105 and is parallel to and does not pass through the groove surface (opening 106) of the protruding structure, which includes: a semiconductor substrate 201, the semiconductor substrate 201 includes a body layer 2011 and an epitaxial layer 2012 located above the body layer 2011; a trench 202 located in the epitaxial layer 2012; a body region 203 and source-drain disposed from bottom to top Region 204, located in the epitaxial layer 2012 on both sides of the trench 202, the source-drain region 204 has a doped ion conductivity type opposite to that of the body region 203; the gate structure 205, Located inside the trench 202; an interlayer dielectric layer 206 is located above the source-drain region 204 and the gate structure 205.
  • the doping ions of the body region 203 are P-type, such as boron or other trivalent elements, and the doping ions of the source-drain region 204 are N-type, such as phosphorus or other pentavalent elements.
  • the gate structure 205 includes a gate oxide layer 2051 at the bottom and sidewalls of the trench 202 and a polysilicon layer 2052 over the gate oxide layer 2051.
  • FIGS. 2A and 2B Comparing FIGS. 2A and 2B, it can be found that the difference between the two lies in the ratio of the trench region to the channel region.
  • the ratio of the trench region in FIG. 2A is greater than the ratio of the trench region in FIG. 2B, while the trench in FIG. 2A
  • the ratio of the channel area is smaller than the ratio of the channel area in FIG. 2B, that is, in the cell layout structure, the arrangement of the protruding structure can increase the length of the channel defined by the boundary of the trench, which can increase the trench
  • the track density makes it possible to further reduce the chip area at the same current.
  • the source region is improved, a convex structure is added on the boundary of the source region, the non-essential region in the source region is fully utilized, and the boundary defined by the trench is increased
  • the length of the channel can increase the channel density, so that under the same current situation, the chip area is further reduced.

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Abstract

一种沟槽型VDMOS的元胞版图结构，包括至少一个元胞，所述元胞包括：若干个并联设置的源区(102)；沟槽(103)，环绕每个所述源区(102)设置，所述沟槽(103)用于形成栅极结构，所述沟槽(103)的边界和所述源区(102)的边界重合，以限定所述元胞的沟道(104)；其中，所述源区(102)的边界上设置有向所述沟槽方向延伸的凸出结构，以增加每个所述元胞的沟道的周长。

Description

一种沟槽型VDMOS的元胞版图结构 技术领域
本申请涉及半导体技术领域，具体而言涉及一种沟槽型VDMOS的元胞版图结构。
背景技术
随着半导体技术的不断发展，VDMOS(垂直双扩散金属氧化物半导体场效应管，Vertical Double-diffuse MOS)器件因具有开关损耗小、输入阻抗高、驱动功率小、频率特性好、跨导高度线性等优点，被越来越广泛地应用在模拟电路和驱动电路，尤其是高压功率部分。
沟槽型VDMOS产品是较为广泛应用的功率器件，一方面，沟槽工艺的成熟使单个元胞的尺寸进一步降低，另一方面，由于沟槽区域穿过P型基区最下端，形成的沟道位于源区与漂移区之间，相比普通VDMOS，可以消除JFET区，导通电阻大大减小，所以沟槽型VDMOS极大提高了MOS功率器件的性能。
发明内容
本申请提供一种沟槽型VDMOS的元胞版图结构及其制造方法，以进一步增大沟道密度，使得在同等电流的情况下，进一步减小芯片面积。
在发明内容部分中引入了一系列简化形式的概念，这将在具体实施方式部分中进一步详细说明。本申请的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。
本申请提供一种沟槽型VDMOS的元胞版图结构，包括至少一个元胞，所述元胞包括：
若干个并联设置的源区；以及
沟槽，环绕每个所述源区设置，所述沟槽用于形成栅极结构，所述沟槽的边界和所述源区的边界重合，以限定所述元胞的沟道；
其中，所述源区的边界上设置有向所述沟槽方向延伸的凸出结构，以增 加所述元胞的沟道的周长。
综上所述，根据本申请的元胞版图结构，对所述源区进行了改进，在所述源区的边界上增加了凸出结构，增加了由沟槽的边界限定的沟道的长度，其可以增大沟道密度，使得在同等电流的情况下，进一步减小芯片面积。
附图说明
本申请的下列附图在此作为本申请的一部分用于理解本申请。附图中示出了本申请的实施例及其描述，用来解释本申请的原理。
附图中：
图1为根据本申请实施例的沟槽型VDMOS的元胞版图结构的示意图；
图2A-图2C为图1所示的沟槽型VDMOS的元胞版图结构分别沿A1-A2、B1-B2和C1-C2的截面图；
图3A-3H为本申请实施例的沟槽型VDMOS的元胞版图结构的变形的示意图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本申请更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本申请可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本申请发生混淆，对于本领域公知的一些技术特征未进行描述。
为了彻底理解本申请，将在下列的描述中提出详细的步骤，以便阐释本申请提出的沟槽型VDMOS的元胞版图结构。显然，本申请的施行并不限定于半导体领域的技术人员所熟习的特殊细节。本申请的较佳实施例详细描述如下，然而除了这些详细描述外，本申请还可以具有其他实施方式。
应当理解的是，当在本说明书中使用术语“包含”和/或“包括”时，其指明存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或附加一个或多个其他特征、整体、步骤、操作、元件、组件和/或它们的组合。
为增大器件工作电流，则需尽量增大器件的沟道宽度，为了在一定的硅片面积内获得尽量大的沟道宽度，一般采用多个元胞并联的方式，并联的元胞越多，器件电流越大，每个元胞的沟道宽度越大，器件电流越大，或者说，元胞沟道密度(元胞沟道周长/元胞面积)越大，器件电流越大。
为了进一步增大沟道密度，使得在同等电流的情况下，进一步减小芯片面积，本申请提出了一种沟槽型VDMOS的元胞版图结构，其中，所述元胞版图结构除了用于VDMOS器件以外，还可以应用于其他类似的结构，下面首先对沟槽型VDMOS的结构进行说明，然后再对所述沟槽型VDMOS的元胞版图结构作进一步的说明。
其中，沟槽型VDMOS的通常结构如图2C所示，其中，图2C为图1所示的沟槽型VDMOS的元胞版图结构分别沿C1-C2的截面图，所述沟槽型VDMOS包括：
半导体衬底201，所述半导体衬底201包括本体层2011和位于所述本体层2011之上的外延层2012；
沟槽202，位于所述外延层2012中；
体区203，位于所述沟槽202两侧的所述外延层2012中；
第一源漏区2041，位于所述体区203内，所述第一源漏区2041的掺杂离子导电类型与所述体区203的掺杂离子导电类型相同；
第二源漏区2042，位于所述沟槽202两侧的所述体区203之上，所述第二源漏区2042的掺杂离子导电类型与所述体区203的掺杂离子导电类型相反；
栅极结构205，位于所述沟槽202内部；
层间介电层206，位于所述第二源漏区2042和所述栅极结构205之上；
接触孔207，位于所述层间介电层206中，并延伸至所述第二源漏区2042和部分所述第一源漏区2041。
其中，所述体区203的掺杂离子为P型，如硼或其他三价元素；所述第一源漏区2041的掺杂离子为P型，如硼或其他三价元素；所述第二源漏区2042的掺杂离子为N型，如磷或其他五价元素。
所述栅极结构205包括位于所述沟槽202底部及侧壁的栅氧化层2051以及位于所述栅氧化层2051之上的多晶硅层2052。
本申请中所述器件的栅极结构205，位于所述沟槽202内部、通过在所述沟槽内填充栅极材料之后形成，因此沟槽的形状和栅极结构的形状相同，下面以在形成沟槽之后并且在没有填充所述栅极材料之前的结构对本申请的所述元胞版图结构进行说明。
具体地，其中，图1为图2A中栅极结构205的上表面沿水平面进行切割的剖面图，如图1所示，所述元胞版图结构包括：元胞区101、围绕所述 元胞区101的过渡区(未示出)和设置在所述过渡区外围的终端区(未示出)，
其中，所述元胞区101包括若干个并联设置的源区102，若干个所述源区102之间由沟槽103隔离，所述沟槽用于在后续的步骤中形成栅极结构，因此所述沟槽的边界即为栅极结构的边界，同时所述沟槽的边界与所述源区102的边界重合，因此沟道为沟槽与源区的相邻界面位置，所述沟槽103的边界或源区102的边界可以用来限定所述元胞中的沟道104。
所述沟槽型VDMOS的元胞版图结构，包括至少一个元胞，所述元胞包括：
若干个并联设置的源区；
沟槽，环绕每个所述源区设置，所述沟槽用于形成栅极结构，所述沟槽的边界和所述源区的边界重合，以限定所述元胞的沟道；
其中，所述源区的边界上设置有向所述沟槽方向延伸的凸出结构，以增加沟道的周长。
需要说明的是，在本申请的实施例中，所述元胞是指在元胞版图结构中并联设置的重复最小单元，即元胞既包括沟槽103也包括源区102(即非沟槽区)，其中，所述凸出结构设置于所述源区的边界上。
其中，在本申请中所述元胞结构并联的源区越多，器件电流越大，每个源区的沟道宽度越大，器件电流越大，因此在此对元胞结构包含的源区102的数目不做限制，其作为重复单元可以根据实际需要进行添加。
其中，所述沟槽为填充栅极材料之前的沟槽，用于形成栅极结构，进而形成沟槽型VDMOS，在本申请中为了进一步提高元胞沟道密度(元胞沟道周长/元胞面积)，从而获得更大器件电流，对所述元胞中沟道的轮廓进行了改进，以增加元胞中沟道周长。
具体地，为了增加元胞中沟道的轮廓，在元胞中所述源区的边界上设置了凸出结构，通过所述凸出结构的设置，使得所述源区的边界的长度得以延伸，从而使所述源区限定的沟道的周长增加。
需要说明的是，在本申请中由于所述源区被所述沟槽包围并且直接接触，因此，所述沟槽的边界与所述源区的边界完全重合，因此当所述源区的形状改进之后，所述沟槽的形状则会进行相应的改进，两者为相互匹配的关系。例如在所述源区上设置凸出结构时，在所述沟槽形成于水平面上的投影中，在所述沟槽上设置有至少一个缺口，以增加相应位置处的所述沟道的周长，其中所述缺口对应所述凸出结构。
下面结合附图对本申请所述凸出结构做进一步的说明，其中，图3A-3H为图2A中栅极结构205的上表面沿水平面进行切割的各实施例剖面图。
其中，如图3G所示，所述源区的至少一个边界上设置有若干相互间隔的凸出结构并且所述凸出结构并非贯穿所述沟槽，以使所述源区的边界呈凹凸不平的形状，通过将所述源区的侧壁设置为凹凸不平的形状来增加元胞中沟道的长度。对应地，所述缺口设置于所述沟槽的内侧壁和/或外侧壁，并且所述缺口并非贯穿所述沟槽，所述沟槽为侧壁凹凸不平的密闭的结构。在所述结构中，只要所述源区的侧壁为非平面形状即可，通过所述设置即可增加所述沟道的周长。
另外，如图3A-3F以及3H所示，在所述图示的结构中，所述源区的至少一个边界上设置有贯穿所述沟槽的所述凸出结构，以将所述沟槽隔断并使所述源区与其相邻的至少另一个源区通过所述凸出结构相连通。相应地，在所述沟槽中，所述缺口贯穿所述沟槽，以将所述沟槽隔断。
在上述示例中，所述凸出结构穿通所述沟槽，以将所述沟槽间断开，使所述沟槽成为不连续、平面上不密闭的结构。其中，凸出结构的侧壁使得源区边界的周长增加，进而增加沟道的周长。
在本申请中所述凸出结构至少包括上述穿通和不穿通所述沟槽的两种方式，下面对两种方式中共同的部分进行说明。
首先，对于本申请中所述源区的在水平面上的投影形状，即所述源区的平面俯视图的形状，在此并不进行限定，可以为任意多边形，例如三角形、四方形、六边形等。
例如附图3A-图3E、3F、3G所示的正方形，或者如附图3H所示的六边形，当然所述源区的形状不局限于上述示例，还可以为其他任何合适的形状，在此不再一一列举。
其中，所述源区有多个边，其中，在所述多边形的结构的至少一边上设置所述凸出结构。
可选地，在所述源区中相对设置的两个边上设置至少一个所述凸出结构。
进一步，所述凸出结构可以设置于所述源区的一个边界上的任意位置，例如位于所述源区的一个边界的中间位置，如图3A和图3E所示；还可以位于所述源区的一个边界的一端的位置，如图3B-3F所示。
进一步，当所述凸出结构位于所述源区的一个边界的一端的位置，还至少包括以下几种：
第一，如图3B所示，所述源区为方形结构，所述元胞版图结构的元胞(基本重复单元)包括四个源区，其中，所述凸出结构位于每个源区的对角线处，并且所述四个源区的一个凸出结构重叠设置，以形成所述重复单元。
第二，如图3C所示，所述源区为方形结构，所述元胞版图结构的元胞(基本重复单元)包括两个源区，其中，所述凸出结构位于每个源区的对角线处，并且所述两个源区的一个凸出结构重叠设置，然后以此为重复单元设置多个，例如如图3C所示，设置两个上述的重复单元，以形成具有四个源区的结构，并且所述重复单元共用一个沟槽。
其中，附图3F为附图3C的变形，区别仅在于所述凸出结构的位置，例如在附图3C中所述凸出结构位于源区的右侧，在附图3F中所述凸出结构位于源区的左侧。
第三，如图3D所示，所述源区为方形结构，所述元胞版图结构的元胞(基本重复单元)包括四个源区，其中，所述凸出结构位于每个源区的一个边的两端，将四个源区结合形成重复单元之后，所述凸出结构位于所述重复单元的四个顶角上。
进一步，每个所述源区被单独的所述沟槽环绕，或相邻的所述源区共用部分所述沟槽。
在上述示例中，如图3A所示，在所述四个源区中，相邻的源区可以共用一个沟槽。在其他实施例中，源区也可以各自有单独的沟槽，但是相邻的沟槽相互连通，即沟槽的宽度为正常宽度的2倍，如图3H所示，在此不做限定。
进一步，可选地，所述源区的侧壁轮廓为竖直平面或弯曲面。相应地，所述缺口的断面为平面或曲面。
具体地，如图3A-3E所示，所述源区的侧壁为竖直的平面，其侧壁在水平面上的投影为直线。在图3F所示的实施例中，所述源区的侧壁为弯曲的曲面，其侧壁在水平面上的投影为具有一定弧度的曲线，当然所述源区的侧壁还可以为其他形状，只要能够增加沟槽长度，均可以应用于本申请。
进一步，所述凸出结构的侧壁的轮廓为竖直平面，或所述凸出结构的至少一个侧壁的轮廓为弯曲面。
具体地，如图3A-3E所示，所述凸出结构的侧壁的轮廓为竖直平面，其侧壁在水平面上的投影为方形，凸出结构的侧壁轮廓可以为立方体形结构，例如长方体结构等。
进一步，所述凸出结构的侧壁的轮廓还可以为渐变式的，例如宽度沿向沟槽延伸的方向逐渐减小，比如所述凸出结构在水平面上的投影形状为台阶形结构，如图3E所示。当然还可以是其他宽度梯度减小的形状，在此不做限定。
上述为沟槽型VDMOS的元胞版图结构中源区的形状和沟槽所做的描述，下面结合附图对所述沟槽型VDMOS的元胞版图结构中其他结构作进一步的说明。其中，图2A-图2C为图1所示的元胞结构的截面图，其中图2A为图1源区102沿平行地穿过所述凸出结构的沟槽表面(开口106)的直线(即A1-A2)的截面图，其包括：半导体衬底201，所述半导体衬底201包括本体层2011和位于所述本体层2011之上的外延层2012；沟槽202，位于所述外延层2012中；自下而上设置的体区203和源漏区204，位于所述沟槽202两侧的所述外延层2012中，所述源漏区204的掺杂离子导电类型与所述体区203的掺杂离子导电类型相反；栅极结构205，位于所述沟槽202内部；层间介电层206，位于所述源漏区204和所述栅极结构205之上。
具体地，所述半导体衬底的本体层2011可以是以下所提到的材料中的至少一种：硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。半导体衬底201上可以被定义有源区。可选地，其中所述半导体衬底进行N型掺杂，即所述本体层2011和所述外延层2012的掺杂离子为N型，如磷或其他五价元素。
所述体区203的掺杂离子为P型，如硼或其他三价元素，所述源漏区204的掺杂离子为N型，如磷或其他五价元素。
所述栅极结构205包括位于所述沟槽202底部及侧壁的栅氧化层2051以及位于所述栅氧化层2051之上的多晶硅层2052。在其他实施例里，栅极结构205也可为现有技术中的任意分离式栅极结构。
图2B为源区102沿未穿过接触孔105、平行于且未穿过所述凸出结构的沟槽表面(开口106)的直线(B1-B2)的截面图，其包括：半导体衬底201，所述半导体衬底201包括本体层2011和位于所述本体层2011之上的外延层2012；沟槽202，位于所述外延层2012中；自下而上设置的体区203和源漏区204，位于所述沟槽202两侧的所述外延层2012中，所述源漏区204的掺杂离子导电类型与所述体区203的掺杂离子导电类型相反；栅极结构205，位于所述沟槽202内部；层间介电层206，位于所述源漏区204和所述栅极 结构205之上。
所述体区203的掺杂离子为P型，如硼或其他三价元素，所述源漏区204的掺杂离子为N型，如磷或其他五价元素。
所述栅极结构205包括位于所述沟槽202底部及侧壁的栅氧化层2051以及位于所述栅氧化层2051之上的多晶硅层2052。
对比图2A和图2B可以发现，两者的区别在于沟槽区域和沟道区域的比例，图2A中的沟槽区域的比例大于图2B中的沟槽区域的比例，而图2A中的沟道区域的比例小于图2B中的沟道区域的比例，即在元胞版图结构中，由于所述凸出结构的设置可以增加由沟槽的边界限定的沟道的长度，进而可以增大沟道密度，使得在同等电流的情况下，进一步减小芯片面积。
根据本申请的元胞版图结构，对所述源区进行了改进，在所述源区的边界上增加了凸出结构，充分利用了源区中的非必要区域增加了由沟槽的边界限定的沟道的长度，其可以增大沟道密度，使得在同等电流的情况下，进一步减小芯片面积。
本申请已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本申请限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本申请并不局限于上述实施例，根据本申请的教导还可以做出更多种的变型和修改，这些变型和修改均落在本申请所要求保护的范围以内。本申请的保护范围由附属的权利要求书及其等效范围所界定。

Claims (15)

  1. 一种沟槽型VDMOS的元胞版图结构，包括至少一个元胞，所述元胞包括：
    若干个并联设置的源区；以及
    沟槽，环绕每个所述源区设置，所述沟槽用于形成栅极结构，所述沟槽的边界和所述源区的边界重合，以限定所述元胞的沟道；
    其中，所述源区的边界上设置有向所述沟槽方向延伸的凸出结构，以增加所述元胞的沟道的周长。
  2. 根据权利要求1所述的元胞版图结构，其中，所述源区的至少一个边界上设置有若干相互间隔的所述凸出结构并且所述凸出结构并非贯穿所述沟槽，以使所述源区的边界呈凹凸不平的形状。
  3. 根据权利要求1所述的元胞版图结构，其中，所述源区的至少一个边界上设置有贯穿所述沟槽的所述凸出结构，以将所述沟槽隔断并使所述源区与其相邻的至少另一个源区通过所述凸出结构相连通。
  4. 根据权利要求1所述的元胞版图结构，其中，所述源区的侧壁轮廓为竖直平面或弯曲面。
  5. 根据权利要求1所述的元胞版图结构，其中，所述凸出结构的侧壁的轮廓为竖直平面，或所述凸出结构的至少一个侧壁的轮廓为弯曲面。
  6. 根据权利要求1所述的元胞版图结构，其中，所述凸出结构在水平面上的投影形状为方形或台阶形，或所述凸出结构在水平面上的投影的轮廓为曲线。
  7. 根据权利要求1所述的元胞版图结构，其中，所述凸出结构设置于所述源区的至少一边上的中间位置，和/或所述凸出结构设置于所述源区的至少一边上的端部上。
  8. 根据权利要求7所述的元胞版图结构，其中，所述源区为方形结构，每个所述元胞包括四个源区，所述凸出结构位于每个源区的对角线处，并且所述四个源区的一个凸出结构重叠设置。
  9. 根据权利要求7所述的元胞版图结构，其中，所述源区为方形结构，每个所述元胞包括两个源区，所述凸出结构位于每个源区的对角线处，并且所述两个源区的一个凸出结构重叠设置。
  10. 根据权利要求7所述的元胞版图结构，其中，所述源区为方形结构，每个所述元胞包括四个源区，所述凸出结构位于每个源区的一个边的两端。
  11. 根据权利要求1所述的元胞版图结构，其中，在每个源区相对的两个边上各设置有一个所述凸出结构；和/或所述凸出结构位于所述源区的对角线的端部上；和/或所述凸出结构位于所述源区的一条边的两个端部上。
  12. 根据权利要求1所述的元胞版图结构，其中，每个所述源区被单独的所述沟槽环绕，或相邻的所述源区共用部分所述沟槽。
  13. 根据权利要求1所述的元胞版图结构，其中，所述元胞还包括：
    半导体衬底，所述半导体衬底包括本体层和位于所述本体层之上的外延层，所述沟槽位于所述外延层中；
    体区，位于所述外延层中且位于所述沟槽两侧；
    第一源漏区，位于所述体区内，所述第一源漏区的掺杂离子导电类型与所述体区的掺杂离子导电类型相同；
    第二源漏区，位于所述体区之上且位于所述沟槽两侧，所述第二源漏区的掺杂离子导电类型与所述体区的掺杂离子导电类型相反；
    栅极结构，填充于所述沟槽内部；
    层间介电层，位于所述第二源漏区和所述栅极结构之上；以及
    接触孔，位于所述源区内的所述层间介电层中，并延伸至所述第二源漏区和部分所述第一源漏区。
  14. 根据权利要求13所述的元胞版图结构，其中，所述栅极结构包括位于所述沟槽底部及侧壁的栅氧化层，以及位于所述栅氧化层之上的多晶硅层。
  15. 根据权利要求13所述的元胞版图结构，其中，所述体区的掺杂离子为P型，所述第二源漏区的掺杂离子为N型。
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