WO2020132884A1 - 电容器和制备电容器的方法 - Google Patents

电容器和制备电容器的方法 Download PDF

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Publication number
WO2020132884A1
WO2020132884A1 PCT/CN2018/123575 CN2018123575W WO2020132884A1 WO 2020132884 A1 WO2020132884 A1 WO 2020132884A1 CN 2018123575 W CN2018123575 W CN 2018123575W WO 2020132884 A1 WO2020132884 A1 WO 2020132884A1
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Prior art keywords
layer
conductive
electrode
conductive layer
insulating layer
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PCT/CN2018/123575
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English (en)
French (fr)
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陆斌
沈健
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深圳市汇顶科技股份有限公司
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Priority to CN201880002918.6A priority Critical patent/CN111615751B/zh
Priority to EP18944231.2A priority patent/EP3754725A4/en
Priority to PCT/CN2018/123575 priority patent/WO2020132884A1/zh
Publication of WO2020132884A1 publication Critical patent/WO2020132884A1/zh
Priority to US17/022,225 priority patent/US11239308B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H01L29/945—Trench capacitors

Definitions

  • the embodiments of the present application relate to the field of capacitors, and more particularly, to a capacitor and a method of manufacturing the capacitor.
  • Capacitor is an important electronic component. With the continuous development of modern electronic systems to multi-function, high integration, low power consumption, and miniaturization, the existing capacitor manufacturing technology has been difficult to meet the diverse needs of various high-end applications.
  • Wafer-level three-dimensional (3D) capacitors are a new type of capacitors manufactured on silicon wafers using semiconductor processing technology in recent years. Compared to commonly used multilayer ceramic capacitors, wafer-level three-dimensional capacitors have significant advantages in terms of chip minimum thickness, frequency response, and temperature coefficient. Wafer-level 3D capacitors have a wide range of application scenarios in consumer electronics that pursue the ultimate in device volume, or in medical, automotive, and aerospace electronics that require strict device performance and reliability.
  • the embodiments of the present application provide a capacitor and a method for manufacturing the capacitor, which can increase the capacitance density of the capacitor.
  • a capacitor including: an electrode layer including a first electrode and a second electrode separated from each other; a stacked-layer structure including an n-layer dielectric layer and an n+1-layer conductive layer, the n-layer dielectric layer Forming a structure in which the conductive layer and the dielectric layer are adjacent to each other with the n+1 conductive layer, and the stacked structure forms at least two columnar structures, n is a positive integer; an interconnect structure is used to connect the n+1 layer An odd-numbered conductive layer in the conductive layer is electrically connected to the first electrode, and an even-numbered conductive layer in the n+1 conductive layer is electrically connected to the second electrode.
  • the capacitor of the embodiment of the present application adopts a stacked structure in which conductive layers and dielectric layers are alternately stacked, and is provided with a plurality of columnar structures, which can obtain a larger capacitance value in the case of a smaller device size, thereby being able to increase the capacitance value of the capacitor density.
  • the at least two columnar structures include at least one first columnar structure and at least one second columnar structure, wherein the size of the first columnar structure is larger than the size of the second columnar structure.
  • the at least two columnar structures include one first columnar structure and at least two second columnar structures.
  • the aspect ratio of the second columnar structure is greater than a predetermined threshold.
  • the predetermined threshold may be 10; the aspect ratio of the second columnar structure may be 30.
  • the interconnect structure is connected to the n+1 conductive layer at the top of the first columnar structure.
  • the interconnection structure is connected to the n+1 conductive layer at the top of the first columnar structure and below the stacked structure. This can reduce the interconnection structure provided at the first columnar structure, thereby reducing the size of the first columnar structure and further increasing the capacitance density.
  • the stacked structure is provided with a step structure, and the interconnect structure is connected to the n+1 conductive layer through the step structure.
  • the columnar structure is a rectangular parallelepiped structure or a cylindrical structure.
  • the capacitor further includes: an insulating layer disposed above and below the stacked structure.
  • the interconnection structure is a conductive via that is respectively connected to the n+1 conductive layer through the insulating layer.
  • n is greater than or equal to 5.
  • a method for manufacturing a capacitor including: preparing a plurality of holes or trenches on a substrate to obtain a first structure; and preparing a first stacked structure on the first structure, wherein The first stacked structure includes m dielectric layers and m+1 conductive layers.
  • the m dielectric layers and the m+1 conductive layers form a structure in which the conductive layer and the dielectric layer are adjacent to each other, and m is a positive integer;
  • a second laminated structure is structurally prepared, wherein the second laminated structure includes a k-layer dielectric layer and a k-layer conductive layer, the k-layer dielectric layer and the k-layer conductive layer form a conductive layer and a dielectric layer phase with each other Adjacent structure, and the first laminated structure forms a laminated structure where the conductive layer and the dielectric layer are adjacent to each other, the laminated structure forms a columnar structure at the hole or trench, k is a positive integer;
  • a second insulating layer is prepared on the second stacked structure; a first electrode and a second electrode are prepared, wherein the
  • the method for manufacturing a capacitor according to an embodiment of the present invention can obtain a stacked structure including more conductive layers and dielectric layers by increasing the stacked structure twice, which increases the capacitance value of the capacitor and utilizes multiple holes or trenches
  • the grooves form a plurality of columnar structures of a stacked structure, which can further increase the capacitance value of the capacitor, thereby improving the capacitance density of the capacitor.
  • the plurality of holes or trenches include a first hole or trench and a second hole or trench, and the size of the first hole or trench is larger than that of the second hole or trench size of.
  • the aspect ratio of the second hole or trench is greater than a predetermined threshold.
  • the method before the first stacked structure is prepared on the first structure, the method further includes: preparing an etch protection layer on the first structure; wherein, the removing Exposing the first stacked structure of the substrate includes: removing the substrate, exposing the etch protection layer, and then removing the etch protection layer, exposing the first stack structure.
  • the method before the inverting the second structure, the method further includes smoothing the surface of the first insulating layer.
  • the method further includes: bonding the surface of the first insulating layer to the carrier.
  • the method further includes: removing the carrier sheet and the bonding layer.
  • the method further includes: smoothing the surface of the second insulating layer.
  • the surface of the second insulating layer is smoothed to expose the uppermost conductive layer of the second stacked structure.
  • the method before the preparing the first electrode and the second electrode, the method further includes: preparing a first interconnection structure, wherein the first interconnection structure includes connecting to all or part of the conductive layer, respectively Conductive vias.
  • the first electrode when the first interconnect structure includes conductive vias connected to all conductive layers, the first electrode is electrically connected to the odd-numbered conductive layers through the first interconnect structure, so The second electrode is electrically connected to the even-numbered conductive layer through the first interconnect structure.
  • the method further includes: preparing a first stacked structure on the first structure After that, a second interconnection structure is prepared; wherein, the first electrode is electrically connected to the odd-numbered conductive layer through the first interconnection structure and the second interconnection structure, and the second electrode passes through the first interconnection structure Electrically connected to the even-numbered conductive layer.
  • the preparing the first interconnect structure includes: etching the second insulating layer at the first hole or trench to form a first stepped structure to expose the conductive layer to be connected; and depositing A first etch stop layer; depositing a third insulating layer on the first etch stop layer, wherein the etch resistance of the first etch stop layer is greater than the third insulating layer; for a specific conductive layer , Etching the third insulating layer to obtain a hole passing through the third insulating layer to the first etch stop layer on the first step structure; removing the first inscription in the hole An etch stop layer; depositing a metal in the hole to obtain a conductive via that connects to the specific conductive layer through the third insulating layer and the first etch stop layer.
  • the preparing the second interconnection structure includes: before the preparing the first insulating layer on the first stacked structure, etching the first stacked structure to form a second step Structure, exposing the conductive layer to be connected; depositing a second etch stop layer, wherein the etch resistance of the second etch stop layer is greater than that of the first insulating layer; in the first stack After the first insulating layer is structurally prepared, the first insulating layer is etched for a specific conductive layer to obtain the second etch stop layer passing through the first insulating layer to the second step structure A hole; removing the second etch stop layer in the hole; depositing a metal in the hole to obtain a connection through the first insulating layer and the second etch stop layer to the specific conductive layer Conductive vias and form metal interconnections between the conductive layers to be connected.
  • the method further includes: preparing a fourth insulating layer on the second interconnection structure.
  • the method further includes: obtaining an independent capacitor by cutting.
  • FIG. 1 is a schematic diagram of a capacitor according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a capacitor according to another embodiment of the present application.
  • FIG. 3 is an equivalent circuit diagram of the capacitor of the embodiment of the present application.
  • FIG. 4 is a schematic flowchart of a method for manufacturing a capacitor according to an embodiment of the present application.
  • 5-17 are schematic diagrams of the manufacturing process of the capacitor of the embodiment of the present application.
  • FIG. 1 shows a schematic diagram of a capacitor 100 according to an embodiment of the present application.
  • the capacitor 100 is a wafer-level 3D capacitor, and FIG. 1 is a cross-sectional view thereof.
  • the capacitor 100 may include a first electrode 110, a second electrode 120, a stacked structure 130 and an interconnect structure 150.
  • the first electrode 110 and the second electrode 120 are positive and negative electrodes of the capacitor 100.
  • the first electrode 110 and the second electrode 120 are separated from each other to form an electrode layer.
  • the materials of the first electrode 110 and the second electrode 120 may use various conductive materials, such as metal aluminum.
  • the stacked structure 130 includes n dielectric layers and n+1 conductive layers.
  • n is a positive integer.
  • n is 5, that is, the stacked structure 130 may include 6 conductive layers, such as the conductive layers 131-136 shown in FIG. 1, and 5 dielectric layers, such as in FIG. 1 Dielectric layers 137-141 shown.
  • the n-layer dielectric layer and the n+1-layer conductive layer form a structure in which a conductive layer and a dielectric layer are adjacent to each other, that is, the stacked structure 130 is a layer in which conductive layers and dielectric layers are alternately stacked Stacked structure. Since there is one more conductive layer, the uppermost layer and the lowermost layer of the stacked structure 130 are conductive layers.
  • the stacked structure 130 forms at least two columnar structures, for example, the first columnar structure 145 and the second columnar structure 146 as shown in FIG. 1.
  • the columnar structure may be a rectangular parallelepiped structure (including a wall structure) or a cylindrical structure.
  • the material of the dielectric layer in the stacked structure 130 may be silicon oxide, silicon nitride, metal oxide, metal nitride, etc., such as silicon dioxide, silicon nitride, or high dielectric Constant materials, including alumina, hafnium oxide, zirconia, titania, Y 2 O 3 , La 2 O 3 , HfSiO 4 , LaAlO 3 , SrTiO 3 , LaLuO 3, etc.; can also be one or more of the above materials combination.
  • the material of the conductive layer in the stacked structure 130 may be heavily doped polysilicon, carbon material, or various metals such as aluminum, tungsten, copper, titanium, tantalum, or titanium nitride, tantalum nitride Low-resistivity compounds, or stacks and combinations of the above conductive materials.
  • the interconnection structure 150 is used to electrically connect the odd-numbered conductive layers of the n+1 conductive layers to the first electrode 110, and electrically connect the even-numbered conductive layers of the n+1 conductive layers to all Narrate the second electrode 120.
  • the order of the conductive layers involved may be the order from one side to the other side of the stacked structure 140, for example, the order from top to bottom or the order from bottom to top .
  • the following uses the sequence from bottom to top as an example.
  • the conductive layers 131-136 are the first to sixth conductive layers, respectively.
  • the odd-numbered conductive layers in the conductive layers 131-136 that is, the first, third, and fifth conductive layers are electrically connected to the first electrode 110 through the interconnection structure 150
  • the even-numbered conductive layers 131-136 A conductive layer that is, the second, fourth, and sixth conductive layers are electrically connected to the second electrode 120 through the interconnection structure 150.
  • the material of the interconnection structure 150 may use various conductive materials, and may be the same as or different from the material of the conductive layer in the stacked structure 130, for example, titanium nitride and metal tungsten may be used.
  • the at least two columnar structures include at least one first columnar structure 145 and at least one second columnar structure 146, wherein the size of the first columnar structure 145 is larger than the The size of the second columnar structure 146. That is, for the capacitor 100, it includes a columnar structure of two sizes.
  • the size of the columnar structure may be the width of the columnar structure, that is, the width in the lateral direction in FIG. 1.
  • the size of the first columnar structure 145 may be 20 microns, and the size of the second columnar structure 146 may be 2 microns, but this embodiment of the present application is not limited thereto.
  • the at least two columnar structures include one first columnar structure 145 and at least two second columnar structures 146.
  • the aspect ratio of the second columnar structure 146 is greater than a predetermined threshold.
  • the predetermined threshold may be 10; the aspect ratio of the second columnar structure may be 30.
  • the use of more small-sized columnar structures with large aspect ratios can maximize the capacitance density.
  • the small-sized columnar structure is inconvenient to provide the interconnection structure 150, and therefore, a large-sized columnar structure may be used to provide the interconnection structure 150.
  • the use of a large-sized first columnar structure 145 and a plurality of small-sized second columnar structures 146 not only facilitates the setting of the interconnection structure 150, but also greatly increases the capacitance density.
  • the interconnect structure 150 is connected to the n+1 conductive layer at the top of the first columnar structure 145.
  • the interconnection structure 150 is electrically conductive with the n+1 layer at the top of the first columnar structure 145 and under the stacked structure 130 ⁇ Layer connection.
  • the interconnection structure 150 is only provided at the position of the first columnar structure 145. In this embodiment, a part of the interconnection structure 150 may be distributed under the stacked structure 130. It is easier to realize that a part of the interconnection structure is dispersedly arranged under the stacked structure 130, so that the interconnection structure provided at the first columnar structure 145 can be reduced, thereby reducing the size of the first columnar structure 145 and further increasing the capacitance density.
  • the stacked structure 130 is provided with a step structure, and the interconnection structure 150 is connected to the n+1 conductive layer through the step structure.
  • the arrangement of the step structure facilitates connection isolation between different conductive layers.
  • the capacitor 100 may further include:
  • the insulating layer 160 is disposed above and below the stacked structure 130.
  • the interconnection structure 150 is a conductive via that is respectively connected to the n+1 conductive layer through the insulating layer 160.
  • the material of the insulating layer 160 may be an organic polymer material, including polyimide (Polyimide), Parylene (Parylene), benzocyclobutene (BCB), etc.; or some inorganic materials, Including spin coated glass (Spin on glass, SOG), undoped silicon glass (Undoped Silicon (Glass, USG), silicon oxide synthesized from tetraethoxysilane (Tetraethyl Orthosilicate, TEOS), silicon oxide, nitrogen Chemicals, ceramics; can also be a combination of the above materials.
  • organic polymer material including polyimide (Polyimide), Parylene (Parylene), benzocyclobutene (BCB), etc.
  • some inorganic materials Including spin coated glass (Spin on glass, SOG), undoped silicon glass (Undoped Silicon (Glass, USG), silicon oxide synthesized from tetraethoxysilane (Tetraethyl Orthosilicate, TEOS), silicon oxide,
  • FIG. 3 shows an equivalent circuit diagram of the capacitor 100 of the embodiment of the present application.
  • the alternately stacked 6 conductive layers and 5 dielectric layers are equivalent to 5 capacitors connected in series (each dielectric layer corresponds to one capacitor).
  • these five capacitors are connected in parallel to obtain the capacitor 100 of the embodiment of the present application. Therefore, the capacitor 100 of the embodiment of the present application has a larger capacitance value.
  • the capacitor of the embodiment of the present application adopts a stacked structure in which conductive layers and dielectric layers are alternately stacked, and is provided with a plurality of columnar structures, which can obtain a larger capacitance value in the case of a smaller device size, thereby being able to increase the capacitance value of the capacitor density.
  • the capacitor of the embodiment of the present application is described above, and the method of manufacturing the capacitor of the embodiment of the present application is described below.
  • the method for manufacturing a capacitor according to an embodiment of the present application may prepare the foregoing capacitor according to the embodiment of the present application, and the related descriptions in the following embodiments and the foregoing embodiments may refer to each other.
  • FIG. 4 shows a schematic flowchart of a method 400 for manufacturing a capacitor according to an embodiment of the present application.
  • a silicon wafer is used as the substrate 510.
  • photolithography is used, for example, a photoresist is first coated on the wafer, and then exposed and developed, and then deep reactive ion etching is used (Deep Reactive Ion Etching, DRIE) process, processing multiple holes or trenches.
  • DRIE Deep Reactive Ion Etching
  • the plurality of holes or grooves include a first hole or groove and a second hole or groove, and the size of the first hole or groove is larger than the size of the second hole or groove. That is to say, the plurality of holes or grooves include large or small holes or grooves of two sizes.
  • the aspect ratio of the second hole or trench is greater than a predetermined threshold.
  • the opening width of the first hole or trench may be 20 microns and the depth may be 100 microns
  • the opening width of the second hole or trench may be 2 microns and the depth may be 50 microns.
  • Two sizes of holes or grooves can be made simultaneously or separately.
  • a layer of silicon dioxide may be grown on the surface of the hole or trench by a thermal oxidation process to serve as a corrosion protection layer 610 when the substrate is subsequently removed.
  • the first stacked structure includes m dielectric layers and m+1 conductive layers.
  • the m dielectric layers and the m+1 conductive layers form a structure where the conductive layer and the dielectric layer are adjacent to each other, and m is positive Integer.
  • the first stacked structure may be formed by alternately depositing conductive layers and dielectric layers.
  • the conductive layer can be deposited by atomic layer deposition (Atomic layer deposition, ALD), physical vapor deposition (Physical Vapor Deposition (PVD), chemical vapor deposition (Chemical Vapor Deposition, CVD), organic metal chemical vapor deposition, electroplating, etc.).
  • ALD atomic layer deposition
  • PVD Physical Vapor Deposition
  • CVD chemical vapor deposition
  • organic metal chemical vapor deposition organic metal chemical vapor deposition, electroplating, etc.
  • the dielectric layer can be deposited by thermal oxidation, ALD, PVD, CVD and other methods.
  • a low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) process may be used to deposit a layer of 200 nm thick heavily doped polysilicon as the conductive layer 133 on the surface of the corrosion protection layer 610; ALD is used; Process, deposit a layer of aluminum oxide with a thickness of 50 nm on the surface of the conductive layer 133 as the dielectric layer 138; use LPCVD process to deposit a layer of heavily doped polysilicon with a thickness of 200 nm on the surface of the dielectric layer 138 as the conductive layer 132; with the ALD process, A layer of aluminum oxide with a thickness of 50 nm is deposited on the surface of the conductive layer 132 as the dielectric layer 137; a layer of heavily doped polysilicon with a thickness of 500 nm is deposited on the surface of the dielectric layer 137 as the conductive layer 131 by the LPCVD process.
  • LPCVD Low Pressure Chemical Vapor Deposition
  • a CVD process may be used to deposit a thick layer of silicon dioxide on the surface of the conductive layer 131 as the first insulating layer 161 to fill the large holes or trenches.
  • the surface of the first insulating layer 161 may be smoothed.
  • CMP chemical mechanical polishing
  • the surface of the first insulating layer 161 may also be bonded to the carrier 910, and the bonding layer 920 is between the first insulating layer 161 and the carrier 910 in FIG. 9.
  • the surface of the first insulating layer 161 may be bonded on the carrier 910 through a bonding process, for example, glass frit bonding.
  • the substrate can be removed by wet etching, or a combination of wet etching and dry etching.
  • the second stacked structure includes a k-layer dielectric layer and a k-layer conductive layer, the k-layer dielectric layer and the k-layer conductive layer form a structure in which a conductive layer and a dielectric layer are adjacent to each other, and are stacked with the first
  • the layer structure forms a stacked structure in which the conductive layer and the dielectric layer are adjacent to each other, the stacked structure forms a columnar structure at the hole or trench, and k is a positive integer.
  • the preparation method of the second laminated structure is similar to that of the first laminated structure.
  • an ALD process may be used to deposit a 50-nm aluminum oxide layer on the surface of the conductive layer 133 as the dielectric layer 139; an LPCVD process is used to deposit a 200-nm-thick re-doped layer on the surface of the dielectric layer 139 Heteropolysilicon is used as the conductive layer 134; ALD process is used to deposit a 50-nm-thick aluminum oxide layer on the surface of the conductive layer 134 as the dielectric layer 140; LPCVD process is used to deposit a 200-nm-thick layer of heavily doped polysilicon on the surface of the dielectric layer 140 As the conductive layer 135; using the ALD process, deposit a layer of 50 nm aluminum oxide on the surface of the conductive layer 135 as the dielectric layer 141; use the LPCVD process, deposit a layer of 200 nm thick heavily doped polysilicon on the surface of the dielectric layer 141 as the conductive Layer 136.
  • a thick layer of silicon dioxide may be deposited on the surface of the conductive layer 136 as the second insulating layer 162 using a CVD process.
  • the surface of the second insulating layer 162 may be smoothed.
  • the surface of the second insulating layer 162 can be smoothed using a CMP process to obtain the structure shown in FIG. 12.
  • the surface of the second insulating layer 162 is smoothed to expose the uppermost conductive layer 136 of the second stacked structure. This can save subsequent etching steps and reduce costs.
  • the first interconnect structure may be prepared in the following manner.
  • the second insulating layer 162 at the first hole or trench is etched to form a first step structure to expose the conductive layer to be connected.
  • a multi-step lithography process may be used to form a step above the position of the first hole or trench to expose each conductive layer.
  • a first etch stop layer is deposited.
  • a layer of silicon nitride can be deposited as the first etch stop layer 1510 using a CVD process.
  • a third insulating layer 163 is deposited on the first etch stop layer 1510.
  • the etch resistance of the first etch stop layer 1510 is greater than that of the third insulating layer 163.
  • a CVD process may be used to deposit a thick layer of silicon dioxide on the first etch stop layer 1510 as the third insulating layer 163.
  • the third insulating layer 163 is etched to obtain a hole that passes through the third insulating layer 163 to the first etch stop layer 1510 on the first step structure.
  • a via hole penetrating the third insulating layer 163 may be opened at a position corresponding to each step through a photolithography process. Since the material of the first etch stop layer 1510 is more resistant to etching than the third insulating layer 163, the bottom of each via hole can stay on the first etch stop layer 1510 of the corresponding step.
  • the first etch stop layer in the hole is removed.
  • the first etch stop layer exposed at the bottom of the hole can be removed by a dry or wet process.
  • a metal is deposited in the hole to obtain a conductive via that is connected to a specific conductive layer through the third insulating layer 163 and the first etch stop layer 1510.
  • a layer of titanium nitride can be deposited in the hole and filled with metal tungsten.
  • a planarization process is used to remove excess conductive material and insulating material on the surface to obtain the structure shown in FIG. 16.
  • the first electrode is electrically connected to the odd-numbered conductive layer in the m+k+1 conductive layer
  • the second electrode is electrically connected to the even-numbered conductive layer in the m+k+1 conductive layer.
  • a layer of metallic aluminum can be deposited using the PVD process, and the first electrode 110 and the second electrode 120 can be formed using photolithography, where the first electrode 110 communicates with the conductive layer 131, the conductive layer 133 and the conductive layer 135 ; The second electrode 120 communicates with the conductive layer 132, the conductive layer 134 and the conductive layer 136.
  • the thickness of the device is reduced.
  • the bonding layer and the carrier sheet can be removed, and after removing the bonding layer and the carrier sheet, a capacitor as shown in FIG. 1 can be obtained.
  • the carrier when the carrier and the bonding layer cannot be removed, the carrier can be thinned.
  • the first electrode 110 is electrically connected to the odd-numbered conductive layer through the first interconnection structure
  • the second electrode 120 is electrically connected to the even-numbered conductive layer through the first interconnection structure .
  • the first interconnect structure and the second interconnect structure including conductive vias respectively connected to part of the conductive layers may be prepared on both sides of the stacked structure.
  • the second interconnect structure may be prepared.
  • the second interconnect structure may be prepared in the following manner. It should be understood that, in addition to the following description, reference may be made to the preparation method of the first interconnect structure.
  • the first stacked structure is etched to form a second stepped structure to expose the conductive layer to be connected.
  • a second etch stop layer 1520 is deposited.
  • the etching resistance of the second etch stop layer 1520 is greater than that of the first insulating layer 161.
  • the first insulating layer 161 is etched to obtain the second etching stop through the first insulating layer 161 to the second step structure Layer 1520 holes.
  • the second etch stop layer in the hole is removed.
  • a fourth insulating layer 164 may also be prepared on the second interconnect structure.
  • both the first interconnect structure and the second interconnect structure include conductive vias respectively connected to part of the conductive layer, and the first electrode 110 is electrically connected through the first interconnect structure and the second interconnect structure In the odd-numbered conductive layer, the second electrode 120 is electrically connected to the even-numbered conductive layer through the first interconnect structure.
  • the method for manufacturing a capacitor according to an embodiment of the present invention can obtain a stacked structure including more conductive layers and dielectric layers by increasing the stacked structure twice, which increases the capacitance value of the capacitor and utilizes multiple holes or trenches
  • the grooves form a plurality of columnar structures of a stacked structure, which can further increase the capacitance value of the capacitor, thereby improving the capacitance density of the capacitor.

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Abstract

本申请实施例公开了一种电容器和制备电容器的方法。所述电容器包括：电极层，包括相互分离的第一电极和第二电极；叠层结构，包括n层电介质层和n+1层导电层，所述n层电介质层和所述n+1层导电层形成导电层与电介质层彼此相邻的结构，所述叠层结构形成至少两个柱状结构，n为正整数；互联结构，用于将所述n+1层导电层中的奇数层导电层电连接至所述第一电极，将所述n+1层导电层中的偶数层导电层电连接至所述第二电极。本申请实施例的技术方案，能够提高电容器的容值密度。

Description

电容器和制备电容器的方法 技术领域
本申请实施例涉及电容器领域，并且更具体地，涉及一种电容器和制备电容器的方法。
背景技术
电容器是一种重要的电子元件。随着现代电子系统不断向多功能、高集成、低功耗、微型化发展，现有的电容器制造技术已经难以满足各类高端应用的多样化需求。
晶圆级三维(3D)电容器是近年来出现的一种利用半导体加工技术在硅晶圆上制造的新型电容器。相比于常用的多层陶瓷电容器，晶圆级三维电容器在芯片的最小厚度、频率响应、温度系数等方面具有显著的优点。在对器件体积追求极致的消费类电子，或者对器件性能和可靠性要求严苛的医疗、车载、航天电子等领域，晶圆级3D电容器具有十分广泛的应用场景。
然而，目前晶圆级3D电容器的容值密度仍然有限，如何提高电容器的容值密度，成为一个亟待解决的技术问题。
发明内容
本申请实施例提供了一种电容器和制备电容器的方法，能够提高电容器的容值密度。
第一方面，提供了一种电容器，包括：电极层，包括相互分离的第一电极和第二电极；叠层结构，包括n层电介质层和n+1层导电层，所述n层电介质层和所述n+1层导电层形成导电层与电介质层彼此相邻的结构，所述叠层结构形成至少两个柱状结构，n为正整数；互联结构，用于将所述n+1层导电层中的奇数层导电层电连接至所述第一电极，将所述n+1层导电层中的偶数层导电层电连接至所述第二电极。
本申请实施例的电容器，采用导电层与电介质层交替堆叠的叠层结构，并设置多个柱状结构，能够在较小器件尺寸的情况下得到较大的电容值，从而能够提高电容器的容值密度。
在一些可能的实现方式中，所述至少两个柱状结构包括至少一个第一柱 状结构和至少一个第二柱状结构，其中，所述第一柱状结构的尺寸大于所述第二柱状结构的尺寸。
在一些可能的实现方式中，所述至少两个柱状结构包括一个所述第一柱状结构和至少两个所述第二柱状结构。
采用一个大尺寸的第一柱状结构和多个小尺寸的第二柱状结构，既便于设置互联结构，又能较大限度的提高容值密度。
在一些可能的实现方式中，所述第二柱状结构的深宽比大于预定阈值。例如，所述预定阈值可以为10；所述第二柱状结构的深宽比可以为30。
在一些可能的实现方式中，所述互联结构在所述第一柱状结构的顶端与所述n+1层导电层连接。
在一些可能的实现方式中，所述互联结构在所述第一柱状结构的顶端以及所述叠层结构的下方与所述n+1层导电层连接。这样可以减少第一柱状结构处设置的互联结构，从而可以减小第一柱状结构的尺寸，进一步提高容值密度。
在一些可能的实现方式中，所述叠层结构设置有台阶结构，所述互联结构通过所述台阶结构与所述n+1层导电层连接。
在一些可能的实现方式中，所述柱状结构为长方体结构或圆柱体结构。
在一些可能的实现方式中，所述电容器还包括：绝缘层，设置于所述叠层结构的上方以及下方。
在一些可能的实现方式中，所述互联结构为穿过所述绝缘层分别连接至所述n+1层导电层的导电通孔。
在一些可能的实现方式中，n大于或等于5。
第二方面，提供了一种制备电容器的方法，包括：在衬底上制备多个孔或沟槽，得到第一结构；在所述第一结构上制备第一叠层结构，其中，所述第一叠层结构包括m层电介质层和m+1层导电层，所述m层电介质层和所述m+1层导电层形成导电层与电介质层彼此相邻的结构，m为正整数；在所述第一叠层结构上制备第一绝缘层，得到第二结构；将所述第二结构翻转；去除所述衬底，露出所述第一叠层结构；在所述第一叠层结构上制备第二叠层结构，其中，所述第二叠层结构包括k层电介质层和k层导电层，所述k层电介质层和所述k层导电层形成导电层与电介质层彼此相邻的结构，且与所述第一叠层结构形成导电层与电介质层彼此相邻的叠层结构，所述叠层结 构在孔或沟槽处形成柱状结构，k为正整数；在所述第二叠层结构上制备第二绝缘层；制备第一电极和第二电极，其中，所述第一电极电连接至m+k+1层导电层中的奇数层导电层，所述第二电极电连接至所述m+k+1层导电层中的偶数层导电层。
本发明实施例的制备电容器的方法，通过两次制备叠层结构的方式，可以得到包括较多导电层和电介质层的叠层结构，增大电容器的电容值，并且，利用多个孔或沟槽形成叠层结构的多个柱状结构，可以进一步增大电容器的电容值，从而能够提高电容器的容值密度。
在一些可能的实现方式中，所述多个孔或沟槽包括第一孔或沟槽以及第二孔或沟槽，所述第一孔或沟槽的尺寸大于所述第二孔或沟槽的尺寸。
在一些可能的实现方式中，所述第二孔或沟槽的深宽比大于预定阈值。
在一些可能的实现方式中，在所述在所述第一结构上制备第一叠层结构之前，所述方法还包括：在所述第一结构上制备刻蚀保护层；其中，所述去除所述衬底，露出所述第一叠层结构，包括：去除所述衬底，露出所述刻蚀保护层，再去除所述刻蚀保护层，露出所述第一叠层结构。
在一些可能的实现方式中，在所述将所述第二结构翻转之前，所述方法还包括：将所述第一绝缘层的表面磨平。
在一些可能的实现方式中，在所述将所述第二结构翻转之后，所述方法还包括：将所述第一绝缘层的表面键合到载片上。
在一些可能的实现方式中，在所述制备第一电极和第二电极之后，所述方法还包括：去除所述载片和键合层。
在一些可能的实现方式中，在所述在所述第二叠层结构上制备第二绝缘层之后，所述方法还包括：将所述第二绝缘层的表面磨平。
在一些可能的实现方式中，所述第二绝缘层的表面磨平至露出所述第二叠层结构最上方的导电层。
在一些可能的实现方式中，在所述制备第一电极和第二电极之前，所述方法还包括：制备第一互联结构，其中，所述第一互联结构包括分别连接至全部或部分导电层的导电通孔。
在一些可能的实现方式中，在所述第一互联结构包括分别连接至全部导电层的导电通孔时，所述第一电极通过所述第一互联结构电连接所述奇数层导电层，所述第二电极通过所述第一互联结构电连接至所述偶数层导电层。
在一些可能的实现方式中，在所述第一互联结构包括分别连接至部分导电层的导电通孔时，所述方法还包括：在所述在所述第一结构上制备第一叠层结构之后，制备第二互联结构；其中，所述第一电极通过所述第一互联结构和所述第二互联结构电连接所述奇数层导电层，所述第二电极通过所述第一互联结构电连接至所述偶数层导电层。
在一些可能的实现方式中，所述制备第一互联结构包括：刻蚀所述第一孔或沟槽处的所述第二绝缘层，形成第一台阶结构，露出待连接的导电层；沉积第一刻蚀停止层；在所述第一刻蚀停止层上沉积第三绝缘层，其中，所述第一刻蚀停止层的耐刻蚀性大于所述第三绝缘层；针对特定导电层，刻蚀所述第三绝缘层，得到穿过所述第三绝缘层至所述第一台阶结构上的所述第一刻蚀停止层的孔；去除所述孔内的所述第一刻蚀停止层；在所述孔内沉积金属，得到穿过所述第三绝缘层和所述第一刻蚀停止层连接至所述特定导电层的导电通孔。
在一些可能的实现方式中，所述制备第二互联结构包括：在所述在所述第一叠层结构上制备第一绝缘层之前，刻蚀所述第一叠层结构，形成第二台阶结构，露出待连接的导电层；沉积第二刻蚀停止层，其中，所述第二刻蚀停止层的耐刻蚀性大于所述第一绝缘层；在所述在所述第一叠层结构上制备第一绝缘层之后，针对特定导电层，刻蚀所述第一绝缘层，得到穿过所述第一绝缘层至所述第二台阶结构上的所述第二刻蚀停止层的孔；去除所述孔内的所述第二刻蚀停止层；在所述孔内沉积金属，得到穿过所述第一绝缘层和所述第二刻蚀停止层连接至所述特定导电层的导电通孔，并形成待连接导电层之间的金属互联。
在一些可能的实现方式中，在所述制备第二互联结构之后，所述方法还包括：在所述第二互联结构上制备第四绝缘层。
在一些可能的实现方式中，所述方法还包括：通过切割得到独立的电容器。
附图说明
图1是本申请一个实施例的电容器的示意图。
图2是本申请另一个实施例的电容器的示意图。
图3是本申请实施例的电容器的等效电路图。
图4是本申请实施例的制备电容器的方法的示意性流程图。
图5-17是本申请实施例的电容器的制备过程的示意图。
具体实施方式
下面将结合附图，对本申请实施例中的技术方案进行描述。
图1示出了本申请一个实施例的电容器100的示意图。
电容器100为晶圆级3D电容器，图1为其截面图。
如图1所示，电容器100可以包括第一电极110，第二电极120，叠层结构130和互联结构150。
第一电极110和第二电极120为电容器100的正负两个电极。第一电极110和第二电极120相互分离，形成电极层。第一电极110和第二电极120的材料可以采用各种导电材料，例如金属铝。
叠层结构130，包括n层电介质层和n+1层导电层。n为正整数。可选地，在一个实施例中，n为5，即，叠层结构130可以包括6层导电层，例如图1中示出的导电层131-136，以及5层电介质层，例如图1中示出的电介质层137-141。
如图1所示，所述n层电介质层和所述n+1层导电层形成导电层与电介质层彼此相邻的结构，即，所述叠层结构130为导电层与电介质层交替堆叠的叠层结构。由于导电层多一层，所述叠层结构130的最上层和最下层为导电层。
另外，所述叠层结构130形成至少两个柱状结构，例如，如图1中所示的第一柱状结构145和第二柱状结构146。
可选地，所述柱状结构可以为长方体结构(包括墙体结构)或圆柱体结构。
柱状结构的存在，相当于增加了电容器的极板面积，因此有利于提高电容器的电容值。
可选地，叠层结构130中的电介质层的材料可以是硅的氧化物，硅的氮化物，金属的氧化物，金属的氮化物等，例如二氧化硅，氮化硅，或者高介电常数材料，包括氧化铝，氧化铪，氧化锆，二氧化钛，Y 2O 3，La 2O 3，HfSiO 4，LaAlO 3，SrTiO 3，LaLuO 3等；也可以是上述一种材料或多种材料的组合。
可选地，叠层结构130中的导电层的材料可以是重掺杂多晶硅，碳材料， 或者是铝、钨、铜、钛、钽等各类金属，也可以是氮化钛、氮化钽等低电阻率的化合物，或者是上述几种导电材料的叠层、组合。
互联结构150，用于将所述n+1层导电层中的奇数层导电层电连接至所述第一电极110，将所述n+1层导电层中的偶数层导电层电连接至所述第二电极120。
应理解，在本申请实施例中，所涉及的导电层的顺序可以为从叠层结构140的一侧到另一侧的顺序，例如，从上到下的顺序或者是从下到上的顺序。为了便于描述，以下以从下到上的顺序为例进行说明。例如，图1中，导电层131-136分别为第1-6层导电层。
如图1所示，导电层131-136中的奇数层导电层，即第1，3，5层导电层通过互联结构150电连接至所述第一电极110，导电层131-136中的偶数层导电层，即第2，4，6层导电层通过互联结构150电连接至所述第二电极120。
互联结构150的材料可以采用各种导电材料，可以与叠层结构130中的导电层的材料相同或不同，例如，可以采用氮化钛和金属钨。
可选地，在本申请一个实施例中，所述至少两个柱状结构包括至少一个第一柱状结构145和至少一个第二柱状结构146，其中，所述第一柱状结构145的尺寸大于所述第二柱状结构146的尺寸。也就是说，对于电容器100，其包括两种尺寸的柱状结构。
在本申请实施例中，柱状结构的尺寸可以为柱状结构的宽度，即图1中横向的宽度。
例如，第一柱状结构145的尺寸可以为20微米，第二柱状结构146的尺寸可以为2微米，但本申请实施例对此并不限定。
可选地，在本申请一个实施例中，如图1所示，所述至少两个柱状结构包括一个所述第一柱状结构145和至少两个所述第二柱状结构146。
可选地，所述第二柱状结构146的深宽比大于预定阈值。例如，所述预定阈值可以为10；所述第二柱状结构的深宽比可以为30。
从提高容值密度的角度来说，采用较多深宽比大的小尺寸柱状结构能够最大限度的提高容值密度。然而，小尺寸柱状结构不便于设置互联结构150，因此，可以采用一个大尺寸的柱状结构设置互联结构150。也就是说，采用一个大尺寸的第一柱状结构145和多个小尺寸的第二柱状结构146，既便于 设置互联结构150，又能较大限度的提高容值密度。
可选地，在本申请一个实施例中，如图1所示，所述互联结构150在所述第一柱状结构145的顶端与所述n+1层导电层连接。
可选地，在本申请一个实施例中，如图2所示，所述互联结构150在所述第一柱状结构145的顶端以及所述叠层结构130的下方与所述n+1层导电层连接。
在前述实施例中，互联结构150仅设置在第一柱状结构145的位置处。在本实施例中，可以将互联结构150的一部分分散设置到所述叠层结构130的下方。在所述叠层结构130的下方分散设置一部分互联结构较容易实现，这样可以减少第一柱状结构145处设置的互联结构，从而可以减小第一柱状结构145的尺寸，进一步提高容值密度。
应理解，除了互联结构150的设置不同外，图2和图1的其他设置相同，为了简洁，不再赘述。
如图1和图2所示，所述叠层结构130设置有台阶结构，所述互联结构150通过所述台阶结构与所述n+1层导电层连接。台阶结构的设置，便于不同导电层之间的连接隔离。
可选地，在本申请一个实施例中，如图1和图2所示，所述电容器100还可以包括：
绝缘层160，设置于所述叠层结构130的上方以及下方。
应理解，叠层结构的上方以及下方是相对于叠层结构的整体而言的，也就是说，叠层结构的上方指叠层结构顶层的上方，叠层结构的下方指叠层结构底层的下方。
在这种情况下，所述互联结构150为穿过所述绝缘层160分别连接至所述n+1层导电层的导电通孔。
如图1和图2所示，通过在绝缘层160中设置导电通孔，可以实现第一电极110和第二电极120到相应导电层的电连接。
可选地，绝缘层160的材料可以是有机的聚合物材料，包括聚酰亚胺(Polyimide)，帕里纶(Parylene)，苯并环丁烯(BCB)等；也可以是一些无机材料，包括旋转涂布玻璃(Spin on glass，SOG)，未掺杂硅玻璃(Undoped Silicon Glass，USG)，由四乙氧基硅烷(Tetraethyl Orthosilicate，TEOS)合成的硅氧化物，硅的氧化物、氮化物，陶瓷；还可以是上述材料的组合。
图3示出了本申请实施例的电容器100的等效电路图。
以n为5为例，如图3所示，交替堆叠的6层导电层和5层电介质层等效于5个互相串联的电容器(每层电介质层对应一个电容器)。在采用本申请实施例的互联结构150后，这5个电容器并联，得到本申请实施例的电容器100。因此，本申请实施例的电容器100具有较大的电容值。
本申请实施例的电容器，采用导电层与电介质层交替堆叠的叠层结构，并设置多个柱状结构，能够在较小器件尺寸的情况下得到较大的电容值，从而能够提高电容器的容值密度。
以上描述了本申请实施例的电容器，下面描述本申请实施例的制备电容器的方法。本申请实施例的制备电容器的方法可以制备前述本申请实施例的电容器，下述实施例和前述实施例中的相关描述可以相互参考。
图4示出了本申请实施例的制备电容器的方法400的示意性流程图。
401，在衬底上制备多个孔或沟槽，得到第一结构。
如图5所示，选用硅晶圆作为衬底510，在衬底510正面，利用光刻，例如先在晶圆上涂覆光刻胶，再经过曝光、显影，然后利用深反应离子刻蚀(Deep Reactive Ion Etching，DRIE)工艺，加工出多个孔或沟槽。
可选地，所述多个孔或沟槽包括第一孔或沟槽以及第二孔或沟槽，所述第一孔或沟槽的尺寸大于所述第二孔或沟槽的尺寸。也就是说，所述多个孔或沟槽包括一大一小两种尺寸的孔或沟槽。
可选地，所述第二孔或沟槽的深宽比大于预定阈值。
作为一个举例，第一孔或沟槽的开口宽度可以为20微米，深度可以为100微米，第二孔或沟槽的开口宽度可以为2微米，深度可以为50微米。
两种尺寸的孔或沟槽，可以同时制作，也可以分开制作。
402，在所述第一结构上制备刻蚀保护层。
例如，如图6所示，可以利用热氧化工艺，在孔或沟槽表面生长一层二氧化硅，作为后续去除衬底时的腐蚀保护层610。
403，在所述第一结构上制备第一叠层结构。
所述第一叠层结构包括m层电介质层和m+1层导电层，所述m层电介质层和所述m+1层导电层形成导电层与电介质层彼此相邻的结构，m为正整数。
所述第一叠层结构可以通过交替沉积导电层和电介质层的方式形成。
导电层可以采用原子层沉积(Atomic layer deposition，ALD)、物理气相沉积(Physical Vapor Deposition，PVD)、化学气相沉积(Chemical Vapor Deposition，CVD)、有机金属化学气相沉积、电镀等方法沉积。电介质层可以采用热氧化法、ALD、PVD、CVD等方法沉积。
例如，如图7所示，可以采用低压力化学气相沉积(Low Pressure Chemical Vapor Deposition，LPCVD)工艺，在腐蚀保护层610表面沉积一层200纳米厚的重掺杂多晶硅作为导电层133；用ALD工艺，在导电层133表面沉积一层50纳米厚的氧化铝作为电介质层138；用LPCVD工艺，在电介质层138表面沉积一层200纳米厚的重掺杂多晶硅作为导电层132；用ALD工艺，在导电层132表面沉积一层50纳米厚的氧化铝作为电介质层137；用LPCVD工艺，在电介质层137表面沉积一层500纳米厚的重掺杂多晶硅作为导电层131。最后，得到如图7所示结构。可选地，小孔或沟槽可被填满，大或沟槽未被填满。
404，在所述第一叠层结构上制备第一绝缘层，得到第二结构。
例如，如图8所示，可以采用CVD工艺，在导电层131表面沉积一层厚的二氧化硅作为第一绝缘层161，将大孔或沟槽填满。
可选地，还可以将所述第一绝缘层161的表面磨平。例如，可以利用化学机械抛光(Chemical Mechanical Polishing，CMP)工艺，将第一绝缘层161表面磨平，得到如图8所示的第二结构。
405，将所述第二结构翻转。
可选地，如图9所示，还可以将所述第一绝缘层161的表面键合到载片910上，图9中第一绝缘层161和载片910之间为键合层920。
例如，可以通过键合工艺，例如，玻璃浆料键合(glass frit bonding)，将第一绝缘层161的表面，键合在载片910上。
406，去除所述衬底，露出所述第一叠层结构。
所述衬底可以利用湿法腐蚀，或者湿法腐蚀与干法刻蚀结合的工艺去除。
例如，可以先用80摄氏度的高浓度KOH溶液，去除衬底，露出刻蚀保护层；再用氢氟酸溶液，去除刻蚀保护层，露出第一叠层结构的导电层133，如图10所示。
407，在所述第一叠层结构上制备第二叠层结构。
所述第二叠层结构包括k层电介质层和k层导电层，所述k层电介质层和所述k层导电层形成导电层与电介质层彼此相邻的结构，且与所述第一叠层结构形成导电层与电介质层彼此相邻的叠层结构，所述叠层结构在孔或沟槽处形成柱状结构，k为正整数。
所述第二叠层结构的制备方式与所述第一叠层结构类似。
例如，如图11所示，可以采用ALD工艺，在导电层133表面沉积一层50纳米后的氧化铝作为电介质层139；用LPCVD工艺，在电介质层139表面沉积一层200纳米厚的重掺杂多晶硅作为导电层134；用ALD工艺，在导电层134表面沉积一层50纳米厚的氧化铝作为电介质层140；用LPCVD工艺，在电介质层140表面沉积一层200纳米厚的重掺杂多晶硅作为导电层135；用ALD工艺，在导电层135表面沉积一层50纳米后的氧化铝作为电介质层141；用LPCVD工艺，在电介质层141表面沉积一层200纳米厚的重掺杂多晶硅作为导电层136。最后，得到如图11所示结构。
408，在所述第二叠层结构上制备第二绝缘层。
例如，如图12所示，可以采用CVD工艺，在导电层136表面沉积一层厚的二氧化硅作为第二绝缘层162。
可选地，还可以将所述第二绝缘层162的表面磨平。例如，可以利用CMP工艺，将第二绝缘层162的表面磨平，得到如图12所示的结构。
可选地，作为另一个实施例，如图13所示，所述第二绝缘层162的表面磨平至露出所述第二叠层结构最上方的导电层136。这样可以节省后续的刻蚀步骤，降低成本。
409，制备第一互联结构。
可选地，第一互联结构可以采用下述方式制备。
刻蚀所述第一孔或沟槽处的所述第二绝缘层162，形成第一台阶结构，露出待连接的导电层。例如，如图14所示，可以利用多步光刻工艺，在所述第一孔或沟槽的位置上方形成台阶，露出各个导电层。
沉积第一刻蚀停止层。例如，如图15所示，可以利用CVD工艺，沉积一层氮化硅作为第一刻蚀停止层1510。
在所述第一刻蚀停止层1510上沉积第三绝缘层163。所述第一刻蚀停止层1510的耐刻蚀性大于所述第三绝缘层163。例如，可以利用CVD工艺，在第一刻蚀停止层1510上沉积一层厚的二氧化硅作为第三绝缘层163。
针对特定导电层，刻蚀所述第三绝缘层163，得到穿过所述第三绝缘层163至所述第一台阶结构上的所述第一刻蚀停止层1510的孔。例如，可以通过光刻工艺，在每个台阶对应的位置，打开穿透第三绝缘层163的导通孔。由于第一刻蚀停止层1510的材料相对于第三绝缘层163更耐刻蚀，因此可以将每个导通孔的底部停留在相应台阶的第一刻蚀停止层1510上。
去除所述孔内的所述第一刻蚀停止层。例如，可以利用干法或者湿法工艺去除孔底部露出的第一刻蚀停止层。
在所述孔内沉积金属，得到穿过所述第三绝缘层163和所述第一刻蚀停止层1510连接至特定导电层的导电通孔。例如，可以在孔中沉积一层氮化钛并填充金属钨。最后利用平坦化工艺去除表面多余的导电材料和绝缘材料，得到如图16所示结构。
410，制备第一电极和第二电极。
所述第一电极电连接至m+k+1层导电层中的奇数层导电层，所述第二电极电连接至所述m+k+1层导电层中的偶数层导电层。
例如，如图17所示，可以利用PVD工艺，沉积一层金属铝，利用光刻形成第一电极110和第二电极120，其中第一电极110连通导电层131，导电层133和导电层135；第二电极120连通导电层132，导电层134和导电层136。
411，减薄所述载片或者去除所述载片和键合层。
通过该步骤降低器件的厚度。一种实现方式中，可以去除键合层以及载片，去除键合层以及载片后，得到如图1所示的电容器。另一种实现方式中，在不能去除载片和键合层的情况下，可以对载片进行减薄处理。
在上述实施例中，通过制备包括分别连接至全部导电层的导电通孔的第一互联结构，可以得到如图1所示的电容器。在这种情况下，所述第一电极110通过所述第一互联结构电连接所述奇数层导电层，所述第二电极120通过所述第一互联结构电连接至所述偶数层导电层。
可选地，对于如图2所示的电容器，可以通过在叠层结构的两面分别制备包括分别连接至部分导电层的导电通孔的第一互联结构和第二互联结构得到。
具体地，可以在制备第一叠层结构之后，制备第二互联结构。
可选地，第二互联结构可以采用下述方式制备。应理解，除以下描述外， 其他可参考第一互联结构的制备方式。
在制备第一绝缘层161之前，刻蚀所述第一叠层结构，形成第二台阶结构，露出待连接的导电层。
沉积第二刻蚀停止层1520。
所述第二刻蚀停止层1520的耐刻蚀性大于所述第一绝缘层161。
在制备第一绝缘层161之后，针对特定导电层，刻蚀所述第一绝缘层161，得到穿过所述第一绝缘层161至所述第二台阶结构上的所述第二刻蚀停止层1520的孔。
去除所述孔内的所述第二刻蚀停止层。
在所述孔内沉积金属，得到穿过所述第一绝缘层161和所述第二刻蚀停止层1520连接至特定导电层的导电通孔，并形成待连接导电层之间的金属互联。
可选地，在制备第二互联结构之后，还可以在所述第二互联结构上制备第四绝缘层164。
在本实施例中，第一互联结构和第二互联结构均包括分别连接至部分导电层的导电通孔，所述第一电极110通过所述第一互联结构和所述第二互联结构电连接所述奇数层导电层，所述第二电极120通过所述第一互联结构电连接至所述偶数层导电层。
通过上述方式可以在一个晶圆上制备多个电容器，再通过切割得到独立的电容器。
本发明实施例的制备电容器的方法，通过两次制备叠层结构的方式，可以得到包括较多导电层和电介质层的叠层结构，增大电容器的电容值，并且，利用多个孔或沟槽形成叠层结构的多个柱状结构，可以进一步增大电容器的电容值，从而能够提高电容器的容值密度。
应理解，本申请实施例中的具体的例子只是为了帮助本领域技术人员更好地理解本申请实施例，而非限制本申请实施例的范围。
应理解，在本申请实施例和所附权利要求书中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请实施例。例如，在本申请实施例和所附权利要求书中所使用的单数形式的“一种”、“上述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限 于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (27)

  1. 一种电容器，其特征在于，包括：
    电极层，包括相互分离的第一电极和第二电极；
    叠层结构，包括n层电介质层和n+1层导电层，所述n层电介质层和所述n+1层导电层形成导电层与电介质层彼此相邻的结构，所述叠层结构形成至少两个柱状结构，n为正整数；
    互联结构，用于将所述n+1层导电层中的奇数层导电层电连接至所述第一电极，将所述n+1层导电层中的偶数层导电层电连接至所述第二电极。
  2. 根据权利要求1所述的电容器，其特征在于，所述至少两个柱状结构包括至少一个第一柱状结构和至少一个第二柱状结构，其中，所述第一柱状结构的尺寸大于所述第二柱状结构的尺寸。
  3. 根据权利要求2所述的电容器，其特征在于，所述至少两个柱状结构包括一个所述第一柱状结构和至少两个所述第二柱状结构。
  4. 根据权利要求2或3所述的电容器，其特征在于，所述第二柱状结构的深宽比大于预定阈值。
  5. 根据权利要求2至4中任一项所述的电容器，其特征在于，所述互联结构在所述第一柱状结构的顶端与所述n+1层导电层连接。
  6. 根据权利要求2至4中任一项所述的电容器，其特征在于，所述互联结构在所述第一柱状结构的顶端以及所述叠层结构的下方与所述n+1层导电层连接。
  7. 根据权利要求1至6中任一项所述的电容器，其特征在于，所述叠层结构设置有台阶结构，所述互联结构通过所述台阶结构与所述n+1层导电层连接。
  8. 根据权利要求1至7中任一项所述的电容器，其特征在于，所述柱状结构为长方体结构或圆柱体结构。
  9. 根据权利要求1至8中任一项所述的电容器，其特征在于，所述电容器还包括：
    绝缘层，设置于所述叠层结构的上方以及下方。
  10. 根据权利要求9所述的电容器，其特征在于，所述互联结构为穿过所述绝缘层分别连接至所述n+1层导电层的导电通孔。
  11. 根据权利要求1至9中任一项所述的电容器，其特征在于，n大于 或等于5。
  12. 一种制备电容器的方法，其特征在于，包括：
    在衬底上制备多个孔或沟槽，得到第一结构；
    在所述第一结构上制备第一叠层结构，其中，所述第一叠层结构包括m层电介质层和m+1层导电层，所述m层电介质层和所述m+1层导电层形成导电层与电介质层彼此相邻的结构，m为正整数；
    在所述第一叠层结构上制备第一绝缘层，得到第二结构；
    将所述第二结构翻转；
    去除所述衬底，露出所述第一叠层结构；
    在所述第一叠层结构上制备第二叠层结构，其中，所述第二叠层结构包括k层电介质层和k层导电层，所述k层电介质层和所述k层导电层形成导电层与电介质层彼此相邻的结构，且与所述第一叠层结构形成导电层与电介质层彼此相邻的叠层结构，所述叠层结构在孔或沟槽处形成柱状结构，k为正整数；
    在所述第二叠层结构上制备第二绝缘层；
    制备第一电极和第二电极，其中，所述第一电极电连接至m+k+1层导电层中的奇数层导电层，所述第二电极电连接至所述m+k+1层导电层中的偶数层导电层。
  13. 根据权利要求12所述的方法，其特征在于，所述多个孔或沟槽包括第一孔或沟槽以及第二孔或沟槽，所述第一孔或沟槽的尺寸大于所述第二孔或沟槽的尺寸。
  14. 根据权利要求13所述的方法，其特征在于，所述第二孔或沟槽的深宽比大于预定阈值。
  15. 根据权利要求12至14中任一项所述的方法，其特征在于，在所述在所述第一结构上制备第一叠层结构之前，所述方法还包括：
    在所述第一结构上制备刻蚀保护层；
    其中，所述去除所述衬底，露出所述第一叠层结构，包括：
    去除所述衬底，露出所述刻蚀保护层，再去除所述刻蚀保护层，露出所述第一叠层结构。
  16. 根据权利要求12至15中任一项所述的方法，其特征在于，在所述将所述第二结构翻转之前，所述方法还包括：
    将所述第一绝缘层的表面磨平。
  17. 根据权利要求16所述的方法，其特征在于，在所述将所述第二结构翻转之后，所述方法还包括：
    将所述第一绝缘层的表面键合到载片上。
  18. 根据权利要求17所述的方法，其特征在于，在所述制备第一电极和第二电极之后，所述方法还包括：
    减薄所述载片或者去除所述载片和键合层。
  19. 根据权利要求12至18中任一项所述的方法，其特征在于，在所述在所述第二叠层结构上制备第二绝缘层之后，所述方法还包括：
    将所述第二绝缘层的表面磨平。
  20. 根据权利要求19所述的方法，其特征在于，所述第二绝缘层的表面磨平至露出所述第二叠层结构最上方的导电层。
  21. 根据权利要求12至20中任一项所述的方法，其特征在于，在所述制备第一电极和第二电极之前，所述方法还包括：
    制备第一互联结构，其中，所述第一互联结构包括分别连接至全部或部分导电层的导电通孔。
  22. 根据权利要求21所述的方法，其特征在于，在所述第一互联结构包括分别连接至全部导电层的导电通孔时，所述第一电极通过所述第一互联结构电连接所述奇数层导电层，所述第二电极通过所述第一互联结构电连接至所述偶数层导电层。
  23. 根据权利要求21所述的方法，其特征在于，在所述第一互联结构包括分别连接至部分导电层的导电通孔时，所述方法还包括：
    在所述在所述第一结构上制备第一叠层结构之后，制备第二互联结构；
    其中，所述第一电极通过所述第一互联结构和所述第二互联结构电连接所述奇数层导电层，所述第二电极通过所述第一互联结构电连接至所述偶数层导电层。
  24. 根据权利要求21至23中任一项所述的方法，其特征在于，所述制备第一互联结构包括：
    刻蚀所述第一孔或沟槽处的所述第二绝缘层，形成第一台阶结构，露出待连接的导电层；
    沉积第一刻蚀停止层；
    在所述第一刻蚀停止层上沉积第三绝缘层，其中，所述第一刻蚀停止层的耐刻蚀性大于所述第三绝缘层；
    针对特定导电层，刻蚀所述第三绝缘层，得到穿过所述第三绝缘层至所述第一台阶结构上的所述第一刻蚀停止层的孔；
    去除所述孔内的所述第一刻蚀停止层；
    在所述孔内沉积金属，得到穿过所述第三绝缘层和所述第一刻蚀停止层连接至所述特定导电层的导电通孔。
  25. 根据权利要求23所述的方法，其特征在于，其特征在于，所述制备第二互联结构包括：
    在所述在所述第一叠层结构上制备第一绝缘层之前，刻蚀所述第一叠层结构，形成第二台阶结构，露出待连接的导电层；
    沉积第二刻蚀停止层，其中，所述第二刻蚀停止层的耐刻蚀性大于所述第一绝缘层；
    在所述在所述第一叠层结构上制备第一绝缘层之后，针对特定导电层，刻蚀所述第一绝缘层，得到穿过所述第一绝缘层至所述第二台阶结构上的所述第二刻蚀停止层的孔；
    去除所述孔内的所述第二刻蚀停止层；
    在所述孔内沉积金属，得到穿过所述第一绝缘层和所述第二刻蚀停止层连接至所述特定导电层的导电通孔，并形成待连接导电层之间的金属互联。
  26. 根据权利要求23或25所述的方法，其特征在于，在所述制备第二互联结构之后，所述方法还包括：
    在所述第二互联结构上制备第四绝缘层。
  27. 根据权利要求12至26中任一项所述的方法，其特征在于，所述方法还包括：
    通过切割得到独立的电容器。
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