WO2021022416A1 - 电容器及其制作方法 - Google Patents

电容器及其制作方法 Download PDF

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Publication number
WO2021022416A1
WO2021022416A1 PCT/CN2019/099100 CN2019099100W WO2021022416A1 WO 2021022416 A1 WO2021022416 A1 WO 2021022416A1 CN 2019099100 W CN2019099100 W CN 2019099100W WO 2021022416 A1 WO2021022416 A1 WO 2021022416A1
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Prior art keywords
layer
conductive
trench
conductive layer
semiconductor substrate
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PCT/CN2019/099100
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English (en)
French (fr)
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陆斌
沈健
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2019/099100 priority Critical patent/WO2021022416A1/zh
Priority to CN201980001402.4A priority patent/CN112602191B/zh
Priority to EP19919567.8A priority patent/EP3800663B1/en
Priority to US17/029,035 priority patent/US11362173B2/en
Publication of WO2021022416A1 publication Critical patent/WO2021022416A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/012—Form of non-self-supporting electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H01G4/306—Stacked capacitors made by thin film techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H01L29/945—Trench capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers

Definitions

  • This application relates to the field of capacitors, and more specifically, to capacitors and methods of making them.
  • Capacitors can play the role of bypassing, filtering, decoupling, etc. in the circuit, and are an indispensable part of ensuring the normal operation of the circuit.
  • MLCC Multi-layer Ceramic Capacitors
  • the embodiments of the present application provide a capacitor and a manufacturing method thereof, which can manufacture a capacitor with a small volume and a high capacitance value density.
  • a capacitor in a first aspect, includes:
  • the laminated structure is arranged above the semiconductor substrate and includes an n-layer conductive layer and an m-layer dielectric layer.
  • the n-layer conductive layer and the m-layer dielectric layer form a structure in which the conductive layer and the dielectric layer are adjacent to each other, At least one i-th isolation trench is provided in the i-th conductive layer of the n-layer conductive layer, and the at least one i-th isolation trench divides the i-th conductive layer into at least two electrically isolated layers Conductive region, the (i+1)th conductive layer of the n-layer conductive layer is arranged above the i-th conductive layer and in the at least one i-th isolation trench, and the isolation trench in the odd-numbered conductive layer There is a first overlap area in the vertical direction, and the isolation trenches in the even-numbered conductive layers have a second overlap area in the vertical direction. The first overlap area and the second overlap area do not overlap, m, n , I is a positive integer, and
  • At least one first externally connected electrode the first externally connected electrode is electrically connected to all odd-numbered conductive layers in the n-layer conductive layer through a first conductive via structure, and the first conductive via structure is disposed on the first conductive via 2.
  • At least one second external electrode is electrically connected to all even-numbered conductive layers in the n-layer conductive layer through a second conductive via structure, and the second conductive via structure is disposed on the first Within an overlapping area.
  • At least one n-th isolation trench is provided in the n-th conductive layer of the n-th conductive layer, and the at least one n-th isolation trench divides the n-th conductive layer Are at least two conductive areas that are electrically isolated from each other.
  • the number and/or size of isolation trenches formed on different odd-numbered conductive layers in the n-layer conductive layer are the same; and/or,
  • the number and/or size of isolation trenches formed on different even-numbered conductive layers in the n-layer conductive layer are the same.
  • isolation trenches formed on the different odd-numbered conductive layers in the n-layer conductive layer completely overlap in the vertical direction; and/or,
  • isolation trenches formed on different even-numbered conductive layers in the n-layer conductive layer completely overlap in the vertical direction.
  • the i-th conductive layer in the n-layer conductive layer is provided with an i-th trench array around the i-th isolation trench, and the i+1-th layer of the n-layer conductive layer The conductive layer is arranged in the i-th trench array.
  • the size of the trenches in the i-th trench array is smaller than the size of the i-th isolation trench, and/or the depth of the trenches in the i-th trench array is smaller than The depth of the i-th isolation trench.
  • the number and/or size of the trenches in the trench arrays formed on different conductive layers are the same.
  • trench arrays formed on different conductive layers completely overlap in the vertical direction.
  • the second external electrode is also electrically connected to the semiconductor substrate through the second conductive via structure.
  • the semiconductor substrate is formed of a material with a resistivity less than a threshold, or a heavily doped conductive layer or a conductive region with a resistivity less than the threshold is formed on the surface of the semiconductor substrate.
  • the capacitor further includes: an etch stop structure provided on the upper surface of the semiconductor substrate to prevent the first conductive via structure from being electrically connected to the semiconductor substrate.
  • the projection of the etch stop structure on the semiconductor substrate is greater than or equal to the second overlapping area.
  • the semiconductor substrate includes at least one substrate trench, and the at least one substrate trench enters the semiconductor substrate downward from the upper surface of the semiconductor substrate, and the n
  • the first conductive layer of the conductive layers is disposed in the at least one substrate trench.
  • the number of trenches in the at least one substrate trench is the same as the number of isolation trenches provided in an even-numbered conductive layer in the n-layer conductive layer; and/or,
  • the size of the trench in the at least one substrate trench is the same as the size of the isolation trench provided in the even-numbered conductive layer in the n-layer conductive layer.
  • a projection of the at least one substrate trench on the semiconductor substrate is greater than or equal to the second overlap area.
  • the semiconductor substrate further includes an array of substrate trenches disposed around the at least one substrate trench, and the array of substrate trenches extends from the upper surface of the semiconductor substrate to The semiconductor substrate is entered downward, and the first conductive layer of the n-layer conductive layer is arranged in the substrate trench array.
  • the size of the trench in the substrate trench array is smaller than the size of the trench in the at least one substrate trench, and/or the size of the trench in the substrate trench array
  • the depth of the trench is smaller than the depth of the trench in the at least one substrate trench.
  • the capacitor further includes: an electrode layer disposed above the laminated structure, the electrode layer includes at least one first conductive region and at least one second conductive region that are separated from each other, so The first conductive area forms the first external electrode, and the second conductive area forms the second external electrode.
  • the capacitor further includes: an interconnection structure, including at least one insulating layer, the first conductive via structure and the second conductive via structure, and the at least one insulating layer is provided Above the laminated structure, the first conductive via structure and the second conductive via structure penetrate the at least one insulating layer.
  • the conductive layer includes at least one of the following:
  • Heavily doped polysilicon layer carbon layer, aluminum layer, copper layer, tungsten layer, titanium layer, tantalum layer, platinum layer, nickel layer, ruthenium layer, iridium layer, rhodium layer, tantalum nitride layer, titanium nitride layer, nitrogen Aluminum titanium layer, silicon nitride tantalum layer, carbon tantalum nitride layer.
  • the dielectric layer includes at least one of the following:
  • Silicon oxide layer silicon nitride layer, silicon oxynitride layer, metal oxide layer, metal nitride layer, metal oxynitride layer.
  • a method for manufacturing a capacitor including:
  • a stacked structure is prepared over the semiconductor substrate, the stacked structure includes an n conductive layer and an m dielectric layer, the n conductive layer and the m dielectric layer form a structure in which the conductive layer and the dielectric layer are adjacent to each other At least one i-th isolation trench is provided in the i-th conductive layer in the n-layer conductive layer, and the at least one i-th isolation trench divides the i-th conductive layer into at least two electrically isolated layers.
  • the (i+1)th conductive layer of the n-layer conductive layer is arranged above the i-th conductive layer and in the at least one i-th isolation trench, and the isolation trenches in the odd-numbered conductive layer
  • the groove has a first overlap area in the vertical direction, and the isolation trenches in the even-numbered conductive layers have a second overlap area in the vertical direction.
  • the first overlap area and the second overlap area do not overlap, m, n and i are positive integers, and n ⁇ 2, 1 ⁇ i ⁇ n-1;
  • first external electrode Prepares at least one first external electrode and at least one second external electrode, wherein the first external electrode is electrically connected to all odd-numbered conductive layers in the n-layer conductive layer through a first conductive via structure, and the first The two external electrodes are electrically connected to all even-numbered conductive layers in the n-layer conductive layer through a second conductive via structure, the first conductive via structure is disposed in the second overlapping area, and the second conductive via structure The through hole structure is arranged in the first overlapping area.
  • At least one n-th isolation trench is provided in the n-th conductive layer of the n-th conductive layer, and the at least one n-th isolation trench divides the n-th conductive layer Are at least two conductive areas that are electrically isolated from each other.
  • the number and/or size of isolation trenches formed on different odd-numbered conductive layers in the n-layer conductive layer are the same; and/or,
  • the number and/or size of isolation trenches formed on different even-numbered conductive layers in the n-layer conductive layer are the same.
  • isolation trenches formed on the different odd-numbered conductive layers in the n-layer conductive layer completely overlap in the vertical direction; and/or,
  • isolation trenches formed on different even-numbered conductive layers in the n-layer conductive layer completely overlap in the vertical direction.
  • the i-th conductive layer in the n-layer conductive layer is provided with an i-th trench array around the i-th isolation trench, and the i+1-th layer of the n-layer conductive layer The conductive layer is arranged in the i-th trench array.
  • the size of the trenches in the i-th trench array is smaller than the size of the i-th isolation trench, and/or the depth of the trenches in the i-th trench array is smaller than The depth of the i-th isolation trench.
  • the number and/or size of the trenches in the trench arrays formed on different conductive layers are the same.
  • trench arrays formed on different conductive layers completely overlap in the vertical direction.
  • the second external electrode is also electrically connected to the semiconductor substrate through the second conductive via structure.
  • the semiconductor substrate is formed of a material with a resistivity less than a threshold, or a heavily doped conductive layer or a conductive region with a resistivity less than the threshold is formed on the surface of the semiconductor substrate.
  • the method further includes:
  • An etch stop structure is prepared, and the etch stop structure is disposed on the upper surface of the semiconductor substrate to prevent the first conductive via structure from being electrically connected to the semiconductor substrate.
  • the projection of the etch stop structure on the semiconductor substrate is greater than or equal to the second overlapping area.
  • the method further includes:
  • At least one substrate trench is prepared on the semiconductor substrate, the at least one substrate trench enters the semiconductor substrate downward from the upper surface of the semiconductor substrate, and the first in the n-layer conductive layer A conductive layer is arranged in the at least one substrate trench.
  • the number of trenches in the at least one substrate trench is the same as the number of isolation trenches provided in an even-numbered conductive layer in the n-layer conductive layer; and/or,
  • the size of the trench in the at least one substrate trench is the same as the size of the isolation trench provided in the even-numbered conductive layer in the n-layer conductive layer.
  • a projection of the at least one substrate trench on the semiconductor substrate is greater than or equal to the second overlapping area.
  • the method further includes:
  • a substrate trench array arranged around the at least one substrate trench is prepared on the semiconductor substrate, and the substrate trench array enters the semiconductor substrate downward from the upper surface of the semiconductor substrate ,
  • the first conductive layer of the n-layer conductive layer is arranged in the substrate trench array.
  • the size of the trench in the substrate trench array is smaller than the size of the trench in the at least one substrate trench, and/or the size of the trench in the substrate trench array
  • the depth of the trench is smaller than the depth of the trench in the at least one substrate trench.
  • the preparing at least one first external electrode and at least one second external electrode includes:
  • An electrode layer is prepared above the laminated structure, the electrode layer includes at least one first conductive region and at least one second conductive region that are separated from each other, the first conductive region forms the first external electrode, and the second conductive region Two conductive regions form the second external electrode.
  • the method further includes:
  • the interconnection structure includes at least one insulating layer, the first conductive via structure and the second conductive via structure, the at least one insulating layer is disposed above the laminated structure, The first conductive via structure and the second conductive via structure penetrate the at least one insulating layer.
  • trench capacitors are prepared in the conductive layer in the laminated structure, and multiple photolithography and thin film deposition steps with consistent parameters are repeatedly used to reduce the alignment of the multilayer conductive layer in the laminated structure. Accuracy requirements can increase the number of stacked capacitor layers while maintaining a low processing cost, and further increase the capacitance density of the capacitor.
  • Fig. 1 is a schematic structural diagram of a capacitor provided by the present application.
  • FIG. 2 is a schematic diagram of a first isolation trench according to an embodiment of the present application.
  • Fig. 3 is a schematic structural diagram of another capacitor according to an embodiment of the present application.
  • Fig. 4 is a schematic structural diagram of still another capacitor according to an embodiment of the present application.
  • Fig. 5 is a schematic structural diagram of still another capacitor according to an embodiment of the present application.
  • Fig. 6 is a schematic structural diagram of a semiconductor substrate according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of yet another semiconductor substrate according to an embodiment of the present application.
  • Fig. 8 is a schematic flowchart of a method for manufacturing a capacitor according to an embodiment of the present application.
  • 9a to 9n are schematic diagrams of a manufacturing method of a capacitor according to an embodiment of the present application.
  • 10a to 10l are schematic diagrams of a manufacturing method of a capacitor according to an embodiment of the present application.
  • capacitors in the embodiments of the present application can perform functions such as bypassing, filtering, and decoupling in the circuit.
  • the capacitor described in the embodiments of the present application may be a 3D silicon capacitor, which is a new type of capacitor based on semiconductor wafer processing technology. Compared with traditional MLCC (Multilayer Ceramic Capacitors), 3D silicon capacitors have the advantages of small size, high precision, high stability, and long life.
  • the basic processing flow requires processing high-aspect-ratio deep holes (Via), trenches (Trench), pillars (Pillar), wall (Wall) and other 3D structures on the wafer or substrate first, and then in the 3D structure An insulating film and a low-resistivity conductive material are deposited on the surface to make the lower electrode, the dielectric layer and the upper electrode of the capacitor in sequence.
  • this application proposes a new type of capacitor structure and manufacturing method.
  • the stacked capacitor layers can be improved while maintaining low processing costs.
  • Count further increase the capacitance density of the capacitor.
  • the capacitors in FIGS. 1 to 7 are only examples, the number of conductive layers and the number of dielectric layers included in the laminated structure are only examples, and the number of conductive layers and the number of dielectric layers included in the laminated structure are not It is not limited to the capacitors shown in FIGS. 1 to 7, and can be flexibly set according to actual needs.
  • FIG. 1 is a possible structure diagram of a capacitor 100 according to an embodiment of the present application.
  • the capacitor 100 includes a semiconductor substrate 110, a stacked structure 120, at least one first external electrode 130 and at least one second external electrode 140.
  • the stacked structure 120 is disposed above the semiconductor substrate 110.
  • the stacked structure 120 includes n conductive layers and m dielectric layers, and the n conductive layers Layer and the m-layer dielectric layer form a structure in which the conductive layer and the dielectric layer are adjacent to each other, the i-th conductive layer in the n-layer conductive layer is provided with at least one i-th isolation trench, and the at least one i-th isolation trench
  • the i-th conductive layer is divided into at least two conductive regions that are electrically isolated from each other, and the (i+1)th conductive layer of the n-th conductive layer is disposed above the i-th conductive layer and the at least one i-th isolation trench In the groove, the isolation trenches in the odd-numbered conductive layers have a first overlap area in the vertical direction, and the isolation trenches in the even-numbered conductive layers have a second overlap area in the vertical direction.
  • the first overlap area and the The second overlapping area does not overlap, m, n, i are positive integers, and n ⁇ 2, 1 ⁇ i ⁇ n-1; the first external electrode 130 is electrically connected to the n-layer conductive via the first conductive via structure 161 For all odd-numbered conductive layers in the layer, the first conductive via structure 161 is disposed in the second overlapping area; the second external electrode 140 is electrically connected to the n-layer conductive layer through the second conductive via structure 162 For all the even-numbered conductive layers of, the second conductive via structure 162 is disposed in the first overlapping area.
  • At least one n-th isolation trench is provided in the n-th conductive layer of the n-th conductive layer, and the at least one n-th isolation trench divides the n-th conductive layer into at least two electrically isolated layers.
  • a conductive area is provided in the n-th conductive layer of the n-th conductive layer, and the at least one n-th isolation trench divides the n-th conductive layer into at least two electrically isolated layers.
  • the cross-sectional shapes of different isolation trenches provided in the same conductive layer may be the same or different.
  • FIG. 1 in the embodiment of the present application is a cross section along the longitudinal direction of the semiconductor substrate.
  • the isolation trenches in the odd-numbered conductive layers in the n-layer conductive layer have a first overlapping area in the vertical direction, and the second conductive via structure 162 is disposed in the first overlapping area Therefore, the second external electrode 140 can be electrically connected to all the even-numbered conductive layers in the n-layer conductive layer through the second conductive via structure 162.
  • the isolation trenches in the even-numbered conductive layers of the n-layer conductive layer have a second overlapping area in the vertical direction, and the first conductive via structure 161 is disposed in the second overlapping area, so that the first An external electrode 130 can be electrically connected to all odd-numbered conductive layers in the n-layer conductive layer through the first conductive via structure 161.
  • the first overlapping area and the second overlapping area do not overlap, which can prevent a short circuit between the first external electrode 130 and the second external electrode 140.
  • trench capacitors are prepared in the conductive layer of the laminated structure, and multiple photolithography and film deposition steps with consistent parameters are repeatedly used to reduce the alignment accuracy requirements of the multilayer conductive layer in the laminated structure. It can increase the number of stacked capacitor layers while maintaining a low processing cost, and further increase the capacitance density of the capacitor.
  • the isolation trench in the odd-numbered conductive layer has a first overlapping area in the vertical direction. It can also be understood that the isolation trench in the odd-numbered conductive layer is in the semiconductor
  • the projection on the substrate 110 has a first overlapping area. In the same way, the isolation trenches in the even-numbered conductive layers have a second overlap area in the vertical direction. It can also be understood that the projections of the isolation trenches in the even-numbered conductive layers on the semiconductor substrate 110 have a second overlap. area. The first overlapping area and the second overlapping area do not overlap. It can also be understood that the projection of the isolation trenches in the odd-numbered conductive layer on the semiconductor substrate 110 and the isolation trenches in the even-numbered conductive layer on the semiconductor substrate 110 There is no overlap area between the projections on the substrate 110.
  • the isolation trench provided in the conductive layer may be a trench with a large difference in length and width, or may also be a pillar-shaped (Pillar) or wall-shaped (Wall) 3D structure .
  • the cross-section can be understood as a cross-section parallel to the surface of the semiconductor substrate 110, while in FIG.
  • two adjacent conductive layers in the n-layer conductive layer are electrically isolated by a dielectric layer, and the specific values of m and n can be flexibly configured according to actual needs.
  • the two adjacent conductive layers are electrically isolated.
  • a dielectric layer needs to be provided between the first conductive layer in the laminated structure 120 and the semiconductor substrate 110 to isolate the first conductive layer.
  • external electrodes in the embodiments of the present application may also be referred to as pads or external pads.
  • the semiconductor substrate 110 may be a silicon wafer, including monocrystalline silicon, polycrystalline silicon, and amorphous silicon.
  • the semiconductor substrate 110 may also be other semiconductor substrates, including silicon-on-insulator (SOI) wafers, silicon carbide (SiC), gallium nitride (GaN), and gallium arsenide (SiC). GaAs) and other III-V compound semiconductor wafers; or glass substrates; or organic polymer substrates; or substrates containing epitaxial layers, oxide layers, doped layers, and bonding layers on the surface.
  • SOI silicon-on-insulator
  • SiC silicon carbide
  • GaN gallium nitride
  • SiC gallium arsenide
  • the thickness of the semiconductor substrate 110 can also be flexibly set according to actual needs.
  • the semiconductor substrate 110 can be The substrate 110 is thinned.
  • the material of the first external electrode 130 and the second external electrode 140 may be metal, such as copper, aluminum, or the like.
  • the first external electrode 130 and the second external electrode 140 may also include low resistivity Ti, TiN, Ta, TaN layers as adhesion layers and/or barrier layers; they may also include some metal layers on the surface of the external electrodes, for example Ni, Pd (palladium), Au, Sn (tin), Ag are used for subsequent wire bonding or welding processes.
  • the conductive layer includes at least one of the following:
  • Heavily doped polysilicon layer carbon layer, aluminum layer, copper layer, tungsten layer, titanium layer, tantalum layer, platinum layer, nickel layer, ruthenium layer, iridium layer, rhodium layer, tantalum nitride layer, titanium nitride layer, nitrogen Aluminum titanium layer, silicon nitride tantalum layer, carbon tantalum nitride layer.
  • the material of the conductive layer in the laminated structure 120 may be heavily doped polysilicon, carbon, aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), platinum (Pt), ruthenium (Ru), iridium (Ir), rhodium (Rh), nickel (Ni) and other metals, tantalum nitride (TaN), titanium nitride (TiN), titanium aluminum nitride (TiAlN), nitride Silicon tantalum (TaSiN), tantalum carbon nitride (TaCN) and other low-resistivity compounds, or a combination of the above materials, and a laminated structure.
  • the specific conductive material and layer thickness can be adjusted according to the capacitance, frequency characteristics, loss and other requirements of the capacitor.
  • the conductive layer in the laminated structure 120 may also include some other conductive materials, which is not limited in the embodiment of the present application.
  • the dielectric layer includes at least one of the following:
  • Silicon oxide layer silicon nitride layer, silicon oxynitride layer, metal oxide layer, metal nitride layer and metal oxynitride layer.
  • the material of the dielectric layer in the laminated structure 120 may be silicon oxide, silicon nitride, silicon oxynitride, metal oxide, metal nitride, or metal oxynitride.
  • SiO 2 , SiN, SiON, or high-k materials including Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 , Y 2 O 3 , La 2 O 3 , HfSiO 4 , LaAlO 3 , SrTiO 3 , LaLuO 3 and so on.
  • the dielectric layer in the laminated structure 120 can be one layer or multiple laminated layers, and can be one material or a combination or mixture of multiple materials. The specific insulation material and layer thickness can be adjusted according to the capacitance, frequency characteristics, loss and other requirements of the capacitor.
  • the dielectric layer in the laminated structure 120 may also include some other insulating materials, which is not limited in the embodiment of the present application.
  • the order of the m-layer dielectric layer is: on the semiconductor substrate 110, the distance from the semiconductor substrate 110 is ascending.
  • the order of the n-layer conductive layer is: on the semiconductor substrate 110, the distance from the semiconductor substrate 110 is from small to large.
  • first external electrode 130 is electrically connected to all odd-numbered conductive layers in the n-layer conductive layer through the first conductive via structure 161
  • second external electrode 140 is electrically connected through the second conductive via structure 162. It is electrically connected to all the even-numbered conductive layers in the n-layer conductive layer, thereby avoiding multiple photolithography to form multiple stepped structures, and the first external electrode 130 and the second external electrode 140 are separated from the conductive layer through the multiple stepped structures. Electrical connection, reducing photolithography steps, and reducing the cost of manufacturing capacitors.
  • first external electrode 130 is electrically connected to all odd-numbered conductive layers in the n-layer conductive layer
  • second external electrode 140 is electrically connected to all even-numbered conductive layers in the n-layer conductive layer, so that Give full play to the effect of the laminated structure to increase the capacitance density of the capacitor.
  • the capacitor 100 includes a laminated structure, denoted as laminated structure 1, and includes two first external electrodes and two second external electrodes, and the two first external electrodes are respectively denoted as first external electrodes A And the first external electrode B, the two second external electrodes are respectively denoted as the second external electrode C and the second external electrode D, and the laminated structure 1 includes 5 conductive layers and 4 dielectric layers, 5 conductive layers in sequence Denoted as conductive layer 1, conductive layer 2, conductive layer 3, conductive layer 4, and conductive layer 5, the four dielectric layers are respectively denoted as dielectric layer 1, dielectric layer 2, dielectric layer 3, and dielectric layer 4, respectively.
  • the first external electrode A is electrically connected to the conductive layer 1, the conductive layer 3 and the conductive layer 5, and the first external electrode B is also electrically connected to the conductive layer 1, the conductive layer 3 and the conductive layer 5.
  • the second external electrode C is electrically connected to the conductive layer 2 and the conductive layer 4, and the second external electrode D is also electrically connected to the conductive layer 2 and the conductive layer 4.
  • the capacitor corresponding to the electrode C, the conductive layer 1 and the conductive layer 2 form a capacitor 1, the capacitance value is denoted as C1, the conductive layer 2 and the conductive layer 3 form a capacitor 2, the capacitance value is denoted as C2, the conductive layer 3 and the The conductive layer 4 forms a capacitor 3, the capacitance value is denoted as C3, the conductive layer 4 and the conductive layer 5 form a capacitor 4, the capacitance value is denoted as C4, the capacitor 1, the capacitor 2, the capacitor 3 and the capacitor 4 are connected in parallel, and its equivalent capacitance i
  • the capacitance value is recorded as C1, the conductive layer 2 and the conductive layer 3 form a capacitor 2, the capacitance value is recorded as C2, the conductive layer 3
  • the capacitors corresponding to the first external electrode A and the second external electrode D can also form a similar series-parallel structure, and the capacitors corresponding to the first external electrode B and the second external electrode C can also be similar.
  • the series-parallel structure will not be repeated here.
  • multiple photolithography and thin film deposition steps with consistent parameters are repeatedly used to prepare the laminated structure 120.
  • all odd-numbered conductive layers in the laminated structure 120 use the same etching parameters
  • All even-numbered conductive layers in the layer structure 120 use the same etching parameters, thereby reducing the alignment accuracy requirements of the multilayer conductive layers in the stacked structure 120.
  • the number and/or size of isolation trenches formed on different odd-numbered conductive layers in the n-layer conductive layer are the same; and/or, the different conductive layers in the n-layer The number and/or size of the isolation trenches formed on the even-numbered conductive layers are the same.
  • the projection positions and/or projection areas of isolation trenches provided on different conductive layers on the semiconductor substrate 110 are the same; and/or, in the In all odd-numbered conductive layers in the n-layer conductive layer, the number and/or size of isolation trenches provided on different conductive layers are the same.
  • the isolation trenches formed on the different odd-numbered conductive layers in the n-layer conductive layer completely overlap in the vertical direction; and/or, the different conductive layers in the n-layer The isolation trenches formed on the even-numbered conductive layers completely overlap in the vertical direction.
  • the projection positions and/or projection areas of isolation trenches provided on different conductive layers on the semiconductor substrate 110 are the same; and/or, in the In all even-numbered conductive layers in the n-layer conductive layer, the number and/or size of isolation trenches provided on different conductive layers are the same.
  • isolation trenches provided on different conductive layers completely overlap in the vertical direction; and/or, all of the n-layer conductive layers In the even-numbered conductive layers, isolation trenches provided on different conductive layers completely overlap in the vertical direction.
  • the number of isolation trenches provided on the odd-numbered conductive layer and the number of isolation trenches provided on the even-numbered conductive layer may be the same or different.
  • the number of isolation trenches provided on the odd-numbered conductive layer is equal to the number of isolation trenches provided on the even-numbered conductive layer.
  • the laminated structure 120 may include 5 conductive layers, such as the first conductive layer 1201 and the second conductive layer shown in FIG. 1202, the third conductive layer 1203, the fourth conductive layer 1204, the fifth conductive layer 1205, and five dielectric layers, such as the first dielectric layer 1211, the second dielectric layer 1212, The third dielectric layer 1213, the fourth dielectric layer 1214, and the fifth dielectric layer 1215.
  • the first dielectric layer 1211 is disposed between the semiconductor substrate 110 and the first conductive layer 1201, and the second dielectric layer 1212 is disposed between the first conductive layer 1201 and the second conductive layer 1202 Meanwhile, the third dielectric layer 1213 is disposed between the second conductive layer 1202 and the third conductive layer 1203, and the fourth dielectric layer 1214 is disposed between the third conductive layer 1203 and the fourth layer. Between the conductive layers 1204, the fifth dielectric layer 1215 is disposed between the fourth conductive layer 1204 and the fifth conductive layer 1205. Specifically, as shown in FIG.
  • the first conductive layer 1201 is provided with a first isolation trench 11
  • the second conductive layer 1202 is provided with a second isolation trench 12
  • the third conductive layer 1203 is provided with The third isolation trench 13
  • the fourth conductive layer 1204 is provided with a fourth isolation trench 14
  • the fifth conductive layer 1205 is provided with a fifth isolation trench 15.
  • the first isolation trench 11, the third isolation trench 13 and the fifth isolation trench 15 completely overlap in the vertical direction, and the first conductive layer 1201, the third conductive layer 1203, and the The number and/or size of isolation trenches formed on the fifth conductive layer 1205 are the same.
  • the second isolation trench 12 and the fourth isolation trench 14 completely overlap in the vertical direction, and the isolation trench formed on the second conductive layer 1202 and the fourth conductive layer 1204
  • the number and/or size are the same.
  • the isolation trenches provided in the odd-numbered conductive layers are misaligned with the isolation trenches provided in the even-numbered conductive layers. That is, the isolation trenches in the odd-numbered conductive layers have a first overlap area in the vertical direction, and the isolation trenches in the even-numbered conductive layers have a second overlap area in the vertical direction, and the first overlap area and the The second overlapping area does not overlap.
  • first isolation trench 11 may be as shown in FIG. 2, and the third isolation trench 13 and the fifth isolation trench 15 are similar to the first isolation trench 11.
  • the i-th conductive layer in the n-layer conductive layer is provided with an i-th trench array around the i-th isolation trench, and the i+1-th conductive layer in the n-layer conductive layer A conductive layer is arranged in the i-th trench array.
  • the size of the trenches in the i-th trench array is smaller than the size of the i-th isolation trench, and/or the depth of the trenches in the i-th trench array is smaller than that of the i-th isolation trench depth.
  • the size of the trenches in the i-th trench array may be 1 ⁇ m, and the size of the i-th isolation trench may be 5 ⁇ m, which is not limited in this application.
  • the projection positions and/or projection areas of the trench arrays provided on different conductive layers on the semiconductor substrate 110 are the same.
  • the number and/or size of the trenches in the trench arrays provided on different conductive layers are the same.
  • the trench arrays formed on different conductive layers completely overlap in the vertical direction.
  • the depth and width of the trenches in the trench array provided in the n-layer conductive layer can be flexibly set according to actual needs.
  • the trenches in the trench array provided in the n-layer conductive layer have a high aspect ratio (High aspect ratio).
  • the trench array and isolation trenches provided in the same conductive layer can be formed in the same etching step.
  • providing an array of trenches in the n-layer conductive layer can further increase the capacitance of the capacitor formed in the laminated structure 120.
  • the laminated structure 120 may include 4 conductive layers, such as the first conductive layer 1201 and the second conductive layer shown in FIG. 3 1202, the third conductive layer 1203 and the fourth conductive layer 1204, and 4 dielectric layers, such as the first dielectric layer 1211, the second dielectric layer 1212, the third dielectric layer 1213, and the The fourth dielectric layer 1214.
  • the first dielectric layer 1211 is disposed between the semiconductor substrate 110 and the first conductive layer 1201, and the second dielectric layer 1212 is disposed between the first conductive layer 1201 and the second conductive layer 1202 Meanwhile, the third dielectric layer 1213 is disposed between the second conductive layer 1202 and the third conductive layer 1203, and the fourth dielectric layer 1214 is disposed between the third conductive layer 1203 and the fourth layer. Between the conductive layers 1204. Specifically, as shown in FIG.
  • the first conductive layer 1201 is provided with a first isolation trench 11 and a first trench array 21, and the second conductive layer 1202 is provided with a second isolation trench 12 and a second The trench array 22, the third conductive layer 1203 is provided with a third isolation trench 13 and a third trench array 23, and the fourth conductive layer 1204 is provided with only the fourth isolation trench 14.
  • the size of the trenches in the first trench array 21 is smaller than the size of the first isolation trench 11, and the depth of the trenches in the first trench array 21 is smaller than that of the first isolation trench.
  • the size of the trenches in the second trench array 22 is smaller than the size of the second isolation trench 12, and the depth of the trenches in the second trench array 22 is smaller than that of the second isolation trench 12 Depth;
  • the size of the trenches in the third trench array 23 is smaller than the size of the third isolation trench 13, and the depth of the trenches in the third trench array 23 is smaller than the depth of the third isolation trench 13.
  • the projection positions and/or projection areas of the first trench array 21, the second trench array 22, and the third trench array 23 on the semiconductor substrate 110 are the same; the first trench array The groove array 21, the second groove array 22, and the third groove array 23 have the same number and/or size of grooves.
  • the trench arrays formed on different conductive layers can completely overlap in the vertical direction.
  • first isolation trench 11 may be as shown in FIG. 2 above, and the third isolation trench 13 is similar to the first isolation trench 11.
  • the semiconductor substrate 110 is made of a material with a resistivity less than a threshold, or the surface of the semiconductor substrate 110 is provided with a heavily doped conductive layer or a conductive area with a resistivity less than the threshold. . That is, the semiconductor substrate 110 is conductive, or the area of the semiconductor substrate 110 in contact with the laminated structure 120 is conductive.
  • a material with a resistivity less than the threshold can be considered as a conductive material.
  • the semiconductor substrate 110 is a heavily doped substrate
  • the semiconductor substrate 110 may also be doped to form a p++-type or n++-type low-resistivity conductive layer or conductive region.
  • a low-resistivity conductive material is deposited on the surface of the semiconductor substrate 110, such as using a PVD or ALD process to deposit TiN and/or TaN and/or Pt and other metals, or using a CVD process to deposit heavily doped polysilicon, metal tungsten , Carbon materials.
  • the semiconductor substrate 110 is formed of a material with a resistivity less than the threshold, it can be considered that the semiconductor substrate 110 is a heavily doped low resistivity substrate; a heavily doped resistor is formed on the surface of the semiconductor substrate 110 A conductive layer with a rate lower than the threshold can be considered as a heavily doped low-resistivity conductive layer formed on the surface of the semiconductor substrate 110; a conductive region with a heavily doped resistivity less than the threshold is formed on the surface of the semiconductor substrate 110. A heavily doped low-resistivity conductive region is formed on the surface of the semiconductor substrate 110.
  • the second external electrode 140 is also electrically connected to the semiconductor substrate 110 through the second conductive via structure 162.
  • the second conductive via structure 162 extends into the semiconductor substrate 110 after penetrating the isolation trenches in the odd-numbered conductive layers in the n-layer conductive layer, and the second external electrode 140
  • the second conductive via structure 162 is electrically connected to the semiconductor substrate 110 and all even-numbered conductive layers in the n-layer conductive layer; the first conductive via structure 161 penetrates through the even-numbered conductive layers of the n-layer conductive layer After the isolation trench in the conductive layer, it extends into the first conductive layer in the stacked structure 120.
  • the capacitor 100 further includes: an etch stop structure 150 disposed on the upper surface of the semiconductor substrate 110 to prevent the first conductive via structure 161 It is electrically connected to the semiconductor substrate 110.
  • the first conductive via structure 161 extends to the upper surface of the etch stop structure 150 after penetrating the laminated structure 120.
  • the etching stop structure 150 can effectively prevent the first conductive via structure 161 is electrically connected to the semiconductor substrate 110.
  • the projection of the etch stop structure 150 on the semiconductor substrate 110 is greater than or equal to the second overlapping area. To ensure that the etch stop structure 150 can prevent the first conductive via structure 161 from being electrically connected to the semiconductor substrate 110.
  • the etch stop structure 150 is more resistant to etching than the conductive layer and the dielectric layer in the stacked structure 120.
  • the first conductive via structure 161 can be The bottom of the etch stop structure 150 rests on the etch stop structure 150.
  • the etching stop structure 150 can be silicon oxide, silicon nitride, silicon-containing glass (Undoped Silicon Glass (Undoped Silicon Glass, USG), Borosilicate glass (BSG), phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG)); it can also be atomic layer deposition (ALD) ) Deposited alumina; or sprayed or spin-coated spin-on glass (SOG), polyimide (Polyimide), etc.; or a combination of the above materials.
  • silicon oxide silicon nitride
  • silicon-containing glass Undoped Silicon Glass (Undoped Silicon Glass, USG), Borosilicate glass (BSG), phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG)
  • ALD atomic layer deposition
  • SOG spin-coated spin-on glass
  • Polyimide Polyimide
  • the semiconductor substrate 110 includes at least one substrate trench 30, and the at least one substrate trench 30 extends downward from the upper surface of the semiconductor substrate 110. Entering the semiconductor substrate 110, the first conductive layer of the n-layer conductive layer is disposed in the at least one substrate trench.
  • the number of trenches in the at least one substrate trench 30 is the same as the number of isolation trenches provided in the even-numbered conductive layers in the n-layer conductive layer; and/or, the at least one substrate trench
  • the size of the trench in 30 is the same as the size of the isolation trench provided in the even-numbered conductive layer in the n-layer conductive layer.
  • the projection of the at least one substrate trench 30 on the semiconductor substrate 110 is greater than or equal to the second overlap area.
  • the semiconductor substrate 110 further includes a substrate trench array disposed around the at least one substrate trench, and the substrate trench array extends from the upper surface of the semiconductor substrate 110 to It enters the semiconductor substrate 110, and the first conductive layer of the n-layer conductive layer is disposed in the substrate trench array.
  • the size of the trenches in the substrate trench array 40 is smaller than the size of the trenches in the at least one substrate trench 30, and/or the depth of the trenches in the substrate trench array 40 It is smaller than the depth of the trench in the at least one substrate trench 30.
  • the capacitor 100 further includes an interconnection structure 160, wherein the interconnection structure 160 includes at least one insulating layer 163, the first conductive via structure 161 and the second conductive via structure 162. As shown in FIGS. 1 to 7, the at least one insulating layer 163 is disposed above the laminated structure 120, and the first conductive via structure 161 and the second conductive via structure 162 penetrate the at least one insulating layer 163.
  • the at least one insulating layer 163 may also be referred to as an intermetal dielectric layer (IMD) or an interlayer dielectric layer (ILD).
  • IMD intermetal dielectric layer
  • ILD interlayer dielectric layer
  • the first conductive via structure 161 and the second conductive via structure 162 may also be referred to as conductive channels.
  • the at least one insulating layer 163 covers the laminated structure 120, and the at least one insulating layer 163 can fill a cavity or gap formed on the upper surface of the laminated structure 120 to improve the structural integrity of the capacitor And mechanical stability.
  • the material of the at least one insulating layer 163 may be an organic polymer material, including polyimide, Parylene, benzocyclobutene (BCB), etc.; or Some inorganic materials, including spin-on glass (SOG), undoped silicon glass (USG), boro-silicate glass (BSG), phosphor-silicate glass (phospho-silicate glass, PSG), boro-phospho-silicate glass (BPSG), silicon oxide synthesized from Tetraethyl Orthosilicate (TEOS), silicon oxide, nitride, ceramic; it can also be the above materials A combination or stack of layers.
  • SOG spin-on glass
  • USG undoped silicon glass
  • BSG boro-silicate glass
  • phosphor-silicate glass phospho-silicate glass
  • PSG boro-phospho-silicate glass
  • BPSG boro-phospho-silicate glass
  • the material of the first conductive via structure 161 and the second conductive via structure 162 may be made of a low-resistivity conductive material, such as heavily doped polysilicon, tungsten, Ti, TiN, Ta, TaN.
  • first conductive via structure 161 and the second conductive via structure 162 may be specifically determined according to the manufacturing process of the capacitor 100, which is not limited in the embodiment of the present application.
  • the at least one first external electrode 130 and the at least one second external electrode 140 are disposed above the laminated structure 120.
  • the capacitor 100 further includes: an electrode layer disposed above the laminated structure 120, the electrode layer including at least one first conductive region and at least one second conductive region that are separated from each other, and the first conductive region forms The first external electrode 130 and the second conductive area form the second external electrode 140, as shown in FIGS. 1-7. That is, the at least one first external electrode 130 and the at least one second external electrode 140 can be formed by one etching, which reduces the etching steps.
  • the electrode layer is disposed above the interconnect structure 160, and the first external electrode 130 is electrically connected to the odd numbers in the stacked structure 120 through the first conductive via structure 161.
  • a conductive layer, the second external electrode 140 is electrically connected to the even-numbered conductive layers in the stacked structure 120 through the second conductive via structure 162.
  • trench capacitors are fabricated separately in the semiconductor substrate and the conductive layer, and the process of fabricating a single capacitor can be reused, which reduces the alignment accuracy requirements of the multilayer conductive layer, and can be used without increasing the difficulty of the process. Further improve the capacitance density of the capacitor.
  • the capacitors of the embodiments of the present application are described above, and the method for preparing the capacitors of the embodiments of the present application is described below.
  • the method for preparing a capacitor of the embodiment of the present application can prepare the capacitor of the foregoing embodiment of the present application, and the following embodiments and related descriptions in the foregoing embodiments can be referred to each other.
  • FIG. 8 is a schematic flowchart of a method for manufacturing a capacitor according to an embodiment of the present application, but these steps or operations are only examples, and the embodiment of the present application may also perform other operations or variations of each operation in FIG. 8.
  • FIG. 8 shows a schematic flowchart of a method 200 for manufacturing a capacitor according to an embodiment of the present application. As shown in FIG. 8, the manufacturing method 200 of the capacitor includes:
  • Step 210 Prepare a stacked structure over the semiconductor substrate, the stacked structure including an n conductive layer and an m dielectric layer, the n conductive layer and the m dielectric layer form a structure in which the conductive layer and the dielectric layer are adjacent to each other At least one i-th isolation trench is provided in the i-th conductive layer of the n-layer conductive layer, and the at least one i-th isolation trench divides the i-th conductive layer into at least two conductive regions electrically isolated from each other ,
  • the (i+1)th conductive layer of the n-layer conductive layer is disposed above the i-th conductive layer and in the at least one i-th isolation trench, and the isolation trenches in the odd-numbered conductive layer are in the vertical direction
  • the isolation trenches in the even-numbered conductive layers have a second overlap area in the vertical direction, the first overlap area does not overlap the second overlap area
  • m, n, and i are positive
  • Step 220 Prepare at least one first external electrode and at least one second external electrode, wherein the first external electrode is electrically connected to all odd-numbered conductive layers in the n-layer conductive layer through the first conductive via structure, and the first The two external electrodes are electrically connected to all even-numbered conductive layers in the n-layer conductive layer through a second conductive via structure, the first conductive via structure is disposed in the second overlapping area, and the second conductive via structure is disposed In the first overlapping area.
  • At least one n-th isolation trench is provided in the n-th conductive layer of the n-th conductive layer, and the at least one n-th isolation trench divides the n-th conductive layer into at least two electrically isolated layers.
  • a conductive area is provided in the n-th conductive layer of the n-th conductive layer, and the at least one n-th isolation trench divides the n-th conductive layer into at least two electrically isolated layers.
  • capacitors as shown in FIGS. 1 to 7 can be prepared.
  • each material layer described in steps 210-220 refers to the surface substantially parallel to the upper surface of the semiconductor substrate, and the inner surface of each material layer refers to the upper surface of the material layer in the trench.
  • the surface, the upper surface and the inner surface can be regarded as a whole.
  • the number and/or size of isolation trenches formed on different odd-numbered conductive layers in the n-layer conductive layer are the same; and/or, the number and/or size of isolation trenches formed on different even-numbered conductive layers in the n-layer conductive layer The number and/or size of the isolation trenches are the same.
  • the number and/or size of isolation trenches formed on different conductive layers are the same; and/or, all even-numbered conductive layers in the n-layer conductive layer In the conductive layer, the number and/or size of isolation trenches formed on different conductive layers are the same.
  • isolation trenches formed on different odd-numbered conductive layers in the n-layer conductive layer completely overlap in the vertical direction; and/or, formed on different even-numbered conductive layers in the n-layer conductive layer The isolation trenches completely overlap in the vertical direction.
  • isolation trenches formed on different conductive layers completely overlap in the vertical direction; and/or, all even-numbered conductive layers in the n-layer In the conductive layer, the isolation trenches formed on different conductive layers completely overlap in the vertical direction.
  • all odd-numbered conductive layers in the n-layer conductive layer can use the same photolithography and deposition process, and all even-numbered conductive layers in the n-layer conductive layer can use the same photolithography and deposition process, so that Reduce process complexity and processing cost.
  • the i-th conductive layer in the n-layer conductive layer is provided with an i-th trench array around the i-th isolation trench, and the (i+1)th conductive layer in the n-layer conductive layer is disposed on the i groove array. That is, no trench array is provided in the nth conductive layer of the n conductive layer.
  • the size of the trenches in the i-th trench array is smaller than the size of the i-th isolation trench, and/or the depth of the trenches in the i-th trench array is smaller than that of the i-th isolation trench depth.
  • the size of the trenches in the i-th trench array may be 1 ⁇ m, and the size of the i-th isolation trench may be 5 ⁇ m, which is not limited in this application.
  • the depth of the i-th isolation trench is greater than that of the i-th trench array.
  • the i-th groove array is deeper. That is, the i-th trench array does not penetrate the i-th conductive layer.
  • the number and/or size of the trenches in the trench arrays formed on different conductive layers are the same.
  • the trench arrays formed on different conductive layers completely overlap in the vertical direction.
  • the same etching parameters can be used to make the number and/or size of the trenches in the trench arrays formed on different conductive layers the same.
  • the number and/or size of the trenches in the trench array formed on different conductive layers may also be different, for example, the trenches in the trench array formed on the odd-numbered conductive layer
  • the number and/or size of the grooves are different from the number and/or size of the grooves in the groove array formed on the even-numbered conductive layer, which is not limited in the embodiment of the present application.
  • the second external electrode 140 is also electrically connected to the semiconductor substrate 110 through the second conductive via structure 162. That is, the semiconductor substrate 110 is conductive, or the area of the semiconductor substrate 110 in contact with the laminated structure 120 is conductive.
  • the semiconductor substrate 110 is formed of a material with a resistivity less than a threshold, or the surface of the semiconductor substrate 110 is formed with a heavily doped conductive layer or a conductive region with a resistivity less than the threshold.
  • the second conductive via structure 162 penetrates through the n-layer conductive layer. After the isolation trenches in the odd-numbered conductive layers extend into the semiconductor substrate 110, the second external electrode 140 is electrically connected to the semiconductor substrate 110 and the n-layer conductive layer through the second conductive via structure 162 All even-numbered conductive layers; the first conductive via structure 161 extends into the first conductive layer of the stacked structure 120 after passing through the isolation trenches in the even-numbered conductive layers of the n-layer conductive layer.
  • the method 200 further includes:
  • An etch stop structure 150 is prepared, and the etch stop structure 150 is disposed on the upper surface of the semiconductor substrate 110 to prevent the first conductive via structure 161 from being electrically connected to the semiconductor substrate 110.
  • the etch stop structure 150 can prevent the first conductive via structure 161 from extending Enter the semiconductor substrate 110.
  • the etch stop structure 150 can effectively prevent the first conductive via structure 161 from being The semiconductor substrate 110 is electrically connected.
  • the projection of the etch stop structure 150 on the semiconductor substrate 110 is greater than or equal to the second overlapping area. To ensure that the etch stop structure 150 can prevent the first conductive via structure 161 from being electrically connected to the semiconductor substrate 110.
  • the method 200 further includes:
  • At least one substrate trench 30 is prepared on the semiconductor substrate 110, and the at least one substrate trench 30 enters the semiconductor substrate 110 downward from the upper surface of the semiconductor substrate 110, and the first n-layer conductive layer A conductive layer is arranged in the at least one substrate trench.
  • the first conductive via structure 161 extends into the at least one substrate trench 30.
  • the at least one substrate trench 30 can prevent the first conductive via structure 161 from extending into the semiconductor substrate 110.
  • the at least one substrate trench 30 can effectively prevent the first conductive via structure 161 is electrically connected to the semiconductor substrate 110.
  • the number of trenches in the at least one substrate trench 30 is the same as the number of isolation trenches provided in the even-numbered conductive layers in the n-layer conductive layer; and/or, the at least one substrate trench
  • the size of the trench in 30 is the same as the size of the isolation trench provided in the even-numbered conductive layer in the n-layer conductive layer.
  • the projection of the at least one substrate trench 30 on the semiconductor substrate 110 is greater than or equal to the second overlap area.
  • the method 200 further includes:
  • a substrate trench array 40 arranged around the at least one substrate trench 30 is prepared on the semiconductor substrate 110, and the substrate trench array 40 enters the semiconductor substrate downward from the upper surface of the semiconductor substrate 110 110.
  • the first conductive layer of the n-layer conductive layer is disposed in the substrate trench array 40.
  • the size of the trenches in the substrate trench array 40 is smaller than the size of the trenches in the at least one substrate trench 30, and/or the depth of the trenches in the substrate trench array 40 It is smaller than the depth of the trench in the at least one substrate trench 30.
  • the foregoing step 220 may specifically be: preparing an electrode layer above the laminated structure 120, the electrode layer including at least one first conductive region and at least one second conductive region that are separated from each other, and the first conductive region forms the The first external electrode 130, and the second conductive area forms the second external electrode 140.
  • the method 200 further includes:
  • the interconnection structure 160 includes at least one insulating layer 163, the first conductive via structure 161 and the second conductive via structure 162, and the at least one insulating layer 163 is disposed on the surface of the stacked structure 120. Above, the first conductive via structure 161 and the second conductive via structure 162 penetrate the at least one insulating layer 163.
  • the laminated structure 220 includes: a first conductive layer 1201, a second conductive layer 1202, a third conductive layer 1203, and a fourth conductive layer 1203.
  • the above step 210 and step 220 may specifically be the preparation process shown in step 1a to step 1n (FIGS. 9a-9n) to prepare the capacitor 100 shown in FIG. 5.
  • the capacitor 100 as shown in Figs. 1 and 4 can also be prepared, which can refer to the capacitor preparation process shown in steps 1a to 1n (Figs. 9a-9n).
  • FIG. 9a-9n the capacitor preparation process shown in steps 1a to 1n
  • Step 1a select a heavily doped single crystal silicon wafer as the semiconductor substrate 110, as shown in FIG. 9a, that is, the semiconductor substrate 110 is conductive;
  • Step 1b deposit an etching stop layer on the upper surface of the semiconductor substrate 110 as shown in FIG. 9a, and perform a photolithography process to form an etching stop structure 150, as shown in FIG. 9b;
  • Step 1c deposit a first dielectric layer 1211 on the upper surface of the semiconductor substrate 110 and the etch stop structure 150, and deposit a first conductive layer 1201 on the upper surface of the first dielectric layer 1211, as shown in FIG. 9c Shown
  • Step 1d using patterning techniques such as photolithography, nanoimprinting, and laser direct writing, to form a mask layer of pattern A on the upper surface of the first conductive layer 1201, and then use an etching process on the first conductive layer 1201
  • a first isolation trench 11 is prepared.
  • the first isolation trench 11 divides the first conductive layer 1201 into two conductive regions that are electrically isolated from each other, as shown in FIG. 9d, a top view of the first isolation trench 11 It can be as shown in Figure 2 above;
  • step 1e firstly, a second dielectric layer 1212 is deposited on the upper surface of the first conductive layer 1201, the sidewalls and bottom of the first isolation trench 11, and the second dielectric layer 1212 is conductive to the first layer.
  • the layer 1201 is conformal, and then, a second conductive layer 1202 is deposited on the upper and inner surfaces of the second dielectric layer 1212, and the second conductive layer 1202 fills the first isolation trench 11, as shown in FIG. 9e Shown
  • Step 1f using patterning techniques such as photolithography, nanoimprinting, and laser direct writing, to form a mask layer of pattern B on the upper surface of the second conductive layer 1202, and then use an etching process on the second conductive layer 1202
  • a second isolation trench 12 is prepared above, and the second isolation trench 12 divides the second conductive layer 1202 into two conductive regions electrically isolated from each other, as shown in FIG. 9f;
  • step 1g firstly, a third dielectric layer 1213 is deposited on the upper surface of the second conductive layer 1202, the sidewalls and bottom of the first isolation trench 12, and the third dielectric layer 1213 is conductive to the second layer.
  • the layer 1202 is conformal.
  • a third conductive layer 1203 is deposited on the upper and inner surfaces of the third dielectric layer 1213, and the third conductive layer 1203 fills the second isolation trench 12, as shown in FIG. 9g Shown
  • Step 1h using patterning techniques such as photolithography, nanoimprinting, and laser direct writing, to form a mask layer of pattern A on the upper surface of the third conductive layer 1203, and then use an etching process on the third conductive layer 1203
  • a third isolation trench 13 is prepared above, and the third isolation trench 13 divides the third conductive layer 1203 into two conductive regions electrically isolated from each other, as shown in FIG. 9h;
  • Step 1i firstly, a fourth dielectric layer 1214 is deposited on the upper surface of the third conductive layer 1203, the sidewalls and bottom of the third isolation trench 13, and the fourth dielectric layer 1214 is conductive to the third layer.
  • the layer 1203 is conformal.
  • a fourth conductive layer 1204 is deposited on the upper and inner surfaces of the fourth dielectric layer 1214, and the fourth conductive layer 1204 fills the third isolation trench 13, as shown in FIG. 9i Shown
  • Step 1j using patterning techniques such as photolithography, nanoimprinting, and laser direct writing, to form a mask layer of pattern B on the upper surface of the fourth conductive layer 1204, and then use an etching process on the fourth conductive layer 1204
  • a fourth isolation trench 14 is prepared above, and the fourth isolation trench 14 divides the fourth conductive layer 1204 into two conductive regions electrically isolated from each other, as shown in FIG. 9j;
  • step 1k first, a fifth dielectric layer 1215 is deposited on the upper surface of the fourth conductive layer 1204, the sidewalls and bottom of the fourth isolation trench 14, and the fifth dielectric layer 1215 is conductive to the fourth layer.
  • the layer 1204 is conformal.
  • a fifth conductive layer 1205 is deposited on the upper and inner surfaces of the fifth dielectric layer 1215, and the fifth conductive layer 1205 fills the fourth isolation trench 14, as shown in FIG. 9k Shown
  • Step 11 Use patterning techniques such as photolithography, nanoimprinting, and laser direct writing to form a mask layer of pattern A on the upper surface of the fifth conductive layer 1205, and then use an etching process to form a mask layer on the fifth conductive layer 1205.
  • a fifth isolation trench 15 is prepared above, and the fifth isolation trench 15 divides the fifth conductive layer 1205 into two conductive regions electrically isolated from each other, as shown in FIG. 91;
  • an insulating layer 163 is deposited on the upper surface of the fifth conductive layer 1205 and in the fifth isolation trench 15.
  • the first conductive via structure 161 and The second conductive via structure 162 the first conductive via structure 161 penetrates the second isolation trench 12 and the fourth isolation trench 14, and extends to the upper surface of the etch stop structure 150, the second conductive The via structure 162 penetrates the first isolation trench 11, the third isolation trench 13 and the fifth isolation trench 15, and extends into the semiconductor substrate 110, thereby preparing an interconnection structure 160, as shown in FIG. 9n;
  • a first external electrode 130 and a second external electrode 140 are prepared above the interconnect structure 160, wherein the first external electrode 130 is electrically connected to all the n-layer conductive layers through the first conductive via structure 161 An odd-numbered conductive layer, the second external electrode 140 is electrically connected to the semiconductor substrate 110 and all even-numbered conductive layers in the n-layer conductive layer through the second conductive via structure 162, as shown in FIG. 5.
  • the laminated structure 220 includes: a first conductive layer 1201, a second conductive layer 1202, a third conductive layer 1203, and a fourth conductive layer 1203; One conductive layer 1204, and a first dielectric layer 1211, a second dielectric layer 1212, a third dielectric layer 1213, and a fourth dielectric layer 1214.
  • the above-mentioned step 210 and step 220 may specifically be the preparation process shown in step 2a to step 21 (FIGS. 10a-10l) to prepare the capacitor 100 as shown in FIG. 7.
  • the capacitor 100 as shown in FIG. 3 and FIG. 6 can also be prepared, which can refer to the capacitor preparation process shown in step 2a to step 21 (FIGS. 10a-10l).
  • FIG. 3 and FIG. 6 can also be prepared, which can refer to the capacitor preparation process shown in step 2a to step 21 (FIGS. 10a-10l).
  • Step 2a selecting a high-resistance silicon wafer as the semiconductor substrate 110, as shown in FIG. 10a;
  • step 2b a layer of photoresist is spin-coated on the upper surface of the semiconductor substrate 110 as shown in FIG. 10a, and after exposure and development, the substrate trench 30 and the substrate trench array 40 are produced by dry etching, and The high-temperature diffusion process forms heavily doped conductive regions on the inner wall of the substrate trench 30, the inner wall of the substrate trench array 40 and the upper surface of the semiconductor substrate 110, as shown in FIG. 10b;
  • Step 2c depositing a first dielectric layer 1211 on the upper surface of the semiconductor substrate 110, the substrate trench 30 and the substrate trench array 40, and depositing a first dielectric layer on the upper surface of the first dielectric layer 1211
  • a conductive layer 1201 the first dielectric layer 1211 is conformal to the semiconductor substrate 110, and the first conductive layer 1201 fills the substrate trench 30 and the substrate trench array 40, as shown in FIG. 10c Show
  • Step 2d using patterning techniques such as photolithography, nanoimprinting, and laser direct writing, to form a mask layer of pattern A on the upper surface of the first conductive layer 1201, and then use an etching process on the first conductive layer 1201
  • the first isolation trench 11 divides the first conductive layer 1201 into two conductive regions electrically isolated from each other.
  • the first trench array 21 The size of the trench is smaller than the size of the first isolation trench 11, and the depth of the trench in the first trench array 21 is smaller than the depth of the first isolation trench 11.
  • the first isolation trench The top view of the trench 11 may be as shown in Figure 2 above;
  • Step 2e first, deposit a second dielectric layer 1212 on the upper surface of the first conductive layer 1201, the sidewalls and bottom of the first isolation trench 11, and the sidewalls and bottom of the first trench array 21,
  • the second dielectric layer 1212 is conformal to the first conductive layer 1201.
  • a second conductive layer 1202 is deposited on the upper and inner surfaces of the second dielectric layer 1212, and the second conductive layer 1202 will The first isolation trench 11 and the first trench array 21 are filled, as shown in FIG. 10e;
  • Step 2f using patterning techniques such as photolithography, nanoimprinting, and laser direct writing, to form a mask layer of pattern B on the upper surface of the second conductive layer 1202, and then use an etching process on the second conductive layer 1202
  • a second isolation trench 12 and a second trench array 22 are prepared above.
  • the second isolation trench 12 divides the second conductive layer 1202 into two conductive regions electrically isolated from each other.
  • the size of the trench of is smaller than the size of the second isolation trench 12, and the depth of the trench in the second trench array 22 is smaller than the depth of the second isolation trench 12, as shown in FIG. 10f;
  • Step 2g first, deposit a third dielectric layer 1213 on the upper surface of the second conductive layer 1202, the sidewalls and bottom of the first isolation trench 12, and the sidewalls and bottom of the second trench array 22,
  • the third dielectric layer 1213 is conformal to the second conductive layer 1202.
  • a third conductive layer 1203 is deposited on the upper and inner surfaces of the third dielectric layer 1213, and the third conductive layer 1203 will The second isolation trench 12 and the second trench array 22 are filled, as shown in FIG. 10g;
  • Step 2h using patterning techniques such as photolithography, nanoimprinting, laser direct writing, etc., to form a mask layer of pattern A on the upper surface of the third conductive layer 1203, and then use an etching process on the third conductive layer 1203
  • the third isolation trench 13 divides the third conductive layer 1203 into two conductive regions that are electrically isolated from each other.
  • the size of the trench is smaller than the size of the third isolation trench 13, and the depth of the trench in the third trench array 23 is smaller than the depth of the third isolation trench 13, as shown in FIG. 10h;
  • Step 2i First, deposit a fourth dielectric layer 1214 on the upper surface of the third conductive layer 1203, the sidewalls and bottom of the third isolation trench 13, the sidewalls and bottom of the second trench array 22, The fourth dielectric layer 1214 is conformal to the third conductive layer 1203. Then, a fourth conductive layer 1204 is deposited on the upper and inner surfaces of the fourth dielectric layer 1214, and the fourth conductive layer 1204 will The third isolation trench 13 and the third trench array 23 are filled, as shown in FIG. 10i;
  • Step 2j using patterning techniques such as photolithography, nanoimprinting, laser direct writing, etc., to form a mask layer of pattern C on the upper surface of the fourth conductive layer 1204.
  • pattern C has only grooves Array related patterns, and then use an etching process to prepare a fourth isolation trench 14 on the fourth conductive layer 1204.
  • the fourth isolation trench 14 divides the fourth conductive layer 1204 into two electrically isolated conductive layers. Area, as shown in Figure 10j;
  • an insulating layer 163 is deposited on the upper surface of the fourth conductive layer 1204 and in the fourth isolation trench 14, as shown in FIG. 10k, the first conductive via structure 161 and The second conductive via structure 162, the first conductive via structure 161 penetrates the second isolation trench 12 and the fourth isolation trench 14, and extends into the substrate trench 30, the second conductive via The structure 162 penetrates the first isolation trench 11 and the third isolation trench 13, and extends into the heavily doped conductive region formed by diffusion on the semiconductor substrate 110, thereby preparing an interconnection structure 160, as shown in FIG. 101;
  • Step 21 Prepare a first external electrode 130 and a second external electrode 140 above the interconnect structure 160, wherein the first external electrode 130 is electrically connected to all the n-layer conductive layers through the first conductive via structure 161 Odd-numbered conductive layers, the second external electrode 140 is electrically connected to the semiconductor substrate 110 and all even-numbered conductive layers in the n-layer conductive layer through the second conductive via structure 162, as shown in FIG. 7.
  • the trench capacitor is prepared in the conductive layer in the laminated structure, and multiple photolithography and film deposition steps with consistent parameters are repeatedly used to reduce the Multi-layer conductive layer alignment accuracy requirements can increase the number of stacked capacitor layers while maintaining low processing costs, and further increase the capacitance density of capacitors.
  • a capacitor as shown in FIG. 5 is fabricated in the first embodiment.
  • the capacitor manufacturing method in the first embodiment can also be used to manufacture capacitors as shown in Figs. 1 and 4, but there are some differences in the laminated structure and the arrangement of the semiconductor substrate. Repeat it again.
  • a capacitor as shown in FIG. 7 is produced.
  • the capacitor manufacturing method in the second embodiment can also be used to manufacture capacitors as shown in FIGS. 3 and 6, but there are some differences in the laminated structure and the arrangement of the semiconductor substrate. For the sake of brevity, I will not Repeat it again.
  • Step 1 Choose a heavily doped single crystal silicon wafer as the substrate.
  • Step 2 Depositing a layer of silicon carbide (SiC) as an etching stop layer on the surface of the substrate, and performing photolithography processing to form an etching stop structure.
  • SiC silicon carbide
  • Step 3 First, use a Low Pressure Chemical Vapor Deposition (LPCVD) process to deposit a layer of silicon oxynitride (SiON) as the first dielectric layer on the surface of the substrate. Next, a layer of heavily doped polysilicon is deposited as the first conductive layer by LPCVD process.
  • LPCVD Low Pressure Chemical Vapor Deposition
  • Step 4 Spin coating a layer of photoresist on the surface of the first conductive layer, and after exposure and development, dry etching is used to form the first isolation trench.
  • the first isolation trench divides the first conductive layer into two electrically isolated regions.
  • Step 5 Depositing a layer of SiON as the second dielectric layer on the surface of the first conductive layer and the sidewall and bottom of the first isolation trench. Next, a layer of heavily doped polysilicon is deposited as the second conductive layer by an LPCVD process, and the second conductive layer fills the first isolation trench.
  • Step 6 Spin-coating a layer of photoresist on the surface of the second conductive layer, and after exposure and development, dry etching is used to form a second isolation trench.
  • the second isolation trench is aligned with the etch stop structure formed in step two.
  • Step 7 Repeat steps 3 to 6 several times.
  • Step 8 Using a plasma-enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process, a layer of silicon oxide is deposited on the surface of the nth conductive layer as an intermetallic dielectric layer.
  • PECVD plasma-enhanced chemical vapor deposition
  • Step 9 Spin-coating a layer of photoresist on the surface of the intermetallic dielectric layer, and after exposure and development, dry etching is used to make two via holes.
  • One of the via holes penetrates the odd-numbered isolation trenches and reaches the substrate depth; the other via hole penetrates the even-numbered isolation trenches, and the depth stops at the etching stop structure.
  • Step 10 First, use a Metal-organic Chemical Vapor Deposition (MOCVD) process to fill the via holes with metal tungsten to form a vertical conductive channel. Then, a chemical mechanical polishing (CMP) process is used to remove excess tungsten on the surface. Then physical vapor deposition (Physical Vapor Deposition, PVD) a layer of Ti/TiN, a layer of Al, and finally photolithography to form two electrodes.
  • MOCVD Metal-organic Chemical Vapor Deposition
  • CMP chemical mechanical polishing
  • Step 1 Select a high-resistance silicon wafer as the substrate.
  • Step 2 Spin-coating a layer of photoresist on the surface of the wafer, and after exposure and development, dry etching is used to produce substrate grooves and substrate groove arrays.
  • the substrate trench has a larger opening size than the substrate trench array, when the trenches of two sizes are simultaneously formed by dry etching, the depth of the substrate trench is deeper than that of the substrate trench array.
  • BSG boro-silicate glass
  • Step 3 First, use an Atomic layer deposition (ALD) process to deposit a layer of Al 2 O 3 as the first dielectric layer, and then use an LPCVD process to deposit a thick layer of heavily doped polysilicon to connect the substrate trench and the substrate The trench array is filled up as the first conductive layer.
  • ALD Atomic layer deposition
  • Step 4 Spin-coating a layer of photoresist on the surface of the first conductive layer, and after exposure and development, dry etching is used to fabricate the first isolation trench and the first trench array. Wherein, the depth of the first isolation trench reaches the first dielectric layer, which separates the first conductive layer into two electrical isolation regions; the first trench array is located inside the first conductive layer.
  • Step 5 First use ALD process to deposit a layer of Al 2 O 3 as the second dielectric layer, and then use LPCVD process to deposit a thick layer of heavily doped polysilicon to fill the first isolation trench and the first trench array as the first Two conductive layers.
  • Step 6 Spin-coating a layer of photoresist on the surface of the second conductive layer, and after exposure and development, dry etching is used to form a second isolation trench and a second trench array. Wherein, the depth of the second isolation trench reaches the second dielectric layer; the second trench array is located inside the second conductive layer.
  • Step 7 Repeat steps 3 to 6 to sequentially fabricate a third dielectric layer, a third conductive layer, a third isolation trench, and a third trench array.
  • Step 8 First use ALD process to deposit a layer of Al 2 O 3 as the fourth dielectric layer, and then use LPCVD process to deposit a thick layer of heavily doped polysilicon to fill the third isolation trench and the third trench array as the first Four conductive layers.
  • Step 9 Using photolithography and etching processes, a fourth isolation trench is formed on the fourth conductive layer, and the depth of the trench reaches the fourth dielectric layer.
  • Step ten using a PECVD process to deposit a layer of silicon oxide as an intermetallic dielectric layer on the surface of the fourth conductive layer.
  • Step 11 Spin-coating a layer of photoresist on the surface of the intermetallic dielectric layer, and after exposure and development, dry etching is used to make two via holes.
  • One of the via holes vertically penetrates the odd-numbered isolation trenches and reaches the depth of the substrate trench filled with the first conductive layer; the other via hole penetrates the even-numbered isolation trenches and reaches the liner depth.
  • Step 12 First, use the MOCVD process to fill the via hole with metal tungsten to form a vertical conductive channel. Then the CMP process is used to remove excess tungsten on the surface. Then PVD a layer of Ti/TiN, a layer of Al, and finally lithography to form two electrodes.

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Abstract

本申请实施例提供一种电容器及其制作方法，电容器包括：半导体衬底；叠层结构，包括n层导电层和m层电介质层，第i层导电层中设置有至少一个第i隔离沟槽，第i+1层导电层设置于第i层导电层的上方和至少一个第i隔离沟槽内，奇数层导电层中的隔离沟槽在竖直方向上存在第一重叠区域，偶数层导电层中的隔离沟槽在竖直方向上存在第二重叠区域，第一重叠区域与第二重叠区域不重叠，m、n、i为正整数，且n≥2，1≤i≤n-1；至少一个第一外接电极通过设置于第二重叠区域内的第一导电通孔结构电连接至所有奇数层导电层；至少一个第二外接电极通过设置于第一重叠区域内的第二导电通孔结构电连接至所有偶数层导电层。

Description

电容器及其制作方法 技术领域
本申请涉及电容器领域，并且更具体地，涉及电容器及其制作方法。
背景技术
电容器在电路中可以起到旁路、滤波、去耦等作用，是保证电路正常运转的不可或缺的一部分。随着现代电子系统不断向多功能、高集成、低功耗、微型化发展，传统的多层陶瓷电容(Multi-layer Ceramic Capacitors，MLCC)已经难以满足应用端日益严苛的小体积、高容量的需求。如何制备小体积、高容量的电容器，成为一个亟待解决的技术问题。
发明内容
本申请实施例提供一种电容器及其制作方法，能够制备小体积、高容值密度的电容器。
第一方面，提供了一种电容器，所述电容器包括：
半导体衬底；
叠层结构，设置于所述半导体衬底的上方，包括n层导电层和m层电介质层，所述n层导电层和所述m层电介质层形成导电层与电介质层彼此相邻的结构，所述n层导电层中的第i层导电层中设置有至少一个第i隔离沟槽，所述至少一个第i隔离沟槽将所述第i层导电层分割为彼此电隔离的至少两个导电区域，所述n层导电层中的第i+1层导电层设置于所述第i层导电层的上方和所述至少一个第i隔离沟槽内，奇数层导电层中的隔离沟槽在竖直方向上存在第一重叠区域，偶数层导电层中的隔离沟槽在竖直方向上存在第二重叠区域，所述第一重叠区域与所述第二重叠区域不重叠，m、n、i为正整数，且n≥2，1≤i≤n-1；
至少一个第一外接电极，所述第一外接电极通过第一导电通孔结构电连接至所述n层导电层中的所有奇数层导电层，所述第一导电通孔结构设置于所述第二重叠区域内；
至少一个第二外接电极，所述第二外接电极通过第二导电通孔结构电连接至所述n层导电层中的所有偶数层导电层，所述第二导电通孔结构设置于 所述第一重叠区域内。
在一些可能的实现方式中，所述n层导电层中的第n层导电层中设置有至少一个第n隔离沟槽，所述至少一个第n隔离沟槽将所述第n层导电层分割为彼此电隔离的至少两个导电区域。
在一些可能的实现方式中，
所述n层导电层中不同的奇数层导电层上所形成的隔离沟槽的数量和/或尺寸相同；和/或，
所述n层导电层中不同的偶数层导电层上所形成的隔离沟槽的数量和/或尺寸相同。
在一些可能的实现方式中，
所述n层导电层中不同的奇数层导电层上所形成的隔离沟槽在竖直方向上完全重叠；和/或，
所述n层导电层中不同的偶数层导电层上所形成的隔离沟槽在竖直方向上完全重叠。
在一些可能的实现方式中，所述n层导电层中的第i层导电层在第i隔离沟槽的周围设置有第i沟槽阵列，所述n层导电层中的第i+1层导电层设置于所述第i沟槽阵列内。
在一些可能的实现方式中，所述第i沟槽阵列中的沟槽的尺寸小于所述第i隔离沟槽的尺寸，和/或，所述第i沟槽阵列中的沟槽的深度小于所述第i隔离沟槽的深度。
在一些可能的实现方式中，在所述n层导电层中，不同的导电层上所形成的沟槽阵列中沟槽的数量和/或尺寸相同。
在一些可能的实现方式中，在所述n层导电层中，不同的导电层上所形成的沟槽阵列在竖直方向上完全重叠。
在一些可能的实现方式中，所述第二外接电极还通过所述第二导电通孔结构电连接至所述半导体衬底。
在一些可能的实现方式中，所述半导体衬底由电阻率小于阈值的材料形成，或者，所述半导体衬底的表面形成有重掺杂的电阻率小于阈值的导电层或者导电区域。
在一些可能的实现方式中，所述电容器还包括：刻蚀停止结构，设置于所述半导体衬底的上表面，以防止所述第一导电通孔结构与所述半导体衬底 电连接。
在一些可能的实现方式中，所述刻蚀停止结构在所述半导体衬底上的投影大于或者等于所述第二重叠区域。
在一些可能的实现方式中，所述半导体衬底包括至少一个衬底沟槽，所述至少一个衬底沟槽自所述半导体衬底的上表面向下进入所述半导体衬底，所述n层导电层中的第一层导电层设置于所述至少一个衬底沟槽内。
在一些可能的实现方式中，
所述至少一个衬底沟槽中的沟槽数量与所述n层导电层中的偶数层导电层中设置的隔离沟槽的数量相同；和/或，
所述至少一个衬底沟槽中的沟槽尺寸与所述n层导电层中的偶数层导电层中设置的隔离沟槽的尺寸相同。
在一些可能的实现方式中，所述至少一个衬底沟槽在所述半导体衬底上的投影大于或者等于所述第二重叠区域。
在一些可能的实现方式中，所述半导体衬底还包括设置于所述至少一个衬底沟槽周围的衬底沟槽阵列，所述衬底沟槽阵列自所述半导体衬底的上表面向下进入所述半导体衬底，所述n层导电层中的第一层导电层设置于所述衬底沟槽阵列内。
在一些可能的实现方式中，所述衬底沟槽阵列中的沟槽的尺寸小于所述至少一个衬底沟槽中的沟槽的尺寸，和/或，所述衬底沟槽阵列中的沟槽的深度小于所述至少一个衬底沟槽中的沟槽的深度。
在一些可能的实现方式中，所述电容器还包括：电极层，设置于所述叠层结构的上方，所述电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，所述第一导电区域形成所述第一外接电极，所述第二导电区域形成所述第二外接电极。
在一些可能的实现方式中，所述电容器还包括：互联结构，包括至少一层绝缘层、所述第一导电通孔结构和所述第二导电通孔结构，所述至少一层绝缘层设置于所述叠层结构的上方，所述第一导电通孔结构和所述第二导电通孔结构贯穿所述至少一层绝缘层。
在一些可能的实现方式中，所述导电层包括以下中的至少一层：
重掺杂多晶硅层，碳层，铝层，铜层，钨层，钛层，钽层，铂层，镍层，钌层，铱层，铑层，氮化钽层，氮化钛层，氮化铝钛层，氮化硅钽层，氮化 碳钽层。
在一些可能的实现方式中，所述电介质层包括以下中的至少一层：
硅的氧化物层，硅的氮化物层，硅的氮氧化物层，金属的氧化物层，金属的氮化物层，金属的氮氧化物层。
第二方面，提供了一种电容器的制作方法，包括：
在半导体衬底上方制备叠层结构，所述叠层结构包括n层导电层和m层电介质层，所述n层导电层和所述m层电介质层形成导电层与电介质层彼此相邻的结构，所述n层导电层中的第i层导电层中设置有至少一个第i隔离沟槽，所述至少一个第i隔离沟槽将所述第i层导电层分割为彼此电隔离的至少两个导电区域，所述n层导电层中的第i+1层导电层设置于所述第i层导电层的上方和所述至少一个第i隔离沟槽内，奇数层导电层中的隔离沟槽在竖直方向上存在第一重叠区域，偶数层导电层中的隔离沟槽在竖直方向上存在第二重叠区域，所述第一重叠区域与所述第二重叠区域不重叠，m、n、i为正整数，且n≥2，1≤i≤n-1；
制备至少一个第一外接电极和至少一个第二外接电极，其中，所述第一外接电极通过第一导电通孔结构电连接至所述n层导电层中的所有奇数层导电层，所述第二外接电极通过第二导电通孔结构电连接至所述n层导电层中的所有偶数层导电层，所述第一导电通孔结构设置于所述第二重叠区域内，所述第二导电通孔结构设置于所述第一重叠区域内。
在一些可能的实现方式中，所述n层导电层中的第n层导电层中设置有至少一个第n隔离沟槽，所述至少一个第n隔离沟槽将所述第n层导电层分割为彼此电隔离的至少两个导电区域。
在一些可能的实现方式中，
所述n层导电层中不同的奇数层导电层上所形成的隔离沟槽的数量和/或尺寸相同；和/或，
所述n层导电层中不同的偶数层导电层上所形成的隔离沟槽的数量和/或尺寸相同。
在一些可能的实现方式中，
所述n层导电层中不同的奇数层导电层上所形成的隔离沟槽在竖直方向上完全重叠；和/或，
所述n层导电层中不同的偶数层导电层上所形成的隔离沟槽在竖直方向 上完全重叠。
在一些可能的实现方式中，所述n层导电层中的第i层导电层在第i隔离沟槽的周围设置有第i沟槽阵列，所述n层导电层中的第i+1层导电层设置于所述第i沟槽阵列内。
在一些可能的实现方式中，所述第i沟槽阵列中的沟槽的尺寸小于所述第i隔离沟槽的尺寸，和/或，所述第i沟槽阵列中的沟槽的深度小于所述第i隔离沟槽的深度。
在一些可能的实现方式中，在所述n层导电层中，不同的导电层上所形成的沟槽阵列中沟槽的数量和/或尺寸相同。
在一些可能的实现方式中，在所述n层导电层中，不同的导电层上所形成的沟槽阵列在竖直方向上完全重叠。
在一些可能的实现方式中，所述第二外接电极还通过所述第二导电通孔结构电连接至所述半导体衬底。
在一些可能的实现方式中，所述半导体衬底由电阻率小于阈值的材料形成，或者，所述半导体衬底的表面形成有重掺杂的电阻率小于阈值的导电层或者导电区域。
在一些可能的实现方式中，所述方法还包括：
制备刻蚀停止结构，所述刻蚀停止结构设置于所述半导体衬底的上表面，以防止所述第一导电通孔结构与所述半导体衬底电连接。
在一些可能的实现方式中，所述刻蚀停止结构在所述半导体衬底上的投影大于或者等于所述第二重叠区域。
在一些可能的实现方式中，所述方法还包括：
在所述半导体衬底上制备至少一个衬底沟槽，所述至少一个衬底沟槽自所述半导体衬底的上表面向下进入所述半导体衬底，所述n层导电层中的第一层导电层设置于所述至少一个衬底沟槽内。
在一些可能的实现方式中，
所述至少一个衬底沟槽中的沟槽数量与所述n层导电层中的偶数层导电层中设置的隔离沟槽的数量相同；和/或，
所述至少一个衬底沟槽中的沟槽尺寸与所述n层导电层中的偶数层导电层中设置的隔离沟槽的尺寸相同。
在一些可能的实现方式中，所述至少一个衬底沟槽在所述半导体衬底上 的投影大于或者等于所述第二重叠区域。
在一些可能的实现方式中，所述方法还包括：
在所述半导体衬底上制备设置于所述至少一个衬底沟槽周围的衬底沟槽阵列，所述衬底沟槽阵列自所述半导体衬底的上表面向下进入所述半导体衬底，所述n层导电层中的第一层导电层设置于所述衬底沟槽阵列内。
在一些可能的实现方式中，所述衬底沟槽阵列中的沟槽的尺寸小于所述至少一个衬底沟槽中的沟槽的尺寸，和/或，所述衬底沟槽阵列中的沟槽的深度小于所述至少一个衬底沟槽中的沟槽的深度。
在一些可能的实现方式中，所述制备至少一个第一外接电极和至少一个第二外接电极，包括：
在所述叠层结构上方制备电极层，所述电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，所述第一导电区域形成所述第一外接电极，所述第二导电区域形成所述第二外接电极。
在一些可能的实现方式中，所述方法还包括：
制备互联结构，所述互联结构包括至少一层绝缘层、所述第一导电通孔结构和所述第二导电通孔结构，所述至少一层绝缘层设置于所述叠层结构的上方，所述第一导电通孔结构和所述第二导电通孔结构贯穿所述至少一层绝缘层。
因此，在本申请实施例中，在叠层结构中的导电层中制备沟槽式电容器，重复使用多个参数一致的光刻和薄膜沉积步骤，降低叠层结构中的多层导电层对准精度要求，可以在维持较低加工成本的同时，提高堆叠的电容层数，进一步增加电容器的容值密度。
进一步地，在本申请实施例中，不需要多次光刻形成用于互联结构进行电连接的台阶结构，可以减少制备电容器所需的光刻次数，降低工艺难度，以及降低电容器制备成本。
附图说明
图1是本申请提供的一种电容器的示意性结构图。
图2是根据本申请实施例的第一隔离沟槽的示意图。
图3是根据本申请实施例的又一种电容器的示意性结构图。
图4是根据本申请实施例的再一种电容器的示意性结构图。
图5是根据本申请实施例的再一种电容器的示意性结构图。
图6是根据本申请实施例的一种半导体衬底的示意性结构图。
图7是根据本申请实施例的又一种半导体衬底的示意性结构图。
图8是根据本申请实施例的一种电容器的制作方法的示意性流程图。
图9a至图9n是本申请实施例的一种电容器的制作方法的示意图。
图10a至图10l是本申请实施例的一种电容器的制作方法的示意图。
具体实施方式
下面将结合附图，对本申请实施例中的技术方案进行描述。
应理解，本申请实施例的电容器在电路中可以起到旁路、滤波、去耦等作用。
本申请实施例所述的电容器可以是3D硅电容器，3D硅电容器是一种基于半导体晶圆加工技术的新型电容器。与传统的MLCC(多层陶瓷电容)相比，3D硅电容器具有小尺寸、高精度、高稳定性、长寿命等优点。其基本的加工流程需要先在晶圆或衬底上加工出高深宽比的深孔(Via)、沟槽(Trench)、柱状(Pillar)、墙状(Wall)等3D结构，接着在3D结构表面沉积绝缘薄膜和低电阻率导电材料依次制作电容的下电极、电介质层和上电极。
借助于先进的半导体加工工艺，制作超薄型、高可靠性的电容器已经成为可能。为了提高容值密度，现有硅电容一般采用多层堆叠的技术方案。通过在三维结构表面制作垂直堆叠的2-3个电容器，再利用金属互联结构将多个电容并联。然而，多层硅电容的整个制作流程涉及多个步骤的光刻和沉积步骤，加工成本因此较为昂贵。
在此背景下，本申请提出了一种新型的电容器的结构和制作方法，通过重复使用多个参数一致的光刻和薄膜沉积步骤，可以在维持较低加工成本的同时，提高堆叠的电容器层数，进一步增加电容器的容值密度。
以下，结合图1至图7，详细介绍本申请实施例的电容器。
应理解，图1至图7中的电容器仅仅只是示例，叠层结构所包括的导电层的数量以及电介质层的数量仅仅只是示例，叠层结构所包括的导电层的数量以及电介质层的数量并不局限于图1至图7中的电容器所示，可以根据实际需要灵活设置。
需要说明的是，为便于理解，在以下示出的实施例中，对于不同实施例 中示出的结构中，相同的结构采用相同的附图标记，并且为了简洁，省略对相同结构的详细说明。
图1是本申请一个实施例的电容器100的一种可能的结构图。如图1所示，该电容器100包括半导体衬底110、叠层结构120、至少一个第一外接电极130、至少一个第二外接电极140。
具体地，如图1所示，在该电容器100中，该叠层结构120设置于该半导体衬底110的上方，该叠层结构120包括n层导电层和m层电介质层，该n层导电层和该m层电介质层形成导电层与电介质层彼此相邻的结构，该n层导电层中的第i层导电层设置有至少一个第i隔离沟槽，该至少一个第i隔离沟槽将该第i层导电层分割为彼此电隔离的至少两个导电区域，该n层导电层中的第i+1层导电层设置于该第i层导电层的上方和该至少一个第i隔离沟槽内，奇数层导电层中的隔离沟槽在竖直方向上存在第一重叠区域，偶数层导电层中的隔离沟槽在竖直方向上存在第二重叠区域，该第一重叠区域与该第二重叠区域不重叠，m、n、i为正整数，且n≥2，1≤i≤n-1；该第一外接电极130通过第一导电通孔结构161电连接至该n层导电层中的所有奇数层导电层，该第一导电通孔结构161设置于所述第二重叠区域内；该第二外接电极140通过第二导电通孔结构162电连接至该n层导电层中的所有偶数层导电层，该第二导电通孔结构162设置于该第一重叠区域内。
可选地，该n层导电层中的第n层导电层中设置有至少一个第n隔离沟槽，该至少一个第n隔离沟槽将该第n层导电层分割为彼此电隔离的至少两个导电区域。
可选地，在该叠层结构120中，同一导电层中所设置的不同的隔离沟槽的横截面的形状可以相同，也可以不同。
需要说明的是，本申请实施例中图1是沿着半导体衬底纵向的截面。
在本申请实施例中，该n层导电层中的奇数层导电层中的隔离沟槽在竖直方向上存在第一重叠区域，且第二导电通孔结构162设置于该第一重叠区域内，从而，第二外接电极140可以通过该第二导电通孔结构162电连接至该n层导电层中的所有偶数层导电层。同理，该n层导电层中的偶数层导电层中的隔离沟槽在竖直方向上存在第二重叠区域，且第一导电通孔结构161设置于该第二重叠区域内，从而，第一外接电极130可以通过该第一导电通孔结构161电连接至该n层导电层中的所有奇数层导电层。该第一重叠区域 与该第二重叠区域不重叠，可以防止该第一外接电极130与该第二外接电极140之间出现短路现象。
在本申请实施例中，在叠层结构中的导电层中制备沟槽式电容器，重复使用多个参数一致的光刻和薄膜沉积步骤，降低叠层结构中的多层导电层对准精度要求，可以在维持较低加工成本的同时，提高堆叠的电容层数，进一步增加电容器的容值密度。
进一步地，在本申请实施例中，不需要多次光刻形成用于互联结构进行电连接的台阶结构，可以减少制备电容器所需的光刻次数，降低工艺难度，以及降低电容器制备成本。
需要说明的是，在该n层导电层中，奇数层导电层中的隔离沟槽在竖直方向上存在第一重叠区域，也可以理解为，奇数层导电层中的隔离沟槽在该半导体衬底110上的投影存在第一重叠区域。同理，偶数层导电层中的隔离沟槽在竖直方向上存在第二重叠区域，也可以理解为，偶数层导电层中的隔离沟槽在该半导体衬底110上的投影存在第二重叠区域。该第一重叠区域与该第二重叠区域不重叠，也可以理解为，奇数层导电层中的隔离沟槽在该半导体衬底110上的投影与偶数层导电层中的隔离沟槽在该半导体衬底110上的投影之间不存在重叠区域。
可选地，在该叠层结构120中，导电层中所设置的隔离沟槽可以为长和宽尺寸相差较大的沟槽，或者还可以是柱状(Pillar)或墙状(Wall)3D结构。这里横截面可以理解为与半导体衬底110表面平行的截面，而图1中则是沿着半导体衬底110纵向的截面。
在本申请实施例中，该n层导电层中相邻的两个导电层通过电介质层电隔离，以及m和n的具体数值可以根据实际需要灵活配置，只需满足该n层导电层中相邻两个导电层之间电隔离。
例如，在该半导体衬底110不参与形成电容器100的电极板的情况下，该叠层结构120中的第一层导电层可以直接设置在该半导体衬底110的上表面，即n＝m+1。
又例如，在该半导体衬底110参与形成电容器100的电极板的情况下，该叠层结构120中的第一层导电层与该半导体衬底110之间需要设置电介质层，以隔离该第一层导电层和该半导体衬底110，即n＝m。
应理解，本申请实施例中外接电极也可以称之为焊盘或者外接焊盘。
可选地，在本申请实施例中，该半导体衬底110可以为硅晶圆，包括单晶硅、多晶硅、不定形硅。该半导体衬底110也可以是别的半导体衬底，包括绝缘衬底上的硅(Silicon-On-Insulator，SOI)晶圆，碳化硅(SiC)、氮化镓(GaN)、砷化镓(GaAs)等III-V族元素的化合物半导体晶圆；或者是玻璃衬底；或者是有机聚合物衬底；或者表面包含外延层、氧化层、掺杂层、键合层的衬底。
需要注意的是，在本申请实施例中，该半导体衬底110的厚度也可以根据实际需要灵活设置，例如，在该半导体衬底110的厚度因太厚而不能满足需求时，可以对该半导体衬底110进行减薄处理。
可选地，该第一外接电极130和该第二外接电极140的材料可以是金属，例如铜、铝等。该第一外接电极130和该第二外接电极140还可以包含低电阻率的Ti，TiN，Ta，TaN层作为黏附层和/或阻挡层；还可能包含位于外接电极表面的一些金属层，例如Ni、Pd(钯)、Au、Sn(锡)、Ag，用于后续打线或焊接工艺。
可选地，本申请实施例中，该导电层包括以下中的至少一层：
重掺杂多晶硅层，碳层，铝层，铜层，钨层，钛层，钽层，铂层，镍层，钌层，铱层，铑层，氮化钽层，氮化钛层，氮化铝钛层，氮化硅钽层，氮化碳钽层。
也就是说，该叠层结构120中的导电层的材料可以是重掺杂多晶硅，碳，铝(Al)、钨(W)、铜(Cu)、钛(Ti)、钽(Ta)、铂(Pt)、钌(Ru)、铱(Ir)、铑(Rh)、镍(Ni)等金属，氮化钽(TaN)、氮化钛(TiN)、氮化铝钛(TiAlN)、氮化硅钽(TaSiN)、氮化碳钽(TaCN)等低电阻率化合物，或者上述材料的组合、叠层结构。具体导电材料和层厚可根据电容器的容值、频率特性、损耗等需求来调整。当然，该叠层结构120中的导电层还可以包括一些其他的导电材料，本申请实施例对此不作限定。
可选地，本申请实施例中，该电介质层包括以下中的至少一层：
硅的氧化物层，硅的氮化物层，硅的氮氧化物层，金属的氧化物层，金属的氮化物层和金属的氮氧化物层。
也就是说，该叠层结构120中的电介质层的材料可以是硅的氧化物，硅的氮化物，硅的氮氧化物，金属的氧化物，金属的氮化物，金属的氮氧化物。例如SiO 2，SiN，SiON，或者高介电常数(high-k)材料，包括Al 2O 3，HfO 2， ZrO 2，TiO 2，Y 2O 3，La 2O 3，HfSiO 4，LaAlO 3，SrTiO 3，LaLuO 3等。该叠层结构120中的电介质层可以是一层或包含多个叠层，可以是一种材料或多种材料的组合、混合。具体绝缘材料和层厚可根据电容器的容值、频率特性、损耗等需求来调整。当然，该叠层结构120中的电介质层还可以包括一些其他的绝缘材料，本申请实施例对此不作限定。
需要说明的是，在该叠层结构120中，该m层电介质层的顺序是：在半导体衬底110上，与半导体衬底110的距离从小到大的顺序。同理，该n层导电层的顺序是：在半导体衬底110上，与半导体衬底110的距离从小到大的顺序。
需要说明的是，该第一外接电极130通过第一导电通孔结构161电连接至该n层导电层中的所有奇数层导电层，以及该第二外接电极140通过第二导电通孔结构162电连接至该n层导电层中的所有偶数层导电层，从而可以避免多次光刻形成多个台阶结构，以及第一外接电极130和第二外接电极140通过多个台阶结构与导电层分别电连接，减少光刻步骤，降低制备电容器的成本。
进一步地，该第一外接电极130电连接至该n层导电层中的所有奇数层导电层，以及该第二外接电极140电连接至该n层导电层中的所有偶数层导电层，从而可以充分发挥叠层结构增加电容器的容值密度的效果。
作为一个示例，假设该电容器100包括叠层结构，记为叠层结构1，以及包括2个第一外接电极和2个第二外接电极，2个第一外接电极分别记为第一外接电极A和第一外接电极B，2个第二外接电极分别记为第二外接电极C和第二外接电极D，以及该叠层结构1包括5层导电层和4层电介质层，5层导电层依次分别记为导电层1、导电层2、导电层3、导电层4和导电层5，4层电介质层依次分别记为电介质层1、电介质层2、电介质层3和电介质层4。
具体地，该第一外接电极A电连接该导电层1、该导电层3和该导电层5，该第一外接电极B也电连接该导电层1、该导电层3和该导电层5，该第二外接电极C电连接该导电层2和该导电层4，该第二外接电极D也电连接该导电层2和该导电层4，则针对该第一外接电极A与该第二外接电极C对应的电容器，该导电层1与该导电层2形成电容器1，容值记为C1，该导电层2与该导电层3形成电容器2，容值记为C2，该导电层3与该导电层4形 成电容器3，容值记为C3，该导电层4与该导电层5形成电容器4，容值记为C4，电容器1、电容器2、电容器3和电容器4并联，其等效电容i的容值记为Ci，则Ci＝C1+C2+C3+C4；则针对该第一外接电极B与该第二外接电极D对应的电容器，该导电层1与该导电层2形成电容器1，容值记为C1，该导电层2与该导电层3形成电容器2，容值记为C2，该导电层3与该导电层4形成电容器3，容值记为C3，该导电层4与该导电层5形成电容器4，容值记为C4，电容器1、电容器2、电容器3和电容器4并联，其等效电容j的容值记为Cj，则Cj＝C1+C2+C3+C4。当然，针对该第一外接电极A与该第二外接电极D对应的电容器也可以形成类似的串并联结构，针对该第一外接电极B与该第二外接电极C对应的电容器也可以形成类似的串并联结构，在此不再赘述。
在本申请实施例中，重复使用多个参数一致的光刻和薄膜沉积步骤来制备叠层结构120，例如，该叠层结构120中的所有奇数层导电层采用相同的刻蚀参数，该叠层结构120中的所有偶数层导电层采用相同的刻蚀参数，从而，降低了该叠层结构120中的多层导电层的对准精度要求。
可选地，在本申请实施例中，该n层导电层中不同的奇数层导电层上所形成的隔离沟槽的数量和/或尺寸相同；和/或，该n层导电层中不同的偶数层导电层上所形成的隔离沟槽的数量和/或尺寸相同。
例如，在该n层导电层中的所有奇数层导电层中，不同的导电层上设置的隔离沟槽在该半导体衬底110上的投影位置和/或投影面积相同；和/或，在该n层导电层中的所有奇数层导电层中，不同的导电层上设置的隔离沟槽的数量和/或尺寸相同。
可选地，在本申请实施例中，该n层导电层中不同的奇数层导电层上所形成的隔离沟槽在竖直方向上完全重叠；和/或，该n层导电层中不同的偶数层导电层上所形成的隔离沟槽在竖直方向上完全重叠。
例如，在该n层导电层中的所有偶数层导电层中，不同的导电层上设置的隔离沟槽在该半导体衬底110上的投影位置和/或投影面积相同；和/或，在该n层导电层中的所有偶数层导电层中，不同的导电层上设置的隔离沟槽的数量和/或尺寸相同。
可选地，在该n层导电层中的所有奇数层导电层中，不同的导电层上设置的隔离沟槽在竖直方向上完全重叠；和/或，在该n层导电层中的所有偶数 层导电层中，不同的导电层上设置的隔离沟槽在竖直方向上完全重叠。
可选地，在该n层导电层中，奇数层导电层上设置的隔离沟槽的数量与偶数层导电层上设置的隔离沟槽的数量可以相同也可以不同。
例如，如图1所示，在该n层导电层中，奇数层导电层上设置的隔离沟槽的数量等于偶数层导电层上设置的隔离沟槽的数量。
可选地，在一个实施例中，n＝5，m＝5，即该叠层结构120可以包括5层导电层，例如图1中示出的第一层导电层1201、第二层导电层1202、第三层导电层1203、第四层导电层1204和第五层导电层1205，以及5层电介质层，例如图1中示出的第一层电介质层1211、第二层电介质层1212、第三层电介质层1213、第四层电介质层1214和第五层电介质层1215。该第一层电介质层1211设置于该半导体衬底110与该第一层导电层1201之间，该第二层电介质层1212设置于该第一层导电层1201与该第二层导电层1202之间，该第三层电介质层1213设置于该第二层导电层1202与该第三层导电层1203之间，该第四层电介质层1214设置于该第三层导电层1203与该第四层导电层1204之间，该第五层电介质层1215设置于该第四层导电层1204与该第五层导电层1205之间。具体地，如图1所示，该第一层导电层1201设置有第一隔离沟槽11，该第二层导电层1202设置有第二隔离沟槽12，该第三层导电层1203设置有第三隔离沟槽13，该第四层导电层1204设置有第四隔离沟槽14，该第五层导电层1205设置有第五隔离沟槽15。该第一隔离沟槽11、该第三隔离沟槽13和该第五隔离沟槽15在竖直方向上完全重叠，以及，该第一层导电层1201、该第三层导电层1203和该第五层导电层1205上所形成的隔离沟槽的数量和/或尺寸相同。同理，该第二隔离沟槽12和该第四隔离沟槽14在竖直方向上完全重叠，以及，该第二层导电层1202和该第四层导电层1204上所形成的隔离沟槽的数量和/或尺寸相同。如图1所示，奇数层导电层中设置的隔离沟槽与偶数层导电中设置的隔离沟槽错位分布。也即，奇数层导电层中的隔离沟槽在竖直方向上存在第一重叠区域，偶数层导电层中的隔离沟槽在竖直方向上存在第二重叠区域，该第一重叠区域与该第二重叠区域不重叠。
需要说明的是，该第一隔离沟槽11的侧视图和俯视图可以如图2所示，该第三隔离沟槽13和该第五隔离沟槽15与该第一隔离沟槽11类似。
可选地，在本申请实施例中，该n层导电层中的第i层导电层在第i隔 离沟槽的周围设置有第i沟槽阵列，该n层导电层中的第i+1层导电层设置于该第i沟槽阵列内。
可选地，该第i沟槽阵列中的沟槽的尺寸小于该第i隔离沟槽的尺寸，和/或，该第i沟槽阵列中的沟槽的深度小于该第i隔离沟槽的深度。
例如，该第i沟槽阵列中的沟槽的尺寸可以为1μm，该第i隔离沟槽的尺寸可以为5μm，本申请对此不作限定。
可选地，在该n层导电层，不同的导电层上设置的沟槽阵列在该半导体衬底110上的投影位置和/或投影面积相同。
可选地，在该n层导电层中，不同的导电层上设置的沟槽阵列中沟槽的数量和/或尺寸相同。
可选地，在该n层导电层中，不同的导电层上所形成的沟槽阵列在竖直方向上完全重叠。
需要说明的是，在该n层导电层中设置的沟槽阵列中的沟槽的深宽可以根据实际需要灵活设置。优选地，该n层导电层中设置的沟槽阵列中的沟槽具有高深宽比(High aspect ratio)。同一导电层中所设置的沟槽阵列和隔离沟槽可以在同一刻蚀步骤中形成。
需要说明的是，在该n层导电层中设置沟槽阵列，可以进一步增加该叠层结构120中所形成的电容器的容值。
可选地，在一个实施例中，n＝4，m＝4，即该叠层结构120可以包括4层导电层，例如图3中示出的第一层导电层1201、第二层导电层1202、第三层导电层1203和第四层导电层1204，以及4层电介质层，例如图3中示出的第一层电介质层1211、第二层电介质层1212、第三层电介质层1213和第四层电介质层1214。该第一层电介质层1211设置于该半导体衬底110与该第一层导电层1201之间，该第二层电介质层1212设置于该第一层导电层1201与该第二层导电层1202之间，该第三层电介质层1213设置于该第二层导电层1202与该第三层导电层1203之间，该第四层电介质层1214设置于该第三层导电层1203与该第四层导电层1204之间。具体地，如图3所示，该第一层导电层1201设置有第一隔离沟槽11和第一沟槽阵列21，该第二层导电层1202设置有第二隔离沟槽12和第二沟槽阵列22，该第三层导电层1203设置有第三隔离沟槽13和第三沟槽阵列23，该第四层导电层1204设置仅有第四隔离沟槽14。如图3所示，该第一沟槽阵列21中的沟槽的尺寸 小于该第一隔离沟槽11的尺寸，该第一沟槽阵列21中的沟槽的深度小于该第一隔离沟槽11的深度；该第二沟槽阵列22中的沟槽的尺寸小于该第二隔离沟槽12的尺寸，该第二沟槽阵列22中的沟槽的深度小于该第二隔离沟槽12的深度；该第三沟槽阵列23中的沟槽的尺寸小于该第三隔离沟槽13的尺寸，该第三沟槽阵列23中的沟槽的深度小于该第三隔离沟槽13的深度。如图3所示，该第一沟槽阵列21、该第二沟槽阵列22和该第三沟槽阵列23在该半导体衬底110上的投影位置和/或投影面积相同；该第一沟槽阵列21、该第二沟槽阵列22和该第三沟槽阵列23这3个沟槽阵列中的沟槽的数量和/或尺寸相同。不同的导电层上所形成的沟槽阵列在竖直方向上可以完全重叠。
需要说明的是，该第一隔离沟槽11的侧视图和俯视图可以如上图2所示，该第三隔离沟槽13与该第一隔离沟11槽类似。
可选地，在本申请实施例中，该半导体衬底110由电阻率小于阈值的材料设置，或者，该半导体衬底110的表面设置有重掺杂的电阻率小于阈值的导电层或者导电区域。也即，该半导体衬底110导电，或者，该半导体衬底110中与该叠层结构120接触的区域导电。
需要说明的是，电阻率小于阈值的材料即可认为是导电材料。
例如，该半导体衬底110为重掺杂衬底，
又例如，也可以对该半导体衬底110进行掺杂，形成p++型或n++型的低电阻率导电层或导电区域。
再例如，在该半导体衬底110的表面沉积低电阻率导电材料，如用PVD或ALD工艺沉积TiN和/或TaN和/或Pt等金属，或者用CVD工艺，沉积重掺杂多晶硅、金属钨、碳材料。
需要说明的是，该半导体衬底110由电阻率小于阈值的材料形成即可认为该半导体衬底110为重掺杂低电阻率衬底；该半导体衬底110的表面形成有重掺杂的电阻率小于阈值的导电层即可认为该半导体衬底110的表面形成有重掺杂低电阻率导电层；该半导体衬底110的表面形成有重掺杂的电阻率小于阈值的导电区域即可认为该半导体衬底110的表面形成有重掺杂低电阻率导电区域。
可选地，在本申请实施例中，该第二外接电极140还通过该第二导电通孔结构162电连接至该半导体衬底110。
例如，如图4所示，该第二导电通孔结构162在贯穿该n层导电层中的 奇数层导电层中的隔离沟槽之后，延伸进入该半导体衬底110，该第二外接电极140通过该第二导电通孔结构162电连接至该半导体衬底110和该n层导电层中的所有偶数层导电层；该第一导电通孔结构161在贯穿该n层导电层中的偶数层导电层中的隔离沟槽之后，延伸进入该叠层结构120中的第一层导电层中。
应理解，除了该第二导电通孔结构162的设置不同之外，图4和图1的其他设置相同，为了简洁，不再赘述。
可选地，在本申请实施例中，该电容器100还包括：刻蚀停止结构150，该刻蚀停止结构150设置于该半导体衬底110的上表面，以防止该第一导电通孔结构161与该半导体衬底110电连接。具体地，如图5所示，该第一导电通孔结构161在贯穿该叠层结构120之后，延伸至该刻蚀停止结构150的上表面。
需要说明的是，在该第一导电通孔结构161与该第二导电通孔结构162在同一刻蚀步骤中形成的情况下，该刻蚀停止结构150能够有效防止该第一导电通孔结构161与该半导体衬底110电连接。
可选地，该刻蚀停止结构150在该半导体衬底110上的投影大于或者等于该第二重叠区域。以确保该刻蚀停止结构150能够防止该第一导电通孔结构161与该半导体衬底110电连接。
应理解，该刻蚀停止结构150相对于叠层结构120中的导电层和电介质层更耐刻蚀，在刻蚀该第一导电通孔结构161时，可以将该第一导电通孔结构161的底部停留在该刻蚀停止结构150上。
可选地，该刻蚀停止结构150可以是化学气相淀积(Chemical Vapor Deposition，CVD)工艺沉积的氧化硅、氮化硅、含硅玻璃(未掺杂硅玻璃(Undoped Silicon Glass，USG)、硼硅玻璃(boro-silicate glass，BSG)、磷硅玻璃(phospho-silicateglass，PSG)、硼磷硅玻璃(boro-phospho-silicateglass，BPSG))；还可以是原子层沉积(Atomic layer deposition，ALD)沉积的氧化铝；或者是喷涂、旋涂的旋转涂布玻璃(Spin on glass，SOG)、聚酰亚胺(Polyimide)等；还可以是上述材料的组合。
应理解，除了该第一导电通孔结构161和该刻蚀停止结构150的设置不同之外，图5和图4的其他设置相同，为了简洁，不再赘述。
可选地，在本申请实施例中，如图6所示，该半导体衬底110包括至少 一个衬底沟槽30，该至少一个衬底沟槽30自该半导体衬底110的上表面向下进入该半导体衬底110，该n层导电层中的第一层导电层设置于该至少一个衬底沟槽内。
可选地，该至少一个衬底沟槽30中的沟槽数量与该n层导电层中的偶数层导电层中设置的隔离沟槽的数量相同；和/或，该至少一个衬底沟槽30中的沟槽尺寸与该n层导电层中的偶数层导电层中设置的隔离沟槽的尺寸相同。
可选地，该至少一个衬底沟槽30在该半导体衬底110上的投影大于或者等于该第二重叠区域。
应理解，除了未设置该至少一个衬底沟槽30之外，图6和图3的其他设置相同，为了简洁，不再赘述。
可选地，如图7所示，该半导体衬底110还包括设置于该至少一个衬底沟槽周围的衬底沟槽阵列，该衬底沟槽阵列自该半导体衬底110的上表面向下进入该半导体衬底110，该n层导电层中的第一层导电层设置于该衬底沟槽阵列内。
可选地，该衬底沟槽阵列40中的沟槽的尺寸小于该至少一个衬底沟槽30中的沟槽的尺寸，和/或，该衬底沟槽阵列40中的沟槽的深度小于该至少一个衬底沟槽30中的沟槽的深度。
应理解，除了未设置该衬底沟槽阵列40之外，图7和图6的其他设置相同，为了简洁，不再赘述。
可选地，在本申请实施例中，该电容器100还包括互联结构160，其中，该互联结构160包括至少一层绝缘层163、该第一导电通孔结构161和该第二导电通孔结构162。如图1至图7所示，该至少一层绝缘层163设置于该叠层结构120的上方，该第一导电通孔结构161和该第二导电通孔结构162贯穿该至少一层绝缘层163。
需要说明的是，该至少一层绝缘层163也可以称之为金属间介质层(IMD)或者层间介质层(ILD)。该第一导电通孔结构161和该第二导电通孔结构162也可以称之为导电通道。
可选地，该至少一层绝缘层163包覆该叠层结构120，以及该至少一层绝缘层163可以填充该叠层结构120上表面形成的空腔或者空隙，以提升电容器的结构完整性和机械稳定性。
可选地，该至少一层绝缘层163的材料可以是有机的聚合物材料，包括聚酰亚胺(Polyimide)，帕里纶(Parylene)，苯并环丁烯(BCB)等；也可以是一些无机材料，包括旋转涂布玻璃(Spin on glass，SOG)，未掺杂硅玻璃(Undoped Silicon Glass，USG)，硼硅玻璃(boro-silicate glass，BSG)，磷硅玻璃(phospho-silicateglass，PSG)，硼磷硅玻璃(boro-phospho-silicateglass，BPSG)，由四乙氧基硅烷(Tetraethyl Orthosilicate，TEOS)合成的硅氧化物，硅的氧化物、氮化物，陶瓷；还可以是上述材料的组合或者叠层。
可选地，该第一导电通孔结构161和该第二导电通孔结构162的材料可以由低电阻率导电材料构成，例如重掺杂多晶硅，钨，Ti，TiN，Ta，TaN。
应理解，该第一导电通孔结构161和该第二导电通孔结构162的形状和数量可以根据该电容器100的制作工艺具体确定，本申请实施例对此不作限定。
可选地，在一些实施例中，该至少一个第一外接电极130和该至少一个第二外接电极140设置于该叠层结构120的上方。可选地，该电容器100还包括：电极层，设置于该叠层结构120的上方，该电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，该第一导电区域形成该第一外接电极130，该第二导电区域形成该第二外接电极140，具体如图1至图7所示。也即，该至少一个第一外接电极130和该至少一个第二外接电极140可以通过一次刻蚀形成，减少了刻蚀步骤。
具体地，如图1至图7所示，该电极层设置于该互联结构160的上方，该第一外接电极130通过该第一导电通孔结构161电连接至该叠层结构120中的奇数层导电层，该第二外接电极140通过该第二导电通孔结构162电连接至该叠层结构120中的偶数层导电层。
在本申请实施例中，在半导体衬底和导电层中分别制作沟槽式电容器，可以重复使用制作单个电容的工艺，降低多层导电层对准精度要求，能够在不增加工艺难度的情况下进一步提高电容器的容值密度。
以上描述了本申请实施例的电容器，下面描述本申请实施例的制备电容器的方法。本申请实施例的制备电容器的方法可以制备前述本申请实施例的电容器，下述实施例和前述实施例中的相关描述可以相互参考。
以下，结合图8，详细介绍本申请实施例的电容器的制作方法。
应理解，图8是本申请实施例的电容器的制作方法的示意性流程图，但 这些步骤或操作仅是示例，本申请实施例还可以执行其他操作或者图8中的各个操作的变形。
图8示出了根据本申请实施例的电容器的制作方法200的示意性流程图。如图8所示，该电容器的制作方法200包括：
步骤210，在半导体衬底上方制备叠层结构，该叠层结构包括n层导电层和m层电介质层，该n层导电层和该m层电介质层形成导电层与电介质层彼此相邻的结构，该n层导电层中的第i层导电层中设置有至少一个第i隔离沟槽，该至少一个第i隔离沟槽将该第i层导电层分割为彼此电隔离的至少两个导电区域，该n层导电层中的第i+1层导电层设置于该第i层导电层的上方和该至少一个第i隔离沟槽内，奇数层导电层中的隔离沟槽在竖直方向上存在第一重叠区域，偶数层导电层中的隔离沟槽在竖直方向上存在第二重叠区域，该第一重叠区域与该第二重叠区域不重叠，m、n、i为正整数，且n≥2，1≤i≤n-1；
步骤220，制备至少一个第一外接电极和至少一个第二外接电极，其中，该第一外接电极通过第一导电通孔结构电连接至该n层导电层中的所有奇数层导电层，该第二外接电极通过第二导电通孔结构电连接至该n层导电层中的所有偶数层导电层，该第一导电通孔结构设置于该第二重叠区域内，该第二导电通孔结构设置于该第一重叠区域内。
可选地，该n层导电层中的第n层导电层中设置有至少一个第n隔离沟槽，该至少一个第n隔离沟槽将该第n层导电层分割为彼此电隔离的至少两个导电区域。
具体地，基于上述步骤210-220可以制备如图1至图7所示的电容器。
应理解，步骤210-220中所述的各材料层的上表面是指该材料层与半导体衬底上表面基本平行的表面，而各材料层的内表面是指位于沟槽内材料层的上表面，上表面和内表面可以视为一个整体。
可选地，该n层导电层中不同的奇数层导电层上所形成的隔离沟槽的数量和/或尺寸相同；和/或，该n层导电层中不同的偶数层导电层上所形成的隔离沟槽的数量和/或尺寸相同。
例如，在该n层导电层中的所有奇数层导电层中，不同的导电层上所形成的隔离沟槽的数量和/或尺寸相同；和/或，在该n层导电层中的所有偶数层导电层中，不同的导电层上所形成的隔离沟槽的数量和/或尺寸相同。
可选地，该n层导电层中不同的奇数层导电层上所形成的隔离沟槽在竖直方向上完全重叠；和/或，该n层导电层中不同的偶数层导电层上所形成的隔离沟槽在竖直方向上完全重叠。
例如，在该n层导电层中的所有奇数层导电层中，不同的导电层上所形成的隔离沟槽在竖直方向上完全重叠；和/或，在该n层导电层中的所有偶数层导电层中，不同的导电层上所形成的隔离沟槽在竖直方向上完全重叠。
也即，该n层导电层中的所有奇数层导电层可以采用相同的光刻和沉积工艺，该n层导电层中的所有偶数层导电层可以采用相同的光刻和沉积工艺，从而，可以降低工艺复杂度和加工成本。
可选地，该n层导电层中的第i层导电层在第i隔离沟槽的周围设置有第i沟槽阵列，该n层导电层中的第i+1层导电层设置于该第i沟槽阵列内。也即，该n层导电层中的第n层导电层中未设置沟槽阵列。
可选地，该第i沟槽阵列中的沟槽的尺寸小于该第i隔离沟槽的尺寸，和/或，该第i沟槽阵列中的沟槽的深度小于该第i隔离沟槽的深度。
例如，该第i沟槽阵列中的沟槽的尺寸可以为1μm，该第i隔离沟槽的尺寸可以为5μm，本申请对此不作限定。
需要说明的是，由于该第i隔离沟槽的尺寸较大，在同一刻蚀步骤中同时形成该第i隔离沟槽和该第i沟槽阵列时，该第i隔离沟槽的深度较该第i沟槽阵列更深。也即，该第i沟槽阵列未贯穿该第i层导电层。
可选地，在该n层导电层中，不同的导电层上所形成的沟槽阵列中沟槽的数量和/或尺寸相同。
可选地，在该n层导电层中，不同的导电层上所形成的沟槽阵列在竖直方向上完全重叠。
也即，可以采用相同的刻蚀参数，以使不同的导电层上所形成的沟槽阵列中沟槽的数量和/或尺寸相同。
当然，在该n层导电层中，不同的导电层上所形成的沟槽阵列中沟槽的数量和/或尺寸也可以不相同，例如，奇数层导电层上所形成的沟槽阵列中沟槽的数量和/或尺寸与偶数层导电层上所形成的沟槽阵列中沟槽的数量和/或尺寸不相同，本申请实施例对此并不限定。
可选地，该第二外接电极140还通过该第二导电通孔结构162电连接至该半导体衬底110。也即，该半导体衬底110导电，或者，该半导体衬底110 中与该叠层结构120接触的区域导电。
可选地，该半导体衬底110由电阻率小于阈值的材料形成，或者，该半导体衬底110的表面形成有重掺杂的电阻率小于阈值的导电层或者导电区域。
需要说明的是，在该第二外接电极140通过该第二导电通孔结构162电连接至该半导体衬底110的情况下，该第二导电通孔结构162在贯穿该n层导电层中的奇数层导电层中的隔离沟槽之后，延伸进入该半导体衬底110，该第二外接电极140通过该第二导电通孔结构162电连接至该半导体衬底110和该n层导电层中的所有偶数层导电层；该第一导电通孔结构161在贯穿该n层导电层中的偶数层导电层中的隔离沟槽之后，延伸进入该叠层结构120中的第一层导电层中。
可选地，在本申请实施例中，该方法200还包括：
制备刻蚀停止结构150，该刻蚀停止结构150设置于该半导体衬底110的上表面，以防止该第一导电通孔结构161与该半导体衬底110电连接。
需要说明的是，在该第二外接电极140通过该第二导电通孔结构162电连接至该半导体衬底110的情况下，该刻蚀停止结构150可以防止该第一导电通孔结构161延伸进入该半导体衬底110。尤其是，在该第一导电通孔结构161与该第二导电通孔结构162在同一刻蚀步骤中形成的情况下，该刻蚀停止结构150能够有效防止该第一导电通孔结构161与该半导体衬底110电连接。
可选地，该刻蚀停止结构150在该半导体衬底110上的投影大于或者等于该第二重叠区域。以确保该刻蚀停止结构150能够防止该第一导电通孔结构161与该半导体衬底110电连接。
可选地，该方法200还包括：
在该半导体衬底110上制备至少一个衬底沟槽30，该至少一个衬底沟槽30自该半导体衬底110的上表面向下进入该半导体衬底110，该n层导电层中的第一层导电层设置于该至少一个衬底沟槽内。
需要说明的是，在该第二外接电极140通过该第二导电通孔结构162电连接至该半导体衬底110的情况下，该第一导电通孔结构161延伸进入该至少一个衬底沟槽30，从而，该至少一个衬底沟槽30可以防止该第一导电通孔结构161延伸进入该半导体衬底110。尤其是，在该第一导电通孔结构161与该第二导电通孔结构162在同一刻蚀步骤中形成的情况下，该至少一个衬 底沟槽30能够有效防止该第一导电通孔结构161与该半导体衬底110电连接。
可选地，该至少一个衬底沟槽30中的沟槽数量与该n层导电层中的偶数层导电层中设置的隔离沟槽的数量相同；和/或，该至少一个衬底沟槽30中的沟槽尺寸与该n层导电层中的偶数层导电层中设置的隔离沟槽的尺寸相同。
可选地，该至少一个衬底沟槽30在该半导体衬底110上的投影大于或者等于该第二重叠区域。
可选地，该方法200还包括：
在该半导体衬底110上制备设置于该至少一个衬底沟槽30周围的衬底沟槽阵列40，该衬底沟槽阵列40自该半导体衬底110的上表面向下进入该半导体衬底110，该n层导电层中的第一层导电层设置于该衬底沟槽阵列40内。
可选地，该衬底沟槽阵列40中的沟槽的尺寸小于该至少一个衬底沟槽30中的沟槽的尺寸，和/或，该衬底沟槽阵列40中的沟槽的深度小于该至少一个衬底沟槽30中的沟槽的深度。
可选地，上述步骤220具体可以是：在该叠层结构120上方制备电极层，该电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，该第一导电区域形成该第一外接电极130，该第二导电区域形成该第二外接电极140。
可选地，该方法200还包括：
制备互联结构160，该互联结构160包括至少一层绝缘层163、该第一导电通孔结构161和该第二导电通孔结构162，该至少一层绝缘层163设置于该叠层结构120的上方，该第一导电通孔结构161和该第二导电通孔结构162贯穿该至少一层绝缘层163。
可选地，在一个实施例中，假设m＝5，n＝5，即该叠层结构220包括：第一层导电层1201、第二层导电层1202、第三层导电层1203、第四层导电层1204和第五层导电层1205，以及第一层电介质层1211、第二层电介质层1212、第三层电介质层1213、第四层电介质层1214和第五层电介质层1215。在这一实施例中，上述步骤210和步骤220具体可以是如步骤1a至步骤1n(图9a-9n)所示的制备流程，以制备如图5所示的电容器100。当然，也可 以制备如图1和图4所示的电容器100，其可以参考如步骤1a至步骤1n(图9a-9n)所示的电容器制备流程，为了简洁，在此不再赘述。
步骤1a，选取重掺杂单晶硅晶圆作为半导体衬底110，如图9a所示，即该半导体衬底110导电；
步骤1b，在如图9a所示的半导体衬底110的上表面沉积刻蚀停止层，并进行光刻处理，以形成刻蚀停止结构150，如图9b所示；
步骤1c，在该半导体衬底110和该刻蚀停止结构150的上表面沉积第一层电介质层1211，以及在该第一层电介质层1211的上表面沉积第一层导电层1201，如图9c所示；
步骤1d，利用光刻、纳米压印、激光直写等图形化技术在该第一层导电层1201的上表面形成图案A的掩模层，再利用刻蚀工艺在该第一层导电层1201上制备第一隔离沟槽11，该第一隔离沟槽11将该第一层导电层1201分割为彼此电隔离的两个导电区域，如图9d所示，该第一隔离沟槽11的俯视图可以如上图2所示；
步骤1e，首先，在该第一层导电层1201的上表面、该第一隔离沟槽11的侧壁和底部沉积第二层电介质层1212，该第二层电介质层1212与该第一层导电层1201共形，然后，在该第二层电介质层1212的上表面和内表面沉积第二层导电层1202，该第二层导电层1202将该第一隔离沟槽11填满，如图9e所示；
步骤1f，利用光刻、纳米压印、激光直写等图形化技术在该第二层导电层1202的上表面形成图案B的掩模层，再利用刻蚀工艺在该第二层导电层1202上制备第二隔离沟槽12，该第二隔离沟槽12将该第二层导电层1202分割为彼此电隔离的两个导电区域，如图9f所示；
步骤1g，首先，在该第二层导电层1202的上表面、该第一隔离沟槽12的侧壁和底部沉积第三层电介质层1213，该第三层电介质层1213与该第二层导电层1202共形，然后，在该第三层电介质层1213的上表面和内表面沉积第三层导电层1203，该第三层导电层1203将该第二隔离沟槽12填满，如图9g所示；
步骤1h，利用光刻、纳米压印、激光直写等图形化技术在该第三层导电层1203的上表面形成图案A的掩模层，再利用刻蚀工艺在该第三层导电层1203上制备第三隔离沟槽13，该第三隔离沟槽13将该第三层导电层1203 分割为彼此电隔离的两个导电区域，如图9h所示；
步骤1i，首先，在该第三层导电层1203的上表面、该第三隔离沟槽13的侧壁和底部沉积第四层电介质层1214，该第四层电介质层1214与该第三层导电层1203共形，然后，在该第四层电介质层1214的上表面和内表面沉积第四层导电层1204，该第四层导电层1204将该第三隔离沟槽13填满，如图9i所示；
步骤1j，利用光刻、纳米压印、激光直写等图形化技术在该第四层导电层1204的上表面形成图案B的掩模层，再利用刻蚀工艺在该第四层导电层1204上制备第四隔离沟槽14，该第四隔离沟槽14将该第四层导电层1204分割为彼此电隔离的两个导电区域，如图9j所示；
步骤1k，首先，在该第四层导电层1204的上表面、该第四隔离沟槽14的侧壁和底部沉积第五层电介质层1215，该第五层电介质层1215与该第四层导电层1204共形，然后，在该第五层电介质层1215的上表面和内表面沉积第五层导电层1205，该第五层导电层1205将该第四隔离沟槽14填满，如图9k所示；
步骤1l，利用光刻、纳米压印、激光直写等图形化技术在该第五层导电层1205的上表面形成图案A的掩模层，再利用刻蚀工艺在该第五层导电层1205上制备第五隔离沟槽15，该第五隔离沟槽15将该第五层导电层1205分割为彼此电隔离的两个导电区域，如图9l所示；
步骤1m，在该第五层导电层1205的上表面和该第五隔离沟槽15内沉积绝缘层163，如图9m所示，利用刻蚀工艺和沉积工艺制备第一导电通孔结构161和第二导电通孔结构162，该第一导电通孔结构161贯穿该第二隔离沟槽12和该第四隔离沟槽14，并延伸至该刻蚀停止结构150的上表面，该第二导电通孔结构162贯穿该第一隔离沟槽11、该第三隔离沟槽13和该第五隔离沟槽15，并延伸进入该半导体衬底110，从而制备互联结构160，如图9n所示；
步骤1n，在该互联结构160的上方制备第一外接电极130和第二外接电极140，其中，该第一外接电极130通过第一导电通孔结构161电连接至该n层导电层中的所有奇数层导电层，该第二外接电极140通过第二导电通孔结构162电连接至该半导体衬底110和该n层导电层中的所有偶数层导电层，如图5所示。
可选地，在一个实施例中，假设m＝4，n＝4，即该叠层结构220包括：第一层导电层1201、第二层导电层1202、第三层导电层1203和第四层导电层1204，以及第一层电介质层1211、第二层电介质层1212、第三层电介质层1213和第四层电介质层1214。在这一实施例中，上述步骤210和步骤220具体可以是如步骤2a至步骤2l(图10a-10l)所示的制备流程，以制备如图7所示的电容器100。当然，也可以制备如图3和图6所示的电容器100，其可以参考如步骤2a至步骤2l(图10a-10l)所示的电容器制备流程，为了简洁，在此不再赘述。
步骤2a，选取高阻硅晶圆作为半导体衬底110，如图10a所示；
步骤2b，在如图10a所示的半导体衬底110的上表面旋涂一层光刻胶，曝光、显影之后，利用干法刻蚀制作衬底沟槽30和衬底沟槽阵列40，利用高温扩散工艺，在衬底沟槽30内壁、衬底沟槽阵列40内壁和半导体衬底110上表面形成重掺杂导电区域，如图10b所示；
步骤2c，在该半导体衬底110上表面、该衬底沟槽30和该衬底沟槽阵列40内沉积第一层电介质层1211，以及在该第一层电介质层1211的上表面沉积第一层导电层1201，该第一层电介质层1211与该半导体衬底110共形，该第一层导电层1201将该衬底沟槽30和该衬底沟槽阵列40填满，如图10c所示；
步骤2d，利用光刻、纳米压印、激光直写等图形化技术在该第一层导电层1201的上表面形成图案A的掩模层，再利用刻蚀工艺在该第一层导电层1201上制备第一隔离沟槽11和第一沟槽阵列21，该第一隔离沟槽11将该第一层导电层1201分割为彼此电隔离的两个导电区域，该第一沟槽阵列21中的沟槽的尺寸小于该第一隔离沟槽11的尺寸，该第一沟槽阵列21中的沟槽的深度小于该第一隔离沟槽11的深度，如图10d所示，该第一隔离沟槽11的俯视图可以如上图2所示；
步骤2e，首先，在该第一层导电层1201的上表面、该第一隔离沟槽11的侧壁和底部、该第一沟槽阵列21的侧壁和底部沉积第二层电介质层1212，该第二层电介质层1212与该第一层导电层1201共形，然后，在该第二层电介质层1212的上表面和内表面沉积第二层导电层1202，该第二层导电层1202将该第一隔离沟槽11和该第一沟槽阵列21填满，如图10e所示；
步骤2f，利用光刻、纳米压印、激光直写等图形化技术在该第二层导电 层1202的上表面形成图案B的掩模层，再利用刻蚀工艺在该第二层导电层1202上制备第二隔离沟槽12和第二沟槽阵列22，该第二隔离沟槽12将该第二层导电层1202分割为彼此电隔离的两个导电区域，该第二沟槽阵列22中的沟槽的尺寸小于该第二隔离沟槽12的尺寸，该第二沟槽阵列22中的沟槽的深度小于该第二隔离沟槽12的深度，如图10f所示；
步骤2g，首先，在该第二层导电层1202的上表面、该第一隔离沟槽12的侧壁和底部、该第二沟槽阵列22的侧壁和底部沉积第三层电介质层1213，该第三层电介质层1213与该第二层导电层1202共形，然后，在该第三层电介质层1213的上表面和内表面沉积第三层导电层1203，该第三层导电层1203将该第二隔离沟槽12和该第二沟槽阵列22填满，如图10g所示；
步骤2h，利用光刻、纳米压印、激光直写等图形化技术在该第三层导电层1203的上表面形成图案A的掩模层，再利用刻蚀工艺在该第三层导电层1203上制备第三隔离沟槽13和第三沟槽阵列23，该第三隔离沟槽13将该第三层导电层1203分割为彼此电隔离的两个导电区域，该第三沟槽阵列23中的沟槽的尺寸小于该第三隔离沟槽13的尺寸，该第三沟槽阵列23中的沟槽的深度小于该第三隔离沟槽13的深度，如图10h所示；
步骤2i，首先，在该第三层导电层1203的上表面、该第三隔离沟槽13的侧壁和底部、该第二沟槽阵列22的侧壁和底部沉积第四层电介质层1214，该第四层电介质层1214与该第三层导电层1203共形，然后，在该第四层电介质层1214的上表面和内表面沉积第四层导电层1204，该第四层导电层1204将该第三隔离沟槽13和该第三沟槽阵列23填满，如图10i所示；
步骤2j，利用光刻、纳米压印、激光直写等图形化技术在该第四层导电层1204的上表面形成图案C的掩模层，该图案C与图案B相比仅少了沟槽阵列相关图案，再利用刻蚀工艺在该第四层导电层1204上制备第四隔离沟槽14，该第四隔离沟槽14将该第四层导电层1204分割为彼此电隔离的两个导电区域，如图10j所示；
步骤2k，在该第四层导电层1204的上表面和该第四隔离沟槽14内沉积绝缘层163，如图10k所示，利用刻蚀工艺和沉积工艺制备第一导电通孔结构161和第二导电通孔结构162，该第一导电通孔结构161贯穿该第二隔离沟槽12和该第四隔离沟槽14，并延伸进入该衬底沟槽30内，该第二导电通孔结构162贯穿该第一隔离沟槽11和该第三隔离沟槽13，并延伸进入该半 导体衬底110上扩散形成的重掺杂导电区域，从而制备互联结构160，如图10l所示；
步骤2l，在该互联结构160的上方制备第一外接电极130和第二外接电极140，其中，该第一外接电极130通过第一导电通孔结构161电连接至该n层导电层中的所有奇数层导电层，该第二外接电极140通过第二导电通孔结构162电连接至该半导体衬底110和该n层导电层中的所有偶数层导电层，如图7所示。
因此，在本申请实施例提供的电容器的制作方法中，在叠层结构中的导电层中制备沟槽式电容器，重复使用多个参数一致的光刻和薄膜沉积步骤，降低叠层结构中的多层导电层对准精度要求，可以在维持较低加工成本的同时，提高堆叠的电容层数，进一步增加电容器的容值密度。
进一步地，在本申请实施例中，不需要多次光刻形成用于互联结构进行电连接的台阶结构，可以减少制备电容器所需的光刻次数，降低工艺难度，以及降低电容器制备成本。
下面结合两个具体地实施例对本申请的电容器的制作方法作进一步说明。为了便于理解，在实施例一中制作如图5所示的电容器。当然，利用该实施例一中的电容器的制作方法还可以制作如图1和图4所示的电容器，只是在叠层结构、半导体衬底的设置等部分有所区别，为了简洁，在此不再赘述。在实施例二中制作如图7所示的电容器。当然，利用该实施例二中的电容器的制作方法还可以制作如图3和图6所示的电容器，只是在叠层结构、半导体衬底的设置等部分有所区别，为了简洁，在此不再赘述。
实施例一
步骤一：选取重掺杂单晶硅晶圆作为衬底。
步骤二：在衬底表面沉积一层碳化硅(SiC)作为刻蚀停止层，并进行光刻处理，以形成刻蚀停止结构。
步骤三：先用低压力化学气相沉积法(Low Pressure Chemical Vapor Deposition，LPCVD)工艺，在衬底表面沉积一层氮氧化硅(SiON)作为第一电介质层。接着，用LPCVD工艺沉积一层重掺杂多晶硅作为第一导电层。
步骤四：在第一导电层表面旋涂一层光刻胶，曝光显影之后，利用干法刻蚀制作第一隔离沟槽。该第一隔离沟槽将第一导电层分割成电隔离的两个区域。
步骤五：在第一导电层表面和第一隔离沟槽侧壁、底部沉积一层SiON作为第二电介质层。接着，用LPCVD工艺沉积一层重掺杂多晶硅作为第二导电层，第二导电层将第一隔离沟槽填满。
步骤六：在第二导电层表面旋涂一层光刻胶，曝光显影之后，利用干法刻蚀制作第二隔离沟槽。第二隔离沟槽与步骤二形成的刻蚀停止结构对准。
步骤七：多次重复步骤三至步骤六。
步骤八：利用等离子体增强化学的气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)工艺，在第n导电层表面沉积一层氧化硅作为金属间介质层。
步骤九：在金属间介质层表面旋涂一层光刻胶，曝光显影之后，利用干法刻蚀制作两个导通孔。其中一个导通孔，穿透编号为奇数的隔离沟槽，深度到达衬底；另一个导通孔，穿透编号为偶数的隔离沟槽，深度停在刻蚀停止结构。
步骤十：先利用金属有机化学气相沉积法(Metal-organic Chemical Vapor Deposition，MOCVD)工艺，将导通孔填满金属钨，形成垂直的导电通道。接着用化学机械研磨(CMP)工艺去除表面多余的钨。然后物理气相沉积(Physical Vapor Deposition，PVD)一层Ti/TiN，一层Al，最后光刻形成两个电极。
实施例二
步骤一：选取高阻硅晶圆作为衬底。
步骤二：在晶圆表面旋涂一层光刻胶，曝光、显影之后，利用干法刻蚀制作衬底沟槽和衬底沟槽阵列。其中，由于衬底沟槽比衬底沟槽阵列的开口尺寸大，在干法刻蚀同时形成两种尺寸的沟槽时，衬底沟槽的深度较衬底沟槽阵列更深。制作完沟槽后，在沟槽内沉积硼硅玻璃(boro-silicate glass，BSG)，利用高温扩散工艺，在衬底沟槽和衬底沟槽阵列内壁及衬底表面形成重掺杂导电区。最后去除BGS。
步骤三：先利用原子层沉积(Atomic layer deposition，ALD)工艺沉积一层Al 2O 3作为第一电介质层，接着利用LPCVD工艺沉积一层厚的重掺杂多晶硅将衬底沟槽和衬底沟槽阵列填满，作为第一导电层。
步骤四：在第一导电层表面旋涂一层光刻胶，曝光、显影之后，利用干法刻蚀制作第一隔离沟槽和第一沟槽阵列。其中，第一隔离沟槽的深度到达 第一电介质层，将第一导电层分隔成两个电隔离区域；第一沟槽阵列位于第一导电层内部。
步骤五：先利用ALD工艺沉积一层Al 2O 3作为第二电介质层，接着利用LPCVD工艺沉积一层厚的重掺杂多晶硅将第一隔离沟槽和第一沟槽阵列填满，作为第二导电层。
步骤六：在第二导电层表面旋涂一层光刻胶，曝光、显影之后，利用干法刻蚀制作第二隔离沟槽和第二沟槽阵列。其中，第二隔离沟槽的深度到达第二电介质层；第二沟槽阵列位于第二导电层内部。
步骤七：重复步骤三至步骤六，依次制作第三电介质层、第三导电层、第三隔离沟槽、第三沟槽阵列。
步骤八：先利用ALD工艺沉积一层Al 2O 3作为第4电介质层，接着利用LPCVD工艺沉积一层厚的重掺杂多晶硅将第三隔离沟槽和第三沟槽阵列填满，作为第四导电层。
步骤九：利用光刻和刻蚀工艺，在第四导电层上形成第四隔离沟槽，沟槽深度到达第四电介质层。
步骤十：利用PECVD工艺，在第四导电层表面沉积一层氧化硅作为金属间介质层。
步骤十一：在金属间介质层表面旋涂一层光刻胶，曝光显影之后，利用干法刻蚀制作两个导通孔。其中一个导通孔，垂直穿透编号为奇数的隔离沟槽，深度到达填充了第一导电层的衬底沟槽；另一个导通孔，穿透编号为偶数的隔离沟槽，深度到达衬底上扩散形成的重掺杂导电区。
步骤十二：先利用MOCVD工艺，将导通孔填满金属钨，形成垂直的导电通道。接着用CMP工艺去除表面多余的钨。然后PVD一层Ti/TiN，一层Al，最后光刻形成两个电极。
本领域普通技术人员可以意识到，以上结合附图详细描述了本申请的优选实施方式，但是，本申请并不限于上述实施方式中的具体细节，在本申请的技术构思范围内，可以对本申请的技术方案进行多种简单变型，这些简单变型均属于本申请的保护范围。
另外需要说明的是，在上述具体实施方式中所描述的各个具体技术特征，在不矛盾的情况下，可以通过任何合适的方式进行组合，为了避免不必要的重复，本申请对各种可能的组合方式不再另行说明。
此外，本申请的各种不同的实施方式之间也可以进行任意组合，只要其不违背本申请的思想，其同样应当视为本申请所申请的内容。

Claims (40)

  1. 一种电容器，其特征在于，所述电容器包括：
    半导体衬底；
    叠层结构，设置于所述半导体衬底的上方，包括n层导电层和m层电介质层，所述n层导电层和所述m层电介质层形成导电层与电介质层彼此相邻的结构，所述n层导电层中的第i层导电层中设置有至少一个第i隔离沟槽，所述至少一个第i隔离沟槽将所述第i层导电层分割为彼此电隔离的至少两个导电区域，所述n层导电层中的第i+1层导电层设置于所述第i层导电层的上方和所述至少一个第i隔离沟槽内，奇数层导电层中的隔离沟槽在竖直方向上存在第一重叠区域，偶数层导电层中的隔离沟槽在竖直方向上存在第二重叠区域，所述第一重叠区域与所述第二重叠区域不重叠，m、n、i为正整数，且n≥2，1≤i≤n-1；
    至少一个第一外接电极，所述第一外接电极通过第一导电通孔结构电连接至所述n层导电层中的所有奇数层导电层，所述第一导电通孔结构设置于所述第二重叠区域内；
    至少一个第二外接电极，所述第二外接电极通过第二导电通孔结构电连接至所述n层导电层中的所有偶数层导电层，所述第二导电通孔结构设置于所述第一重叠区域内。
  2. 根据权利要求1所述的电容器，其特征在于，所述n层导电层中的第n层导电层中设置有至少一个第n隔离沟槽，所述至少一个第n隔离沟槽将所述第n层导电层分割为彼此电隔离的至少两个导电区域。
  3. 根据权利要求1或2所述的电容器，其特征在于，
    所述n层导电层中不同的奇数层导电层上所形成的隔离沟槽的数量和/或尺寸相同；和/或，
    所述n层导电层中不同的偶数层导电层上所形成的隔离沟槽的数量和/或尺寸相同。
  4. 根据权利要求1至3中任一项所述的电容器，其特征在于，
    所述n层导电层中不同的奇数层导电层上所形成的隔离沟槽在竖直方向上完全重叠；和/或，
    所述n层导电层中不同的偶数层导电层上所形成的隔离沟槽在竖直方向上完全重叠。
  5. 根据权利要求1至4中任一项所述的电容器，其特征在于，所述n层导电层中的第i层导电层在第i隔离沟槽的周围设置有第i沟槽阵列，所述n层导电层中的第i+1层导电层设置于所述第i沟槽阵列内。
  6. 根据权利要求5所述的电容器，其特征在于，所述第i沟槽阵列中的沟槽的尺寸小于所述第i隔离沟槽的尺寸，和/或，所述第i沟槽阵列中的沟槽的深度小于所述第i隔离沟槽的深度。
  7. 根据权利要求5或6所述的电容器，其特征在于，在所述n层导电层中，不同的导电层上所形成的沟槽阵列中沟槽的数量和/或尺寸相同。
  8. 根据权利要求5至7中任一项所述的电容器，其特征在于，在所述n层导电层中，不同的导电层上所形成的沟槽阵列在竖直方向上完全重叠。
  9. 根据权利要求1至8中任一项所述的电容器，其特征在于，所述第二外接电极还通过所述第二导电通孔结构电连接至所述半导体衬底。
  10. 根据权利要求9所述的电容器，其特征在于，所述半导体衬底由电阻率小于阈值的材料形成，或者，所述半导体衬底的表面形成有重掺杂的电阻率小于阈值的导电层或者导电区域。
  11. 根据权利要求9或10所述的电容器，其特征在于，所述电容器还包括：刻蚀停止结构，设置于所述半导体衬底的上表面，以防止所述第一导电通孔结构与所述半导体衬底电连接。
  12. 根据权利要求11所述的电容器，其特征在于，所述刻蚀停止结构在所述半导体衬底上的投影大于或者等于所述第二重叠区域。
  13. 根据权利要求1至10中任一项所述的电容器，其特征在于，所述半导体衬底包括至少一个衬底沟槽，所述至少一个衬底沟槽自所述半导体衬底的上表面向下进入所述半导体衬底，所述n层导电层中的第一层导电层设置于所述至少一个衬底沟槽内。
  14. 根据权利要求13所述的电容器，其特征在于，
    所述至少一个衬底沟槽中的沟槽数量与所述n层导电层中的偶数层导电层中设置的隔离沟槽的数量相同；和/或，
    所述至少一个衬底沟槽中的沟槽尺寸与所述n层导电层中的偶数层导电层中设置的隔离沟槽的尺寸相同。
  15. 根据权利要求13或14所述的电容器，其特征在于，所述至少一个衬底沟槽在所述半导体衬底上的投影大于或者等于所述第二重叠区域。
  16. 根据权利要求13至15中任一项所述的电容器，其特征在于，所述半导体衬底还包括设置于所述至少一个衬底沟槽周围的衬底沟槽阵列，所述衬底沟槽阵列自所述半导体衬底的上表面向下进入所述半导体衬底，所述n层导电层中的第一层导电层设置于所述衬底沟槽阵列内。
  17. 根据权利要求16所述的电容器，其特征在于，所述衬底沟槽阵列中的沟槽的尺寸小于所述至少一个衬底沟槽中的沟槽的尺寸，和/或，所述衬底沟槽阵列中的沟槽的深度小于所述至少一个衬底沟槽中的沟槽的深度。
  18. 根据权利要求1至17中任一项所述的电容器，其特征在于，所述电容器还包括：电极层，设置于所述叠层结构的上方，所述电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，所述第一导电区域形成所述第一外接电极，所述第二导电区域形成所述第二外接电极。
  19. 根据权利要求1至18中任一项所述的电容器，其特征在于，所述电容器还包括：互联结构，包括至少一层绝缘层、所述第一导电通孔结构和所述第二导电通孔结构，所述至少一层绝缘层设置于所述叠层结构的上方，所述第一导电通孔结构和所述第二导电通孔结构贯穿所述至少一层绝缘层。
  20. 根据权利要求1至19中任一项所述的电容器，其特征在于，所述导电层包括以下中的至少一层：
    重掺杂多晶硅层，碳层，铝层，铜层，钨层，钛层，钽层，铂层，镍层，钌层，铱层，铑层，氮化钽层，氮化钛层，氮化铝钛层，氮化硅钽层，氮化碳钽层。
  21. 根据权利要求1至20中任一项所述的电容器，其特征在于，所述电介质层包括以下中的至少一层：
    硅的氧化物层，硅的氮化物层，硅的氮氧化物层，金属的氧化物层，金属的氮化物层，金属的氮氧化物层。
  22. 一种电容器的制作方法，其特征在于，包括：
    在半导体衬底上方制备叠层结构，所述叠层结构包括n层导电层和m层电介质层，所述n层导电层和所述m层电介质层形成导电层与电介质层彼此相邻的结构，所述n层导电层中的第i层导电层中设置有至少一个第i隔离沟槽，所述至少一个第i隔离沟槽将所述第i层导电层分割为彼此电隔离的至少两个导电区域，所述n层导电层中的第i+1层导电层设置于所述第i层导电层的上方和所述至少一个第i隔离沟槽内，奇数层导电层中的隔离沟槽 在竖直方向上存在第一重叠区域，偶数层导电层中的隔离沟槽在竖直方向上存在第二重叠区域，所述第一重叠区域与所述第二重叠区域不重叠，m、n、i为正整数，且n≥2，1≤i≤n-1；
    制备至少一个第一外接电极和至少一个第二外接电极，其中，所述第一外接电极通过第一导电通孔结构电连接至所述n层导电层中的所有奇数层导电层，所述第二外接电极通过第二导电通孔结构电连接至所述n层导电层中的所有偶数层导电层，所述第一导电通孔结构设置于所述第二重叠区域内，所述第二导电通孔结构设置于所述第一重叠区域内。
  23. 根据权利要求22所述的方法，其特征在于，所述n层导电层中的第n层导电层中设置有至少一个第n隔离沟槽，所述至少一个第n隔离沟槽将所述第n层导电层分割为彼此电隔离的至少两个导电区域。
  24. 根据权利要求22或23所述的方法，其特征在于，
    所述n层导电层中不同的奇数层导电层上所形成的隔离沟槽的数量和/或尺寸相同；和/或，
    所述n层导电层中不同的偶数层导电层上所形成的隔离沟槽的数量和/或尺寸相同。
  25. 根据权利要求22至24中任一项所述的方法，其特征在于，
    所述n层导电层中不同的奇数层导电层上所形成的隔离沟槽在竖直方向上完全重叠；和/或，
    所述n层导电层中不同的偶数层导电层上所形成的隔离沟槽在竖直方向上完全重叠。
  26. 根据权利要求22至25中任一项所述的方法，其特征在于，所述n层导电层中的第i层导电层在第i隔离沟槽的周围设置有第i沟槽阵列，所述n层导电层中的第i+1层导电层设置于所述第i沟槽阵列内。
  27. 根据权利要求26所述的方法，其特征在于，所述第i沟槽阵列中的沟槽的尺寸小于所述第i隔离沟槽的尺寸，和/或，所述第i沟槽阵列中的沟槽的深度小于所述第i隔离沟槽的深度。
  28. 根据权利要求26或27所述的方法，其特征在于，在所述n层导电层中，不同的导电层上所形成的沟槽阵列中沟槽的数量和/或尺寸相同。
  29. 根据权利要求26至28中任一项所述的方法，其特征在于，在所述n层导电层中，不同的导电层上所形成的沟槽阵列在竖直方向上完全重叠。
  30. 根据权利要求22至29中任一项所述的方法，其特征在于，所述第二外接电极还通过所述第二导电通孔结构电连接至所述半导体衬底。
  31. 根据权利要求30所述的方法，其特征在于，所述半导体衬底由电阻率小于阈值的材料形成，或者，所述半导体衬底的表面形成有重掺杂的电阻率小于阈值的导电层或者导电区域。
  32. 根据权利要求30或31所述的方法，其特征在于，所述方法还包括：
    制备刻蚀停止结构，所述刻蚀停止结构设置于所述半导体衬底的上表面，以防止所述第一导电通孔结构与所述半导体衬底电连接。
  33. 根据权利要求32所述的方法，其特征在于，所述刻蚀停止结构在所述半导体衬底上的投影大于或者等于所述第二重叠区域。
  34. 根据权利要求22至31中任一项所述的方法，其特征在于，所述方法还包括：
    在所述半导体衬底上制备至少一个衬底沟槽，所述至少一个衬底沟槽自所述半导体衬底的上表面向下进入所述半导体衬底，所述n层导电层中的第一层导电层设置于所述至少一个衬底沟槽内。
  35. 根据权利要求34所述的方法，其特征在于，
    所述至少一个衬底沟槽中的沟槽数量与所述n层导电层中的偶数层导电层中设置的隔离沟槽的数量相同；和/或，
    所述至少一个衬底沟槽中的沟槽尺寸与所述n层导电层中的偶数层导电层中设置的隔离沟槽的尺寸相同。
  36. 根据权利要求34或35所述的方法，其特征在于，所述至少一个衬底沟槽在所述半导体衬底上的投影大于或者等于所述第二重叠区域。
  37. 根据权利要求34至36中任一项所述的方法，其特征在于，所述方法还包括：
    在所述半导体衬底上制备设置于所述至少一个衬底沟槽周围的衬底沟槽阵列，所述衬底沟槽阵列自所述半导体衬底的上表面向下进入所述半导体衬底，所述n层导电层中的第一层导电层设置于所述衬底沟槽阵列内。
  38. 根据权利要求37所述的方法，其特征在于，所述衬底沟槽阵列中的沟槽的尺寸小于所述至少一个衬底沟槽中的沟槽的尺寸，和/或，所述衬底沟槽阵列中的沟槽的深度小于所述至少一个衬底沟槽中的沟槽的深度。
  39. 根据权利要求22至38中任一项所述的方法，其特征在于，所述制 备至少一个第一外接电极和至少一个第二外接电极，包括：
    在所述叠层结构上方制备电极层，所述电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，所述第一导电区域形成所述第一外接电极，所述第二导电区域形成所述第二外接电极。
  40. 根据权利要求22至39中任一项所述的方法，其特征在于，所述方法还包括：
    制备互联结构，所述互联结构包括至少一层绝缘层、所述第一导电通孔结构和所述第二导电通孔结构，所述至少一层绝缘层设置于所述叠层结构的上方，所述第一导电通孔结构和所述第二导电通孔结构贯穿所述至少一层绝缘层。
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US11950430B2 (en) * 2020-10-30 2024-04-02 Ferroelectric Memory Gmbh Memory cell, capacitive memory structure, and methods thereof
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US20230059848A1 (en) * 2021-08-19 2023-02-23 Texas Instruments Incorporated Through wafer trench isolation
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120080772A1 (en) * 2010-10-04 2012-04-05 Denso Corporation Semiconductor device and method of manufacturing the same
CN102456750A (zh) * 2010-10-15 2012-05-16 台湾积体电路制造股份有限公司 用于提高电容器容量和兼容性的方法和装置
CN102969313A (zh) * 2011-08-30 2013-03-13 爱思开海力士有限公司 半导体器件及其制造方法
CN106170858A (zh) * 2014-03-25 2016-11-30 Ipdia公司 电容器结构

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4541789B2 (ja) * 2003-07-14 2010-09-08 日本特殊陶業株式会社 導体用ペースト並びにそれを用いた積層セラミックコンデンサ及び配線基板
US20090141426A1 (en) * 2007-11-29 2009-06-04 Cheol-Seong Hwang Thin film multi-layered ceramic capacitor and method of fabricating the same
TWI400731B (zh) * 2008-08-29 2013-07-01 Ind Tech Res Inst 電容元件及其製造方法
US20100224960A1 (en) * 2009-03-04 2010-09-09 Kevin John Fischer Embedded capacitor device and methods of fabrication
US8492818B2 (en) * 2010-09-14 2013-07-23 International Business Machines Corporation High capacitance trench capacitor
US9159723B2 (en) * 2013-09-16 2015-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing semiconductor device and semiconductor device
US9105759B2 (en) * 2013-11-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitive device and method of making the same
US10043863B2 (en) * 2017-01-06 2018-08-07 International Business Machines Corporation Grated MIM capacitor to improve capacitance
KR20200128315A (ko) * 2019-05-03 2020-11-12 삼성전자주식회사 반도체 소자

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120080772A1 (en) * 2010-10-04 2012-04-05 Denso Corporation Semiconductor device and method of manufacturing the same
CN102456750A (zh) * 2010-10-15 2012-05-16 台湾积体电路制造股份有限公司 用于提高电容器容量和兼容性的方法和装置
CN102969313A (zh) * 2011-08-30 2013-03-13 爱思开海力士有限公司 半导体器件及其制造方法
CN106170858A (zh) * 2014-03-25 2016-11-30 Ipdia公司 电容器结构

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