WO2020215260A1 - 电容器及其制备方法 - Google Patents

电容器及其制备方法 Download PDF

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Publication number
WO2020215260A1
WO2020215260A1 PCT/CN2019/084153 CN2019084153W WO2020215260A1 WO 2020215260 A1 WO2020215260 A1 WO 2020215260A1 CN 2019084153 W CN2019084153 W CN 2019084153W WO 2020215260 A1 WO2020215260 A1 WO 2020215260A1
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Prior art keywords
conductive layer
layer
conductive
capacitor
insulating layer
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PCT/CN2019/084153
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English (en)
French (fr)
Inventor
陆斌
沈健
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深圳市汇顶科技股份有限公司
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Priority to EP19925841.9A priority Critical patent/EP3780098A4/en
Priority to CN201980000616.XA priority patent/CN112136211A/zh
Priority to PCT/CN2019/084153 priority patent/WO2020215260A1/zh
Priority to US17/034,198 priority patent/US20210020737A1/en
Publication of WO2020215260A1 publication Critical patent/WO2020215260A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS

Definitions

  • This application relates to the field of capacitors, and more specifically, to capacitors and methods of making them.
  • Capacitors can play the role of bypassing, filtering, decoupling, etc. in the circuit, and are an indispensable part of ensuring the normal operation of the circuit.
  • the existing capacitor manufacturing technology has been unable to meet the diverse needs of various high-end applications.
  • Wafer-level three-dimensional (3D) capacitors are a new type of capacitor manufactured on silicon wafers using semiconductor processing technology in recent years. Compared with commonly used multilayer ceramic capacitors, wafer-level three-dimensional capacitors have significant advantages in terms of minimum chip thickness, frequency response, and temperature coefficient. In consumer electronics that pursue extreme device size, or medical, automotive, aerospace electronics and other fields that require strict device performance and reliability, wafer-level 3D capacitors have a very wide range of application scenarios.
  • the embodiments of the present application provide a capacitor and a manufacturing method thereof, which can improve the capacitance density of the capacitor.
  • a capacitor including:
  • the first electrode and the second electrode are The first electrode and the second electrode;
  • the laminated structure includes a first conductive layer, at least one dielectric layer, and at least one second conductive layer, the first conductive layer includes at least one slot-shaped support, the at least one dielectric layer and the at least one layer
  • the second conductive layer covers the at least one slot-shaped bracket, and the first conductive layer, the at least one dielectric layer, and the at least one second conductive layer form a structure in which the dielectric layer and the conductive layer are adjacent to each other;
  • the interconnection structure is used to connect the first electrode and the second electrode to at least two adjacent conductive layers, respectively.
  • the capacitor of the embodiment of the present application adopts a laminated structure in which conductive layers and dielectric layers are alternately stacked to form a capacitor, which can obtain a larger capacitance value with a smaller device size, thereby improving the capacitance density of the capacitor.
  • the use of the at least one trough-shaped support to prepare the laminated structure can increase the density of the laminated structure, further increase the capacitance value of the capacitor, and thus can increase the capacitance density of the capacitor.
  • a method for preparing a capacitor including:
  • At least one dielectric layer and at least one second conductive layer are prepared on the first conductive layer to obtain a laminated structure, wherein the at least one dielectric layer and the at least one second conductive layer cover the At least one slot-shaped bracket, the first conductive layer, the at least one dielectric layer, and the at least one second conductive layer form a structure in which the dielectric layer and the conductive layer are adjacent to each other;
  • a first electrode and a second electrode are prepared on the insulating structure, wherein the first electrode and the second electrode are respectively connected to at least two adjacent conductive layers.
  • the method for preparing a capacitor according to an embodiment of the present invention can obtain a laminated structure including more conductive layers and dielectric layers, and increase the capacitance value of the capacitor.
  • the use of the at least one trough-shaped support to prepare the laminated structure can increase the density of the laminated structure, further increase the capacitance value of the capacitor, and thus can increase the capacitance density of the capacitor.
  • a capacitor including:
  • a capacitor prepared according to the method described in the second aspect is a capacitor prepared according to the method described in the second aspect.
  • Fig. 1 is a schematic structural diagram of a capacitor according to an embodiment of the present application.
  • Fig. 2 is another schematic structural diagram of a capacitor according to an embodiment of the present application.
  • Fig. 3 is a partial schematic structural diagram of a modified structure of the capacitor shown in Fig. 2.
  • Fig. 4 is a partial schematic structural diagram of another modified structure of the capacitor shown in Fig. 2.
  • Fig. 5 is a schematic flowchart of a method for preparing a capacitor according to an embodiment of the present application.
  • 6 to 19 are schematic process flow diagrams for preparing the capacitor shown in FIG. 1.
  • 20 to 31 are schematic process flow diagrams for preparing the capacitor shown in FIG. 2.
  • capacitors in the embodiments of the present application can perform functions such as bypassing, filtering, and decoupling in the circuit.
  • the capacitor described in the embodiments of the present application may be a 3D silicon capacitor, which is a new type of capacitor based on semiconductor wafer processing technology. Compared with traditional multilayer ceramic capacitors (MLCC), 3D silicon capacitors have the advantages of small size, high precision, high stability, and long life.
  • the basic processing flow requires processing high-aspect-ratio deep holes (Via), trenches (Trench), pillars (Pillar), wall (Wall) and other 3D structures on the wafer or substrate first, and then in the 3D structure An insulating film and a low-resistivity conductive material are deposited on the surface to make the lower electrode, the dielectric layer and the upper electrode of the capacitor in sequence.
  • FIG. 1 is a schematic structural diagram of a capacitor 100 according to an embodiment of the present application.
  • the capacitor 100 may include a first electrode 1111, a second electrode 1112, a stacked structure 160 and an interconnection structure 190.
  • the first electrode 1111 and the second electrode 1112 are the positive and negative electrodes of the capacitor 100.
  • the first electrode 1111 and the second electrode 1112 are separated from each other to form an electrode layer.
  • the materials of the first electrode 1111 and the second electrode 1112 may adopt various conductive materials, such as metal aluminum.
  • the form of the first electrode 1111 and the second electrode 1112 can be realized in the form of a pad or a solder ball.
  • the laminated structure 160 may include a first conductive layer, at least one dielectric layer, and at least one second conductive layer.
  • the first conductive layer includes at least one trough-shaped support (also called a cup-shaped support).
  • a dielectric layer (also called an insulating layer) and the at least one second conductive layer cover the at least one trough-shaped support, the first conductive layer, the at least one dielectric layer and the at least one
  • the second conductive layer forms a structure in which the dielectric layer and the conductive layer are adjacent to each other.
  • the dielectric layer and the conductive layer are adjacent to each other can be understood as:
  • the layer adjacent to the conductive layer is a dielectric layer, and the layer adjacent to the dielectric layer is a conductive layer.
  • the upper and lower layers of the conductive layer are both dielectric layers, and the upper and lower layers of the dielectric layer are both conductive layers.
  • the plurality of trough-shaped brackets are electrically connected to each other.
  • the plurality of trough-shaped brackets are physically connected (for example, in a top view, the plurality of trough-shaped brackets constitute a "Tic Tac Toe" or grid-shaped component); in another implementation
  • the plurality of slot-shaped brackets are physically separated, and at this time, the bottoms of the plurality of slot-shaped brackets can be electrically connected, so that the plurality of slot-shaped brackets can serve as a conductive layer (that is, the The first conductive layer), the first conductive layer is used for an electrode plate (also called an electrode layer) of the capacitor 100.
  • the at least one trough-shaped bracket may be 4 trough-shaped brackets, for example, the 4 trough-shaped brackets 1611 shown in FIG. 1; at least one dielectric layer may be 2 dielectric layers For example, the dielectric layers 162 and 164 shown in FIG. 1; at least one second conductive layer may be two conductive layers, such as the conductive layers 163 and 165 shown in FIG.
  • the size of the cross-section of the trough-shaped bracket is not limited in the embodiments of the present application.
  • the trough-shaped bracket may be a hole with a small difference between the length and width of the cross-section, or it may be length and width. Trenches with a large difference in size, or may also be a pillar-shaped (Pillar) or wall-shaped (Wall) 3D structure.
  • the cross section can be understood as a cross section parallel to the opening of the trough-shaped bracket.
  • the embodiment of the present application does not specifically limit the direction of the slot-shaped bracket opening, for example, it may be vertical or inclined.
  • the dielectric layer in the stacked structure 160 may include at least one of the following:
  • the material of the dielectric layer in the laminated structure 160 can be silicon oxide, silicon nitride, silicon oxynitride, metal oxide, metal nitride, metal oxynitride, etc., such as silicon dioxide. , Silicon nitride, or high dielectric constant materials, including aluminum oxide, hafnium oxide, zirconium oxide, titanium dioxide, Y 2 O 3 , La 2 O 3 , HfSiO 4 , LaAlO 3 , SrTiO 3 , LaLuO 3, etc.; it can also be One of the above materials or a combination of multiple materials. The specific material and layer thickness of the dielectric layer can be adjusted according to the capacitance, frequency characteristics, loss and other requirements of the capacitor. Of course, the dielectric layer in the laminated structure 160 may also include some other material layers with high dielectric constant characteristics, which is not limited in the embodiment of the present application.
  • the conductive layer (for example, the first conductive layer or the stacked structure 160) in some embodiments of the present application may include at least one of the following:
  • the material of the conductive layer in the stacked structure 160 may be heavily doped polysilicon, carbon material, or aluminum, tungsten, copper, titanium (Ti), tantalum (Ta), platinum (Pt), ruthenium ( Various metals such as Ru), iridium (Ir), and rhodium (Rh) can also be low-resistivity compounds such as titanium nitride and tantalum nitride, or a laminate or combination of the aforementioned conductive materials.
  • the four slot-shaped supports 1611 electrically connected at the bottom are used as a layer of electrode plates, and dielectric layers 162 and 162 are formed on the four slot-shaped supports 1611 electrically connected at the bottom by stacking.
  • the conductive layer 163 can not only increase the surface area of the capacitor, but also because the electrode plate serves as a support for the laminated structure, the laminated density of the laminated structure can be increased, thereby increasing the capacitance density of the capacitor.
  • a slot-shaped bracket with high density and high aspect ratio it can be further used to increase the surface area and stack density.
  • the above-mentioned first conductive layer is used as a layer of electrode plate, and the dielectric layer 162 and the conductive layer 163 can be used to form a capacitor, and the conductive layer 163, the dielectric layer 164 and the conductive layer 165 can be used to form another capacitor. Further, the conductive layer 163 is electrically connected to one electrode, and the above-mentioned first conductive layer and the conductive layer 165 are electrically connected to the other electrode, thereby realizing the parallel connection of the two capacitors, thereby obtaining a capacitor with a large capacitance value. .
  • the use of a stacked structure in which conductive layers and dielectric layers are alternately stacked to form a capacitor can obtain a larger capacitance value with a smaller device size, thereby increasing the capacitance value density of the capacitor.
  • the use of the at least one trough-shaped support to prepare the laminated structure can increase the density of the laminated structure, further increase the capacitance value of the capacitor, and thus can increase the capacitance density of the capacitor.
  • the interconnection structure 190 is used to connect the first electrode 1111 and the second electrode 1112 to at least two adjacent conductive layers, respectively, to ensure that the capacitor 100 can accommodate charges.
  • two adjacent conductive layers can be understood as:
  • Two conductive layers adjacent to a dielectric layer That is, the conductive layer in contact with the upper surface of a dielectric layer and the conductive layer in contact with the lower surface of the dielectric layer.
  • first electrode 1111 and the second electrode 1112 are respectively connected to at least two adjacent conductive layers, which can be understood as:
  • the conductive layer connected by the first electrode 1111 and the conductive layer connected by the second solution 1112 are two adjacent conductive layers.
  • the interconnect structure 190 is used to electrically connect the first electrode 1111 to some or all of the odd-numbered conductive layers in the stacked structure 160, and the second electrode 1112 is electrically connected to some or all of the even-numbered conductive layers in the stacked structure 160.
  • Layer conductive layer to maximize the parallel connection of multiple capacitors in the stacked structure 160.
  • the order of the conductive layers involved can be from one side of the laminated structure 160 to the other, for example, from top to bottom or from bottom to top. order of. For ease of description, the following takes the order from bottom to top as an example for description.
  • the conductive layers 1611, 163, and 165 are the first to third conductive layers, respectively.
  • the odd-numbered conductive layers in the conductive layers 1611, 163, 165 that is, the first and third conductive layers can be electrically connected to the first electrode 1111 through the interconnection structure 190
  • the conductive layers 1611, 163, 165 The even-numbered conductive layer, that is, the second conductive layer, can be electrically connected to the second electrode 1112 through the interconnection structure 190.
  • the material of the interconnection structure 190 may use various conductive materials, which may be the same as or different from the material of the conductive layer in the stacked structure 160, for example, titanium nitride and metal tungsten may be used.
  • the capacitor 100 may further include an insulating structure for covering the laminated structure 160 to protect the laminated structure 160 and reduce interference between the laminated structure 160 and other external circuits.
  • the insulating structure covering the laminated structure 160 can be understood as:
  • the insulating structure covers at least two sides of the laminated structure 160, and is not limited to that the insulating structure needs to completely cover the laminated structure 160.
  • the insulating structure may include a first insulating layer 140 and a second insulating layer 180.
  • the upper surface of the first insulating layer 140 may be formed with a groove structure extending downward, the at least one groove-shaped bracket is disposed in the groove structure of the first insulating layer 140, and at least one second conductive layer in the laminated structure 160 The layer forms at least one first step at the edge of the opening of the groove structure of the first insulating layer 140.
  • the material of the first insulating layer 140 may be an organic polymer material, including polyimide, Parylene, benzocyclobutene (BCB), etc.; it may also be some inorganic materials, including rotating Coated glass (Spin on glass, SOG), undoped silicon glass (Undoped Silicon Glass, USG), borosilicate glass (Boro-silicate glass, BSG), phospho-silicate glass (PSG), borophosphosilicon Glass (Boro-phospho-silicate glass, BPSG), silicon oxide synthesized from Tetraethyl Orthsilicate (TEOS), silicon oxide, nitride, ceramic; it can also be a combination of the above materials.
  • organic polymer material including polyimide, Parylene, benzocyclobutene (BCB), etc.
  • inorganic materials including rotating Coated glass (Spin on glass, SOG), undoped silicon glass (Undoped Silicon Glass, USG), borosilicate glass (Boro-si
  • the dielectric layer 162, the conductive layer 163, and the dielectric layer 164 are aligned and arranged, and the conductive layer 165 and the dielectric layer 164 form a step.
  • the dielectric layer 162 and the conductive layer 163 may be aligned, the dielectric layer 164 and the conductive layer 165 are aligned, and a step is formed between the conductive layer 163 and the dielectric layer 164.
  • the second insulating layer 180 covers the first insulating layer 140 and the stacked structure 160.
  • the material of the second insulating layer 180 may be the same as or different from the material of the first insulating layer 140, which is not specifically limited in this application.
  • the aforementioned interconnection structure 190 may include a first through hole 181 and at least one second through hole 182.
  • the first through hole 181 penetrates the first insulating layer 140, the second insulating layer 180 and the insulating layer 130, and is used to electrically connect the first electrode 1111 to the first conductive layer including the slot-shaped bracket 1611. It should be understood that the capacitor 100 may not include the insulating layer 130. In this case, the first through hole 181 only needs to penetrate the first insulating layer 140 and the second insulating layer 180.
  • At least one second through hole 182 is disposed above the at least one first step and penetrates the second insulating layer 180.
  • the interconnect structure 190 is electrically connected to the stacked structure 160 through the at least one second through hole 182 Part or all of the conductive layers in at least one second conductive layer.
  • the dielectric layer 162 and the conductive layer 163 are aligned and arranged. At this time, the second opening 182 on the left side may only penetrate the second insulating layer 180.
  • the first through hole 181 and the at least one through hole 182 may be filled with a conductive material that is the same as or different from the material of the conductive layer of the stacked structure 160, and may also be provided with a wiring layer for electrically connecting the conductive layers in the stacked structure 160 , This application does not make specific restrictions on this.
  • the capacitor 100 may further include a substrate 110 disposed under the stacked structure 160 to support the stacked structure 160.
  • the substrate 110 may be a low-resistivity single crystal silicon wafer, or a semiconductor substrate, a glass substrate or an organic substrate with a low-resistivity conductive layer on the surface to ensure the electrical conductivity of the above-mentioned multiple trough-shaped supports.
  • the material of the semiconductor substrate includes but is not limited to: silicon, germanium, group III-V elements (silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), etc.), or a combination of the above different materials.
  • the semiconductor substrate may also include an epitaxial layer structure, such as a silicon-on-insulator (SOI) structure, for insulating the substrate.
  • SOI silicon-on-insulator
  • the substrate 110 may be a whole wafer or a part cut from the wafer.
  • the low-resistivity conductive layer may be heavily doped silicon, metal, TiN, TaN, carbon, or conductive organics.
  • the low-resistivity conductive layer may be a conductive layer with a resistivity lower than a preset threshold. The setting of the preset threshold allows the bottoms of the plurality of slot-shaped brackets 1611 in the laminated structure 160 to be electrically connected to serve as a conductive layer of the capacitor 100.
  • the capacitor 100 may include a third conductive layer 120 disposed between the substrate 110 and the laminated structure 160, and the third conductive layer 120 covers at least part of the substrate.
  • the third conductive layer 120 is used to electrically connect the bottoms of the four slot-shaped brackets 1611 shown in FIG. 1 so that the four slot-shaped brackets 1611 can be used as the first conductive layer of the capacitor to improve the stacking structure 160 Laminated density.
  • the capacitor 100 may further include a fourth insulating layer 130 disposed between the third conductive layer 120 and the stacked structure 160, and the fourth insulating layer 130 may At least one through hole is provided, whereby the bottom of the at least one trough-shaped bracket 1611 included in the laminated structure 160 can be arranged in the at least one through hole of the fourth insulating layer 130, thereby further ensuring that the third conductive layer 120 and the conductive layer 163 is insulated to ensure the performance of the capacitor 100.
  • the bottom of the at least one slot-shaped bracket 1611 included in the laminated structure 160 may be arranged in at least one through hole of the fourth insulating layer 130 in a one-to-one correspondence.
  • FIG. 1 is only an example of the capacitor of the present application, and should not be understood as a limitation of the present application.
  • FIG. 2 is another schematic block diagram of a capacitor 200 according to an embodiment of the present application.
  • the capacitor 200 may include a first electrode 281, a second electrode 282, a stacked structure 250 and an interconnection structure 290.
  • the laminated structure 250 may include four slot-shaped brackets 2511, a dielectric layer 252, a conductive layer 253, a dielectric layer 254 and a conductive layer 255.
  • the capacitor 200 may further include a substrate 210 to support the laminated structure 250 and electrically connect the four groove-shaped supports 2511 described above. Further, the capacitor 200 may further include a conductive layer 220 to ensure the conductivity of the four slot-shaped supports 2511 described above. Further, the capacitor 200 may further include an insulating layer 230 to further ensure the insulation between the conductive layers 220 and 253, thereby ensuring the performance of the capacitor 200.
  • the capacitor 200 can be understood as a deformed structure of the capacitor 100, in order to avoid repetition, the corresponding related description is omitted here.
  • the materials of the corresponding conductive and dielectric layers, and the corresponding working principles are omitted here.
  • the structure of the capacitor 200 will be described in detail below.
  • the capacitor 200 may include a third insulating layer 250 for covering the laminated structure 160 to protect the laminated structure 160 and reduce interference between the laminated structure 160 and other external circuits.
  • the capacitor 100 may further include a third insulation 270.
  • the third insulating layer 270 covers the laminated structure 250, and at least one second conductive layer (ie, conductive layers 2511, 252 and 255) in the laminated structure 250 has at least one second step formed in the third insulating layer 270.
  • At least one second conductive layer in the laminated structure 250 has at least one second step formed on the bottom of the third insulating layer 270 close to the groove-shaped support 2511.
  • at least one second conductive layer in the laminated structure 250 forms at least one second step on the bottom of the third insulating layer 270 near the slot-shaped bracket 2511 in a one-to-one correspondence.
  • the aforementioned interconnection structure 290 may include a third through hole 271 and at least one fourth through hole 272.
  • the third through hole 271 penetrates the third insulating layer 270 and is used to electrically connect the first electrode 281 to the first conductive layer including the slot-shaped bracket 2511 through the conductive layer 230.
  • At least one fourth through hole 272 is provided above the at least one second step and penetrates the third insulating layer 270.
  • the interconnection structure 290 may be electrically connected to at least one layer in the stacked structure 250 through the at least one second step. Part or all of the conductive layers in the second conductive layer.
  • the embodiment of the present application does not limit the implementation of the steps of at least one dielectric layer in the laminated structure 250.
  • the dielectric layer 252 and the conductive layer 253 shown in FIG. 2 are aligned, the dielectric layer 254 and the conductive layer 255 are aligned, and the conductive layer 253 and the dielectric layer 254 form a step.
  • the conductive layer 253 and the dielectric layer 254 may be aligned, and the dielectric layer 254 and the conductive layer 255 form a step.
  • the fourth through hole 272 only needs to penetrate the third insulating layer 270; if the upper surface of the second step is In the dielectric layer, the fourth through hole 272 needs to penetrate the third insulating layer 270 and the dielectric layer above the conductive layer at the same time.
  • 3 and 4 are partial schematic structural diagrams of the capacitor 200 after simple deformation.
  • the capacitor 200 includes a substrate 210 and a third conductive layer 220.
  • the slot-shaped support 2511 in the laminated structure 250 can be directly electrically connected to the third conductive layer 220, but the connection between the slot-shaped support 2511 and the third conductive layer 220 is not limited in this application.
  • the bottom of the slot-shaped bracket 2511 in the laminated structure 250 directly contacts the upper surface of the third conductive layer 220.
  • the slot-shaped bracket 2511 in the laminated structure 250 can be embedded in the third conductive layer 220 or penetrate the third conductive layer 220 to increase stability.
  • the trough-shaped bracket 2511 may or may not directly contact the substrate 210, which is not specifically limited in this application.
  • the third conductive layer 220 may be provided with at least one fifth through hole penetrating the third conductive layer 220, and the bottom of the groove-shaped bracket 251 in the laminated structure 250 may be provided on the at least one fifth through hole. Inside the through hole.
  • the capacitor 200 includes a substrate 210 and a third conductive layer 220. At this time, a groove is formed on the upper surface of the substrate 210 extending downward, and the third conductive layer 220 is disposed in the groove of the substrate 210.
  • a laminated structure in which conductive layers and insulating layers are alternately stacked can obtain a larger capacitance value with a smaller device size, thereby improving the capacitance density of the capacitor.
  • the use of the slot-shaped bracket of the first conductive layer as the frame to form a laminated structure can increase the density of the laminated structure and further increase the capacitance density of the capacitor.
  • FIGS. 1 to 4 are only examples and should not be construed as limiting the application.
  • the number of laminated layers and the number of trough-shaped brackets in the laminated structure included in the capacitor are not limited to those shown in the capacitors in FIGS. 1 to 4, and can be determined according to actual needs.
  • the present application also provides a method for preparing the capacitor 100 and the capacitor 200.
  • FIG. 5 is a schematic process flow diagram of a method 300 for preparing a capacitor according to an embodiment of the present application.
  • the method 300 may include:
  • the preparation includes firstly setting a groove-shaped support with an upward opening on the surface of the substrate. Then, a first capacitor is arranged on the cup-shaped support, including a first electrode plate layer, a first dielectric layer and a second electrode plate layer; wherein the first dielectric layer electrically isolates the first and second electrode plate layers. Then, a second capacitor is arranged on the first capacitor, including a second electrode plate layer, a second dielectric layer and a third electrode plate layer; wherein the second dielectric layer electrically isolates the second and third electrode plate layers. Finally, an interconnection structure and pads are arranged, wherein at least one pad is electrically connected to the first electrode plate layer and the third electrode plate layer, and at least one pad is electrically connected to the second electrode plate layer.
  • the method 300 mainly includes the following steps:
  • Step one select the substrate.
  • Step two first use deposition and photolithography processes to form a groove or hole-shaped mold on the upper surface of the substrate, or use an electroplating process to form a groove or hole-shaped mold on the upper surface of the substrate; then, use deposition and surface planarization And an etching (or etching) process to make a groove-shaped (or cup-shaped) support conformal to the inner wall of the mold on the upper surface of the substrate.
  • the trough-shaped bracket is made of conductive material. The bottom of the trough-shaped support is electrically connected to the low-resistance conductive area of the substrate.
  • Step 3 Set the first capacitor on the support, including the first plate layer, the first dielectric layer and the second plate layer.
  • Step 4 Set up a second capacitor on the first capacitor, including the second plate layer, the second dielectric layer and the third plate layer.
  • Step five fabricate interconnection structures and pads. At least one pad is electrically connected to the first electrode plate layer (and/or substrate) and the third electrode plate layer; at least one pad is electrically connected to the second electrode plate layer.
  • etching process may include at least one of the following processes:
  • Dry etching process, wet etching process and laser etching process dry etching process, wet etching process and laser etching process.
  • the dry etching process may include at least one of the following etching processes: reactive ion etching, plasma etching, and ion beam etching (ion beam etching). etching) etc.
  • the etching rate can be changed by changing the mixing ratio of the etching gas.
  • the chemical raw materials of the wet etching process may include, but are not limited to, an etching solution containing hydrofluoric acid.
  • an etching method combining dry etching and wet etching, or laser etching combined with wet etching can effectively ensure the shape of the etching and the flatness of the bottom surface Wait.
  • the deposition process includes but is not limited to:
  • Physical vapor deposition Physical Vapor Deposition, PVD
  • chemical vapor deposition Chemical Vapor Deposition, CVD
  • thermal oxidation Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), etc.
  • Atomic Layer Deposition ALD
  • the foregoing S310 may include part or all of the following steps:
  • Step 1 forming a first insulating layer on the substrate.
  • Step 2 forming a first groove penetrating the first insulating layer.
  • Step 3 Fill the first groove with a first material.
  • Step 4 forming at least one second groove penetrating the first material.
  • Step 5 forming a conductive layer conformal to the inner wall of the at least one second groove on the upper surface of the at least one second groove.
  • Step 6 filling the at least one second groove with a second material.
  • Step 7 removing the second material and the conductive layer above the first insulating layer.
  • Step 8 removing the second material in the at least one second groove to form the first conductive layer.
  • the foregoing S320 may include some or all of the following steps:
  • Step 9 preparing the at least one dielectric layer and the at least one second conductive layer on the first conductive layer.
  • Step 10 forming at least one first step of the at least one dielectric layer and the at least one second conductive layer on the edge of the opening of the first groove to obtain the laminated structure.
  • the foregoing S330 may include some or all of the following steps:
  • Step 11 preparing a second insulating layer on the laminated structure and the first insulating layer.
  • Step 12 forming a first through hole penetrating the first insulating layer and the second insulating layer.
  • Step 13 forming at least one second through hole passing through the second insulating layer above the at least one first step.
  • Step 14 filling the first through hole and the at least one second through hole with a conductive material.
  • the foregoing S340 may include some or all of the following steps:
  • Step 15 forming the first electrode above the first through hole and/or above the second through hole corresponding to part or all of the odd-numbered conductive layers in the laminated structure;
  • Step 16 forming the second electrode above the second through holes corresponding to part or all of the even-numbered conductive layers in the laminated structure.
  • the substrate is selected.
  • the substrate may be a low-resistivity single crystal silicon wafer, or a semiconductor substrate, a glass substrate, or an organic substrate with a low-resistivity conductive layer on the surface.
  • the following description is made by taking the substrate as a silicon wafer as an example.
  • the silicon wafer After the silicon wafer is selected, it is doped by ion implantation and annealing or diffusion, and then a conductive layer 120 with low resistivity is formed on the surface of the silicon wafer 110 to form the structure shown in FIG. 6.
  • the conductive layer 120 may cover the entire upper surface of the substrate 110 or part of the upper surface of the substrate 110. This application is not specifically limited. For ease of description, the conductive layer 120 may cover the substrate 110 below.
  • the method 300 is described as an example on the entire upper surface of.
  • the doping type of the conductive layer is opposite to the original doping type of the substrate.
  • An insulating layer 130 and a first molding material 140 are deposited on the structure shown in FIG. 6 to form the structure shown in FIG. 7.
  • the first modeling material 140 may include, but is not limited to: polysilicon, amorphous silicon, silicon oxide, silicon nitride, silicon oxynitride, TEOS, silicon-containing glass (for example, USG, BSG, PSG, BPSG), or Spin-coated SOG or organic materials, etc.
  • a photolithography process is combined with an etching process (or an etching process) to form a groove 141 with an opening upward on the upper surface of the first molding material 140 to expose the insulating layer. 130 to form the structure shown in FIG. 8.
  • the second molding material 150 is used to fill the groove 141 of the first molding material 140 to form the structure shown in FIG. 9.
  • the second molding material 150 and the first molding material 140 may be different, so that the second molding material 150 can be selectively removed.
  • the second molding material 150 can also be selectively removed in other ways, which is not specifically limited in this application.
  • a groove array (for example, 4 grooves) is made by using a photolithography process and an etching process, and each groove in the groove array penetrates the first molding material 140, The second molding material 150 and the insulating layer 130 expose the conductive layer 120 to form the structure shown in FIG. 10.
  • the number of grooves in the groove array is only an example of the present application, and should not be construed as a limitation of the present application.
  • the grooves in the groove array The number can be a value greater than 4 or less than 4, such as 0.
  • a conductive layer 161 is deposited on the upper surface (including the sidewalls and the bottom) of the above-mentioned groove array to form the structure shown in FIG. 11.
  • the conductive layer 161 and the conductive layer referred to below may use the conductive material referred to above, and to avoid repetition, it will not be repeated here.
  • the conductive layer 161 may be heavily doped polysilicon deposited by the LPCVD process, metal such as TiN, TaN, or Pt deposited by the ALD process, or carbon material deposited by the CVD process.
  • the third molding material 170 is used to fill the above-mentioned groove array to form the structure shown in FIG. 12.
  • the third molding material 170 and the first molding material 140 may be different, so that the third molding material 170 can be selectively removed.
  • the third molding material 170 can also be selectively removed in other ways, which is not specifically limited in this application.
  • a surface planarization process is then used to remove the third molding material 170 and the conductive layer 161 above the first molding material 140 to obtain the first molding material 140 (or remaining
  • the groove-shaped (also called cup-shaped) structure between the second molding material 151) and the remaining third molding material 171 forms the structure shown in FIG. 13.
  • the remaining second molding material 151 and the remaining third molding material 171 are removed, and the first molding material 140 and the insulating layer 130 are retained;
  • the above-mentioned groove-shaped structure is converted into a groove-shaped support 1611, and the bottom of the groove-shaped support 1611 is embedded with an insulating layer 130 and contacts the conductive layer 120 on the surface of the substrate 110, thereby forming the structure shown in FIG. 14.
  • a dielectric layer 162, a conductive layer 163, a dielectric layer 164 and a conductive layer 165 are sequentially deposited to form the structure shown in FIG. 15.
  • a multi-step photolithography process combined with an etching process is used to form steps of the conductive layer 163 and the conductive layer 165 to form the structure shown in FIG. 16.
  • an insulating layer 180 is first deposited to cover the steps of the conductive layer 163 and the conductive layer 165 to form the structure shown in FIG. 17.
  • a first through hole 181 is provided to expose the conductive layer 120 on the surface of the substrate 110, and at least one second through hole 182 is provided to expose the conductive layer 163 and The conductive layer 165 forms the structure shown in FIG. 18.
  • first through hole 181 and the at least one second through hole 182 may be filled with conductive material, or may be provided with a wiring layer for electrical connection.
  • first through hole 181 and the at least one The second through hole 182 may be filled with a conductive material as an example to illustrate the method of preparing a capacitor.
  • the second through hole 182 on the right needs to penetrate the insulating layer 180 and the dielectric layer 163, but the application is not limited to this. For example, assuming that the dielectric layer 163 and the conductive layer 165 are aligned, the second through hole 182 on the right only needs to penetrate the insulating layer 180.
  • the first through hole 181 and the at least one second through hole 182 are filled with a low-resistivity conductive material, and the excess conductive material above the insulating layer 180 is ground away by a surface planarization process, so that one Independent conductive channels to form the structure shown in Figure 19.
  • a conductive material is deposited on the insulating layer 180, and then a pattern is formed by photolithography to form a pad.
  • One of the pads is electrically connected to the conductive layer 163, and the other pad is electrically connected to the conductive layer 165, and is electrically connected to the trough-shaped bracket 1611 through the conductive layer 120, finally forming the structure shown in FIG. 1.
  • the pad may be metal.
  • the pad may include copper or aluminum, and may also include a low resistivity Ti, TiN, Ta, and TaN layer between the pad and the ILD as an adhesion layer and/or barrier layer; and may also include a surface of the pad.
  • Some of the metal layers, such as Ni, Pd, Au, Sn, Ag, are used for subsequent wire bonding or welding processes.
  • FIG. 6 to FIG. 19 are only an example of this application, and should not be construed as a limitation to this application.
  • the above-mentioned preparation process of the conductive layer 120 and/or the insulating layer 130 may be directly omitted. That is, the first molding material 130 is deposited directly on the substrate 110 or the conductive layer 120.
  • a photolithography process combined with an etching process can be used to fabricate a groove array (for example, 4 grooves), each of the groove arrays
  • the groove may penetrate the first molding material 140, the second molding material 150, the insulating layer 130, and the conductive layer 120 to expose the substrate 110.
  • each groove in the groove array can be embedded in the substrate 110.
  • the foregoing S310 may include part or all of the following steps:
  • Step 1 forming a third material on the substrate.
  • Step 2 forming at least one third groove penetrating the third material.
  • Step 3 forming a conductive layer conformal to the inner wall of the at least one third groove on the upper surface of the at least one third groove.
  • Step 4 Fill the at least one third groove with a fourth material.
  • Step 5 removing the fourth material and the conductive layer above the third material.
  • Step 6 removing the third material and the fourth material above the substrate to form the first conductive layer.
  • the foregoing S320 may include some or all of the following steps:
  • Step 7 preparing the at least one dielectric layer and the at least one second conductive layer on the first conductive layer.
  • Step 8 forming at least one second step of the at least one second conductive layer on the substrate to obtain the laminated structure.
  • the foregoing S330 may include some or all of the following steps:
  • Step 9 preparing a third insulating layer on the laminated structure
  • Step 10 forming a third through hole penetrating the third insulating layer
  • Step 11 forming at least one fourth through hole penetrating the third insulating layer above the at least one second step;
  • Step 12 filling the third through hole and the at least one fourth through hole with a conductive material.
  • the foregoing S340 may include some or all of the following steps:
  • Step 13 forming the first electrode above the third through hole and/or above the fourth through hole corresponding to part or all of the odd-numbered conductive layers in the laminated structure;
  • Step 14 forming the second electrode above the fourth through hole corresponding to part or all of the even-numbered conductive layers in the laminated structure.
  • a substrate 210 is selected, and a conductive layer 220 is covered on the substrate 210 to form the structure shown in FIG. 20.
  • the conductive layer 220 is covered with an insulating layer 230, and the insulating layer is covered with a fourth molding material 240 (which may be the same as or different from the above-mentioned first molding material) to form the structure shown in FIG. 21.
  • a photolithography process combined with an etching process (or an etching process)
  • the upper surface of the fourth molding material 240 is extended downward to form at least one third groove 241 that penetrates the fourth molding material 240 with an opening upward.
  • the structure shown in FIG. 22 is formed.
  • a conductive layer 251 is deposited on the upper surface of the at least one third groove 241 to form the structure shown in FIG. 23.
  • a fifth molding material 260 (which may be the same as or different from the above-mentioned first molding material) is filled in the at least one third groove to form the structure shown in FIG. 24.
  • the fifth molding material 260 and the conductive layer 251 above the third material are removed by a photolithography process combined with an etching process to form the structure shown in FIG. 25.
  • etching or etching
  • the dielectric layer 252, the conductive layer 253, the dielectric layer 254, and the conductive layer 255 are sequentially deposited to form the structure shown in FIG. 27.
  • steps of the conductive layer 253 and the conductive layer 255 are formed to form the structure shown in FIG. 28.
  • An insulating layer 270 is deposited on the conductive layer 255, the conductive layer 253, and the insulating layer 230 to form the structure shown in FIG. 29.
  • a third through hole 271 is provided to expose the conductive layer 220 on the surface of the substrate 210.
  • the third through hole 271 and the at least one fourth through hole 272 are filled with a low-resistivity conductive material, and the excess conductive material above the insulating layer 270 is ground using a surface planarization process to obtain independent conductive channels to form FIG. 31
  • a conductive material is deposited on the insulating layer 270, and then a pattern is formed by photolithography to form a pad, thereby obtaining the capacitor shown in FIG. 2.
  • FIG. 20 to FIG. 30 are only an example of this application, and should not be construed as a limitation to this application.
  • the above-mentioned preparation process of the conductive layer 220 and/or the insulating layer 230 may be directly omitted. That is, the first molding material 130 is deposited directly on the substrate 210 or the conductive layer 220.
  • the above-mentioned at least one third groove 241 may penetrate the conductive layer 220 or even be embedded in the substrate 210.
  • the application also provides a capacitor prepared according to the above preparation method.
  • the various embodiments of the method 300 for preparing capacitors listed above can be executed by robots or numerical control processing, and the device software or process used to execute the method 300 can be executed by executing computer program codes stored in the memory. To execute the above method 300.
  • the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, rather than corresponding to the embodiments of the present application.
  • the implementation process constitutes any limitation.
  • the disclosed integrated device, the components in the integrated device, and the method for preparing the integrated device can be implemented in other ways.
  • the integrated device embodiments described above are only exemplary.
  • the division of the layers is only a logical function division, and there may be other division methods in actual implementation.
  • multiple layers or devices may be combined or integrated, for example, the upper electrode plate and the active material layer may be combined into one layer. Or some features (such as the active material layer) can be ignored or not prepared.

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Abstract

一种电容器及其制备方法，该电容器包括：第一电极（1111）和第二电极（1112）；叠层结构（160），包括第一导电层、至少一层电介质层（162，164）和至少一层第二导电层（163，165），该第一导电层包括至少一个槽状支架（1611），该至少一层电介质层和该至少一层第二导电层覆盖该至少一个槽状支架，该第一导电层、该至少一层电介质层和该至少一层第二导电层形成电介质层和导电层彼此相邻的结构；互联结构（190），用于将该第一电极和该第二电极至少分别连接至相邻的两个导电层。采用导电层与电介质层交替堆叠的叠层结构，提高了电容器的容值密度，并且利用槽状支架制备该叠层结构，提高了该叠层结构的叠层密度。

Description

电容器及其制备方法 技术领域
本申请涉及电容器领域，并且更具体地，涉及电容器及其制备方法。
背景技术
电容器在电路中可以起到旁路、滤波、去耦等作用，是保证电路正常运转的不可或缺的一部分。随着现代电子系统不断向多功能、高集成、低功耗、微型化发展，现有的电容器制造技术已经难以满足各类高端应用的多样化需求。
晶圆级三维(3D)电容器是近年来出现的一种利用半导体加工技术在硅晶圆上制造的新型电容器。相比于常用的多层陶瓷电容器，晶圆级三维电容器在芯片的最小厚度、频率响应、温度系数等方面具有显著的优点。在对器件体积追求极致的消费类电子，或者对器件性能和可靠性要求严苛的医疗、车载、航天电子等领域，晶圆级3D电容器具有十分广泛的应用场景。
然而，目前晶圆级3D电容器的容值密度仍然有限，如何提高电容器的容值密度，成为一个亟待解决的技术问题。
发明内容
本申请实施例提供一种电容器及其制备方法，能够提高电容器的容值密度。
第一方面，提供了一种电容器，包括：
第一电极和第二电极；
叠层结构，包括第一导电层、至少一层电介质层和至少一层第二导电层，所述第一导电层包括至少一个槽状支架，所述至少一层电介质层和所述至少一层第二导电层覆盖所述至少一个槽状支架，所述第一导电层、所述至少一层电介质层和所述至少一层第二导电层形成电介质层和导电层彼此相邻的结构；
互联结构，用于将所述第一电极和所述第二电极至少分别连接至相邻的两个导电层。
本申请实施例的电容器，采用导电层与电介质层交替堆叠的叠层结构形 成电容器，能够在较小器件尺寸的情况下得到较大的电容值，从而能够提高电容器的容值密度。此外，利用所述至少一个槽状支架制备所述叠层结构，可以提高所述叠层结构的叠层密度，进一步增大电容器的电容值，从而能够提高电容器的容值密度。
第二方面，提供了一种制备电容器的方法，包括：
在衬底上制备至少一个槽状支架，得到第一导电层；
在所述第一导电层上制备至少一层电介质层和至少一层第二导电层，得到叠层结构，其中，所述至少一层电介质层和所述至少一层第二导电层覆盖所述至少一个槽状支架，所述第一导电层、所述至少一层电介质层和所述至少一层第二导电层形成电介质层和导电层彼此相邻的结构；
在所述叠层结构上制备包括互联结构的绝缘结构；
在所述绝缘结构上制备第一电极和第二电极，其中，所述第一电极和所述第二电极至少分别连接至相邻的两个导电层。
本发明实施例的制备电容器的方法，可以得到包括较多导电层和电介质层的叠层结构，增大电容器的电容值。此外，利用所述至少一个槽状支架制备所述叠层结构，可以提高所述叠层结构的叠层密度，进一步增大电容器的电容值，从而能够提高电容器的容值密度。
第三方面，提供了一种电容器，包括：
按照第二方面所述的方法制备的电容器。
附图说明
图1是本申请实施例的电容器的示意性结构图。
图2是本申请实施例的电容器的另一示意性结构图。
图3是图2所示的电容器的变形结构的部分示意性结构图。
图4是图2所示的电容器的另一变形结构的部分示意性结构图。
图5是本申请实施例的制备电容器的方法的示意性流程图。
图6至图19是制备图1所示的电容器的示意性工艺流程图。
图20至图31是制备图2所示的电容器的示意性工艺流程图。
具体实施方式
下面将结合附图，对本申请实施例中的技术方案进行描述。
应理解，本申请实施例的电容器在电路中可以起到旁路、滤波、去耦等作用。
本申请实施例所述的电容器可以是3D硅电容器，3D硅电容器是一种基于半导体晶圆加工技术的新型电容器。与传统的多层陶瓷电容(Multilayer ceramic capacitor，MLCC)相比，3D硅电容器具有小尺寸、高精度、高稳定性、长寿命等优点。其基本的加工流程需要先在晶圆或衬底上加工出高深宽比的深孔(Via)、沟槽(Trench)、柱状(Pillar)、墙状(Wall)等3D结构，接着在3D结构表面沉积绝缘薄膜和低电阻率导电材料依次制作电容的下电极、电介质层和上电极。
以下，结合图1至图31，详细介绍本申请实的电容器及其制备方法。
需要说明的是，为便于说明，在本申请的实施例中，相同的附图标记表示相同的部件，并且为了简洁，在不同实施例中，省略对相同部件的详细说明。应理解，附图示出的本申请实施例中的各种部件的厚度、长宽等尺寸，以及集成装置的整体厚度、长宽等尺寸仅为示例性说明，而不应对本申请构成任何限定。
此外，为便于理解，在以下示出的实施例中，对于不同实施例中示出的结构中，相同的结构采用相同的附图标记，并且为了简洁，省略对相同结构的详细说明。
图1是本申请实施例的电容器100的示意性结构图。
如图1所示，所述电容器100可以包括第一电极1111、第二电极1112、叠层结构160和互联结构190。
第一电极1111和第二电极1112为电容器100的正负两个电极。第一电极1111和第二电极1112相互分离，形成电极层。第一电极1111和第二电极1112的材料可以采用各种导电材料，例如金属铝。第一电极1111和第二电极1112的形式可以以焊盘或锡球的方式实现。
叠层结构160可以包括第一导电层、至少一层电介质层和至少一层第二导电层，所述第一导电层包括至少一个槽状支架(也可称为杯状支架)，所述至少一层电介质层(也可称为绝缘层)和所述至少一层第二导电层覆盖所述至少一个槽状支架，所述第一导电层、所述至少一层电介质层和所述至少一层第二导电层形成电介质层和导电层彼此相邻的结构。
其中，电介质层和导电层彼此相邻可以理解为：
与导电层相邻的层为电介质层，与电介质层相邻的层为导电层。
即导电层的上一层和下一层均为电介质层，电介质层的上一层和下一层均为导电层。
至少一个槽状支架为多个槽状支架时，所述多个槽状支架彼此电连接。在一种实现中，所述多个槽状支架在物理上是相连的(例如，在俯视图上，所述多个槽状支架组成“井”字形或网格状部件)；在另一种实现中，所述多个槽状支架在物理上是分离开的，此时可以电连接所述多个槽状支架的底部，使得所述多个槽状支架可以充当一层导电层(即所述第一导电层)，所述第一导电层用于电容器100的一个电极板(也可以称为电极层)。
在一个实施例中，如图1所示，至少一个槽状支架可以是4个槽状支架，例如图1中所示的4个槽状支架1611；至少一层电介质层可以是2层电介质层，例如图1中所示的电介质层162和164；至少一层第二导电层可以是2层导电层，例如图1中所示的导电层163和165。
需要说明的是，本申请实施例中对槽状支架的横截面的尺寸不做限定，例如，槽状支架可以为横截面上长和宽尺寸相差较小的孔，或者也可以为长和宽尺寸相差较大的沟槽，或者还可以是柱状(Pillar)或墙状(Wall)3D结构。这里横截面可以理解为与槽状支架的开口平行的截面。当然，本申请实施例对槽状支架开口的方向也不做具体限定，例如可以是竖直的，也可以是倾斜的。
在本申请的一些实施例中，叠层结构160中的电介质层可以包括以下至少一层：
硅的氧化物层、硅的氮化物层、硅的氮氧化物层、金属的氧化物层、金属的氮化物层和金属的氮氧化物层。
即叠层结构160中的电介质层的材料可以是硅的氧化物，硅的氮化物，硅的氮氧化物，金属的氧化物，金属的氮化物和金属的氮氧化物等，例如二氧化硅，氮化硅，或者高介电常数材料，包括氧化铝，氧化铪，氧化锆，二氧化钛，Y 2O 3，La 2O 3，HfSiO 4，LaAlO 3，SrTiO 3，LaLuO 3等；也可以是上述一种材料或多种材料的组合。电介质层的具体材料和层厚可根据电容器的容值、频率特性、损耗等需求来调整。当然，叠层结构160中的电介质层还可以包括一些其他具有高介电常数特性的材料层，本申请实施例对此不作限定。
在本申请的一些实施例中的导电层(例如第一导电层或叠层结构160)可以包括以下至少一层：
重掺杂多晶硅层、碳基材料层、金属层、氮化钛层和氮化钽层。
也就是说，该叠层结构160中的导电层的材料可以是重掺杂多晶硅，碳材料，或者是铝、钨、铜、钛(Ti)、钽(Ta)、铂(Pt)、钌(Ru)、铱(Ir)、铑(Rh)等各类金属，也可以是氮化钛、氮化钽等低电阻率的化合物，或者是上述几种导电材料的叠层、组合。
请继续参见图1，本申请实施例中，底部电连接的4个槽状支架1611作为一层电极板，通过叠层的方式在底部电连接的4个槽状支架1611上形成电介质层162和导电层163，不仅可以提高电容器的表面面积，而且由于电极板作为叠层结构的支架，可以提高叠层结构的叠层密度，进而提高电容器的容值密度。并且，通过设置高密度、高深宽比的槽状支架，可以进一步用于提高表面积和叠层密度。
此外，将上述第一导电层作为一层电极板，其与电介质层162和导电层163可以用于形成一个电容器，导电层163、电介质层164和导电层165可以用于形成另一个电容器。进一步地，将导电层163电连接至一个电极，将上述第一导电层和所述导电层165电连接至另一个电极，由此实现两个电容器的并联，进而可以得到一个大容值的电容器。
综上所述，采用导电层与电介质层交替堆叠的叠层结构形成电容器，能够在较小器件尺寸的情况下得到较大的电容值，从而能够提高电容器的容值密度。此外，利用所述至少一个槽状支架制备所述叠层结构，可以提高所述叠层结构的叠层密度，进一步增大电容器的电容值，从而能够提高电容器的容值密度。
互联结构190用于将所述第一电极1111和所述第二电极1112至少分别连接至相邻的两个导电层，以保证电容器100能够容纳电荷。
其中，相邻的两个导电层可以理解为：
与一个电介质层相邻的两个导电层。即与一个电介质层上表面接触的导电层和与这个电介质层的下表面接触的导电层。
此外，所述第一电极1111和所述第二电极1112至少分别连接至相邻的两个导电层可以理解为：
第一电极1111连接的导电层和第二点解1112连接的导电层为相邻的两 个导电层。
例如，互联结构190用于将所述第一电极1111电连接至叠层结构160中的部分或全部奇数层导电层，所述第二电极1112电连接至叠层结构160中的部分或全部偶数层导电层，以最大程度的并联叠层结构160内的多个电容器。
需要说明的是，在本申请实施例中，所涉及的导电层的顺序可以为从叠层结构160的一侧到另一侧的顺序，例如，从上到下的顺序或者是从下到上的顺序。为了便于描述，以下以从下到上的顺序为例进行说明。
例如，在图1所示的结构中，导电层1611、163、165分别为第1层至第3层导电层。其中，导电层1611、163、165中的奇数层导电层，即第1层和第3层导电层通过互联结构190可以电连接至所述第一电极1111，导电层1611、163、165中的偶数层导电层，即第2层导电层通过互联结构190可以电连接至所述第二电极1112。
互联结构190的材料可以采用各种导电材料，可以与叠层结构160中的导电层的材料相同或不同，例如，可以采用氮化钛和金属钨。
在本申请的一些实施例中，电容器100还可包括绝缘结构，用于包覆所述叠层结构160，以保护叠层结构160以及降低叠层结构160与其他外部电路之间的干扰。
需要说明的是，绝缘结构包覆叠层结构160可以理解为：
绝缘结构至少覆盖叠层结构160的两个侧面，并不限定于绝缘结构需要完整包覆叠层结构160。
在本申请的一些实施例中，请继续参见图1，所述绝缘结构可以包括第一绝缘层140和第二绝缘层180。
第一绝缘层140的上表面可以向下延伸形成有凹槽结构，所述至少一个槽状支架设置在第一绝缘层140的凹槽结构内，叠层结构160内的至少一层第二导电层在第一绝缘层140的凹槽结构的开口边缘形成至少一个第一台阶。
第一绝缘层140的材料可以是有机的聚合物材料，包括聚酰亚胺(Polyimide)，帕里纶(Parylene)，苯并环丁烯(BCB)等；也可以是一些无机材料，包括旋转涂布玻璃(Spin on glass，SOG)，未掺杂硅玻璃(Undoped Silicon Glass，USG)，硼硅玻璃(Boro-silicate glass，BSG)，磷硅玻璃(phospho-silicateglass，PSG)，硼磷硅玻璃(Boro-phospho-silicateglass，BPSG)， 由四乙氧基硅烷(Tetraethyl Orthsilicate，TEOS)合成的硅氧化物，硅的氧化物、氮化物，陶瓷；还可以是上述材料的组合。
结合图1来说，电介质层162、导电层163以及电介质层164对齐设置，且导电层165和电介质层164形成台阶。
当然，图1所述的台阶仅为本申请的示例，不应理解为对本申请的限制。
例如，在其他可替代实施例中，也可以是电介质层162和导电层163对齐设置，电介质层164和导电层165对齐设置，且导电层163与电介质层164之间形成台阶。
第二绝缘层180覆盖所述第一绝缘层140和所述叠层结构160。第二绝缘层180的材料可以和第一绝缘层140的材料相同，也可以不同，本申请对此不做具体限定。
此时，上述互联结构190可以包括第一通孔181和至少一个第二通孔182。
第一通孔181贯通第一绝缘层140、第二绝缘层180以及绝缘层130，用于将第一电极1111电连接至包括槽状支架1611的第一导电层。应理解，电容器100可以不包括绝缘层130，此时，第一通孔181仅需要贯通第一绝缘层140和第二绝缘层180。
至少一个第二通孔182，设置在上述至少一个第一台阶的上方，且贯通所述第二绝缘层180，所述互联结构190通过至少一个第二通孔182电连接至叠层结构160内的至少一层第二导电层中的部分或全部导电层。
需要说明的是，由于图1中的导电层163和电介质层164对齐设置，左侧的第二通孔182需要贯通第二绝缘层180和电介质层164。但本申请并不限于此。
例如，在其他可替代实施例中，电介质层162和导电层163对齐设置，此时，左侧的第二开孔182可以仅贯通第二绝缘层180。
第一通孔181和至少一个通孔182内可以填充有与叠层结构160的导电层的材料相同或不同的导电材料，也可以设置有用于电连接叠层结构160内的导电层的布线层，本申请对此不做具体限定。
请继续参见图1，在本申请的一些实施例中，电容器100还可以包括衬底110，设置在叠层结构160的下方，以支撑叠层结构160。
衬底110可以是低电阻率的单晶硅晶圆，也可以是表面包含低电阻率导电层的半导体衬底、玻璃衬底或有机物衬底，以保证上述多个槽状支架的导 电性能。半导体衬底的材料包括但不限于：硅、锗、III-V族元素(碳化硅(SiC)、氮化镓(GaN)以及砷化镓(GaAs)等)，或上述不同材料的组合。所述半导体衬底还可以包含外延层结构，例如硅晶绝缘体(silicon-on-insulator，SOI)结构，用于绝缘所述衬底。衬底110可以是一整片晶圆，也可以是从晶圆截取的一部分。
低电阻率导电层可以是重掺杂的硅、金属、TiN、TaN、碳或导电有机物。低电阻率导电层可以是电阻率低于预设阈值的导电层。所述预设阈值的设置使得层叠结构160内的多个槽状支架1611的底部电连接后，能够充当电容器100的一个导电层。
以衬底110为表面设置有导电层为例，结合图1来说，电容器100可以包括第三导电层120，设置在所述衬底110和所述叠层结构160之间，第三导电层120至少覆盖部分所述所述衬底。
第三导电层120用于将图1所示的4个槽状支架1611的底部电连接，进而使得这4个槽状支架1611能够作为电容器的第一层导电层，以提高叠层结构160的叠层密度。
请继续参见图1，在本申请的一些实施例中，电容器100还可以包括第四绝缘层130，设置在上述第三导电层120和所述叠层结构160之间，第四绝缘层130可以设置有至少一个通孔，由此叠层结构160包括的至少一个槽状支架1611的底部可以设置在第四绝缘层130的至少一个通孔内，由此进一步保证第三导电层120和导电层163之间绝缘，进而保证电容器100的性能。例如，叠层结构160包括的至少一个槽状支架1611的底部可以以一一对应的方式设置在第四绝缘层130的至少一个通孔内。
应理解，图1仅为本申请电容器的一种示例，不应理解为对本申请的限制。
图2是本申请实施例的电容器200的另一示意性框图。
请参见图2，电容器200可以包括第一电极281、第二电极282、叠层结构250和互联结构290。
叠层结构250可以包括4个槽状支架2511、介电质层252、导电层253、介电质层254以及导电层255。
请继续参见图2，电容器200还可以包括衬底210，以支撑叠层结构250以及电连接上述4个槽状支架2511。进一步地，电容器200还可以包括导电 层220，以保证上述4个槽状支架2511的导电性能。进一步地，电容器200还可以包括绝缘层230，以进一步保证导电层220和253之间绝缘，进而保证电容器200的性能。
应理解，由于电容器200可以理解为电容器100的变形结构，为了避免重复，此处省略相应的相关描述。例如，相应的导电层和电介质层的材料、相应工作原理。
下面对电容器200的结构进行详细说明。
请继续参见图2，电容器200可以包括第三绝缘层250，用于包覆所述叠层结构160，以保护叠层结构160以及降低叠层结构160与其他外部电路之间的干扰。
在本申请的一些实施例中，请继续参见图2，电容器100还可以包括第三绝缘270。第三绝缘层270包覆叠层结构250，叠层结构250内的至少一层第二导电层(即导电层2511、252和255)在第三绝缘层270内形成有至少一个第二台阶。
结合图2来说，叠层结构250内的至少一层第二导电层在第三绝缘层270的靠近槽状支架2511的底部形成有至少一个第二台阶。例如，叠层结构250内的至少一层第二导电层在第三绝缘层270的靠近槽状支架2511的底部以一一对应的方式形成至少一个第二台阶。
此时，上述互联结构290可以包括第三通孔271和至少一个第四通孔272。
第三通孔271贯通所述第三绝缘层270，用于将所述第一电极281通过导电层230电连接至包括槽状支架2511的第一导电层。
至少一个第四通孔272设置在上述至少一个第二台阶的上方，且贯通第三绝缘层270，互联结构290可以通过所述至少一个第二台阶电连接至叠层结构250内的至少一层第二导电层中的部分或全部导电层。
与电容器100类似，本申请实施例对叠层结构250内的至少一层电介质层的台阶的实现方式不做限定。
例如，图2所示的电介质层252和导电层253对齐，电介质层254和导电层255对齐，且导电层253与电介质层254形成一个台阶。但在其他实施例中，也可以是导电层253与电介质层254对齐，且电介质层254和导电层255形成一个台阶。
即在上述至少一个第二台阶位置，如果第二台阶的上表面为导电层所在 的上表面时，则上述第四通孔272仅需要贯穿第三绝缘层270；如果第二台阶的上表面为电介质层，则第四通孔272需要同时贯穿第三绝缘层270和导电层上方的电介质层。
应理解，以上结合附图详细描述了本申请的优选实施方式，但是，本申请并不限于上述实施方式中的具体细节，在本申请的技术构思范围内，可以对本申请的技术方案进行多种简单变型，这些简单变型均属于本申请的保护范围。
图3和图4为电容器200的简单变形后的部分示意性结构图。
假设电容器200包括衬底210和第三导电层220。此时，叠层结构250内的槽状支架2511可以直接电连接至所述第三导电层220，但本申请对槽状支架2511和第三导电层220之间的连接方式不做限定。例如，在图2中，叠层结构250内的槽状支架2511的底部直接接触于第三导电层220的上表面。又例如，在图3中，叠层结构250内的槽状支架2511可以嵌入到第三导电层220的内部，或者贯通第三导电层220，以增加稳固性。此时，槽状支架2511可以与衬底210直接接触，也可以不直接接触，本申请对此不做具体限定。
例如，请参见图3，第三导电层220可以设置有贯通第三导电层220的至少一个第五通孔，叠层结构250内的槽状支架251的底部可以设置在所述至少一个第五通孔内。
进一步地，请参见图4，假设电容器200包括衬底210和第三导电层220。此时，衬底210的上表面向下延伸形成有凹槽，第三导电层220设置在衬底210的凹槽内。
在本申请实施例中，采用导电层与绝缘层交替堆叠的叠层结构，能够在较小器件尺寸的情况下得到较大的电容值，从而能够提高电容器的容值密度。进一步地，采用第一导电层的槽状支架为框架形成叠层结构，能够提高叠层结构的叠层密度，进一步提高电容器的容值密度。
应理解，图1至图4中的电容器仅仅只是示例，不应理解为对本申请的限制。
例如，电容器所包括的叠层结构中叠层的数量和槽状支架的数量并不局限于图1至图4中的电容器所示，可以根据实际需要确定。
本申请还提供了一种制备电容器100和电容器200的方法。
图5是本申请实施例的制备电容器的方法300的示意性工艺流程图。
如图5所示，所述方法300可以包括：
S310，在衬底上制备至少一个槽状支架，得到第一导电层；
S320，在所述第一导电层上制备至少一层电介质层和至少一层第二导电层，得到叠层结构，其中，所述至少一层电介质层和所述至少一层第二导电层覆盖所述至少一个槽状支架，所述第一导电层、所述至少一层电介质层和所述至少一层第二导电层形成电介质层和导电层彼此相邻的结构；
S330，在所述叠层结构上制备包括互联结构的绝缘结构；
S340，在所述绝缘结构上制备第一电极和第二电极，其中，所述第一电极和所述第二电极至少分别连接至相邻的两个导电层。
以制备包括，首先在衬底表面设置开口向上的槽状支架。然后在所述杯状支架上设置第1电容，包含第1极板层，第1电介质层和第2极板层；其中第1电介质层电隔离第1和第2极板层。然后在所述第1电容上设置第2电容，包含第2极板层，第2电介质层和第3极板层；其中第2电介质层电隔离第2和第3极板层。最后，设置互联结构和焊盘，其中至少一个焊盘电连接第1极板层以及第3极板层，至少一个焊盘电连接第2极板层。
或者说，所述方法300的主要包括如下步骤：
步骤一，选取衬底。
步骤二，先利用沉积和光刻工艺在衬底上表面形成沟槽或孔状的模子，或者利用电镀工艺在衬底上表面形成沟槽或孔状的模子；然后，利用沉积、表面平坦化和刻蚀(或腐蚀)工艺，在衬底上表面制作与模子内壁共形的槽状(或杯状)支架。优选地，所述槽状支架由导电材料构成。所述槽状支架的底部与衬底的低电阻导电区域电连接。
步骤三，在支架上设置第一电容，包含第1极板层，第1电介质层和第2极板层。
步骤四，在第一电容上设置第二电容，包含第2极板层，第2电介质层和第3极板层。
步骤五，制作互联结构和焊盘。至少一个焊盘电连接第1极板层(和/或衬底)以及第3极板层；至少一个焊盘电连接第2极板层。
应理解，所述刻蚀工艺可以包括以下工艺中的至少一种：
干法刻蚀工艺、湿法刻蚀工艺和激光刻蚀工艺。
进一步地，所述干法蚀刻(dry etching)工艺可以包括以下刻蚀工艺中的至少一种：反应性离子蚀刻(reactive ion etching)、等离子体蚀刻(plasma etching)以及离子束刻蚀(ion beam etching)等。优选地，可以通过改变蚀刻气体的混合比可以改变蚀刻速度。所述湿法刻蚀工艺的化学原料可以包括但不限于含氢氟酸的刻蚀液。在本申请的一些实施例中，采用干法刻蚀与湿法刻蚀相结合的刻蚀方法，或者采用激光刻蚀结合湿法刻蚀的方法，能够有效保证刻蚀的形状以及底面平整度等。
所述沉积工艺包括但不限于：
物理气相沉积(Physical Vapor Deposition，PVD)工艺和/或化学气相沉积(Chemical Vapor Deposition，CVD)工艺。例如，热氧化、等离子体增强化学的气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)、低压力化学气相沉积法(Low Pressure Chemical Vapor Deposition，LPCVD)等)、原子层沉积(Atomic layer deposition，ALD)、旋涂或喷涂。
下面对制备上述电容器100的方法进行详细说明。
在本申请的一些实施例中，上述S310可包括以下步骤中的部分或全部：
步骤1，在所述衬底上形成第一绝缘层。
步骤2，形成贯通所述第一绝缘层的第一凹槽。
步骤3，在所述第一凹槽内填充第一材料。
步骤4，形成贯通所述第一材料的至少一个第二凹槽。
步骤5，在所述至少一个第二凹槽的上表面制作与所述至少一个第二凹槽的内壁共形的导电层。
步骤6，在所述至少一个第二凹槽内填充第二材料。
步骤7，去除所述第一绝缘层上方的第二材料和导电层。
步骤8，去除所述至少一个第二凹槽内的第二材料，形成所述第一导电层。
在本申请的一些实施例中，上述S320可包括以下步骤中的部分或全部：
步骤9，在所述第一导电层上制备所述至少一层电介质层和所述至少一层第二导电层。
步骤10，在所述第一凹槽的开口边缘，形成所述至少一层电介质层和所述至少一层第二导电层的至少一个第一台阶，得到所述叠层结构。
在本申请的一些实施例中，上述S330可包括以下步骤中的部分或全部：
步骤11，在所述叠层结构和所述第一绝缘层上制备第二绝缘层。
步骤12，形成贯通所述第一绝缘层和所述第二绝缘层的第一通孔。
步骤13，在所述至少一个第一台阶的上方形成贯通所述第二绝缘层的至少一个第二通孔。
步骤14，利用导电材料填充所述在所述第一通孔和所述至少一个第二通孔。
在本申请的一些实施例中，上述S340可包括以下步骤中的部分或全部：
步骤15，在所述第一通孔的上方和/或所述叠层结构内的部分或全部奇数导电层对应的所述第二通孔的上方形成所述第一电极；
步骤16，在所述叠层结构内的部分或全部偶数导电层对应的所述第二通孔的上方形成所述第二电极。
下面结合图6至图19对制备上述电容器100的方法进行详细说明。
选取衬底，所述衬底可以是低电阻率的单晶硅晶圆，也可以是表面包含低电阻率导电层的半导体衬底、玻璃衬底或有机物衬底。为便于描述，下面以所述衬底为硅晶圆为例进行说明。
选取硅晶圆后，通过离子注入并退火的方式或者扩散的方式进行掺杂，进而在硅晶圆110的表面形成低电阻率的导电层120，以形成图6所示的结构。所述导电层120可以覆盖衬底110的整个上表面，也可以覆盖衬底110的上表面的一部分，本申请不做具体限定，为便于描述，下面以所述导电层120可以覆盖衬底110的整个上表面为例对方法300进行说明。优选地，所述导电层的掺杂类型与衬底原本的掺杂类型相反。
在图6所示的结构上沉积绝缘层130和第一造模材料(molding material)140，以形成图7所示的结构。
需要说明的是，所述绝缘层130以及下文涉及的绝缘层可以采用上文涉及的绝缘材料，为避免重复，此处不再赘述。所述第一造模材料140可以包括但不限于：多晶硅、不定形硅、氧化硅、氮化硅、氮氧化硅、TEOS、含硅玻璃(例如USG、BSG、PSG、BPSG)，也可以是旋涂的SOG或有机材料等。
在图7所示的结构上，利用光刻工艺结合刻蚀工艺(或腐蚀工艺)，在所述第一造模材料140的上表面向下延伸形成开口向上的凹槽141，以露出绝缘层130，进而形成图8所示的结构。
在图8所述的结构上，采用第二造模材料150填充上述第一造模材料140的凹槽141，形成图9所示的结构。优选地，所述第二造模材料150和所述第一造模材料140可以不同，由此可以实现选择性的去除第二造模材料150。当然，也可以通过其它方式选择性的去除第二造模材料150，本申请对此不做具体限定。
在图9所示的结构上，利用光刻工艺结合刻蚀工艺制作凹槽阵列(例如4个凹槽)，所述凹槽阵列中的每个凹槽穿透第一造模材料140、第二造模材料150以及绝缘层130，以露出导电层120，进而形成图10所示的结构。
需要说明的是，图10所示的结构中，所述凹槽阵列中凹槽的数量仅为本申请的一种示例，不应理解为对本申请的限制，例如所述凹槽阵列中凹槽的数量可以是大于4或小于4的值，例如0。
在图10所示的结构上，在上述凹槽阵列的上表面(包括侧壁和底部)，沉积导电层161，形成图11所示的结构。
需要说明的是，导电层161以及下文涉及的导电层可以采用上文涉及的导电材料，为避免重复，此处不再赘述。例如，导电层161可以是利用LPCVD工艺沉积的重掺杂多晶硅，也可以是利用ALD工艺沉积的TiN、TaN或Pt等金属，还可以是利用CVD工艺沉积的碳材料。
在图11所示的结构上，利用第三造模材料170填充上述凹槽阵列，以形成图12所示的结构。优选地，所述第三造模材料170和所述第一造模材料140可以不同，由此可以实现选择性的去除第三造模材料170。当然，也可以通过其它方式选择性的去除第三造模材料170，本申请对此不做具体限定。
在图12所示的结构上，然后利用表面平坦化工艺，去除第一造模材料140以上的第三造模材料170和导电层161，得到开口向上的位于第一造模材料140(或剩余第二造模材料151)和剩余第三造模材料171之间的槽状(也可称为杯状)结构，以形成图13所示的结构。
在图13所示的结构上，利用选择性刻蚀(或腐蚀)工艺，去除剩余第二造模材料151和剩余第三造模材料171，保留第一造模材料140和绝缘层130；即将上述槽状结构转换为槽状支架1611，槽状支架1611的底部嵌入绝缘层130，与衬底110表面的导电层120接触，进而形成图14所示的结构。
在图14所示的结构上，依次沉积电介质层162，导电层163，电介质层 164和导电层165，以形成图15所示的结构。
在图15所示的结构上，利用多步光刻工艺结合刻蚀工艺，形成导电层163和导电层165的台阶，形成图16所示的结构。
在图16所示的结构上，先沉积绝缘层180，以覆盖导电层163和导电层165的台阶，形成图17所示的结构。
在图17所示的结构上，利用光刻及刻蚀工艺，设置第一通孔181以露出衬底110表面的导电层120，同时，设置至少一个第二通孔182以露出导电层163和导电层165，形成图18所示的结构。
需要说明的是，第一通孔181和至少一个第二通孔182内可以填充有导电材料，也可以设置有用于电连接的布线层，为了便于说明，下面以第一通孔181和至少一个第二通孔182内可以填充有导电材料为例对制备电容器的方法进行说明。此外，在图18中，右边的第二通孔182需要贯通绝缘层180和电介质层163，但本申请不限于此。例如，假设电介质层163和导电层165对齐设置时，右边的第二通孔182只需要贯通绝缘层180。
在图18所示的结构上，利用低电阻率导电材料填充第一通孔181和至少一个第二通孔182，并利用表面平坦化工艺磨去绝缘层180上方多余的导电材料，得到一个个独立的导电通道，以形成图19所示的结构。
在图19所示的结构上，在绝缘层180上沉积导电材料，再利用光刻形成图形，形成焊盘。其中一个焊盘电连接至导电层163，另一个焊盘电连接至导电层165，并通过导电层120电连接槽状支架1611，最终形成图1所示的结构。
需要说明的是，所述焊盘(pad)可以为金属。所述焊盘(pad)可以包括铜或铝，还可以包括位于pad与ILD之间的低电阻率的Ti，TiN，Ta，TaN层作为黏附层和/或阻挡层；还可以包括位于pad表面的一些金属层，例如Ni、Pd、Au、Sn、Ag，用于后续打线或焊接工艺。
应理解，图6至图19仅为本申请的一种示例，不应理解为对本申请的限制。
例如，在其他可替代实施例中，可以直接在省略上述导电层120和/或绝缘层130的制备过程。即直接在衬底110或者导电层120上沉积第一造模材料130。
又例如，在其他可替代实施例中，在图9所示的结构上，可以利用光刻 工艺结合刻蚀工艺制作凹槽阵列(例如4个凹槽)，所述凹槽阵列中的每个凹槽可以穿透第一造模材料140、第二造模材料150、绝缘层130以及导电层120，以露出衬底110。甚至，所述凹槽阵列中的每个凹槽可以嵌入到衬底110内。
下面对制备上述电容器200的方法进行详细说明。
在本申请的一些实施例中，上述S310可包括以下步骤中的部分或全部：
步骤1，在所述衬底上形成第三材料。
步骤2，形成贯通所述第三材料的至少一个第三凹槽。
步骤3，在所述至少一个第三凹槽的上表面制作与所述至少一个第三凹槽的内壁共形的导电层。
步骤4，在所述至少一个第三凹槽内填充第四材料。
步骤5，去除所述第三材料上方的第四材料和导电层。
步骤6，去除所述衬底上方的所述第三材料和所述第四材料，形成所述第一导电层。
在本申请的一些实施例中，上述S320可包括以下步骤中的部分或全部：
步骤7，在所述第一导电层上制备所述至少一层电介质层和所述至少一层第二导电层。
步骤8，在所述衬底上形成所述至少一层第二导电层的至少一个第二台阶，得到所述叠层结构。
在本申请的一些实施例中，上述S330可包括以下步骤中的部分或全部：
步骤9，在所述叠层结构上制备第三绝缘层；
步骤10，形成贯通所述第三绝缘层的第三通孔；
步骤11，在所述至少一个第二台阶的上方形成贯通所述第三绝缘层的至少一个第四通孔；
步骤12，利用导电材料填充所述在所述第三通孔和所述至少一个第四通孔。
在本申请的一些实施例中，上述S340可包括以下步骤中的部分或全部：
步骤13，在所述第三通孔的上方和/或所述叠层结构内的部分或全部奇数导电层对应的所述第四通孔的上方形成所述第一电极；
步骤14，在所述叠层结构内的部分或全部偶数导电层对应的所述第四通孔的上方形成所述第二电极。
结合图20至图31来说，选取衬底210，并在所述衬底210上覆盖导电层220，以形成图20所示的结构。在导电层220上覆盖绝缘层230，并在绝缘层上覆盖第四造模材料240(可以和上述第一造模材料相同，也可以不同)，形成图21所示的结构。利用光刻工艺结合刻蚀工艺(或腐蚀工艺)，在第四造模材料240的上表面向下延伸形成开口向上的在形成贯通第四造模材料240的至少一个第三凹槽241，以形成图22所示的结构。在所述至少一个第三凹槽241的上表面沉积导电层251，形成图23所示的结构。在所述至少一个第三凹槽内填充第五造模材料260(可以和上述第一造模材料相同，也可以不同)，以形成图24所示的结构。利用光刻工艺结合刻蚀工艺去除所述第三材料上方的第五造模材料260和导电层251，形成图25所示的结构。利用选择性刻蚀(或腐蚀)工艺，去除所述衬底上方的第四造模材料240和第五造模材料260，形成至少一个槽状支架2511，进而得到图26所示的结构。依次沉积电介质层252，导电层253，电介质层254和导电层255，以形成图27所示的结构。利用多步光刻工艺结合刻蚀工艺，形成导电层253和导电层255的台阶，形成图28所示的结构。在导电层255、导电层253和绝缘层230上沉积绝缘层270，形成图29所示的结构。利用光刻及刻蚀工艺，设置第三通孔271以露出衬底210表面的导电层220，同时，设置至少一个第四通孔272以露出导电层253和导电层25，形成图30所示的结构。利用低电阻率导电材料填充第三通孔271和至少一个第四通孔272，并利用表面平坦化工艺磨去绝缘层270上方多余的导电材料，得到一个个独立的导电通道，以形成图31所示的结构。在绝缘层270上沉积导电材料，再利用光刻形成图形，形成焊盘，进而得到图2所示的电容器。
应理解，图20至图30仅为本申请的一种示例，不应理解为对本申请的限制。
例如，在其他可替代实施例中，可以直接在省略上述导电层220和/或绝缘层230的制备过程。即直接在衬底210或者导电层220上沉积第一造模材料130。
又例如，在其他可替代实施例中，在图22所示的结构上，上述至少一个第三凹槽241可以贯通导电层220，甚至可以嵌入到衬底210内。
本申请还提供了一种根据上述制备方法制备的电容器。
应理解，方法实施例与产品实施例可以相互对应，类似的描述可以参照 产品实施例。为了简洁，在此不再赘述。
还应理解，上述列举的制备电容器的方法300的各实施例，可以通过机器人或者数控加工方式来执行，用于执行所述方法300的设备软件或工艺可以通过执行保存在存储器中的计算机程序代码来执行上述方法300。
需要说明的是，在不冲突的前提下，本申请描述的各个实施例和/或各个实施例中的技术特征可以任意的相互组合，组合之后得到的技术方案也应落入本申请的保护范围。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的制备方法，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请所提供的几个实施例中，应该理解到，所揭露的集成装置、集成装置内的部件和制备集成装置的方法，可以通过其它的方式实现。例如，以上所描述的集成装置实施例仅仅是示例性的。例如，所述层的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。例如多个层或器件可以结合或者可以集成，例如，所述上极板和所述活性材料层可以合并为一个层。或一些特征(例如活性材料层)可以忽略或不制备。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (36)

  1. 一种电容器，其特征在于，包括：
    第一电极和第二电极；
    叠层结构，包括第一导电层、至少一层电介质层和至少一层第二导电层，所述第一导电层包括至少一个槽状支架，所述至少一层电介质层和所述至少一层第二导电层覆盖所述至少一个槽状支架，所述第一导电层、所述至少一层电介质层和所述至少一层第二导电层形成电介质层和导电层彼此相邻的结构；
    互联结构，用于将所述第一电极和所述第二电极至少分别连接至相邻的两个导电层。
  2. 根据权利要求1所述的电容器，其特征在于，所述至少一个槽状支架为多个槽状支架，所述多个槽状支架彼此电连接。
  3. 根据权利要求2所述的电容器，其特征在于，所述多个槽状支架在横截面上形成网格结构，或所述多个槽状支架的底部通过导电层电连接。
  4. 根据权利要求1至3中任一项所述的电容器，其特征在于，所述电容器还包括：
    绝缘结构，所述绝缘结构包覆所述叠层结构，所述互联结构设置于所述绝缘结构内。
  5. 根据权利要求4所述的电容器，其特征在于，所述绝缘结构包括：
    第一绝缘层，所述第一绝缘层的上表面向下延伸形成有第一凹槽结构，所述至少一个槽状支架设置在所述第一凹槽结构内，所述至少一层第二导电层在所述第一凹槽结构的开口边缘形成至少一个第一台阶；
    第二绝缘层，所述第二绝缘层覆盖所述第一绝缘层和所述叠层结构。
  6. 根据权利要求5所述的电容器，其特征在于，所述互联结构包括：
    第一通孔，所述第一通孔贯通所述第一绝缘层和所述第二绝缘层，用于将所述第一电极电连接至所述第一导电层；
    至少一个第二通孔，设置在所述至少一个第一台阶的上方，且贯通所述第二绝缘层，所述互联结构通过所述至少一个第二通孔电连接至所述至少一层第二导电层。
  7. 根据权利要求4所述的电容器，其特征在于，所述绝缘结构包括：
    第三绝缘层，所述第三绝缘层包覆所述叠层结构，所述至少一层第二导电层在所述第三绝缘层内形成有至少一个第二台阶。
  8. 根据权利要求7所述的电容器，其特征在于，所述至少一层第二导电层在所述第三绝缘层的靠近所述至少一个槽状支架的底部形成有所述至少一个第二台阶。
  9. 根据权利要求7所述的电容器，其特征在于，所述互联结构包括：
    第三通孔，所述第一通孔贯通所述第三绝缘层，用于将所述第一电极电连接至所述第一导电层；
    至少一个第四通孔，设置在所述至少一个第二台阶的上方，且贯通所述第三绝缘层，所述互联结构通过所述至少一个第四通孔电连接至所述至少一层第二导电层。
  10. 根据权利要求1至9中任一项所述的电容器，其特征在于，所述电容器还包括：
    衬底，设置在所述叠层结构的下方。
  11. 根据权利要求10所述的电容器，其特征在于，所述衬底为电阻率低于预设阈值的晶圆。
  12. 根据权利要求10所述的电容器，其特征在于，所述电容器还包括：
    第三导电层，设置在所述衬底和所述叠层结构之间，所述第三导电层至少覆盖部分所述所述衬底。
  13. 根据权利要求12所述的电容器，其特征在于，所述至少一个槽状支架电连接至所述第三导电层。
  14. 根据权利要求12所述的电容器，其特征在于，所述至少一个槽状支架通过所述第三导电层电连接至所述衬底。
  15. 根据权利要求14所述的电容器，其特征在于，所述第三导电层设置有至少一个第五通孔，所述至少一个槽状支架的底部设置在所述至少一个第五通孔内。
  16. 根据权利要求12至15中任一项所述的电容器，其特征在于，所述衬底的上表面向下延伸形成有第二凹槽结构，所述第三导电层设置在所述第二凹槽结构内。
  17. 根据权利要求1至16中任一项所述的电容器，其特征在于，所述电容器还包括：
    第四绝缘层，所述第四绝缘层设置有至少一个第六通孔，所述至少一个槽状支架的底部设置在所述至少一个第六通孔内。
  18. 根据权利要求1至17中任一项所述的电容器，其特征在于，所述互联结构具体用于将所述第一电极电连接至所述叠层结构内的部分或全部奇数导电层，并将所述第二电极电连接至所述叠层结构内的部分或全部偶数导电层。
  19. 一种制备电容器的方法，其特征在于，包括：
    在衬底上制备至少一个槽状支架，得到第一导电层；
    在所述第一导电层上制备至少一层电介质层和至少一层第二导电层，得到叠层结构，其中，所述至少一层电介质层和所述至少一层第二导电层覆盖所述至少一个槽状支架，所述第一导电层、所述至少一层电介质层和所述至少一层第二导电层形成电介质层和导电层彼此相邻的结构；
    在所述叠层结构上制备包括互联结构的绝缘结构；
    在所述绝缘结构上制备第一电极和第二电极，其中，所述第一电极和所述第二电极至少分别连接至相邻的两个导电层。
  20. 根据权利要求19所述的方法，其特征在于，所述在衬底上制备至少一个槽状支架，得到第一导电层，包括：
    在所述衬底上形成第一绝缘层；
    形成贯通所述第一绝缘层的第一凹槽；
    在所述第一凹槽内填充第一材料；
    形成贯通所述第一材料的至少一个第二凹槽；
    在所述至少一个第二凹槽的上表面制作与所述至少一个第二凹槽的内壁共形的导电层；
    在所述至少一个第二凹槽内填充第二材料；
    去除所述第一绝缘层上方的第二材料和导电层；
    去除所述至少一个第二凹槽内的第二材料，形成所述第一导电层。
  21. 根据权利要求20所述的方法，其特征在于，所述在所述第一导电层上制备至少一层电介质层和至少一层第二导电层，得到叠层结构，包括：
    在所述第一导电层上制备所述至少一层电介质层和所述至少一层第二导电层；
    在所述第一凹槽的开口边缘，形成所述至少一层第二导电层的至少一个 第一台阶，得到所述叠层结构。
  22. 根据权利要求21所述的方法，其特征在于，所述在所述叠层结构上制备包括互联结构的绝缘结构，包括：
    在所述叠层结构和所述第一绝缘层上制备第二绝缘层；
    形成贯通所述第一绝缘层和所述第二绝缘层的第一通孔；
    在所述至少一个第一台阶的上方形成贯通所述第二绝缘层的至少一个第二通孔；
    利用导电材料填充所述在所述第一通孔和所述至少一个第二通孔。
  23. 根据权利要求22所述的方法，其特征在于，所述在所述绝缘结构上制备第一电极和第二电极，包括：
    在所述第一通孔的上方和/或所述叠层结构内的部分或全部奇数导电层对应的所述第二通孔的上方形成所述第一电极；
    在所述叠层结构内的部分或全部偶数导电层对应的所述第二通孔的上方形成所述第二电极。
  24. 根据权利要求20至23中任一项所述的方法，其特征在于，所述衬底为电阻率低于预设阈值的晶圆。
  25. 根据权利要求20至23中任一项所述的方法，其特征在于，所述在所述衬底上形成第一绝缘层，包括：
    在所述衬底上形成第三导电层；
    在所述第三导电层上形成所述第一绝缘层。
  26. 根据权利要求25所述的方法，其特征在于，所述形成贯通所述第一绝缘层的第一凹槽，包括：
    形成贯通所述第一绝缘层和所述第三导电层的所述第一凹槽。
  27. 根据权利要求25所述的方法，其特征在于，所述在第三导电层上形成所述第一绝缘层，包括：
    在所述第三导电层上形成第四绝缘层；
    在所述第四绝缘层上形成所述第一绝缘层；
    其中，所述形成贯通所述第一材料的至少一个第二凹槽，包括：
    形成贯通所述第一材料和所述第四绝缘层的所述至少一个第二凹槽。
  28. 根据权利要求19所述的方法，其特征在于，所述在衬底上制备至少一个槽状支架，得到第一导电层，包括：
    在所述衬底上形成第三材料；
    形成贯通所述第三材料的至少一个第三凹槽；
    在所述至少一个第三凹槽的上表面制作与所述至少一个第三凹槽的内壁共形的导电层；
    在所述至少一个第三凹槽内填充第四材料；
    去除所述第三材料上方的第四材料和导电层；
    去除所述衬底上方的所述第三材料和所述第四材料，形成所述第一导电层。
  29. 根据权利要求28所述的方法，其特征在于，所述在所述第一导电层上制备至少一层电介质层和至少一层第二导电层，得到叠层结构，包括：
    在所述第一导电层上制备所述至少一层电介质层和所述至少一层第二导电层；
    在所述衬底上形成所述至少一层第二导电层的至少一个第二台阶，得到所述叠层结构。
  30. 根据权利要求29所述的方法，其特征在于，所述在所述叠层结构上制备包括互联结构的绝缘结构，包括：
    在所述叠层结构上制备第三绝缘层；
    形成贯通所述第三绝缘层的第三通孔；
    在所述至少一个第二台阶的上方形成贯通所述第三绝缘层的至少一个第四通孔；
    利用导电材料填充所述在所述第三通孔和所述至少一个第四通孔。
  31. 根据权利要求30所述的方法，其特征在于，所述在所述绝缘结构上制备第一电极和第二电极，包括：
    在所述第三通孔的上方和/或所述叠层结构内的部分或全部奇数导电层对应的所述第四通孔的上方形成所述第一电极；
    在所述叠层结构内的部分或全部偶数导电层对应的所述第四通孔的上方形成所述第二电极。
  32. 根据权利要求28至31中任一项所述的方法，其特征在于，所述衬底为电阻率低于预设阈值的晶圆。
  33. 根据权利要求28至31中任一项所述的方法，其特征在于，所述在所述衬底上形成第三材料，包括：
    在所述衬底上形成第三导电层；
    在所述第三导电层上形成所述第三材料。
  34. 根据权利要求33所述的方法，其特征在于，所述形成贯通所述第三材料的至少一个第三凹槽，包括：
    形成贯通所述第三材料和所述第三导电层的所述至少一个第三凹槽。
  35. 根据权利要求33所述的方法，其特征在于，所述在所述第三导电层上形成所述第三材料，包括：
    在所述第三导电层上形成第四绝缘层；
    在所述第四绝缘层上形成所述第三材料；
    其中，所述形成贯通所述第三材料的至少一个第三凹槽，包括：
    形成贯通所述第三材料和所述第四绝缘层的所述至少一个第三凹槽。
  36. 一种电容器，其特征在于，包括：
    根据权利要求19至35中任一项所述的方法制备的电容器。
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