WO2020089726A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2020089726A1
WO2020089726A1 PCT/IB2019/058935 IB2019058935W WO2020089726A1 WO 2020089726 A1 WO2020089726 A1 WO 2020089726A1 IB 2019058935 W IB2019058935 W IB 2019058935W WO 2020089726 A1 WO2020089726 A1 WO 2020089726A1
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Prior art keywords
layer
insulating layer
film
region
metal oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/IB2019/058935
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English (en)
French (fr)
Japanese (ja)
Inventor
中田　昌孝
貴弘 井口
泰靖 保坂
匠 重信
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to US17/288,675 priority Critical patent/US20220013667A1/en
Priority to JP2020554603A priority patent/JPWO2020089726A1/ja
Priority to CN201980072744.5A priority patent/CN112997335A/zh
Priority to KR1020217012635A priority patent/KR20210083269A/ko
Publication of WO2020089726A1 publication Critical patent/WO2020089726A1/ja
Anticipated expiration legal-status Critical
Priority to JP2024106641A priority patent/JP2024153634A/ja
Priority to JP2025280374A priority patent/JP2026065018A/ja
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional [2D] radiating surfaces
    • H05B33/14—Light sources with substantially two-dimensional [2D] radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material, or by the simultaneous addition of the electroluminescent material in or onto the light source
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H10D30/6719—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions having significant overlap between the lightly-doped drains and the gate electrodes, e.g. gate-overlapped LDD [GOLDD] TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/22—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using physical deposition, e.g. vacuum deposition or sputtering
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3424—Deposited materials, e.g. layers characterised by the chemical composition being Group IIB-VIA materials
    • H10P14/3426—Oxides
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3434—Deposited materials, e.g. layers characterised by the chemical composition being oxide semiconductor materials
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3438—Doping during depositing
    • H10P14/3441—Conductivity type
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof.
  • One embodiment of the present invention relates to a display device.
  • the technical field of one embodiment of the present invention disclosed in this specification and the like includes a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an electronic device, a lighting device, an input device, an input / output device, and a driving method thereof. , Or their manufacturing method can be mentioned as an example.
  • a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.
  • Oxide semiconductors using metal oxides are drawing attention as semiconductor materials applicable to transistors.
  • a plurality of oxide semiconductor layers are stacked, and in the plurality of oxide semiconductor layers, the oxide semiconductor layer serving as a channel contains indium and gallium, and the proportion of indium is the proportion of gallium.
  • the field-effect mobility (which may be simply referred to as mobility or ⁇ FE) is increased by increasing the thickness.
  • the metal oxide that can be used for the semiconductor layer can be formed by a sputtering method or the like, it can be used for the semiconductor layer of a transistor included in a large-sized display device.
  • the metal oxide that can be used for the semiconductor layer can be formed by a sputtering method or the like, it can be used for the semiconductor layer of a transistor included in a large-sized display device.
  • it is possible to improve and utilize a part of the production equipment of a transistor using polycrystalline silicon or amorphous silicon capital investment can be suppressed.
  • a transistor including a metal oxide has higher field-effect mobility than a transistor including amorphous silicon, a high-performance display device including a driver circuit can be realized.
  • One object of one embodiment of the present invention is to provide a semiconductor device with favorable electric characteristics.
  • An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.
  • An object of one embodiment of the present invention is to provide a semiconductor device with stable electric characteristics.
  • An object of one embodiment of the present invention is to provide a novel semiconductor device.
  • An object of one embodiment of the present invention is to provide a highly reliable display device.
  • An object of one embodiment of the present invention is to provide a novel display device.
  • One embodiment of the present invention is a semiconductor device including a semiconductor layer, a first insulating layer, a metal oxide layer, a conductive layer, and an insulating region.
  • the first insulating layer covers the top surface and the side surface of the semiconductor layer, and the conductive layer is located on the first insulating layer.
  • the metal oxide layer is located between the first insulating layer and the conductive layer, and the end portion of the metal oxide layer is located inside the end portion of the conductive layer.
  • the insulating region is adjacent to the metal oxide layer and is located between the first insulating layer and the conductive layer.
  • the semiconductor layer has a first region, a pair of second regions, and a pair of third regions. The first region overlaps the metal oxide layer and the conductive layer.
  • the second region sandwiches the first region and overlaps with the insulating region and the conductive layer.
  • the third region sandwiches the first region and the pair of second regions and does not overlap with the conductive layer.
  • the third region preferably includes a portion having a lower resistance than that of the first region.
  • the second region preferably includes a portion having a higher resistance than the third region.
  • the insulating region and the first insulating layer have different relative dielectric constants.
  • the insulating region preferably has a void.
  • the semiconductor device described above preferably further includes a second insulating layer, the second insulating layer is in contact with the upper surface of the first insulating layer, and the insulating region preferably includes the second insulating layer.
  • the first insulating layer contains an oxide or a nitride and the second insulating layer contains an oxide or a nitride.
  • the first insulating layer contains silicon and oxygen
  • the second insulating layer contains silicon and oxygen
  • the first insulating layer preferably contains silicon and oxygen
  • the second insulating layer preferably contains silicon and nitrogen
  • the semiconductor device described above preferably further includes a third insulating layer, the third insulating layer is in contact with the upper surface of the second insulating layer, and the third insulating layer preferably contains a nitride.
  • the third insulating layer preferably contains silicon and nitrogen.
  • the third region preferably contains the first element, and the first element is preferably one or more selected from boron, phosphorus, aluminum, and magnesium.
  • the semiconductor layer and the metal oxide layer each contain indium, and the semiconductor layer and the metal oxide layer have substantially the same indium content.
  • a semiconductor device with favorable electric characteristics can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device with stable electric characteristics can be provided.
  • a new semiconductor device can be provided.
  • a highly reliable display device can be provided.
  • a new display device can be provided.
  • FIG. 1A is a top view illustrating a structural example of a transistor.
  • 1B and 1C are cross-sectional views illustrating a structural example of a transistor.
  • 2A and 2B are cross-sectional views illustrating a structural example of a transistor.
  • 3A and 3B are cross-sectional views each illustrating a structural example of a transistor.
  • 4A and 4B are cross-sectional views each illustrating a structural example of a transistor.
  • FIG. 5A is a top view illustrating a structural example of a transistor.
  • 5B and 5C are cross-sectional views each illustrating a structural example of a transistor.
  • 6A and 6B are cross-sectional views each illustrating a structural example of a transistor.
  • 7A and 7B are cross-sectional views each illustrating a structural example of a transistor.
  • 8A, 8B, 8C, 8D, and 8E are cross-sectional views illustrating a method for manufacturing a transistor.
  • 9A, 9B, and 9C are cross-sectional views illustrating a method for manufacturing a transistor.
  • 10A, 10B, and 10C are cross-sectional views illustrating a method for manufacturing a transistor.
  • 11A, 11B, and 11C are cross-sectional views illustrating a method for manufacturing a transistor.
  • 12A, 12B, and 12C are top views of the display device.
  • FIG. 13 is a cross-sectional view of the display device.
  • FIG. 14 is a cross-sectional view of the display device.
  • FIG. 15 is a cross-sectional view of the display device.
  • FIG. 16 is a cross-sectional view of the display device.
  • FIG. 17A is a block diagram of a display device. 17B and 17C are circuit diagrams of the display device. 18A, 18C, and 18D are circuit diagrams of the display device.
  • FIG. 18B is a timing chart of the display device. 19A and 19B are configuration examples of the display module.
  • 20A and 20B are configuration examples of electronic devices.
  • 21A, 21B, 21C, 21D, and 21E are configuration examples of electronic devices.
  • 22A, 22B, 22C, 22D, 22E, 22F, and 22G are configuration examples of electronic devices.
  • 23A, 23B, 23C, and 23D are configuration examples of electronic devices.
  • FIG. 24 is a STEM image of a cross section.
  • FIG. 25 is a diagram showing the Id-Vg characteristics of the transistor and a STEM image of the cross section.
  • FIG. 26 is a diagram showing an Id-Vg characteristic of a transistor and a STEM image of a cross section.
  • FIG. 27 is a diagram showing the Id-Vg characteristics of the transistor and a STEM image of the cross section.
  • FIG. 28 is a diagram showing a reliability test result of a transistor.
  • FIG. 29 is a diagram showing a cross-sectional structure of the sample.
  • FIG. 30 is a diagram showing the sheet resistance of the sample.
  • FIG. 31 is a STEM image of a cross section.
  • the functions of the source and the drain of the transistor may be switched when the polarity of the transistor or the direction of current flow in circuit operation is changed. Therefore, the terms source and drain can be used interchangeably.
  • the channel length direction of a transistor refers to one of directions parallel to a straight line connecting a source region and a drain region with the shortest distance. That is, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is on. Further, the channel width direction means a direction orthogonal to the channel length direction. Note that depending on the structure and shape of the transistor, the channel length direction and the channel width direction may not be defined as one.
  • the term “electrically connected” includes the case of being connected via “something having an electrical action”.
  • the “object having some kind of electrical action” is not particularly limited as long as it can transfer an electric signal between the connection targets.
  • “things having some kind of electrical action” include electrodes and wirings, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.
  • film and “layer” can be interchanged with each other.
  • conductive layer and “insulating layer” may be interchangeable with the terms “conductive film” and “insulating film”.
  • the top shapes are substantially the same.
  • it includes a case where the upper layer and the lower layer are processed with the same mask pattern or a part of the same mask pattern.
  • the contours do not overlap with each other, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer.
  • off-state current refers to drain current when a transistor is in an off state (also referred to as a non-conducting state or a blocking state).
  • the off state is a state in which the voltage V gs between the gate and the source is lower than the threshold voltage V th in the n-channel transistor (higher than V th in the p-channel transistor) unless otherwise specified.
  • a display panel which is one mode of a display device, has a function of displaying (outputting) an image or the like on a display surface. Therefore, the display panel is one mode of the output device.
  • a connector of FPC Flexible Printed Circuit
  • TCP Transmission Carrier Package
  • a connector of FPC Flexible Printed Circuit
  • TCP Transmission Carrier Package
  • COG Chip On Glass
  • a touch panel which is one mode of a display device has a function of displaying an image or the like on a display surface, and a touch surface of a detected object such as a finger or a stylus touches, presses, or approaches the display surface. And a function as a touch sensor for detecting. Therefore, the touch panel is an aspect of the input / output device.
  • the touch panel can also be called, for example, a display panel (or display device) with a touch sensor or a display panel (or display device) with a touch sensor function.
  • the touch panel can also be configured to have a display panel and a touch sensor panel. Alternatively, the inside or the surface of the display panel may have a function as a touch sensor.
  • a touch panel substrate on which connectors and ICs are mounted may be referred to as a touch panel module, a display module, or simply a touch panel.
  • One embodiment of the present invention is a transistor including a semiconductor layer in which a channel is formed over a formation surface, an insulating layer over the semiconductor layer, a metal oxide layer over the insulating layer, and a conductive layer. Further, the transistor which is one embodiment of the present invention preferably has an insulating region which is adjacent to the metal oxide layer. The insulating region is located between the gate insulating layer and the conductive layer.
  • the semiconductor layer is preferably configured to include a metal oxide having semiconductor characteristics (hereinafter, also referred to as an oxide semiconductor).
  • the end of the metal oxide layer is provided inside the end of the conductive layer.
  • the conductive layer has a portion protruding outward from the end of the metal oxide layer. Part of the metal oxide layer and the conductive layer functions as a gate electrode.
  • the insulating region has a different relative dielectric constant from the insulating layer.
  • the insulating region may include voids.
  • the insulating layer is preferably provided so as to cover the top surface and the side surface of the semiconductor layer. The insulating layer and part of the insulating region function as a gate insulating layer.
  • the semiconductor layer has a first region overlapping with the metal oxide layer and the conductive layer, a second region overlapping with the insulating region and the conductive layer, and a third region not overlapping with the conductive layer.
  • the first region is a region that functions as a channel formation region.
  • the third region has a lower resistance than the first region and functions as a source region or a drain region.
  • the second region has a higher resistance than the third region.
  • the second region overlaps with the conductive layer that functions as a gate electrode with the insulating region interposed, it can also be called an overlap region (Lov region).
  • the second region functions as a buffer region to which the electric field of the gate is not applied or which is less likely to be applied than the first region.
  • a transistor which is one embodiment of the present invention has a second region between a first region which is a channel formation region in a semiconductor layer and a third region which functions as a source region or a drain region. By having the second region, the source-drain breakdown voltage of the transistor can be improved, and a highly reliable transistor can be realized even when driven at a high voltage.
  • FIG. 1A is a top view of the transistor 100
  • FIG. 1B corresponds to a cross-sectional view taken along the dashed-dotted line A1-A2 in FIG. 1A
  • FIG. 1C is a sectional view taken along the dashed-dotted line B1-B2 in FIG. 1A. It corresponds to a sectional view of the plane.
  • FIG. 1A some of components of the transistor 100 (a gate insulating layer and the like) are omitted.
  • the dashed-dotted line A1-A2 direction corresponds to the channel length direction
  • the dashed-dotted line B1-B2 direction corresponds to the channel width direction.
  • the top view of the transistor some of the components are omitted in the following drawings, as in FIG. 1A.
  • the transistor 100 is provided over the substrate 102 and includes an insulating layer 103, a semiconductor layer 108, an insulating layer 110, a metal oxide layer 114, a conductive layer 112, an insulating layer 118, and the like.
  • the island-shaped semiconductor layer 108 is provided over the insulating layer 103.
  • the insulating layer 110 is provided in contact with the top surface of the insulating layer 103 and the top surface and side surfaces of the semiconductor layer 108.
  • the metal oxide layer 114 and the conductive layer 112 are stacked over the insulating layer 110 in this order and have a portion overlapping with the semiconductor layer 108.
  • the insulating layer 118 is provided so as to cover the top surface of the insulating layer 110 and the top and side surfaces of the conductive layer 112.
  • FIG. 2A shows an enlarged view of a region P surrounded by the alternate long and short dash line in FIG. 1B.
  • the transistor 100 has an insulating region 150 adjacent to the metal oxide layer 114.
  • the insulating region 150 is located between the insulating layer 110 and the conductive layer 112.
  • a conductive material can be used as the metal oxide layer 114.
  • Part of the conductive layer 112 and the metal oxide layer 114 function as a gate electrode.
  • Part of the insulating layer 110 and the insulating region 150 functions as a gate insulating layer.
  • the transistor 100 is a so-called top-gate transistor in which a gate electrode is provided over the semiconductor layer 108.
  • the end of the metal oxide layer 114 is located inside the end of the conductive layer 112 on the insulating layer 110.
  • the conductive layer 112 has a portion on the insulating layer 110 that protrudes outward from the end portion of the metal oxide layer 114.
  • the semiconductor layer 108 is configured to include a metal oxide having semiconductor characteristics (hereinafter, also referred to as an oxide semiconductor).
  • the semiconductor layer 108 preferably contains at least indium and oxygen.
  • the semiconductor layer 108 may contain zinc.
  • the semiconductor layer 108 may contain gallium.
  • indium oxide indium zinc oxide (In-Zn oxide), indium gallium zinc oxide (also referred to as In-Ga-Zn oxide, or IGZO), or the like can be used. ..
  • indium tin oxide In—Sn oxide
  • indium tin oxide containing silicon or the like can be used. Note that details of materials that can be used for the semiconductor layer 108 will be described later.
  • the composition of the semiconductor layer 108 greatly affects the electrical characteristics and reliability of the transistor 100. For example, by increasing the content of indium in the semiconductor layer 108, carrier mobility is improved and a transistor with high field-effect mobility can be realized.
  • the semiconductor layer 108 has a region 108C, a pair of regions 108L sandwiching the region 108C, and a pair of regions 108N outside thereof.
  • the region 108C overlaps with the conductive layer 112 and the metal oxide layer 114 and functions as a channel formation region.
  • the region 108L overlaps the conductive layer 112 and the insulating region 150. It can also be said that the region 108L overlaps with the conductive layer 112 and does not overlap with the metal oxide layer 114.
  • the region 108L is a region where a channel can be formed when a gate voltage is applied to the conductive layer 112.
  • the electric field applied to the region 108L is weaker than the electric field applied to the region 108C.
  • the region 108L has a higher resistance than the region 108C, and functions as a buffer region for relaxing the drain electric field.
  • a channel can be formed by the electric field of the conductive layer 112.
  • the region 108L between the region 108C which is a channel formation region and the region 108N which is a source region or a drain region a high drain breakdown voltage and a high on-state current are combined, and the reliability is high.
  • a transistor can be realized.
  • the region 108N does not overlap with either the conductive layer 112 or the metal oxide layer 114 and functions as a source region or a drain region.
  • the width of the conductive layer 112 in the channel length direction of the transistor 100 is indicated by L1.
  • the width of the insulating region in the channel length direction of the transistor 100 is indicated by L2.
  • the low-resistance region 108N has a higher carrier concentration than the region 108C and functions as a source region and a drain region.
  • the region 108N can be referred to as a region having a lower resistance than the region 108C, a region having a high carrier concentration, a region having a large amount of oxygen vacancies, a region having a high hydrogen concentration, or a region having a high impurity concentration.
  • the sheet resistance of the region 108N is 1 ⁇ / ⁇ or more and less than 1 ⁇ 10 3 ⁇ / ⁇ , preferably 1 ⁇ / ⁇ or more and 8 ⁇ 10 2 ⁇ / ⁇ or less. preferable.
  • the higher the electric resistance of the region 108C in the state where no channel is formed the more preferable.
  • the sheet resistance of the region 108C is 1 ⁇ 10 9 ⁇ / ⁇ or more, preferably 5 ⁇ 10 9 ⁇ / ⁇ or more, more preferably Is preferably 1 ⁇ 10 10 ⁇ / ⁇ or more.
  • the region 108L is also referred to as a region having similar or lower resistance, a region having similar or higher carrier concentration, a region having similar or higher oxygen defect density, or a region having similar or higher impurity concentration than the region 108C. it can.
  • the region 108L may also be referred to as a region having similar or higher resistance, a region having similar or lower carrier concentration, a region having similar or lower oxygen defect density, and a region having similar or lower impurity concentration than the region 108N. it can.
  • the sheet resistance of the region 108L is preferably 1 ⁇ 10 3 ⁇ / ⁇ or more and 1 ⁇ 10 9 ⁇ / ⁇ or less, more preferably 1 ⁇ 10 3 ⁇ / ⁇ or more and 1 ⁇ 10 8 ⁇ / ⁇ or less, and further 1 It is preferably not less than ⁇ 10 3 ⁇ / ⁇ and not more than 1 ⁇ 10 7 ⁇ / ⁇ .
  • the sheet resistance can be calculated from the resistance value.
  • the source-drain breakdown voltage of the transistor 100 can be increased by providing such a region 108L between the region 108N and the region 108C.
  • the carrier concentration in the region 108L may not be uniform, and may have a gradient such that the carrier concentration decreases from the region 108N side to the region 108C side.
  • the hydrogen concentration and the oxygen deficiency concentration in the region 108L may have a gradient such that the concentration decreases from the region 108N side to the region 108C side.
  • the region 108L can be formed in a self-aligned manner, a photomask for forming the region 108L is not needed and the manufacturing cost can be reduced. Further, by forming the region 108L in a self-aligning manner, relative displacement between the region 108L and the conductive layer 112 does not occur, so that the width of the region 108L in the semiconductor layer 108 can be approximately matched.
  • a region 108L that functions as an offset region in which the electric field of the gate is not applied or is less likely to be applied than the region 108C can be stably formed between the region 108C and the region 108N in the semiconductor layer 108 without variation. As a result, the source-drain breakdown voltage of the transistor can be improved, and a highly reliable transistor can be realized.
  • the width L2 of the region 108L is preferably 5 nm or more and 2 ⁇ m or less, more preferably 10 nm or more and 1 ⁇ m or less, and further preferably 15 nm or more and 500 nm or less.
  • the width L2 of the region 108L can be determined depending on the thickness of the semiconductor layer 108, the thickness of the insulating layer 110, and the magnitude of the voltage applied between the source and the drain when the transistor 100 is driven.
  • the region 108L between the region 108C and the region 108N By providing the region 108L between the region 108C and the region 108N, the current density at the boundary between the region 108C and the region 108N can be relaxed, heat generation at the boundary between the channel and the source or drain can be suppressed, and a highly reliable transistor or semiconductor can be obtained. It can be a device.
  • the insulating region 150 may include the void 130.
  • the insulating region 150 may include one or more of the void 130 and the insulating layer 118.
  • FIG. 2A shows an example in which the insulating region 150 includes the void 130 and does not include the insulating layer 118.
  • FIG. 2A illustrates an example in which the insulating layer 118 is provided without being in contact with the side surface of the metal oxide layer 114.
  • FIG. 2B shows an example in which the insulating region 150 includes the void 130 and the insulating layer 118.
  • 2B illustrates an example in which the insulating layer 118 is provided in contact with part of the side surface of the metal oxide layer 114.
  • FIG. 3A shows an example in which the insulating region 150 includes the insulating layer 118 and does not include the void 130.
  • 3A illustrates an example in which the insulating layer 118 is provided in contact with the side surface of the metal oxide layer 114.
  • the insulating region 150 when the insulating region 150 includes the void 130 and does not include the insulating layer 118, the insulating region 150 has air, and the relative permittivity ⁇ r of the insulating region 150 is about 1 as in air. ..
  • the relative permittivity ⁇ r of silicon oxide that can be used as the insulating layer 110 is approximately 4.0 to 4.5, and the relative permittivity ⁇ r of silicon nitride is approximately 7.0.
  • the relative permittivity ⁇ r is larger than 1.
  • the relative permittivity ⁇ r of the insulating region 150 can be calculated from the area ratio of the void 130 and the insulating layer 118 in the cross section, and the insulating region 150 The relative permittivity ⁇ r becomes larger than 1. Therefore, when the insulating region 150 includes the void 130, the relative dielectric constants of the insulating region 150 and the insulating layer 110 are different.
  • the term “differing relative permittivity” means that, of the two relative permittivities, the ratio of the relative permittivity of the one having the smaller relative permittivity to the relative permittivity of the other is 2. Indicates 0 or more.
  • the transistor 100 may include a conductive layer 120a and a conductive layer 120b over the insulating layer 118.
  • the conductive layers 120a and 120b function as a source electrode or a drain electrode.
  • the conductive layers 120a and 120b are electrically connected to the region 108N through the openings 141a and 141b provided in the insulating layer 118 and the insulating layer 110, respectively.
  • a conductive film containing a metal or an alloy as the conductive layer 112 because electric resistance can be suppressed.
  • an oxide conductive film may be used for the conductive layer 112.
  • the metal oxide layer 114 has a function of supplying oxygen into the insulating layer 110. Further, the metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 functions as a barrier film that prevents oxygen contained in the insulating layer 110 from diffusing to the conductive layer 112 side. Further, the metal oxide layer 114 also functions as a barrier film which prevents hydrogen and water contained in the conductive layer 112 from diffusing to the insulating layer 110 side. For the metal oxide layer 114, for example, it is preferable to use a material that is less likely to transmit oxygen and hydrogen than at least the insulating layer 110.
  • the metal oxide layer 114 can prevent diffusion of oxygen from the insulating layer 110 to the conductive layer 112 even when a metal material such as aluminum or copper which easily absorbs oxygen is used for the conductive layer 112. .. Even when the conductive layer 112 contains hydrogen, hydrogen can be prevented from diffusing from the conductive layer 112 to the semiconductor layer 108 through the insulating layer 110. As a result, the carrier density in the channel formation region of the semiconductor layer 108 can be extremely low.
  • a metal oxide can be used as the metal oxide layer 114.
  • an oxide containing indium such as indium oxide, indium zinc oxide, indium tin oxide (ITO), or indium tin oxide containing silicon (ITSO) can be used.
  • ITO indium tin oxide
  • ITSO indium tin oxide containing silicon
  • a conductive oxide containing indium is preferable because it has high conductivity.
  • ITSO does not easily crystallize due to the inclusion of silicon and has high flatness, adhesion with a film formed on ITSO is increased.
  • a metal oxide such as zinc oxide or zinc oxide containing gallium can be used as the metal oxide layer 114.
  • a structure in which these are stacked may be used.
  • the metal oxide layer 114 it is preferable to use an oxide material containing one or more elements that are the same as those of the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material applicable to the semiconductor layer 108. At this time, it is preferable to use, as the metal oxide layer 114, a metal oxide film formed using the same sputtering target as that for the semiconductor layer 108 because the devices can be shared.
  • the metal oxide layer 114 is preferably formed using a sputtering device.
  • oxygen can be added to the insulating layer 110 and the semiconductor layer 108 by forming the oxide film in an atmosphere containing oxygen gas.
  • the region 108N of the semiconductor layer 108 is a region containing an impurity element.
  • the impurity element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, or a rare gas.
  • typical examples of rare gases include helium, neon, argon, krypton, xenon, and the like.
  • the process of adding an impurity to the region 108N can be performed through the insulating layer 110 with the conductive layer 112 as a mask.
  • the region 108N has an impurity concentration of 1 ⁇ 10 19 atoms / cm 3 or more and 1 ⁇ 10 23 atoms / cm 3 or less, preferably 5 ⁇ 10 19 atoms / cm 3 or more, 5 ⁇ 10 22 atoms / cm 3 or less, It is more preferable to include a region of 1 ⁇ 10 20 atoms / cm 3 or more and 1 ⁇ 10 22 atoms / cm 3 or less.
  • the concentration of impurities contained in the region 108N may be analyzed by an analysis method such as secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) or X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy). It can.
  • an analysis method such as secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) or X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).
  • SIMS Secondary Ion Mass Spectrometry
  • XPS X-ray Photoelectron Spectroscopy
  • the impurity element preferably exists in an oxidized state.
  • an easily oxidizable element such as boron, phosphorus, magnesium, aluminum, or silicon
  • Such an element that is easily oxidized can exist stably in a state where it is oxidized by being combined with oxygen in the semiconductor layer 108, and therefore, at a high temperature (for example, 400 ° C or higher, 600 ° C or higher, or 800 ° C or higher) in a later step. ), The desorption is suppressed. Further, a large number of oxygen vacancies are generated in the region 108N because the impurity element deprives oxygen in the semiconductor layer 108.
  • the oxygen deficiency and hydrogen in the film combine to serve as a carrier supply source, so that the region 108N has an extremely low resistance.
  • the boron contained in the region 108N can exist in a state of being bonded to oxygen. This can be confirmed by the fact that the spectrum peak due to the B 2 O 3 bond is observed in the XPS analysis. Further, in XPS analysis, a spectral peak due to the state where elemental boron is present alone is not observed, or the peak intensity is extremely small to such an extent that it is buried in background noise observed near the lower limit of measurement.
  • the concentration of the impurity element in each of the regions 108L and 108C is preferably less than or equal to 1/10 of the concentration of the impurity element in the region 108N, further preferably less than or equal to 1/100.
  • An oxide film is preferably used for the insulating layers 103 and 110 which are in contact with the channel formation region of the semiconductor layer 108.
  • an oxide film such as a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film can be used.
  • oxygen desorbed from the insulating layer 103 or the insulating layer 110 can be supplied to the channel formation region of the semiconductor layer 108 by heat treatment or the like in the manufacturing process of the transistor 100, so that oxygen vacancies in the semiconductor layer 108 can be reduced.
  • an oxynitride refers to a substance whose composition contains more oxygen than nitrogen, and an oxynitride is included in an oxide.
  • Nitride oxide refers to a substance whose composition contains more nitrogen than oxygen, and nitride oxide is included in nitride.
  • the insulating layer 110 in contact with the semiconductor layer 108 more preferably has a region containing oxygen in excess of the stoichiometric composition.
  • the insulating layer 110 has an insulating film that can release oxygen.
  • the insulating layer 110 is formed in an oxygen atmosphere, heat treatment in an oxygen atmosphere, plasma treatment, or the like is performed on the formed insulating layer 110, or the insulating layer 110 is formed over the insulating layer 110 in an oxygen atmosphere.
  • Oxygen can be supplied into the insulating layer 110 by forming an oxide film or the like.
  • the insulating layer 110 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method. And the like.
  • CVD chemical vapor deposition
  • PLA pulsed laser deposition
  • ALD atomic layer deposition
  • CVD method there are a plasma chemical vapor deposition (PECVD: Plasma Enhanced CVD) method, a thermal CVD method and the like.
  • the insulating layer 110 is preferably formed by the plasma CVD method.
  • the insulating layer 110 is formed on the semiconductor layer 108, it is preferable that the insulating layer 110 is a film formed under conditions that do not damage the semiconductor layer 108 as much as possible.
  • the film formation can be performed under the condition that the film formation rate (also referred to as a film formation rate) is sufficiently low.
  • a film forming gas used for forming the silicon oxynitride film includes, as a raw material, a deposition gas containing silicon such as silane and disilane, and an oxidizing gas such as oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide. Gas can be used. Further, in addition to the raw material gas, a diluent gas such as argon, helium or nitrogen may be contained.
  • the insulating layer 110 has a region in contact with the region 108C of the semiconductor layer 108, that is, a region overlapping with the conductive layer 112 and the metal oxide layer 114.
  • the insulating layer 110 has a region which is in contact with the region 108L of the semiconductor layer 108 and which does not overlap with the metal oxide layer 114.
  • the insulating layer 110 has a region which is in contact with the region 108N of the semiconductor layer 108 and which does not overlap with the conductive layer 112.
  • a region 110i of the insulating layer 110 which overlaps with the region 108N, may contain the above-described impurity element.
  • the impurity element in the insulating layer 110 preferably exists in a state of being bonded to oxygen.
  • Such an element that is easily oxidized can stably exist in a state of being oxidized by being combined with oxygen in the insulating layer 110, and thus desorption is suppressed even when a high temperature is applied in a later step.
  • the insulating layer 110 contains oxygen which can be released by heating (also referred to as excess oxygen)
  • the excess oxygen and the impurity element are combined and stabilized, so that oxygen is transferred from the insulating layer 110 to the region 108N.
  • Oxygen is less likely to diffuse in a part of the insulating layer 110 containing the oxidized impurity element; therefore, oxygen is supplied to the region 108N from above the insulating layer 110 through the insulating layer 110. It can be suppressed that the resistance of the region 108N is increased.
  • the insulating layer 103 has a region 103i containing the above-described impurity element at or near the interface in contact with the insulating layer 110. Further, as shown in FIG. 2A, the region 103i may be provided at the interface in contact with the region 108N or in the vicinity thereof. At this time, the impurity concentration in a portion overlapping with the region 108N is lower than that in a portion in contact with the insulating layer 110.
  • the insulating layer 110 and the insulating layer 103 may each have a laminated structure.
  • An example in which the insulating layer 110 and the insulating layer 103 each have a stacked structure is illustrated in FIG. 3B.
  • the insulating layer 110 has a stacked structure in which an insulating layer 110a, an insulating layer 110b, and an insulating layer 110c are stacked from the semiconductor layer 108 side.
  • the insulating layer 103 has a stacked structure in which an insulating layer 103a, an insulating layer 103b, an insulating layer 103c, and an insulating layer 103d are stacked from the substrate 102 side. Note that in FIG. 3B, the region 110i and the region 103i are omitted for clarity.
  • the insulating layer 110a has a region in contact with the semiconductor layer 108.
  • the insulating layer 110c has a region in contact with the metal oxide layer 114.
  • the insulating layer 110b is located between the insulating layer 110a and the insulating layer 110c.
  • the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c are preferably insulating films each containing an oxide. At this time, it is preferable that the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c be continuously formed by the same film forming apparatus.
  • insulating layers 110a, 110b, and 110c a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, or a gallium oxide film is used.
  • An insulating layer containing one or more of a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film can be used.
  • the insulating layer 110 that is in contact with the semiconductor layer 108 preferably has a stacked-layer structure of oxide insulating films and more preferably has a region containing oxygen in excess of the stoichiometric composition.
  • the insulating layer 110 has an insulating film that can release oxygen.
  • the insulating layer 110 is formed in an oxygen atmosphere, heat treatment in an oxygen atmosphere, plasma treatment, or the like is performed on the formed insulating layer 110, or the insulating layer 110 is formed over the insulating layer 110 in an oxygen atmosphere.
  • Oxygen can be supplied into the insulating layer 110 by forming an oxide film or the like.
  • the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c are formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulse laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like. Can be formed. Further, as the CVD method, there are a plasma chemical vapor deposition (PECVD) method, a thermal CVD method and the like.
  • PECVD plasma chemical vapor deposition
  • the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c are preferably formed by a plasma CVD method.
  • the insulating layer 110a is formed on the semiconductor layer 108, it is preferable that the insulating layer 110a is a film formed under conditions that do not damage the semiconductor layer 108 as much as possible.
  • the film formation can be performed under the condition that the film formation rate (also referred to as a film formation rate) is sufficiently low.
  • a silicon oxynitride film is formed as the insulating layer 110a by a plasma CVD method
  • damage to the semiconductor layer 108 can be extremely reduced by forming it under low power conditions.
  • a film formed by a film formation method in which damage to the semiconductor layer 108 is reduced is used as the insulating layer 110a in contact with the top surface of the semiconductor layer 108. Therefore, the defect level density at the interface between the semiconductor layer 108 and the insulating layer 110 is reduced, so that the transistor 100 having high reliability can be provided.
  • a film forming gas used for forming the silicon oxynitride film includes, as a raw material, a deposition gas containing silicon such as silane and disilane, and an oxidizing gas such as oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide. Gas can be used. Further, in addition to the raw material gas, a diluent gas such as argon, helium or nitrogen may be contained.
  • the deposition rate can be reduced, and a dense film with few defects can be deposited. it can.
  • the insulating layer 110b is preferably a film formed under the condition that the film forming rate is higher than that of the insulating layer 110a. Thereby, the productivity can be improved.
  • the insulating layer 110b can be deposited under the condition that the deposition rate is increased by increasing the flow rate ratio of the deposition gas to that of the insulating layer 110a.
  • the insulating layer 110c is preferably an extremely dense film in which surface defects are reduced and impurities such as water contained in the atmosphere are not easily adsorbed.
  • the film can be formed under the condition that the film formation rate is sufficiently low.
  • the insulating layer 110c is formed on the insulating layer 110b, the influence on the semiconductor layer 108 at the time of forming the insulating layer 110c is smaller than that of the insulating layer 110a. Therefore, the insulating layer 110c can be formed under a condition of higher power than that of the insulating layer 110a. By reducing the flow rate ratio of the deposition gas and forming the film with relatively high power, a dense film with reduced surface defects can be obtained.
  • a laminated film formed under the conditions in which the insulating layer 110b, the insulating layer 110a, and the insulating layer 110c are arranged in this order from the one having the highest film forming rate can be used as the insulating layer 110.
  • the insulating layer 110 has a higher etching rate under the same conditions for wet etching or dry etching in the order of the insulating layer 110b, the insulating layer 110a, and the insulating layer 110c.
  • the insulating layer 110b is preferably formed thicker than the insulating layers 110a and 110c. By forming the insulating layer 110b having the highest film formation rate thick, the time required for the step of forming the insulating layer 110 can be shortened.
  • the boundary between the insulating layer 110a and the insulating layer 110b and the boundary between the insulating layer 110b and the insulating layer 110c may be unclear in some cases, these boundaries are clearly indicated by broken lines in FIG. 3B. Since the insulating layers 110a and 110b have different film densities, it is possible to observe these boundaries as differences in contrast in a transmission electron microscope (TEM) image in a cross section of the insulating layer 110. Sometimes you can. Similarly, the boundary between the insulating layer 110b and the insulating layer 110c can be observed in some cases.
  • TEM transmission electron microscope
  • the insulating layer 103 has a stacked structure in which an insulating layer 103a, an insulating layer 103b, an insulating layer 103c, and an insulating layer 103d are stacked from the substrate 102 side.
  • the insulating layer 103a is in contact with the substrate 102.
  • the insulating layer 103d is in contact with the semiconductor layer 108.
  • the insulating layer 103 which functions as the second gate insulating layer has a high withstand voltage, a small stress in the film, a difficulty in releasing hydrogen and water, a small number of defects in the film, and an impurity contained in the substrate 102. Among the suppression of diffusion, it is preferable to satisfy one or more, and it is most preferable to satisfy all of these.
  • the four insulating films included in the insulating layer 103 it is preferable to use insulating films containing nitrogen for the insulating layers 103a, 103b, and 103c located on the substrate 102 side. On the other hand, it is preferable to use an insulating film containing oxygen for the insulating layer 103d which is in contact with the semiconductor layer 108. In addition, it is preferable that the four insulating films included in the insulating layer 103 be successively formed using a plasma CVD apparatus without being exposed to the air.
  • a nitrogen-containing insulating film such as a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or a hafnium nitride film can be used.
  • an insulating film that can be used for the insulating layer 110 can be used.
  • the insulating layers 103a and 103c are preferably dense films that can prevent diffusion of impurities from below.
  • the insulating layer 103a is preferably a film capable of blocking impurities contained in the substrate 102
  • the insulating layer 103c is preferably a film capable of blocking hydrogen or water contained in the insulating layer 103b. Therefore, for the insulating layers 103a and 103c, an insulating film formed at a lower film formation rate than the insulating layer 103b can be used.
  • the insulating layer 103b it is preferable to use an insulating film formed under the condition of low stress and high film formation rate.
  • the insulating layer 103b is preferably formed thicker than the insulating layers 103a and 103c.
  • the insulating layer 103b is a film more than the other two insulating films.
  • the film has a low density. Therefore, in a transmission electron microscope image or the like in the cross section of the insulating layer 103, it may be possible to observe as a difference in contrast. Note that the boundary between the insulating layer 103a and the insulating layer 103b and the boundary between the insulating layer 103b and the insulating layer 103c may be unclear in some cases. Therefore, in FIG. 3B, these boundaries are clearly indicated by broken lines.
  • the insulating layer 103d in contact with the semiconductor layer 108 is preferably a dense insulating film in which impurities such as water are less likely to be adsorbed on the surface.
  • impurities such as water are less likely to be adsorbed on the surface.
  • the same insulating film as the insulating layer 110c included in the insulating layer 110 can be used as the insulating layer 103d.
  • the insulating layer 118 functions as a protective layer that protects the transistor 100.
  • an inorganic insulating material such as an oxide or a nitride can be used.
  • an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, or hafnium aluminate can be used.
  • the insulating layer 118 is preferably made of a material having high step coverage. Alternatively, the insulating layer 118 is preferably formed by a film formation method with high step coverage. The PECVD method can be preferably used for forming the insulating layer 118, for example. Note that due to the step between the conductive layer 112 and the insulating layer 110, the coverage with the insulating layer 118 provided thereover is deteriorated, and a stepped portion of the insulating layer 118 or a low-density region (also referred to as a void) is formed.
  • a stepped portion of the insulating layer 118 or a low-density region also referred to as a void
  • impurities such as water or hydrogen enter from the outside, which might lead to deterioration in reliability of the transistor.
  • the insulating layer 118 having high step coverage a highly reliable transistor can be obtained.
  • FIG. 4A shows an example in which the thickness of the insulating layer 110 in a region which does not overlap with the metal oxide layer 114 is smaller than the thickness of the insulating layer 110 in a region which overlaps with the metal oxide layer 114.
  • FIG. 4B illustrates an example in which the thickness of the insulating layer 110 in a region which does not overlap with the conductive layer 112 is smaller than that of the insulating layer 110 in a region which does not overlap with the conductive layer 112. Note that when the insulating layer 110 has a stacked-layer structure as illustrated in FIG.
  • the insulating layer 110c is preferably left in a region which does not overlap with the metal oxide layer 114. With the structure in which the insulating layer 110c remains in the non-overlapping region, adsorption of water to the insulating layer 110 can be efficiently suppressed.
  • the thickness of the insulating layer 110c in a region overlapping with the conductive layer 112 is 1 nm to 50 nm inclusive, preferably 2 nm to 40 nm inclusive, more preferably 3 nm to 30 nm inclusive.
  • FIG. 5A is a top view of the transistor 100A
  • FIG. 5B is a cross-sectional view of the transistor 100A in the channel length direction
  • FIG. 5C is a cross-sectional view of the transistor 100A in the channel width direction.
  • the transistor 100A mainly differs from the configuration example 1 in that the conductive layer 106 is provided between the substrate 102 and the insulating layer 103.
  • the conductive layer 106 has a region overlapping with the semiconductor layer 108 and the conductive layer 112.
  • the conductive layer 112 has a function as a second gate electrode (also referred to as a top gate electrode), and the conductive layer 106 has a function as a first gate electrode (also referred to as a bottom gate electrode). ..
  • part of the insulating layer 110 functions as a second gate insulating layer and part of the insulating layer 103 functions as a first gate insulating layer.
  • the conductive layer 106 may be electrically connected to the conductive layer 112 through the openings 142 provided in the metal oxide layer 114, the insulating layer 110, and the insulating layer 103. .. Accordingly, the same potential can be applied to the conductive layer 106 and the conductive layer 112.
  • the conductive layer 106 can be made of the same material as the conductive layer 112, the conductive layer 120a, or the conductive layer 120b. In particular, it is preferable to use a material containing copper for the conductive layer 106 because wiring resistance can be reduced.
  • the conductive layer 112 and the conductive layer 106 project outward from the end portion of the semiconductor layer 108 in the channel width direction.
  • the entire semiconductor layer 108 in the channel width direction is covered with the conductive layer 112 and the conductive layer 106 with the insulating layer 110 and the insulating layer 103 interposed therebetween.
  • the semiconductor layer 108 can be electrically surrounded by an electric field generated by the pair of gate electrodes. At this time, it is particularly preferable to apply the same potential to the conductive layer 106 and the conductive layer 112. Thus, an electric field for inducing a channel can be effectively applied to the semiconductor layer 108, so that the on-state current of the transistor 100A can be increased. Therefore, the transistor 100A can be miniaturized.
  • the conductive layer 112 and the conductive layer 106 may not be connected. At this time, a constant potential may be applied to one of the pair of gate electrodes and a signal for driving the transistor 100A may be applied to the other. At this time, the threshold voltage when the transistor 100A is driven by the other gate electrode can be controlled by the potential applied to the one gate electrode.
  • the insulating layer 103 preferably has a laminated structure.
  • the insulating layer 103 can have a stacked-layer structure in which the insulating layer 103a, the insulating layer 103b, the insulating layer 103c, and the insulating layer 103d are stacked from the conductive layer 106 side (see FIG. 3B).
  • the insulating layer 103a in contact with the conductive layer 106 is preferably a film which can block a metal element contained in the conductive layer 106. Since the above description can be referred to for the insulating layer 103a, the insulating layer 103b, the insulating layer 103c, and the insulating layer 103d, detailed description thereof is omitted.
  • the insulating layer 103a is not provided and the three insulating films of the insulating layer 103b, the insulating layer 103c, and the insulating layer 103d are provided. May be laminated.
  • FIG. 6A is a cross-sectional view of the transistor 100B in the channel length direction
  • FIG. 6B is a cross-sectional view of the transistor 100B in the channel width direction.
  • the top view of the transistor 100B can be referred to FIG. 5A; therefore, the description is omitted.
  • the transistor 100B mainly differs from the transistor 100A illustrated in the configuration example 2 in that the insulating layer 116 is provided on the insulating layer 118.
  • the insulating layer 116 is provided so as to cover the upper surface of the insulating layer 110.
  • the insulating layer 116 has a function of suppressing diffusion of impurities from above the insulating layer 116 into the semiconductor layer 108.
  • the conductive layers 120a and 120b are electrically connected to the region 108N through the openings 141a and 141b provided in the insulating layer 116, the insulating layer 118, and the insulating layer 110, respectively.
  • an insulating film containing a nitride such as silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, or aluminum nitride oxide can be preferably used.
  • silicon nitride has a blocking property against hydrogen and oxygen, it is possible to prevent both diffusion of hydrogen from the outside to the semiconductor layer and desorption of oxygen from the semiconductor layer to the outside, so that a highly reliable transistor can be obtained. realizable.
  • a metal nitride As the insulating layer 116, it is preferable to use a nitride of aluminum, titanium, tantalum, tungsten, chromium, or ruthenium. In particular, it is particularly preferable to contain aluminum or titanium.
  • aluminum As a sputtering target, an aluminum nitride film formed by a reactive sputtering method using a gas containing nitrogen as a film forming gas, by appropriately controlling the flow rate of nitrogen gas with respect to the total flow rate of the film forming gas, A film having both extremely high insulating properties and extremely high blocking properties against hydrogen and oxygen can be obtained.
  • the thickness of the insulating layer containing the aluminum nitride is preferably 5 nm or more. Even with such a thin film, a high blocking property against hydrogen and oxygen and a function of lowering the resistance of the semiconductor layer can both be achieved.
  • the insulating layer may have any thickness, but in view of productivity, it is preferably 500 nm or less, preferably 200 nm or less, more preferably 50 nm or less.
  • a film whose composition formula satisfies AlN x (x is a real number greater than 0 and 2 or less, preferably x is greater than 0.5 and less than or equal to 1.5) is used. Is preferred. Accordingly, a film having excellent insulating properties and excellent thermal conductivity can be obtained, so that heat dissipation of heat generated when the transistor 100B is driven can be improved.
  • An aluminum titanium nitride film, a titanium nitride film, or the like can be used as the insulating layer 116.
  • a transistor with high on-state current can be obtained.
  • a transistor whose threshold voltage can be controlled can be used. Further, the transistor can have high reliability.
  • FIG. 7A is a cross-sectional view of the transistor 100C in the channel length direction
  • FIG. 7B is a cross-sectional view of the transistor 100C in the channel width direction.
  • the top view of the transistor 100C can be referred to FIG. 5A; therefore, the description is omitted.
  • the transistor 100C mainly differs from the transistor 100A illustrated in the configuration example 2 in that the insulating layer 116 is provided between the insulating layer 118 and the insulating layer 110.
  • the insulating layer 116 is provided so as to cover the upper surface of the insulating layer 118 and the upper and side surfaces of the conductive layer.
  • the insulating layer 116 may be provided in contact with the side surface of the metal oxide layer 114.
  • the insulating layer 116 may be provided in contact with part of the side surface of the metal oxide layer 114.
  • the insulating layer 116 has a function of suppressing diffusion of impurities from above the insulating layer 116 into the semiconductor layer 108.
  • a transistor with high on-state current can be obtained.
  • a transistor whose threshold voltage can be controlled can be used. Further, the transistor can have high reliability.
  • Example of manufacturing method> An example of a method for manufacturing a transistor of one embodiment of the present invention will be described below.
  • the transistor 100A illustrated in the configuration example 2 will be described as an example.
  • the thin films (insulating film, semiconductor film, conductive film, etc.) constituting the semiconductor device are sputtering method, chemical vapor deposition (CVD) method, vacuum vapor deposition method, pulse laser deposition (PLD) method, atomic layer deposition (ALD). ) Method etc. can be used.
  • CVD method include a plasma chemical vapor deposition (PECVD) method and a thermal CVD method.
  • PECVD plasma chemical vapor deposition
  • MOCVD metal organic chemical vapor deposition
  • Thin films (insulating films, semiconductor films, conductive films, etc.) that compose semiconductor devices are spin coat, dip, spray coat, inkjet, dispense, screen print, offset print, doctor knife, slit coat, roll coat, curtain coat, knife. It can be formed by a method such as coating.
  • the thin film When processing a thin film that constitutes a semiconductor device, it is possible to process it using a photolithography method or the like.
  • the thin film may be processed by a nanoimprint method, a sandblast method, a lift-off method, or the like.
  • the island-shaped thin film may be directly formed by a film forming method using a shielding mask such as a metal mask.
  • the following two methods are typically used as the photolithography method.
  • One is a method of forming a resist mask on a thin film to be processed, processing the thin film by etching or the like, and removing the resist mask.
  • the other is a method in which a thin film having photosensitivity is formed and then exposed and developed to process the thin film into a desired shape.
  • the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof.
  • ultraviolet light, KrF laser light, ArF laser light, or the like can be used.
  • the exposure may be performed by a liquid immersion exposure technique.
  • extreme ultraviolet (EUV) light or X-ray may be used.
  • an electron beam may be used instead of the light used for exposure. The use of extreme ultraviolet light, X-rays or electron beams is preferable because it enables extremely fine processing. Note that a photomask is not necessary when exposure is performed by scanning a beam such as an electron beam.
  • etching of the thin film a dry etching method, a wet etching method, a sandblast method, etc. can be used.
  • 8A to 11C show side by side cross-sectional views in the channel length direction and the channel width direction at each stage of the manufacturing process of the transistor 100A.
  • a conductive film is formed over the substrate 102 and processed by etching to form the conductive layer 106 which functions as a gate electrode (FIG. 8A).
  • the wiring resistance can be reduced by using a conductive film containing copper as the conductive film to be the conductive layer 106.
  • a conductive film containing copper As the conductive film to be the conductive layer 106, it is preferable to use a conductive film containing copper. Even when a conductive film containing copper is used for the conductive layer 106, the insulating layer 103 suppresses diffusion of copper toward the semiconductor layer 108, so that a highly reliable transistor can be realized.
  • the insulating layer 103 is formed so as to cover the substrate 102 and the conductive layer 106.
  • the insulating layer 103 can be formed by a PECVD method, an ALD method, a sputtering method, or the like.
  • the insulating layer 103 is formed by stacking an insulating layer 103a, an insulating layer 103b, an insulating layer 103c, and an insulating layer 103d.
  • each insulating layer forming the insulating layer 103 is formed by the PECVD method.
  • the description of Structural Example 1 can be applied to the method for forming the insulating layer 103.
  • a process of supplying oxygen to the insulating layer 103 may be performed.
  • plasma treatment or heat treatment in an oxygen atmosphere can be performed.
  • oxygen may be supplied to the insulating layer 103 by a plasma ion doping method or an ion implantation method.
  • the metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target.
  • the metal oxide film 108f is preferably a dense film with as few defects as possible.
  • the metal oxide film 108f is preferably a high-purity film in which impurities such as hydrogen and water are reduced as much as possible.
  • impurities such as hydrogen and water are reduced as much as possible.
  • oxygen gas and an inert gas for example, helium gas, argon gas, xenon gas, etc.
  • an inert gas for example, helium gas, argon gas, xenon gas, etc.
  • the crystallinity of the metal oxide film 108f can be increased as the proportion of oxygen gas in the entire deposition gas in forming the metal oxide film 108f (hereinafter also referred to as an oxygen flow rate ratio) increases.
  • an oxygen flow rate ratio the proportion of oxygen gas in the entire deposition gas in forming the metal oxide film 108f
  • the lower the oxygen flow rate ratio the lower the crystallinity of the metal oxide film 108f, and the transistor with higher on-state current can be obtained.
  • the film formation conditions for the metal oxide film 108f may be such that the substrate temperature is room temperature or higher and 250 ° C. or lower, preferably room temperature or higher and 200 ° C. or lower, and more preferably the substrate temperature is room temperature or higher and 140 ° C. or lower.
  • the substrate temperature is room temperature or higher and lower than 140 ° C. because productivity is high.
  • the crystallinity can be lowered by forming the metal oxide film 108f in a state where the substrate temperature is room temperature or the substrate is not heated.
  • any one or more of a treatment for desorbing water, hydrogen, an organic substance, and the like adsorbed on the surface of the insulating layer 103 and a treatment for supplying oxygen into the insulating layer 103 before forming the metal oxide film 108f. Is preferably performed.
  • heat treatment can be performed at a temperature of 70 ° C to 200 ° C in a reduced pressure atmosphere.
  • plasma treatment may be performed in an atmosphere containing oxygen.
  • oxygen may be supplied to the insulating layer 103 by plasma treatment in an atmosphere containing an oxidizing gas such as dinitrogen monoxide (N 2 O).
  • oxygen can be supplied while preferably removing organic substances on the surface of the insulating layer 103. After such treatment, it is preferable to continuously form the metal oxide film 108f without exposing the surface of the insulating layer 103 to the air.
  • the semiconductor layer 108 has a stacked-layer structure in which a plurality of semiconductor layers is stacked, after the metal oxide film which is formed first is formed, the surface of the metal oxide film is continuously exposed without being exposed to the atmosphere. It is preferable to form a metal oxide film.
  • the island-shaped semiconductor layer 108 is formed by etching a part of the metal oxide film 108f (FIG. 8C).
  • the metal oxide film 108f may be processed by either the wet etching method or the dry etching method, or both. At this time, part of the insulating layer 103 which does not overlap with the semiconductor layer 108 may be etched and thinned. For example, in the insulating layer 103, the insulating layer 103d may disappear by etching and the surface of the insulating layer 103c may be exposed.
  • the heat treatment it is preferable to perform heat treatment after forming the metal oxide film 108f or after processing the semiconductor layer 108.
  • the heat treatment may improve the film quality of the metal oxide film 108f or the semiconductor layer 108 (eg, reduction of defects, improvement of crystallinity, or the like).
  • oxygen can be supplied from the insulating layer 103 to the metal oxide film 108f or the semiconductor layer 108. At this time, it is more preferable to perform heat treatment before processing the semiconductor layer 108.
  • the temperature of the heat treatment can be typically 150 ° C. or higher and lower than the strain point of the substrate, 200 ° C. or higher and 500 ° C. or lower, or 250 ° C. or higher and 450 ° C. or lower, or 300 ° C. or higher and 450 ° C. or lower.
  • Heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. Alternatively, after heating in the atmosphere, heating may be performed in an atmosphere containing oxygen. Alternatively, the heating may be performed in a dry air atmosphere. Note that it is preferable that the atmosphere for the heat treatment contains as little hydrogen and water as possible.
  • An electric furnace, an RTA (Rapid Thermal Anneal) device, or the like can be used for the heat treatment. By using the RTA device, the heat treatment time can be shortened.
  • heat treatment may be omitted if unnecessary.
  • heat treatment may not be performed here and may also serve as heat treatment performed in a later step. In some cases, it can be combined with the heat treatment in a high-temperature treatment (such as a film-forming step) in a later step.
  • the insulating layer 110 is formed so as to cover the insulating layer 103 and the semiconductor layer 108 (FIG. 8D).
  • each insulating layer forming the insulating layer 110 is formed by the PECVD method.
  • the description in Structural Example 1 can be applied to the method for forming each layer included in the insulating layer 110.
  • the plasma treatment Before forming the insulating layer 110, it is preferable to perform plasma treatment on the surface of the semiconductor layer 108.
  • impurities such as water adsorbed on the surface of the semiconductor layer 108 can be reduced. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 110 can be reduced, so that a highly reliable transistor can be realized.
  • the plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, dinitrogen monoxide, argon, or the like. Further, the plasma treatment and the film formation of the insulating layer 110 are preferably performed continuously without being exposed to the air.
  • the heat treatment it is preferable to perform heat treatment after forming the insulating layer 110.
  • hydrogen or water contained in the insulating layer 110 or adsorbed on the surface can be removed.
  • defects in the insulating layer 110 can be reduced.
  • heat treatment may be omitted if unnecessary.
  • heat treatment may not be performed here and may also serve as heat treatment performed in a later step. In some cases, it can be combined with the heat treatment in a high-temperature treatment (such as a film-forming step) in a later step.
  • the metal oxide film 114f is preferably formed in an atmosphere containing oxygen, for example.
  • it is preferably formed by a sputtering method in an atmosphere containing oxygen. Accordingly, oxygen can be supplied to the insulating layer 110 when the metal oxide film 114f is formed.
  • the metal oxide film 114f is formed by a sputtering method using an oxide target containing a metal oxide similar to that of the semiconductor layer 108.
  • the metal oxide film may be formed by a reactive sputtering method using oxygen as a film forming gas and a metal target.
  • oxygen as a film forming gas
  • a metal target for example, an aluminum oxide film can be formed.
  • the width L2 of the region 108L can be controlled by adjusting the film formation conditions of the metal oxide film 114f. For example, when the metal oxide film 114f is formed, the crystallinity of the metal oxide film 114f becomes higher as the pressure inside the film forming chamber of the film forming apparatus becomes lower, and the width of the region 108L becomes larger when the metal oxide layer 114 is formed later. L2 can be reduced. The higher the pressure in the deposition chamber, the lower the crystallinity of the metal oxide film 114f, and the larger the width L2 of the region 108L can be when the metal oxide layer 114 is formed later. In this way, the width L2 of the region 108L can be controlled by adjusting the pressure in the deposition chamber when the metal oxide film 114f is deposited.
  • the higher the power supply power, the higher the crystallinity of the metal oxide film 114f, and the width L2 of the region 108L can be reduced when the metal oxide layer 114 is formed later.
  • the substrate temperature during the formation of the metal oxide film 108f and the substrate during the formation of the metal oxide film 114f is the same.
  • the ratio of the oxygen flow rate to the total flow rate of the deposition gas introduced into the deposition chamber of the deposition apparatus oxygen flow rate ratio
  • the higher the oxygen partial pressure in the deposition chamber the higher the metal content.
  • the crystallinity of the oxide film 114f is increased, and the width L2 of the region 108L can be reduced when the metal oxide layer 114 is formed later.
  • the ratio of the oxygen flow rate to the total flow rate of the deposition gas introduced into the deposition chamber of the deposition apparatus is, for example, higher than 0% and 100% or less, preferably 10% or more and 100% or less, more preferably 20% or more and 100% or less, further preferably 30% or more and 100% or less, and further preferably Is 40% or more and 100% or less.
  • the oxygen flow rate ratio be 100% and the oxygen partial pressure be as close as possible to 100%.
  • Heat treatment is preferably performed after the metal oxide film 114f is formed.
  • oxygen contained in the insulating layer 110 can be supplied to the semiconductor layer 108.
  • oxygen can be prevented from being released from the insulating layer 110 to the outside and a large amount of oxygen can be supplied to the semiconductor layer 108.
  • oxygen vacancies in the semiconductor layer 108 can be reduced and a highly reliable transistor can be realized.
  • heat treatment may be omitted if unnecessary.
  • heat treatment may not be performed here and may also serve as heat treatment performed in a later step. In some cases, it can be combined with the heat treatment in a high-temperature treatment (such as a film-forming step) in a later step.
  • Opening 142 and Conductive Film 112f [Formation of Opening 142 and Conductive Film 112f] Subsequently, the metal oxide film 114f, the insulating layer 110, and part of the insulating layer 103 are etched, so that an opening 142 reaching the conductive layer 106 is formed. Accordingly, the conductive layer 112 to be formed later and the conductive layer 106 can be electrically connected to each other through the opening 142.
  • a conductive film 112f to be the conductive layer 112 is formed on the metal oxide film 114f (FIG. 9A).
  • the conductive film 112f is preferably made of a low resistance metal or alloy material. Further, as the conductive film 112f, it is preferable to use a material which does not easily release hydrogen and which does not easily diffuse hydrogen. Further, it is preferable to use a material which is not easily oxidized as the conductive film 112f.
  • the conductive film 112f is preferably formed by a sputtering method using a sputtering target containing a metal or an alloy.
  • the conductive film 112f is a stacked film in which a conductive film that is difficult to oxidize and hydrogen does not diffuse and a conductive film having low resistance are stacked.
  • a wet etching method can be preferably used for forming the conductive layer 112 and the metal oxide layer 114.
  • an etchant containing one or more of oxalic acid, phosphoric acid, acetic acid, nitric acid, hydrochloric acid, or sulfuric acid can be used.
  • an etchant containing phosphoric acid, acetic acid, and nitric acid can be preferably used.
  • the metal oxide layer 114 and the conductive layer 112 can be formed in the same step by using a structure in which the etching rate of the metal oxide layer 114 is higher than that of the conductive layer 112. Further, the end portion of the metal oxide layer 114 can be located inside the end portion of the conductive layer 112. The width L2 of the region 108L can be controlled by adjusting the etching time. In addition, since they can be formed in the same process, the process can be simplified and the productivity can be improved.
  • the end portions of the conductive layer 112 and the metal oxide layer 114 are located inside the contour of the resist mask 115 as illustrated in FIG. 9C.
  • the width L1 of the conductive layer 112 is smaller than the width of the resist mask 115, the width of the resist mask 115 may be increased so that the width L1 of the conductive layer 112 is desired.
  • the insulating layer 110 is not etched, and the top surface and the side surface of the semiconductor layer 108 and the insulating layer 103 are covered, so that the semiconductor layer 108 and the insulating layer are formed when the conductive layer 112 and the like are formed. It is possible to prevent a part of 103 from being etched and thinning.
  • a resist mask 115 is formed on the conductive film 112f (FIG. 10A).
  • the conductive film 112f is etched using anisotropic etching to form the conductive layer 112 (FIG. 10B). Dry etching can be preferably used as the anisotropic etching.
  • the metal oxide film 114f is etched by wet etching to form the metal oxide layer 114 (FIG. 10C).
  • the etching time is adjusted so that the end portion of the metal oxide layer 114 is inside the end portion of the conductive layer 112.
  • the width L2 of the region 108L can be controlled by adjusting the etching time.
  • the conductive layer 112 and the metal oxide layer 114 are formed by etching the conductive film 112f and the metal oxide film 114f by an anisotropic etching method and then by using an isotropic etching method.
  • the side faces of the metal oxide film 114f may be etched to make the end faces recede (also referred to as side etching).
  • the metal oxide layer 114 which is located inside the conductive layer 112 in plan view, can be formed.
  • etching conditions or techniques may be used for forming the conductive layer 112 and the metal oxide layer 114, and etching may be performed at least twice.
  • the conductive film 112f may be etched first, and then the metal oxide film 114f may be etched under different etching conditions.
  • the thickness of the insulating layer 110 in a region which is not in contact with the metal oxide layer 114 may be thin (see FIGS. 2A, 2B, 3A, and 3B). ).
  • a plasma ion doping method or an ion implantation method can be preferably used. According to these methods, the concentration profile in the depth direction can be controlled with high accuracy by the acceleration voltage of ions, the dose amount, and the like. The productivity can be improved by using the plasma ion doping method. Further, by using the ion implantation method using mass separation, the purity of the supplied impurity element can be increased.
  • the interface between the semiconductor layer 108 and the insulating layer 110, a portion close to the interface in the semiconductor layer 108, or a portion close to the interface in the insulating layer 110 has a highest concentration. It is preferable to control the processing conditions. Thus, the impurity element 140 with an optimum concentration can be supplied to both the semiconductor layer 108 and the insulating layer 110 by one treatment.
  • the impurity element 140 may be hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, or a rare gas.
  • rare gases include helium, neon, argon, krypton, xenon, and the like.
  • a gas containing the above impurity element can be used.
  • B 2 H 6 gas, BF 3 gas, or the like can be typically used.
  • PH 3 gas can be typically used.
  • a mixed gas obtained by diluting these source gases with a rare gas may be used.
  • raw material gases CH 4 , N 2 , NH 3 , AlH 3 , AlCl 3 , SiH 4 , Si 2 H 6 , F 2 , HF, H 2 , (C 5 H 5 ) 2 Mg, and rare gas, etc.
  • the ion source is not limited to a gas, and a solid or liquid heated and vaporized may be used.
  • the addition of the impurity element 140 can be controlled by setting conditions such as an acceleration voltage and a dose amount in consideration of the composition, density, and thickness of the insulating layer 110 and the semiconductor layer 108.
  • the accelerating voltage can be, for example, 5 kV or more and 100 kV or less, preferably 7 kV or more and 70 kV or less, and more preferably 10 kV or more and 50 kV or less.
  • the dose amount is, for example, 1 ⁇ 10 13 ions / cm 2 or more and 1 ⁇ 10 17 ions / cm 2 or less, preferably 1 ⁇ 10 14 ions / cm 2 or more and 5 ⁇ 10 16 ions / cm 2 or less, and more preferably 1 It can be set in the range of not less than ⁇ 10 15 ions / cm 2 and not more than 3 ⁇ 10 16 ions / cm 2 .
  • the acceleration voltage can be, for example, 10 kV or more and 100 kV or less, preferably 30 kV or more and 90 kV or less, and more preferably 40 kV or more and 80 kV or less.
  • the dose amount is, for example, 1 ⁇ 10 13 ions / cm 2 or more and 1 ⁇ 10 17 ions / cm 2 or less, preferably 1 ⁇ 10 14 ions / cm 2 or more and 5 ⁇ 10 16 ions / cm 2 or less, and more preferably 1 It can be set in the range of not less than ⁇ 10 15 ions / cm 2 and not more than 3 ⁇ 10 16 ions / cm 2 .
  • the method of supplying the impurity element 140 is not limited to this, and for example, plasma treatment or treatment utilizing thermal diffusion by heating may be used.
  • the impurity element can be added by generating plasma in a gas atmosphere containing the impurity element to be added and performing plasma treatment.
  • a dry etching device, an ashing device, a plasma CVD device, a high density plasma CVD device, or the like can be used as the device for generating the plasma.
  • the impurity element 140 can be supplied to the semiconductor layer 108 through the insulating layer 110. Therefore, even when the semiconductor layer 108 has crystallinity, damage that the semiconductor layer 108 receives when the impurity element 140 is supplied can be reduced and the crystallinity can be prevented from being impaired. Therefore, it is suitable when the electrical resistance increases due to the decrease in crystallinity.
  • an insulating layer 118 is formed so as to cover the insulating layer 110, the metal oxide layer 114, and the conductive layer 112 (FIG. 11B).
  • the film formation temperature of the insulating layer 118 may be determined in consideration of the above.
  • the film forming temperature of the insulating layer 118 is preferably 150 ° C. or higher and 400 ° C. or lower, preferably 180 ° C. or higher and 360 ° C. or lower, and more preferably 200 ° C. or higher and 250 ° C. or lower.
  • heat treatment may be performed.
  • the heat treatment makes it possible to more stably form the low-resistance region 108N.
  • the impurity element 140 is appropriately diffused and locally homogenized, so that the region 108N having an ideal impurity element concentration gradient can be formed. Note that if the temperature of the heat treatment is too high (eg, 500 ° C. or higher), the impurity element 140 may diffuse into the channel formation region, which might lead to deterioration in electrical characteristics and reliability of the transistor.
  • heat treatment may be omitted if unnecessary.
  • heat treatment may not be performed here and may also serve as heat treatment performed in a later step.
  • a high temperature treatment for example, a film forming step
  • Opening 141a and Opening 141b [Formation of Opening 141a and Opening 141b] Then, part of the insulating layer 118 and the insulating layer 110 is etched to form an opening 141a and an opening 141b reaching the region 108N.
  • the transistor 100A can be manufactured. For example, when the transistor 100A is applied to a pixel of a display device, a step of forming one or more of a protective insulating layer, a planarization layer, a pixel electrode, or a wiring may be added after this.
  • the formation step of the conductive layer 106 and the formation step of the opening 142 in the above-described Manufacturing Method Example 1 may be omitted. Further, the transistor 100 and the transistor 100A can be formed over the same substrate through the same step.
  • the substrate 102 there is no particular limitation on the material of the substrate 102, but it is necessary that the substrate 102 have at least heat resistance high enough to withstand heat treatment performed later.
  • a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like is used as the substrate 102.
  • a substrate provided with a semiconductor element may be used as the substrate 102.
  • a flexible substrate may be used as the substrate 102, and the semiconductor device may be directly formed on the flexible substrate.
  • a separation layer may be provided between the substrate 102 and the semiconductor device.
  • the peeling layer can be used for separating a semiconductor device over the peeling layer, separating the substrate 102 from the substrate 102, and transferring the semiconductor device to another substrate. At that time, the semiconductor device can be transferred to a substrate having poor heat resistance or a flexible substrate.
  • the conductive layer 112 and the conductive layer 106 which function as gate electrodes, the conductive layer 120a which functions as one of the source electrode and the drain electrode, and the conductive layer 120b which functions as the other are chromium, copper, aluminum, gold, silver, zinc, Form each using a metal element selected from molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, or an alloy containing the above metal element as a component or an alloy in which the above metal elements are combined. You can
  • In—Sn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, and In—Ti—Sn are used.
  • An oxide conductor such as an oxide, an In-Zn oxide, an In-Sn-Si oxide, or an In-Ga-Zn oxide, or a metal oxide film can also be applied.
  • the oxide conductor (OC: Oxide Conductor)
  • OC Oxide Conductor
  • a donor level is formed in the vicinity of the conduction band.
  • the metal oxide has high conductivity and becomes a conductor.
  • the metal oxide converted into a conductor can be referred to as an oxide conductor.
  • the conductive layer 112 and the like may have a laminated structure of a conductive film containing the above oxide conductor (metal oxide) and a conductive film containing a metal or an alloy.
  • a conductive film containing a metal or an alloy wiring resistance can be reduced.
  • a conductive film containing an oxide conductor is preferably applied to the side which is in contact with the insulating layer functioning as a gate insulating film.
  • the conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b have at least one selected from titanium, tungsten, tantalum, and molybdenum among the above metal elements. is there.
  • the tantalum nitride film has conductivity, has a high barrier property against copper, oxygen, or hydrogen, and emits little hydrogen from itself; therefore, the conductive film in contact with the semiconductor layer 108 or the semiconductor layer.
  • the conductive film near 108 can be preferably used.
  • the semiconductor layer 108 preferably contains a metal oxide.
  • the semiconductor layer 108 includes indium and M (M is gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, It is preferable to have one or more kinds selected from hafnium, tantalum, tungsten, or magnesium) and zinc.
  • M is preferably one or more selected from aluminum, gallium, yttrium, or tin.
  • the semiconductor layer 108 is an In-M-Zn oxide
  • M: Zn 1: 1: 1 as the atomic ratio of metal elements of a sputtering target used for forming the In-M-Zn oxide.
  • M: Zn 1: 1: 1.2
  • M: Zn 1: 3: 2
  • M: Zn 1: 3: 4
  • M: Zn 1: 3: 6.
  • the atomic ratio of the semiconductor layer 108 to be formed includes a fluctuation of ⁇ 40% in the atomic ratio of the metal element contained in the above sputtering target.
  • the semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more.
  • the off-state current of the transistor can be reduced by using the metal oxide whose energy gap is wider than that of silicon.
  • a metal oxide having a low carrier concentration for the semiconductor layer 108.
  • the concentration of impurities in the metal oxide may be lowered and the density of defect states may be lowered.
  • low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • the impurities in the metal oxide include, for example, hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
  • hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to become water, which may form oxygen deficiency in the metal oxide. If the channel formation region in the metal oxide contains oxygen vacancies, the transistor might have normally-on characteristics. Further, a defect in which hydrogen is contained in an oxygen vacancy may function as a donor and an electron which is a carrier may be generated. Further, part of hydrogen may be bonded to oxygen which is bonded to a metal atom to generate an electron which is a carrier. Therefore, a transistor including a metal oxide containing a large amount of hydrogen is likely to have normally-on characteristics.
  • the metal oxide may be evaluated not by the donor concentration but by the carrier concentration. Therefore, in this specification and the like, the carrier concentration which is assumed to be a state where no electric field is applied may be used as the parameter of the metal oxide, instead of the donor concentration. That is, the “carrier concentration” described in this specification and the like can be called the “donor concentration” in some cases.
  • the hydrogen concentration obtained by secondary ion mass spectroscopy is less than 1 ⁇ 10 20 atoms / cm 3 , preferably 1 ⁇ 10 19 atoms / cm 3. It is less than 3 , more preferably less than 5 ⁇ 10 18 atoms / cm 3 , and even more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • the carrier concentration of the metal oxide in the channel formation region is preferably 1 ⁇ 10 18 cm ⁇ 3 or less, more preferably less than 1 ⁇ 10 17 cm ⁇ 3, and less than 1 ⁇ 10 16 cm ⁇ 3 . It is more preferable that it is less than 1 ⁇ 10 13 cm ⁇ 3 , and it is further preferable that it is less than 1 ⁇ 10 12 cm ⁇ 3 .
  • the lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but can be set to, for example, 1 ⁇ 10 ⁇ 9 cm ⁇ 3 .
  • the semiconductor layer 108 preferably has a non-single crystal structure.
  • the non-single-crystal structure includes, for example, a CAAC structure, a polycrystalline structure, a microcrystalline structure, or an amorphous structure described later.
  • the amorphous structure has the highest defect level density
  • the CAAC structure has the lowest defect level density.
  • CAAC c-axis aligned aligned crystal
  • the CAAC structure is one of crystal structures such as a thin film including a plurality of nanocrystals (a crystal region whose maximum diameter is less than 10 nm), in which each nanocrystal has a c-axis oriented in a specific direction and an a-axis.
  • the b-axis and the b-axis have a crystal structure having no orientation, and the nanocrystals are continuously connected to each other without forming grain boundaries.
  • a thin film having a CAAC structure is characterized in that the c-axis of each nanocrystal is likely to be oriented in the thickness direction of the thin film, the normal direction of the formation surface, or the normal direction of the thin film surface.
  • CAAC-OS Oxide Semiconductor
  • CAAC-OS is an oxide semiconductor with high crystallinity.
  • the CAAC-OS a clear crystal grain boundary cannot be confirmed, so that it can be said that a decrease in electron mobility due to the crystal grain boundary is unlikely to occur.
  • the crystallinity of an oxide semiconductor might be lowered due to the inclusion of impurities, the generation of defects, or the like; therefore, it can be said that the CAAC-OS is an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the oxide semiconductor including the CAAC-OS has stable physical properties. Therefore, the oxide semiconductor including the CAAC-OS is highly heat resistant and highly reliable.
  • crystallography it is common to take a unit cell having a specific axis as the c-axis among the three axes (crystal axes) of the a-axis, the b-axis, and the c-axis that form the unit cell. ..
  • the two axes parallel to the plane direction of the layer are the a-axis and the b-axis, and the axis intersecting the layer is the c-axis.
  • a crystal having such a layered structure there is graphite classified into a hexagonal system, and the a-axis and the b-axis of its unit cell are parallel to the cleavage plane, and the c-axis is orthogonal to the cleavage plane.
  • InGaZnO 4 crystals having a YbFe 2 O 4 type crystal structure which is a layered structure, can be classified into a hexagonal system, and the a-axis and the b-axis of the unit cell are parallel to the plane direction of the layer and the c-axis.
  • Are orthogonal to the layers ie the a-axis and the b-axis).
  • an oxide semiconductor film having a microcrystalline structure crystal parts may not be clearly confirmed.
  • the crystal part included in the microcrystalline oxide semiconductor film is often 1 nm to 100 nm inclusive, or 1 nm to 10 nm inclusive.
  • an oxide semiconductor film having nanocrystals nc: nanocrystals
  • an oxide semiconductor film having nanocrystals nc: nanocrystals
  • the crystal grain boundary may not be clearly confirmed in an observation image by TEM.
  • the nc-OS film has a periodic atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less).
  • a minute region for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less.
  • the nc-OS film may be indistinguishable from the amorphous oxide semiconductor film depending on the analysis method. For example, when structural analysis is performed on an nc-OS film using an XRD apparatus that uses X-rays having a diameter larger than that of a crystal part, a peak indicating a crystal plane is not detected in the analysis by the out-of-plane method.
  • a diffraction pattern such as a halo pattern is obtained. Is observed.
  • the nc-OS film is subjected to electron beam diffraction (also referred to as nanobeam electron beam diffraction) using an electron beam having a probe diameter close to or smaller than that of the crystal portion (eg, 1 nm to 30 nm). In some cases, a high-luminance region is observed in a circular shape (in a ring shape), and a plurality of spots are observed in the ring-shaped region.
  • the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film.
  • the nc-OS film there is no regularity in crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect states than the CAAC-OS film. Therefore, the nc-OS film may have higher carrier density and higher electron mobility than the CAAC-OS film. Therefore, a transistor including the nc-OS film may have high field-effect mobility.
  • the nc-OS film can be formed by reducing the oxygen flow rate ratio during film formation as compared with the CAAC-OS film. Further, the nc-OS film can be formed by lowering the substrate temperature at the time of film formation as compared with the CAAC-OS film. For example, the nc-OS film can be formed even when the substrate temperature is relatively low (e.g., 130 ° C. or lower) or when the substrate is not heated; therefore, a large glass substrate, a resin substrate, or the like is used. Suitable for use with, and can increase productivity.
  • the substrate temperature is relatively low (e.g., 130 ° C. or lower) or when the substrate is not heated; therefore, a large glass substrate, a resin substrate, or the like is used. Suitable for use with, and can increase productivity.
  • a metal oxide formed at a substrate temperature of room temperature (RT) tends to have an nc crystal structure.
  • the room temperature (RT) referred to here includes the temperature when the substrate is not heated.
  • CAAC c-axis aligned crystal
  • CAC Cloud-Aligned Composite
  • CAC-OS or CAC-metal oxide has a conductive function in a part of the material and an insulating function in a part of the material, and the whole material has a function as a semiconductor.
  • the conductive function is a function of flowing electrons (or holes) serving as carriers
  • the insulating function is the function of electrons serving as carriers. It is a function that does not flow.
  • CAC-OS or CAC-metal oxide has a conductive area and an insulating area.
  • the conductive region has the above-mentioned conductive function
  • the insulating region has the above-mentioned insulating function.
  • the conductive region and the insulating region may be separated at the nanoparticle level.
  • the conductive region and the insulating region may be unevenly distributed in the material.
  • the conductive region may be observed as a cloudy connection at the periphery and connected in a cloud shape.
  • the conductive region and the insulating region may be dispersed in the material in a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less. ..
  • CAC-OS or CAC-metal oxide is composed of components having different band gaps.
  • CAC-OS or CAC-metal oxide is composed of a component having a wide gap due to the insulating region and a component having a narrow gap due to the conductive region.
  • a carrier when flowing a carrier, a carrier mainly flows in the component which has a narrow gap.
  • the component having the narrow gap acts complementarily to the component having the wide gap, and the carrier also flows to the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or CAC-metal oxide is used in the channel formation region of the transistor, a high current driving force, that is, a high on-current and a high field-effect mobility can be obtained in the on state of the transistor.
  • CAC-OS or CAC-metal oxide can also be referred to as a matrix composite material or a metal matrix composite material.
  • FIG. 12A shows a top view of the display device 700.
  • the display device 700 includes a first substrate 701 and a second substrate 705 which are attached to each other with a sealant 712.
  • a pixel portion 702, a source driver circuit portion 704, and a gate driver circuit portion 706 are provided over the first substrate 701 in a region sealed with the first substrate 701, the second substrate 705, and the sealant 712. Be done.
  • the pixel portion 702 is provided with a plurality of display elements.
  • An FPC terminal portion 708 to which an FPC 716 (FPC: Flexible printed circuit) is connected is provided in a portion of the first substrate 701 that does not overlap with the second substrate 705.
  • the FPC 716 supplies various signals and the like to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 through the FPC terminal portion 708 and the signal line 710.
  • a plurality of gate driver circuit units 706 may be provided. Further, the gate driver circuit unit 706 and the source driver circuit unit 704 may be in the form of IC chips separately formed and packaged on a semiconductor substrate or the like. The IC chip can be mounted on the first substrate 701 or the FPC 716.
  • a transistor which is a semiconductor device of one embodiment of the present invention can be applied to the transistors included in the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706.
  • a liquid crystal element, a light emitting element, or the like can be given.
  • a transmissive liquid crystal element, a reflective liquid crystal element, a semi-transmissive liquid crystal element, or the like can be used.
  • the light emitting element include self-luminous light emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), QLEDs (Quantum-dot LEDs), and semiconductor lasers.
  • a shutter type or optical interference type MEMS (Micro Electro Mechanical Systems) element a display element to which a microcapsule method, an electrophoresis method, an electrowetting method, or an electronic powder fluid (registered trademark) method is applied is used. You can also
  • a display device 700A shown in FIG. 12B is an example of a display device to which a resin layer 743 having flexibility is applied instead of the first substrate 701 and which can be used as a flexible display.
  • the pixel portion 702 does not have a rectangular shape, but the corner portion has an arc shape. Further, as shown in a region P1 in FIG. 12B, the pixel portion 702 and the resin layer 743 have a cutout portion in which a part is cut out.
  • the pair of gate driver circuit portions 706 are provided on both sides with the pixel portion 702 interposed therebetween. The gate driver circuit portion 706 is provided along the arcuate contour at the corner of the pixel portion 702.
  • the resin layer 743 has a shape in which a portion where the FPC terminal portion 708 is provided protrudes. Further, a part of the resin layer 743 including the FPC terminal portion 708 can be folded back to the back side in the region P2 in FIG. 12B. By folding a part of the resin layer 743, the display device 700A can be mounted in an electronic device in a state where the FPC 716 is overlapped and arranged on the back side of the pixel portion 702, and space saving of the electronic device can be achieved. ..
  • An IC 717 is mounted on the FPC 716 connected to the display device 700A.
  • the IC 717 has a function as a source driver circuit, for example.
  • the source driver circuit portion 704 in the display device 700A can be configured to include at least one of a protection circuit, a buffer circuit, a demultiplexer circuit, and the like.
  • the display device 700B shown in FIG. 12C is a display device that can be suitably used for an electronic device having a large screen.
  • it can be suitably used for a television device, a monitor device, a personal computer (including a notebook type or a desktop type), a tablet terminal, a digital signage, and the like.
  • the display device 700B has a plurality of source driver ICs 721 and a pair of gate driver circuit units 722.
  • a plurality of source driver ICs 721 are attached to the FPC 723, respectively.
  • one terminal of each of the plurality of FPCs 723 is connected to the first board 701 and the other terminal is connected to the printed board 724.
  • the printed board 724 can be arranged on the back side of the pixel portion 702 and mounted on an electronic device, so that space saving of the electronic device can be achieved.
  • the gate driver circuit portion 722 is formed on the first substrate 701. Thereby, an electronic device with a narrow frame can be realized.
  • a display device having a screen size of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more can be realized. Further, it is possible to realize a display device having an extremely high resolution such as 4K2K or 8K4K.
  • FIGS. 13 to 15 are cross-sectional views taken along the alternate long and short dash line QR shown in FIG. 12A.
  • 16 is a cross-sectional view taken along alternate long and short dash line ST in the display device 700A shown in FIG. 12B.
  • 13 and 14 show a configuration using a liquid crystal element as a display element
  • FIGS. 15 and 16 show a configuration using an EL element.
  • the display device illustrated in FIGS. 13 to 16 includes a lead wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708.
  • the lead wiring portion 711 has a signal line 710.
  • the pixel portion 702 includes a transistor 750 and a capacitor 790.
  • the source driver circuit portion 704 includes a transistor 752.
  • FIG. 14 shows a case where the capacitor 790 is not provided.
  • the transistors illustrated in Embodiment 1 can be applied to the transistors 750 and 752.
  • the transistor used in this embodiment has a highly purified oxide semiconductor film in which formation of oxygen vacancies is suppressed.
  • the transistor can have low off-state current. Therefore, the holding time of the electric signal such as the image signal can be lengthened, and the writing interval of the image signal can be set longer. Therefore, the frequency of refresh operations can be reduced, which leads to an effect of reducing power consumption.
  • the transistor used in this embodiment has a relatively high field-effect mobility, it can be driven at high speed.
  • a switching transistor in a pixel portion and a driver transistor used in a driver circuit portion can be formed over the same substrate. That is, a configuration in which a drive circuit formed of a silicon wafer or the like is not applied is also possible, and the number of parts of the display device can be reduced.
  • a transistor which can be driven at high speed by using a transistor which can be driven at high speed, a high-quality image can be provided.
  • the capacitor 790 illustrated in FIGS. 13, 15, and 16 includes a lower electrode formed by processing the same film as the first gate electrode included in the transistor 750 and a metal oxide that is the same as the semiconductor layer. And an upper electrode formed by.
  • the upper electrode has a low resistance like the source region and the drain region of the transistor 750.
  • a part of an insulating film functioning as a first gate insulating layer of the transistor 750 is provided between the lower electrode and the upper electrode. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric film is sandwiched between a pair of electrodes. Further, a wiring obtained by processing the same film as the source electrode and the drain electrode of the transistor is connected to the upper electrode.
  • a planarization insulating film 770 is provided over the transistor 750, the transistor 752, and the capacitor 790.
  • a transistor having a different structure from the transistor 750 included in the pixel portion 702 and the transistor 752 included in the source driver circuit portion 704 may be used.
  • a top-gate transistor may be applied to either one and a bottom-gate transistor may be applied to the other.
  • the signal line 710 is formed of the same conductive film as the source and drain electrodes of the transistor 750 and the transistor 752. At this time, it is preferable to use a low-resistance material such as a material containing a copper element because a signal delay or the like due to wiring resistance is small and a large screen can be displayed.
  • the FPC terminal portion 708 has a wiring 760, a part of which functions as a connection electrode, an anisotropic conductive film 780, and an FPC 716.
  • the wiring 760 is electrically connected to a terminal included in the FPC 716 through the anisotropic conductive film 780.
  • the wiring 760 is formed using the same conductive film as the source electrode, the drain electrode, and the like of the transistor 750 and the transistor 752.
  • a flexible substrate such as a glass substrate or a plastic substrate can be used.
  • an insulating layer having a barrier property against water or hydrogen is preferably provided between the first substrate 701 and the transistor 750 or the like.
  • a light-shielding film 738, a coloring film 736, and an insulating film 734 in contact with these are provided on the second substrate 705 side.
  • the display device 700 illustrated in FIG. 13 includes a liquid crystal element 775 and a spacer 778.
  • the liquid crystal element 775 includes a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 therebetween.
  • the conductive layer 774 is provided on the second substrate 705 side and has a function as a common electrode.
  • the conductive layer 772 is electrically connected to a source electrode or a drain electrode included in the transistor 750.
  • the conductive layer 772 is formed over the planarization insulating film 770 and functions as a pixel electrode.
  • a material having a property of transmitting visible light or a material having a property of reflecting light can be used.
  • the light-transmitting material for example, an oxide material containing indium, zinc, tin, or the like may be used.
  • the material having reflectivity for example, a material containing aluminum, silver, or the like may be used.
  • the display device 700 becomes a reflective liquid crystal display device.
  • a transmissive liquid crystal display device is obtained.
  • a polarizing plate is provided on the viewing side.
  • a pair of polarizing plates are provided so as to sandwich the liquid crystal element.
  • the display device 700 shown in FIG. 14 shows an example in which a horizontal electric field mode (for example, FFS mode) liquid crystal element 775 is used.
  • a conductive layer 774 serving as a common electrode is provided over the conductive layer 772 with an insulating layer 773 provided therebetween.
  • the alignment state of the liquid crystal layer 776 can be controlled by an electric field generated between the conductive layers 772 and 774.
  • a storage capacitor can be formed by a laminated structure of a conductive layer 774, an insulating layer 773, and a conductive layer 772. Therefore, it is not necessary to separately provide a capacitive element, and the aperture ratio can be increased.
  • an alignment film in contact with the liquid crystal layer 776 may be provided.
  • a polarizing member, a retardation member, an optical member (optical substrate) such as an antireflection member, and a light source such as a backlight and a sidelight can be appropriately provided.
  • the liquid crystal layer 776 includes thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC: Polymer Dispersed Liquid Crystal), polymer network liquid crystal (PNLC: Polymer Network Liquid Crystal), and ferroelectric liquid crystal.
  • PDLC Polymer Dispersed Liquid Crystal
  • PNLC Polymer Network Liquid Crystal
  • ferroelectric liquid crystal An antiferroelectric liquid crystal or the like can be used.
  • liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used.
  • the modes of the liquid crystal element are a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, and an ASM (Axially Symmetrical) mode. It is possible to use OCB (optically compensated birefringence) mode, ECB (electrically controlled birefringence) mode, guest host mode, and the like.
  • a liquid crystal layer 776 may be a scattering type liquid crystal using a polymer dispersion type liquid crystal or a polymer network type liquid crystal. At this time, a monochrome display may be performed without providing the coloring film 736, or a color display may be performed using the coloring film 736.
  • a time-division display method (also referred to as a field sequential driving method) in which color display is performed based on the successive additive color mixing method may be applied.
  • the coloring film 736 can be omitted.
  • the time-division display method it is not necessary to provide sub-pixels that exhibit R (red), G (green), and B (blue), so that it is possible to improve the aperture ratio of pixels and There are advantages such as being able to increase the degree.
  • the display device 700 illustrated in FIG. 15 includes a light emitting element 782.
  • the light emitting element 782 includes a conductive layer 772, an EL layer 786, and a conductive film 788.
  • the EL layer 786 includes a light emitting material such as an organic compound or an inorganic compound.
  • a fluorescent material a fluorescent material, a phosphorescent material, a thermally activated delayed fluorescence (TADF) material, an inorganic compound (quantum dot material, etc.), or the like can be used.
  • TADF thermally activated delayed fluorescence
  • an insulating film 730 which covers a part of the conductive layer 772 is provided over the planarization insulating film 770.
  • the light emitting element 782 is a top emission type light emitting element having a light-transmitting conductive film 788.
  • the light-emitting element 782 may have a bottom emission structure in which light is emitted to the conductive layer 772 side or a dual emission structure in which light is emitted to both the conductive layer 772 side and the conductive film 788 side.
  • the colored film 736 is provided at a position overlapping the light emitting element 782.
  • the light-blocking film 738 is provided in a position overlapping with the insulating film 730, the lead wiring portion 711, and the source driver circuit portion 704. Further, the coloring film 736 and the light shielding film 738 are covered with the insulating film 734. A space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that when the EL layer 786 is formed in an island shape for each pixel or in a stripe shape for each pixel column, that is, when the EL layer 786 is formed by coating separately, the coloring film 736 may not be provided.
  • FIG. 16 shows the configuration of a display device that can be suitably applied to a flexible display.
  • FIG. 16 is a cross-sectional view taken along alternate long and short dash line ST in the display device 700A shown in FIG. 12B.
  • a display device 700A shown in FIG. 16 has a structure in which a support substrate 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744 are laminated in place of the first substrate 701 shown in FIG.
  • the transistor 750, the capacitor 790, and the like are provided over the insulating layer 744 provided over the resin layer 743.
  • the support substrate 745 is a thin substrate that includes organic resin, glass, etc. and is flexible enough.
  • the resin layer 743 is a layer containing an organic resin such as polyimide or acrylic.
  • the insulating layer 744 includes an inorganic insulating film such as silicon oxide, silicon oxynitride, or silicon nitride.
  • the resin layer 743 and the supporting substrate 745 are attached to each other with an adhesive layer 742.
  • the resin layer 743 is preferably thinner than the supporting substrate 745.
  • the display device 700A shown in FIG. 16 has a protective layer 740 instead of the second substrate 705 shown in FIG.
  • the protective layer 740 is attached to the sealing film 732.
  • a glass substrate, a resin film, or the like can be used as the protective layer 740.
  • an optical member such as a polarizing plate or a scattering plate, an input device such as a touch sensor panel, or a structure in which two or more of these are stacked may be applied.
  • the EL layer 786 included in the light emitting element 782 is provided in an island shape over the insulating film 730 and the conductive layer 772. By forming the EL layer 786 so that emission colors are different for each subpixel, color display can be realized without using the coloring film 736. Further, a protective layer 741 is provided so as to cover the light emitting element 782.
  • the protective layer 741 has a function of preventing impurities such as water from diffusing into the light emitting element 782.
  • FIG. 16 shows a bendable area P2.
  • the region P2 in addition to the supporting substrate 745 and the adhesive layer 742, there is a portion where an inorganic insulating film such as the insulating layer 744 is not provided. Further, in the region P2, the resin layer 746 is provided so as to cover the wiring 760.
  • the inorganic insulating film By preventing the inorganic insulating film from being provided in the bendable region P2 as much as possible and by stacking only a conductive layer containing a metal or an alloy and a layer containing an organic material, it is possible to prevent a crack from being generated when bending. be able to.
  • the support substrate 745 since the support substrate 745 is not provided in the region P2, part of the display device 700A can be bent with an extremely small radius of curvature.
  • An input device may be provided in the display device 700 or the display device 700A shown in FIGS. 13 to 16.
  • Examples of the input device include a touch sensor and the like.
  • a sensor method various methods such as a capacitance method, a resistance film method, a surface acoustic wave method, an infrared method, an optical method, and a pressure sensitive method can be used. Alternatively, these two or more may be used in combination.
  • the touch panel has a structure in which an input device is formed between a pair of substrates, a so-called in-cell touch panel, an input device is formed over the display device 700, a so-called on-cell touch panel, or an input device is provided in the display device 700.
  • a so-called out-cell type touch panel that is used by pasting.
  • the display device illustrated in FIG. 17A includes a pixel portion 502, a driver circuit portion 504, a protection circuit 506, and a terminal portion 507. Note that the protection circuit 506 may not be provided.
  • the transistor of one embodiment of the present invention can be applied to the transistors included in the pixel portion 502 and the driver circuit portion 504.
  • the transistor of one embodiment of the present invention may also be applied to the protection circuit 506.
  • the pixel portion 502 has a plurality of pixel circuits 501 that drive a plurality of display elements arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more).
  • the driver circuit portion 504 includes driver circuits such as a gate driver 504a that outputs a scan signal to the gate lines GL_1 to GL_X and a source driver 504b that supplies a data signal to the data lines DL_1 to DL_Y.
  • the gate driver 504a may have at least a shift register.
  • the source driver 504b is configured using, for example, a plurality of analog switches and the like. Alternatively, the source driver 504b may be formed using a shift register or the like.
  • the terminal portion 507 is a portion provided with a terminal for inputting a power supply, a control signal, an image signal, and the like to a display device from an external circuit.
  • the protection circuit 506 is a circuit which, when a potential outside a certain range is applied to the wiring to which it is connected, makes the wiring and another wiring electrically conductive.
  • the protection circuit 506 illustrated in FIG. 17A is applied to various wirings such as a gate line GL which is a wiring between the gate driver 504a and the pixel circuit 501 or a data line DL which is a wiring between the source driver 504b and the pixel circuit 501, for example. Connected.
  • the gate driver 504a and the source driver 504b may each be provided on the same substrate as the pixel portion 502, or may be a substrate on which a gate driver circuit or a source driver circuit is separately formed (for example, a single crystal semiconductor film or a polycrystalline semiconductor).
  • a drive circuit board formed of a film) may be mounted on the board on which the pixel portion 502 is provided by COG or TAB (Tape Automated Bonding).
  • the plurality of pixel circuits 501 shown in FIG. 17A can have the configuration shown in FIG. 17B or 17C, for example.
  • the pixel circuit 501 illustrated in FIG. 17B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. Further, the data line DL_n, the gate line GL_m, the potential supply line VL, and the like are connected to the pixel circuit 501.
  • the potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501.
  • the alignment state of the liquid crystal element 570 is set according to the written data. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Further, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 in each row.
  • the pixel circuit 501 illustrated in FIG. 17C includes a transistor 552, a transistor 554, a capacitor 562, and a light emitting element 572. Further, the data line DL_n, the gate line GL_m, the potential supply line VL_a, the potential supply line VL_b, and the like are connected to the pixel circuit 501.
  • the high power supply potential VDD is applied to one of the potential supply line VL_a and the potential supply line VL_b, and the low power supply potential VSS is applied to the other.
  • the luminance of light emitted from the light emitting element 572 is controlled by controlling the current flowing through the light emitting element 572 according to the potential applied to the gate of the transistor 554.
  • Embodiment 4 a pixel circuit including a memory for correcting the gradation displayed in the pixel and a display device including the pixel circuit will be described.
  • the transistors illustrated in Embodiment 1 can be applied to the transistors used in the pixel circuits illustrated below.
  • FIG. 18A shows a circuit diagram of the pixel circuit 400.
  • the pixel circuit 400 includes a transistor M1, a transistor M2, a capacitor C1, and a circuit 401.
  • the wiring S1, the wiring S2, the wiring G1, and the wiring G2 are connected to the pixel circuit 400.
  • the gate is connected to the wiring G1, one of the source and the drain is connected to the wiring S1, and the other is connected to one electrode of the capacitor C1.
  • the transistor M2 has a gate connected to the wiring G2, one of a source and a drain connected to the wiring S2, and the other connected to the other electrode of the capacitor C1 and the circuit 401, respectively.
  • the circuit 401 is a circuit including at least one display element. Although various elements can be used as the display element, typically, a light emitting element such as an organic EL element or an LED element, a liquid crystal element, or a MEMS (Micro Electro Mechanical Systems) element can be applied.
  • a light emitting element such as an organic EL element or an LED element
  • a liquid crystal element such as an organic EL element or an LED element
  • MEMS Micro Electro Mechanical Systems
  • a node connecting the transistor M1 and the capacitor C1 is a node N1
  • a node connecting the transistor M2 and the circuit 401 is a node N2.
  • the pixel circuit 400 can hold the potential of the node N1 by turning off the transistor M1. Further, the potential of the node N2 can be held by turning off the transistor M2. In addition, by writing a predetermined potential to the node N1 via the transistor M1 with the transistor M2 in the off state, the potential of the node N2 changes in accordance with the displacement of the potential of the node N1 due to capacitive coupling via the capacitor C1. Can be changed.
  • the transistor to which an oxide semiconductor is applied which is illustrated in Embodiment 1, can be applied to one or both of the transistor M1 and the transistor M2. Therefore, the potential of the node N1 or the node N2 can be held for a long time with an extremely low off-state current. Note that in the case where the period for holding the potential of each node is short (specifically, when the frame frequency is 30 Hz or higher), a transistor to which a semiconductor such as silicon is applied may be used.
  • FIG. 18B is a timing chart regarding the operation of the pixel circuit 400.
  • influences of various resistances such as wiring resistance, parasitic capacitances of transistors and wirings, and threshold voltage of transistors are not taken into consideration.
  • one frame period is divided into a period T1 and a period T2.
  • the period T1 is a period for writing a potential to the node N2
  • the period T2 is a period for writing a potential to the node N1.
  • Period T1 a potential for turning on the transistor is applied to both the wiring G1 and the wiring G2. Further, the potential V ref which is a fixed potential is supplied to the wiring S1, and the first data potential V w is supplied to the wiring S2.
  • the potential V ref is applied to the node N1 from the wiring S1 through the transistor M1. Further, the node N2 is supplied with the first data potential V w via the transistor M2. Therefore, a state where the potential difference V w -V ref is held in the capacitor C1.
  • Period T2 a potential for turning on the transistor M1 is applied to the wiring G1 and a potential for turning off the transistor M2 is applied to the wiring G2.
  • the second data potential V data is supplied to the wiring S1.
  • a predetermined constant potential may be applied to the wiring S2 or the wiring S2 may be in a floating state.
  • the second data potential V data is applied to the node N1 through the transistor M1.
  • the potential of the node N2 changes by the potential dV according to the second data potential V data due to the capacitive coupling by the capacitance C1. That is, a potential obtained by adding the first data potential Vw and the potential dV is input to the circuit 401.
  • the potential dV is shown as a positive value in FIG. 18B, it may be a negative value. That is, the second data potential V data may be lower than the potential V ref .
  • the potential dV is generally determined by the capacitance value of the capacitance C1 and the capacitance value of the circuit 401.
  • the potential dV becomes a potential close to the second data potential V data .
  • the pixel circuit 400 can generate a potential to be supplied to the circuit 401 including a display element by combining two types of data signals, so that gradation correction can be performed in the pixel circuit 400. Become.
  • the pixel circuit 400 can also generate a potential exceeding the maximum potential that can be supplied by the source driver connected to the wiring S1 and the wiring S2. For example, when a light emitting element is used, high dynamic range (HDR) display or the like can be performed. Moreover, when a liquid crystal element is used, overdrive drive or the like can be realized.
  • HDR high dynamic range
  • the pixel circuit 400LC illustrated in FIG. 18C includes a circuit 401LC.
  • the circuit 401LC includes a liquid crystal element LC and a capacitor C2.
  • one electrode is connected to one electrode of the node N2 and the capacitor C2, and the other electrode is connected to a wiring to which the potential Vcom2 is applied.
  • the other electrode of the capacitor C2 is connected to a wiring to which the potential Vcom1 is applied.
  • the capacity C2 functions as a storage capacity.
  • the capacitor C2 can be omitted if unnecessary.
  • the pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, it is possible to realize a high-speed display by overdriving and apply a liquid crystal material having a high driving voltage, for example. Further, by supplying a correction signal to the wiring S1 or the wiring S2, the gradation can be corrected in accordance with the operating temperature, the deterioration state of the liquid crystal element LC, or the like.
  • the pixel circuit 400EL illustrated in FIG. 18D includes a circuit 401EL.
  • the circuit 401EL includes a light emitting element EL, a transistor M3, and a capacitor C2.
  • the gate is connected to one electrode of the node N2 and the capacitor C2, one of the source and the drain is connected to the wiring to which the potential V H is applied, and the other is connected to one electrode of the light emitting element EL.
  • the other electrode of the capacitor C2 is connected to the wiring to which the potential Vcom is applied.
  • the other electrode of the light-emitting element EL is connected to a wiring to which the potential V L is applied.
  • the transistor M3 has a function of controlling the current supplied to the light emitting element EL.
  • the capacitor C2 functions as a storage capacitor. The capacitor C2 can be omitted if unnecessary.
  • the transistor M3 may be connected to the cathode side. At that time, the values of the potential V H and the potential V L can be changed as appropriate.
  • the pixel circuit 400EL can flow a large amount of current through the light-emitting element EL, so that, for example, HDR display or the like can be realized. Further, by supplying a correction signal to the wiring S1 or the wiring S2, variation in electrical characteristics of the transistor M3 or the light emitting element EL can be corrected.
  • circuit is not limited to the circuits illustrated in FIGS. 18C and 18D, and may have a configuration in which a transistor or a capacitance is added separately.
  • the display module 6000 illustrated in FIG. 19A includes a display device 6006 to which an FPC 6005 is connected, a frame 6009, a printed board 6010, and a battery 6011 between an upper cover 6001 and a lower cover 6002.
  • a display device manufactured using one embodiment of the present invention can be used as the display device 6006.
  • the display device 6006 can realize a display module with extremely low power consumption.
  • the shape and dimensions of the upper cover 6001 and the lower cover 6002 can be appropriately changed according to the size of the display device 6006.
  • the display device 6006 may have a function as a touch panel.
  • the frame 6009 may have a function of protecting the display device 6006, a function of blocking electromagnetic waves generated by the operation of the printed circuit board 6010, a function of a heat sink, and the like.
  • the printed circuit board 6010 has a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal, a battery control circuit, and the like.
  • FIG. 19B is a schematic sectional view of a display module 6000 including an optical touch sensor.
  • the display module 6000 includes a light emitting unit 6015 and a light receiving unit 6016 provided on the printed board 6010.
  • a pair of light guide portions (a light guide portion 6017a and a light guide portion 6017b) are provided in a region surrounded by the upper cover 6001 and the lower cover 6002.
  • the display device 6006 is provided so as to overlap with the printed circuit board 6010 and the battery 6011 with the frame 6009 interposed therebetween.
  • the display device 6006 and the frame 6009 are fixed to the light guide portions 6017a and 6017b.
  • the light 6018 emitted from the light emitting unit 6015 passes through the upper portion of the display device 6006 by the light guiding unit 6017a and reaches the light receiving unit 6016 through the light guiding unit 6017b.
  • a touch operation can be detected by blocking the light 6018 by a detected object such as a finger or a stylus.
  • a plurality of light emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006.
  • a plurality of light receiving units 6016 are provided at positions facing the light emitting unit 6015. As a result, it is possible to obtain information on the position where the touch operation is performed.
  • the light emitting unit 6015 can use a light source such as an LED element, and it is particularly preferable to use a light source that emits infrared rays.
  • the light receiving unit 6016 can use a photoelectric element that receives the light emitted by the light emitting unit 6015 and converts the light into an electric signal.
  • a photodiode capable of receiving infrared rays can be used.
  • the light emitting portion 6015 and the light receiving portion 6016 can be arranged below the display device 6006, and external light reaches the light receiving portion 6016 and touch sensor Can be prevented from malfunctioning.
  • malfunction of the touch sensor can be suppressed more effectively.
  • the electronic device 6500 shown in FIG. 20A is a personal digital assistant that can be used as a smartphone.
  • the electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like.
  • the display portion 6502 has a touch panel function.
  • the display device of one embodiment of the present invention can be applied to the display portion 6502.
  • FIG. 20B is a schematic cross-sectional view including an end portion of the housing 6501 on the microphone 6506 side.
  • a protective member 6510 having a light-transmitting property is provided on a display surface side of the housing 6501, and a display panel 6511, an optical member 6512, a touch sensor panel 6513, a print are provided in a space surrounded by the housing 6501 and the protective member 6510.
  • a substrate 6517, a battery 6518, and the like are arranged.
  • a display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).
  • a part of the display panel 6511 is folded back in the area outside the display portion 6502. Further, the FPC 6515 is connected to the folded back portion. An IC 6516 is mounted on the FPC 6515. Further, the FPC 6515 is connected to a terminal provided on the printed board 6517.
  • the flexible display panel of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. Further, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted while suppressing the thickness of the electronic device. In addition, a part of the display panel 6511 is folded back and a connection portion with the FPC 6515 is provided on the back side of the pixel portion, whereby an electronic device with a narrow frame can be realized.
  • the electronic devices exemplified below are provided with a display device of one embodiment of the present invention in a display portion. Therefore, the electronic device achieves high resolution. Further, it is possible to provide an electronic device having both a high resolution and a large screen.
  • the display unit of the electronic device of one embodiment of the present invention can display an image having a resolution of, for example, full high-definition, 4K2K, 8K4K, 16K8K, or higher.
  • Examples of the electronic device include electronic devices having a relatively large screen such as a television device, a laptop personal computer, a monitor device, a digital signage, a pachinko machine, and a game machine, as well as a digital camera, a digital video camera, and a digital photo.
  • a relatively large screen such as a television device, a laptop personal computer, a monitor device, a digital signage, a pachinko machine, and a game machine, as well as a digital camera, a digital video camera, and a digital photo.
  • a frame, a mobile phone, a portable game machine, a portable information terminal, a sound reproducing device, and the like can be given.
  • the electronic device to which one embodiment of the present invention is applied can be incorporated along a flat surface or a curved surface of an inner wall or an outer wall of a house or a building, an interior or exterior of an automobile, or the like.
  • FIG. 21A is a diagram showing the appearance of the camera 8000 with the finder 8100 attached.
  • the camera 8000 has a housing 8001, a display portion 8002, operation buttons 8003, a shutter button 8004, and the like.
  • a detachable lens 8006 is attached to the camera 8000.
  • the camera 8000 may have a lens 8006 and a housing integrated with each other.
  • the camera 8000 can take an image by pressing a shutter button 8004 or touching a display portion 8002 which functions as a touch panel.
  • the housing 8001 has a mount having electrodes, and can be connected to a strobe device or the like in addition to the finder 8100.
  • the finder 8100 has a housing 8101, a display portion 8102, buttons 8103, and the like.
  • the housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000.
  • the finder 8100 can display an image or the like received from the camera 8000 on the display portion 8102.
  • the button 8103 has a function as a power button or the like.
  • the display device of one embodiment of the present invention can be applied to the display portion 8002 of the camera 8000 and the display portion 8102 of the finder 8100.
  • the camera 8000 with a built-in viewfinder may be used.
  • FIG. 21B is a diagram showing an appearance of the head mounted display 8200.
  • the head mounted display 8200 has a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205 and the like.
  • a battery 8206 is built in the mounting portion 8201.
  • the cable 8205 supplies electric power from the battery 8206 to the main body 8203.
  • the main body 8203 includes a wireless receiver and the like, and can display received video information on the display portion 8204.
  • the main body 8203 is provided with a camera, and information about movements of a user's eyeballs and eyelids can be used as input means.
  • the mounting portion 8201 may be provided with a plurality of electrodes capable of detecting a current flowing with the movement of the eyeball of the user at a position where the user touches it, and may have a function of recognizing the line of sight. Further, it may have a function of monitoring the pulse of the user by the current flowing through the electrode.
  • the mounting portion 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and has a function of displaying biological information of the user on the display portion 8204 and movement of the head of the user. It may have a function of changing the image displayed on the display portion 8204 in accordance with the above.
  • the display device of one embodiment of the present invention can be applied to the display portion 8204.
  • the head mounted display 8300 includes a housing 8301, a display portion 8302, a band-shaped fixture 8304, and a pair of lenses 8305.
  • the user can view the display on the display portion 8302 through the lens 8305.
  • the display portion 8302 it is preferable to arrange the display portion 8302 so as to be curved because the user can feel a high sense of reality. Further, another image displayed in a different region of the display portion 8302 can be viewed through the lens 8305 so that three-dimensional display using parallax can be performed.
  • the structure is not limited to one display portion 8302 provided, and two display portions 8302 may be provided and one display portion may be arranged for one eye of the user.
  • the display device of one embodiment of the present invention can be applied to the display portion 8302. Since the display device including the semiconductor device of one embodiment of the present invention has extremely high definition, even if the display device is enlarged using the lens 8305 as illustrated in FIG. It is possible to display high-quality images.
  • the electronic devices illustrated in FIGS. 22A to 22G include a housing 9000, a display portion 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (force, displacement, position, speed). , Acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared (Including a function to perform), a microphone 9008, and the like.
  • the electronic devices shown in FIGS. 22A to 22G have various functions. For example, a function of displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, a function of controlling processing by various software (programs), It can have a wireless communication function, a function of reading and processing a program or data recorded in a recording medium, and the like. Note that the functions of the electronic device are not limited to these and can have various functions.
  • the electronic device may have a plurality of display units.
  • the electronic device is provided with a camera or the like and has a function of shooting a still image or a moving image and storing it in a recording medium (external or built in the camera), a function of displaying the taken image on the display unit Good.
  • FIGS. 22A to 22G The details of the electronic devices shown in FIGS. 22A to 22G will be described below.
  • FIG. 22A is a perspective view showing the television device 9100.
  • the television device 9100 can incorporate a large screen, for example, a display portion 9001 having a size of 50 inches or more, or 100 inches or more.
  • FIG. 22B is a perspective view showing the mobile information terminal 9101.
  • the mobile information terminal 9101 can be used as, for example, a smartphone.
  • the portable information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like.
  • the mobile information terminal 9101 can display characters and image information on its plurality of surfaces.
  • FIG. 22B shows an example in which three icons 9050 are displayed.
  • the information 9051 indicated by a dashed rectangle can be displayed on another surface of the display portion 9001. Examples of the information 9051 include notification of an incoming call such as email, SNS, and telephone, title of email, SNS, and the like, sender name, date and time, time, battery level, antenna reception strength, and the like.
  • the icon 9050 or the like may be displayed at the position where the information 9051 is displayed.
  • FIG. 22C is a perspective view showing the portable information terminal 9102.
  • the mobile information terminal 9102 has a function of displaying information on three or more surfaces of the display portion 9001.
  • the information 9052, the information 9053, and the information 9054 are displayed on different surfaces is shown.
  • the user can check the information 9053 displayed at a position where it can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in the chest pocket of clothes. The user can confirm the display without taking out the portable information terminal 9102 from the pocket, and can judge whether or not to receive a call, for example.
  • FIG. 22D is a perspective view showing a wristwatch type portable information terminal 9200.
  • the mobile information terminal 9200 can be used as, for example, a smart watch. Further, the display portion 9001 is provided with a curved display surface, and display can be performed along the curved display surface.
  • the mobile information terminal 9200 can also make a hands-free call by mutual communication with, for example, a headset capable of wireless communication. Further, the portable information terminal 9200 can also perform data transmission with another information terminal or charge by using the connection terminal 9006. Note that the charging operation may be performed by wireless power feeding.
  • FIGS. 22E, 21F, and 21G are perspective views showing a foldable portable information terminal 9201. Further, FIG. 22E is a state in which the mobile information terminal 9201 is expanded, FIG. 22G is a state in which the portable information terminal 9201 is folded, and FIG. 22F is a perspective view in the state of changing from one of FIGS. 22E and 22G to the other.
  • the portable information terminal 9201 is excellent in portability in a folded state and excellent in displayability due to a wide display area without a joint in an expanded state.
  • a display portion 9001 included in the portable information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. For example, the display portion 9001 can be bent with a radius of curvature of 1 mm or more and 150 mm or less.
  • FIG. 23A shows an example of a television device.
  • a display portion 7500 is incorporated in a housing 7101 of the television device 7100.
  • a structure is shown in which the housing 7101 is supported by a stand 7103.
  • the television device 7100 shown in FIG. 23A can be operated with an operation switch included in the housing 7101 or a separate remote controller 7111.
  • a touch panel may be applied to the display portion 7500 and the television device 7100 may be operated by touching the touch panel.
  • the remote controller 7111 may have a display portion in addition to the operation buttons.
  • the television device 7100 may include a television broadcast receiver and a communication device for network connection.
  • FIG. 23B shows a notebook personal computer 7200.
  • the laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like.
  • a display portion 7500 is incorporated in the housing 7211.
  • 23C and 23D show an example of digital signage (digital signage).
  • the digital signage 7300 illustrated in FIG. 23C includes a housing 7301, a display portion 7500, a speaker 7303, and the like. Further, an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like can be provided.
  • FIG. 23D is a digital signage 7400 attached to a column 7401.
  • the digital signage 7400 includes a display portion 7500 provided along the curved surface of the pillar 7401.
  • the wider the display unit 7500 the more information that can be provided at one time, and the more noticeable it is. Therefore, for example, the advertising effect of an advertisement is enhanced.
  • a touch panel to the display portion 7500 so that the user can operate it.
  • it can be used not only for advertising purposes but also for purposes such as providing route information, traffic information, guidance information for commercial facilities, and other information required by users.
  • the digital signage 7300 or the digital signage 7400 can be linked to the information terminal 7311 such as a smartphone owned by the user by wireless communication.
  • the display of the display unit 7500 can be switched by displaying the advertisement information displayed on the display unit 7500 on the screen of the information terminal device 7311 or operating the information terminal device 7311.
  • the digital signage 7300 or the digital signage 7400 can execute a game using the information terminal device 7311 as an operation means (controller). This allows an unspecified number of users to simultaneously participate in the game and enjoy it.
  • the display device of one embodiment of the present invention can be applied to the display portion 7500 in FIGS. 23A to 23D.
  • the electronic device of this embodiment has a display portion; however, one embodiment of the present invention can be applied to an electronic device without a display portion.
  • the etching rate of the material that can be used for the metal oxide layer 114 was evaluated.
  • samples (sample A1 to sample A4) having a metal oxide film formed on a glass substrate were used.
  • the substrate temperature during film formation was 100 ° C., and oxygen gas (oxygen flow rate ratio 100%) was used as the film formation gas.
  • oxygen gas oxygen flow rate ratio 100%
  • the power source of the sample A1 was 2.5 kW (AC) and the pressure was 0.3 Pa.
  • the power source of the sample A2 was 2.5 kW (AC) and the pressure was 0.6 Pa.
  • the power of the sample A3 was set to 4.5 kW (AC) and the pressure was set to 0.3 Pa.
  • the power of the sample A4 was set to 4.5 kW (AC) and the pressure was set to 0.6 Pa.
  • the etching rate was evaluated by the wet etching method.
  • As an etchant a mixed solution of oxalic acid (5% or less), an additive (concentration not disclosed), and water (95% or more) was used.
  • the etchant temperature during etching was 45 ° C.
  • the etching rate was calculated from the film thickness obtained by the optical interference type film thickness measurement.
  • the etching rate shown in this example means the etching rate in the film thickness direction of the metal oxide film.
  • Table 1 shows the etching rate (ER) of each sample. Table 1 also shows the deposition rate (DR) of the metal oxide film.
  • samples (sample B1 to sample B4) corresponding to the transistor 100 shown in FIG. 1 were prepared and the cross-sectional shape was evaluated.
  • an insulating layer having a thickness of 150 nm was formed over a glass substrate.
  • a first silicon oxynitride film having a thickness of about 5 nm, a second silicon oxynitride film having a thickness of about 140 nm, and a third silicon oxynitride film having a thickness of about 5 nm were respectively formed by a plasma CVD method. A film was formed.
  • the film formation of the first silicon oxynitride film was performed by setting the flow rates of the silane gas and the dinitrogen monoxide gas to be 24 sccm and 18000 sccm, the pressure was 200 Pa, the film formation power was 130 W, and the substrate temperature was 350 ° C.
  • the second silicon oxynitride film was formed by setting the flow rates of the silane gas and the dinitrogen monoxide gas at 200 sccm and 4000 sccm, the pressure at 300 Pa, the film formation power at 750 W, and the substrate temperature at 350 ° C.
  • the flow rates of silane gas and dinitrogen monoxide gas were 20 sccm and 3000 sccm, respectively, the pressure was 40 Pa, the film formation power was 500 W, and the substrate temperature was 350 ° C.
  • a metal oxide film having a thickness of about 20 nm was formed on the insulating layer by the sputtering method.
  • the substrate temperature during film formation was 100 ° C., and oxygen gas (oxygen flow rate ratio 100%) was used as the film formation gas.
  • four samples (sample B1 to sample B4) with different power supply power and pressure at the time of forming the metal oxide film were prepared.
  • the power source of the sample B1 was 2.5 kW (AC) and the pressure was 0.3 Pa.
  • the power source of the sample B2 was 2.5 kW (AC) and the pressure was 0.6 Pa.
  • the power source of the sample B3 was 4.5 kW (AC) and the pressure was 0.3 Pa.
  • the power of the sample B4 was set to 4.5 kW (AC) and the pressure was set to 0.6 Pa.
  • a conductive film was formed on the metal oxide film.
  • a molybdenum film having a thickness of about 100 nm was formed by a sputtering method.
  • the conductive film was etched using the resist pattern as a mask to obtain a conductive layer.
  • a dry etching method was used for etching, and SF 6 gas was used as an etching gas.
  • Example 1 the metal oxide film was etched to obtain a metal oxide layer.
  • a wet etching method was used for etching. Since the description of Example 1 can be referred to as the etchant, detailed description thereof will be omitted.
  • the etching treatment time was set to 75 seconds for each of sample B1 to sample B4.
  • sample B1 to sample B4 were thinned by a focused ion beam (FIB), and the cross section was observed by scanning transmission electron microscopy (STEM).
  • FIB focused ion beam
  • FIG. 24 shows STEM images of cross sections of sample B1 to sample B4.
  • FIG. 24 is a transmission electron image (TE image) with a magnification of 100,000 times, showing power supply power (Power) at the time of forming the metal oxide layer in the vertical direction, and forming the metal oxide layer in the horizontal direction. The pressure (Pressure) at the time is shown.
  • the glass substrate is Glass
  • the insulating layer is SiON
  • the metal oxide layer is IGZO
  • the conductive layer is Mo
  • the platinum coating used as an antistatic film for cross-section observation is Pt
  • the carbon coating used as a protective film Is described as C.
  • the width L2 which is the difference between the positions of the end of the conductive layer (Mo) and the end of the metal oxide layer (IGZO), is shown.
  • the edge of the metal oxide layer (IGZO) was located inside the edge of the conductive layer (Mo) in all the samples. Further, it was confirmed that the width L2 tends to become smaller when the power supply power at the time of forming the metal oxide film is increased. It was confirmed that the width L2 tended to decrease when the pressure during the formation of the metal oxide film was lowered. It was also confirmed that the etching rate of the metal oxide film shown in Example 1 and the width L2 have a substantially linear correlation.
  • the width L2 can be controlled by changing the film forming conditions of the metal oxide.
  • samples (sample C1 to sample C3) corresponding to the transistor 100A shown in FIG. 5 were manufactured, and electrical characteristics and cross-sectional shapes were evaluated.
  • the transistor 100A illustrated in Embodiment 1 can be used for the structure of the manufactured transistor.
  • a tungsten film having a thickness of about 100 nm was formed on a glass substrate by a sputtering method and processed to obtain a first gate electrode. Then, a first silicon nitride film having a thickness of approximately 240 nm, a second silicon nitride film having a thickness of approximately 60 nm, and a silicon oxynitride film having a thickness of approximately 3 nm are formed as a first gate insulating layer by a plasma CVD method. It was formed by stacking.
  • the first silicon nitride film was formed by setting the flow rates of silane gas, nitrogen gas, and ammonia gas at 290 sccm, 2000 sccm, and 2000 sccm, the pressure at 200 Pa, the film forming power at 3000 W, and the substrate temperature at 350 ° C.
  • the second silicon nitride film was formed by setting the flow rates of silane gas, nitrogen gas, and ammonia gas at 200 sccm, 2000 sccm, and 100 sccm, the pressure at 100 Pa, the film formation power at 2000 W, and the substrate temperature at 350 ° C.
  • the silicon oxynitride film was formed by setting the flow rates of silane gas and dinitrogen monoxide gas at 20 sccm and 3000 sccm, the pressure at 40 Pa, the film forming power at 3000 W, and the substrate temperature at 350 ° C.
  • a metal oxide film having a thickness of 40 nm was formed on the first gate insulating layer and processed to obtain a semiconductor layer.
  • the substrate temperature during film formation was 100 ° C.
  • a mixed gas of oxygen gas and argon gas was used as a film forming gas, and the oxygen flow rate ratio was set to 50%. Further, the power supply was 2.5 kW (AC) and the pressure was 0.6 Pa.
  • heat treatment was performed at 350 ° C. for 1 hour in a nitrogen gas atmosphere, and then heat treatment was performed at 350 ° C. for 1 hour in a mixed atmosphere of nitrogen gas and oxygen gas.
  • the film formation of the first silicon oxynitride film was performed by setting the flow rates of the silane gas and the dinitrogen monoxide gas to be 24 sccm and 18000 sccm, the pressure was 200 Pa, the film formation power was 130 W, and the substrate temperature was 350 ° C.
  • the second silicon oxynitride film was formed by setting the flow rates of the silane gas and the dinitrogen monoxide gas at 200 sccm and 4000 sccm, the pressure at 300 Pa, the film formation power at 750 W, and the substrate temperature at 350 ° C.
  • the flow rates of silane gas and dinitrogen monoxide gas were 20 sccm and 3000 sccm, respectively, the pressure was 40 Pa, the film formation power was 500 W, and the substrate temperature was 350 ° C.
  • a metal oxide film was formed on the second gate insulating layer by the sputtering method.
  • the substrate temperature during film formation was 100 ° C.
  • Oxygen gas oxygen flow rate ratio 100%
  • the power supply was 4.5 kW (AC) and the pressure was 0.3 Pa.
  • sample C1 to sample C3 having different thicknesses of the metal oxide film were prepared.
  • the sample C1 has a metal oxide film thickness of 20 nm. In sample C2, the thickness of the metal oxide film was 30 nm. Sample C3 has a metal oxide film thickness of 40 nm.
  • a molybdenum film having a thickness of about 100 nm was formed as a conductive film on the metal oxide film by a sputtering method.
  • the conductive film was etched using the resist pattern as a mask to obtain a conductive layer.
  • a dry etching method was used for etching, and SF 6 gas was used as an etching gas.
  • Example 1 the metal oxide film was etched to obtain a metal oxide layer.
  • a wet etching method was used for etching. Since the description of Example 1 can be referred to as the etchant, detailed description thereof will be omitted.
  • the etching treatment time was set to 75 seconds for each of sample C1 to sample C3.
  • boron was added as an impurity element using the conductive layer as a mask.
  • a plasma ion doping apparatus was used to add impurities.
  • B 2 H 6 gas was used as a gas for supplying boron.
  • a silicon oxynitride film having a thickness of about 300 nm was formed as a protective insulating layer covering the transistor by the plasma CVD method.
  • the film formation of the protective insulating layer was performed by setting the flow rates of silane gas and nitrogen gas at 290 sccm and 4000 sccm, the pressure at 133 Pa, the film forming power at 1000 W, and the substrate temperature at 350 ° C.
  • a part of the protective insulating layer and the second gate insulating layer was opened by etching, a molybdenum film was formed by a sputtering method, and this was processed to obtain a source electrode and a drain electrode. Then, an acrylic film having a thickness of about 1.5 ⁇ m was formed as a flattening layer, and heat treatment was performed under a nitrogen atmosphere at a temperature of 250 ° C. for 1 hour.
  • sample C1 to sample C3 each having a transistor formed on a glass substrate were obtained.
  • the voltage applied to the gate electrode (hereinafter, also referred to as the gate voltage (Vg)) was applied from -15V to + 20V in steps of 0.25V. Further, the voltage applied to the source electrode (hereinafter, also referred to as source voltage (Vs)) is 0 V (comm), and the voltage applied to the drain electrode (hereinafter, also referred to as drain voltage (Vd)) is 0.1 V and 10 V.
  • Vg gate voltage
  • the gate bias stress test As one of the indexes for evaluating the reliability of the transistor, the characteristics of the transistor are evaluated by holding the electric field applied to the gate.
  • a PBTS (Positive Bias Temperature) test and a negative gate bias test are performed in which a positive potential is applied to the gate with respect to the source potential and the drain potential.
  • a test in which a potential is maintained at a high temperature is called an NBTS (Negative Bias Temperature Stress) test.
  • the PBTS test and the NBTS test performed in the state of irradiating light such as white LED light are respectively PBTIS (Positive Bias Temperature Illumination Stress) test and NBTI (Negative Bias Temperature Illination) test.
  • a positive potential is applied to the gate when the transistor is turned on (a state in which current flows), so that the amount of fluctuation in threshold voltage in the PBTS test is large. Is one of the important items to be noted as an index of transistor reliability.
  • the PBTS test and the NBTIS test are shown.
  • the substrate on which the transistor was formed was kept at 60 ° C., 0 V was applied to the source and drain of the transistor, and 20 V or ⁇ 20 V was applied to the gate, and this state was kept for 1 hour.
  • about 10000 lx of white LED light was used for light irradiation in the NBTIS test.
  • FIG. 25 shows the Id-Vg characteristics of the transistor in sample C1 and the STEM image of the cross section.
  • FIG. 26 shows the Id-Vg characteristics of the transistor in sample C2 and the STEM image of the cross section.
  • FIG. 27 shows the Id-Vg characteristics of the transistor and the STEM image of the cross section in the sample C3. 25 to 27 show Id-Vg characteristics under the condition that the transistor channel lengths are different in the vertical direction, and show two types of transistors having channel lengths of 2 ⁇ m, 3 ⁇ m, and channel width of 50 ⁇ m.
  • the horizontal axis represents the gate voltage (Vg) and the vertical axis represents the drain current (Id).
  • FIGS. 25 to 27 cross-sectional STEM images are shown at the bottom of each of FIGS. 25 to 27.
  • the silicon nitride layer is described as SiN
  • the silicon oxynitride layer as SiON
  • the metal oxide layer as IGZO
  • the conductive layer as Mo.
  • the width L2 which is the difference between the positions of the end of the conductive layer (Mo) and the end of the metal oxide layer (IGZO), is shown.
  • the width L2 tends to become smaller as the metal oxide layer becomes thicker. That is, it was found that the width L2 can be controlled by changing the film thickness of the metal oxide.
  • FIG. 28 shows the variation amount ( ⁇ Vth) of the threshold voltage before and after the PBTS test and the NBTIS test in sample C1 to sample C3.
  • the horizontal axis represents the thickness of the metal oxide layer
  • the vertical axis represents the variation amount ( ⁇ Vth) of the threshold voltage.
  • the resistance of the metal oxide film was evaluated.
  • sample D For the evaluation, a sample (sample D) having a metal oxide film formed on a glass substrate was used. The cross-sectional structure of sample D is shown in FIG.
  • a 100-nm-thick metal oxide film 214 was formed over the glass substrate 200.
  • the substrate temperature during film formation was 100 ° C.
  • Oxygen gas oxygen flow rate ratio 100% was used as a film forming gas.
  • the power supply was 4.5 kW (AC) and the pressure was 0.3 Pa.
  • a conductive film 212 was formed on the metal oxide film 214.
  • a molybdenum film having a thickness of about 50 nm was formed by a sputtering method.
  • an insulating film 218 was formed on the conductive film 212.
  • a silicon oxynitride film having a thickness of about 300 nm was formed by a plasma CVD method.
  • the insulating film 218 was formed by setting the flow rates of the silane gas and the dinitrogen monoxide gas at 290 sccm and 4000 sccm, the pressure at 133 Pa, the film forming power at 1000 W, and the substrate temperature at 350 ° C.
  • the insulating film 218 and the conductive film 212 were removed by a dry etching method. SF 6 gas was used for etching.
  • ⁇ Resistance measurement> the resistance of the metal oxide film 214 in the film thickness direction was evaluated. Specifically, the film thickness and resistance of the metal oxide film 214 are measured, and then the surface side of the metal oxide film 214 is partially removed by etching to reduce the film thickness, and the film thickness and resistance are measured again. Repeated.
  • the sheet resistance of the metal oxide film 214 is shown in FIG. In FIG. 30, the horizontal axis represents the amount of reduction of the metal oxide film 214, and the vertical axis represents the sheet resistance.
  • the sheet resistance was as low as 1 ⁇ 10 3 ⁇ / ⁇ or less from the surface of the metal oxide film 214 to a depth of about 80 nm. It was confirmed that the metal oxide film 214 functions as a conductive film even when it is thickened to about 80 nm.
  • samples (sample E1 to sample E4) corresponding to the transistor 100 shown in FIG. 1 were manufactured and the cross-sectional shape was evaluated.
  • the film type and film forming conditions of the insulating layer corresponding to the insulating layer 118 which is the protective insulating layer are different.
  • a sample having an insulating layer, a metal oxide layer, a conductive layer and a protective insulating layer formed on a glass substrate was used.
  • an insulating layer having a thickness of 150 nm was formed over a glass substrate.
  • a first silicon oxynitride film having a thickness of about 5 nm, a second silicon oxynitride film having a thickness of about 140 nm, and a third silicon oxynitride film having a thickness of about 5 nm were respectively formed by a plasma CVD method. A film was formed.
  • the film formation of the first silicon oxynitride film was performed by setting the flow rates of the silane gas and the dinitrogen monoxide gas to be 24 sccm and 18000 sccm, the pressure was 200 Pa, the film formation power was 130 W, and the substrate temperature was 350 ° C.
  • the second silicon oxynitride film was formed by setting the flow rates of the silane gas and the dinitrogen monoxide gas at 200 sccm and 4000 sccm, the pressure at 300 Pa, the film formation power at 750 W, and the substrate temperature at 350 ° C.
  • the flow rates of silane gas and dinitrogen monoxide gas were 20 sccm and 3000 sccm, respectively, the pressure was 40 Pa, the film formation power was 500 W, and the substrate temperature was 350 ° C.
  • a metal oxide film having a thickness of about 20 nm was formed on the insulating layer by the sputtering method.
  • the substrate temperature during film formation was 100 ° C., and oxygen gas (oxygen flow rate ratio 100%) was used as the film formation gas.
  • the power supply was 4.5 kW (AC) and the pressure was 0.3 Pa.
  • a conductive film was formed on the metal oxide film.
  • a molybdenum film having a thickness of about 100 nm was formed by a sputtering method.
  • the conductive film was etched using the resist pattern as a mask to obtain a conductive layer.
  • a dry etching method was used for etching, and SF 6 gas was used as an etching gas.
  • Example 1 the metal oxide film was etched to obtain a metal oxide layer.
  • a wet etching method was used for etching. Since the description of Example 1 can be referred to as the etchant, detailed description thereof will be omitted.
  • the etching time was set to 75 seconds for each of sample E1 to sample E4.
  • an insulating film having a thickness of about 300 nm was formed as a protective insulating layer by the plasma CVD method.
  • four samples (sample E1 to sample E4) with different film types and film forming conditions of the protective insulating layer were prepared.
  • a silicon oxynitride film was formed as a protective insulating layer.
  • the silicon oxynitride film was formed by setting the flow rates of silane gas and dinitrogen monoxide gas at 290 sccm and 4000 sccm, the pressure at 133 Pa, the film forming power at 1000 W, and the substrate temperature at 350 ° C.
  • a silicon oxynitride film was formed as a protective insulating layer.
  • the silicon oxynitride film was formed by setting the flow rates of the silane gas and the dinitrogen monoxide gas at 150 sccm and 1000 sccm, the pressure at 200 Pa, the film forming power at 2000 W, and the substrate temperature at 350 ° C.
  • a silicon oxynitride film was formed as a protective insulating layer.
  • the silicon oxynitride film was formed by using silane gas, dinitrogen monoxide gas, nitrogen gas, and ammonia gas at flow rates of 150 sccm, 1000 sccm, 5000 sccm, and 100 sccm, a pressure of 200 Pa, a film-forming power of 2000 W, and a substrate temperature of 350 ° C.
  • a silicon nitride film was formed as a protective insulating layer.
  • the silicon nitride film was formed by setting the flow rates of silane gas, nitrogen gas, and ammonia gas at 150 sccm, 5000 sccm, and 100 sccm, the pressure at 200 Pa, the film formation power at 2000 W, and the substrate temperature at 350 ° C.
  • sample E1 to sample E4 were thinned by a focused ion beam (FIB), and the cross section was observed by scanning transmission electron microscopy (STEM).
  • FIB focused ion beam
  • FIG. 31 shows STEM images of cross sections of sample E1 to sample E4.
  • FIG. 31 is a transmission electron image (TE image) at a magnification of 100,000 times.
  • the glass substrate is shown as Glass
  • the insulating layer is shown as SiON1
  • the conductive layer is shown as Mo
  • the metal oxide layer is shown as IGZO.
  • a silicon oxynitride film is described as SiON2
  • a silicon nitride oxide film is described as SiNO
  • SiN silicon nitride film
  • the light-colored region observed between the conductive layer (Mo) and the metal oxide layer (IGZO) indicates a void.
  • sample E1 and sample E2 using silicon oxynitride as a protective insulating layer sample E2 has a smaller void than sample E1, and the protective insulating layer is between the conductive layer (Mo) and the metal oxide layer (IGZO). It was found that (SiON2) was formed. It was found that the size of the void between the conductive layer (Mo) and the metal oxide layer (IGZO) can be controlled by changing the film formation conditions of the protective insulating layer.
  • sample E3 using silicon oxynitride as the protective insulating layer tended to have smaller voids. It was found that the size of the void between the conductive layer (Mo) and the metal oxide layer (IGZO) can be controlled by changing the film type of the protective insulating layer.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Semiconductor Integrated Circuits (AREA)
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CN201980072744.5A CN112997335A (zh) 2018-11-02 2019-10-21 半导体装置
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