WO2020057501A1 - 驱动背板、显示面板、电子设备及驱动背板的制造方法 - Google Patents

驱动背板、显示面板、电子设备及驱动背板的制造方法 Download PDF

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Publication number
WO2020057501A1
WO2020057501A1 PCT/CN2019/106183 CN2019106183W WO2020057501A1 WO 2020057501 A1 WO2020057501 A1 WO 2020057501A1 CN 2019106183 W CN2019106183 W CN 2019106183W WO 2020057501 A1 WO2020057501 A1 WO 2020057501A1
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layer
facing away
electrode
gate
gate insulating
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PCT/CN2019/106183
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English (en)
French (fr)
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李海旭
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京东方科技集团股份有限公司
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Priority to US16/651,400 priority Critical patent/US11139321B2/en
Publication of WO2020057501A1 publication Critical patent/WO2020057501A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a driving backplane, an electronic device, a display panel, and a method of manufacturing the driving backplane.
  • the related MicroLED display panel generally includes a driving substrate and a light emitting device layer provided on the driving substrate.
  • the light emitting device layer includes LEDs distributed in an array. Each LED of the light emitting device layer is driven by the driving substrate to emit light independently, thereby realizing the related MicroLED display panel display. image.
  • embodiments of the present disclosure provide a display panel.
  • Embodiments of the present disclosure provide an electronic device, a display panel, a driving backplane, and a method for manufacturing the driving backplane, which are convenient for mounting a light emitting device and are beneficial for reducing an exhaust amount of a planarization layer.
  • a driving backplane including:
  • a driving device layer provided on the base substrate and including an electrode layer
  • a planarization layer is provided on a surface of the driving device layer facing away from the base substrate, and at least one protruding portion and a surface of the driving device layer facing away from the driving device layer are provided. At least one base portion adjacent to the protruding portion, wherein each protruding portion has a greater thickness than each base portion in a direction perpendicular to a plane on which the base substrate is located;
  • a conductive layer is provided on a surface of each protruding portion facing away from the driving device layer, and is connected to an electrode layer of the driving device layer;
  • a septum layer provided on a surface of the conductive layer facing away from the planarization layer;
  • a binding layer covers a surface of the spacer layer facing away from the conductive layer and a surface of the conductive layer facing away from the planarization layer, and the binding layer is used for setting a light emitting device.
  • the driving backplane further includes a black matrix, and the black matrix is provided at each base portion, and a corresponding protruding portion is not covered by the black matrix.
  • the spacer layer at least partially covers a surface of the conductive layer facing away from the planarization layer, and extends to a recess formed between adjacent protrusions of the planarization layer. Inside the slot.
  • a height of the spacer layer protruding beyond the black matrix is not less than 1 ⁇ m.
  • the driving backplane further includes:
  • An insulating layer provided on a surface of the base portion facing away from the base substrate and extending to the conductive layer and covering a part of the conductive layer; the black matrix provided on the insulating layer facing away from the planarization layer s surface.
  • the binding layer covers a region of the insulating layer that is stacked with a conductive layer.
  • a distance between the conductive layer and a bottom of the base portion is the same as a thickness of the black matrix.
  • the driving device layer further includes:
  • a buffer layer provided on the base substrate
  • An active layer provided on a surface of the buffer layer facing away from the base substrate;
  • a first gate insulating layer covering the active layer and an area of the buffer layer not covered by the active layer
  • a gate provided on a surface of the first gate insulating layer facing away from the active layer;
  • An interlayer dielectric layer provided on a surface of the second gate insulating layer facing away from the gate;
  • the electrode layer is disposed on a surface of the interlayer dielectric layer facing away from the second gate insulating layer, and includes a source electrode and a drain electrode, and each of the source electrode and the drain electrode passes a corresponding first via hole. Connected to the active layer, the respective first vias extending through the interlayer dielectric layer, the second gate insulating layer, and the first gate insulating layer to reach the surface of the active layer facing away from the substrate .
  • the driving device layer includes:
  • a capacitor electrode is provided on a surface of the first gate insulating layer facing away from the gate, and the orthographic projection of the capacitor electrode on the first gate insulating layer coincides with the gate, and the interlayer dielectric layer
  • the capacitor electrode and a region of the second gate insulating layer that are not covered by the capacitor electrode can cover the capacitor electrode and the gate to form a storage capacitor.
  • the at least one protruding portion includes a plurality of protruding portions
  • the at least one base portion includes a plurality of base portions
  • the conductive layer includes a plurality of electrode groups, and each of the electrode groups is provided on a surface of each of the protrusions facing away from the driving device layer.
  • Each of the electrode groups includes a first electrode and a first electrode. Two electrodes, and the first electrode is connected to the drain through a second via;
  • the septum layer includes a plurality of septum portions, and each of the septum portions is provided on a surface of each of the electrode groups facing away from the planarization layer, and each of the septum portions is separated by a corresponding one.
  • the bonding layer includes a plurality of pads, and each of the pads is provided on a surface of each of the spacer portions facing away from the planarization layer, and is connected to the corresponding first electrode and second electrode. ;
  • the black matrix includes a plurality of light shielding units, and each of the light shielding units is disposed in each of the bases in a one-to-one correspondence.
  • the orthographic projection of each electrode group on the driving device layer and the orthographic projection of the corresponding protrusion on the driving device layer at least partially overlap;
  • each spacer part on the driving device layer partially overlaps with the orthographic projection of the corresponding electrode group on the driving device layer;
  • each light-shielding unit on the driving device layer at least partially overlaps with the orthographic projection of the corresponding base on the driving device layer.
  • a method for manufacturing a driving backplane including:
  • a binding layer is formed on a surface of the spacer layer facing away from the conductive layer, the binding layer is connected to the conductive layer, and the binding layer is used for setting a light emitting device.
  • the method further includes:
  • a black matrix is formed in the base, and the protrusions protrude from the black matrix.
  • forming the driving device layer on the base substrate includes:
  • a first via is formed, and the first via penetrates the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer to reach the upper surface of the active layer facing away from the base substrate, and exposes the active layer.
  • a source and drain are formed on a surface of the interlayer dielectric layer facing away from the second gate insulating layer, and the source and drain are connected to the active layer through respective first vias.
  • the step of “forming a driving device layer on the base substrate” further includes:
  • a capacitor electrode is formed on a surface of the second gate insulating layer facing away from the gate.
  • the orthographic projection of the capacitor electrode on the first gate insulating layer coincides with the gate to form a storage capacitor with the gate.
  • the step of “etching the conductive material layer to form a pattern of the conductive layer” includes:
  • the conductive layer is formed into an electrode group by etching the conductive layer, and each electrode group includes a first electrode and a second electrode disposed at intervals.
  • the first electrode and the second electrode extend through the conductive layer and extend to The recessed recesses within a portion of the thickness of the planarization layer are spaced apart from each other, and the first electrode is connected to the drain through the second via; the electrode group covers the planarization layer, and the area outside the electrode group exposes the planarization layer. Groove.
  • a binding layer is formed on the surface of the spacer layer facing away from the conductive layer by photolithography and printing, and the binding layer extends to an area of the conductive layer that is not covered by the spacer layer to connect with the conductive layer.
  • a display panel including:
  • a light emitting device is disposed on the binding layer.
  • an electronic device including the display panel according to any one of the above.
  • FIG. 1 is a schematic structural diagram of a driving backplane according to an embodiment of the present disclosure.
  • FIG. 2 is a flowchart of a method for manufacturing a driving backplane according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram after completing step S110 in FIG. 2.
  • FIG. 4 is a schematic structural diagram after completing step S120 in FIG. 2.
  • FIG. 5 is a schematic structural diagram after completing step S130 in FIG. 2.
  • FIG. 6 is a schematic structural diagram after completing step S140 in FIG. 2.
  • FIG. 7 is a schematic structural diagram after completing step S150 in FIG. 2.
  • FIG. 8 is a schematic structural diagram after completing step S160 in FIG. 2.
  • FIG. 9 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • the embodiments of the present disclosure provide a driving backplane suitable for a display panel, such as a MicroLED display panel.
  • the driving backplane includes, for example, a base substrate 1, a driving device layer 2, a planarization layer 3, a conductive layer 4, a spacer layer 5, and a binding layer 6; Includes black matrix 7, where:
  • the driving device layer 2 is provided on the base substrate 1 and includes an electrode layer, for example.
  • the planarization layer 3 is provided on, for example, a surface of the driving device layer 2 facing away from the base substrate 1, and the surface of the planarizing layer 3 facing away from the driving device layer 2 has at least one protruding portion 301 and at least one protruding portion 301 disposed next to the protruding portion 301.
  • the conductive layer 4 is disposed on a surface of the protruding portion 301 facing away from the driving device layer 2, and is in conductive connection with the electrode layer of the driving device layer 2.
  • the spacer layer 5 is disposed on the surface of the conductive layer 4 facing away from the planarization layer 3 and at least partially covering the surface of the conductive layer 4 facing away from the planarization layer 3; and the spacer layer 5 extends at least partially, for example, as shown in the figure. Entering into the planarization layer (for example, extending into a recessed recess formed between two adjacent protruding portions 301).
  • the binding layer 6 at least partially covers the surface of the spacer layer 5 facing away from the conductive layer 4 and the surface of the conductive layer 4 facing away from the planarizing layer 3 and is not covered by the spacer layer 5.
  • the binding layer 6 is used for setting Light emitting device.
  • the black matrix 7 is provided on the base portion 302, and the protruding portion 301 is not shielded by the black matrix 7, so that the protruding portion 301 protrudes to be exposed from the black matrix.
  • the planarization layer 3 has a protrusion 301 and a base 302
  • the black matrix 7 is located above the base 302
  • the binding layer 6 is located above the protrusion 301, and the binding layer 6 is cushioned.
  • the base substrate 1 is, for example, glass or other transparent materials, and its shape is, for example, rectangular, circular, or the like, which is not particularly limited herein.
  • the driving device layer 2 is provided on, for example, the base substrate 1 and includes, for example, a plurality of driving devices configured to drive the light emitting devices provided on the driving backplane, for example. Is a thin film transistor.
  • the driving device layer 2 includes, for example, a buffer layer 21, an active layer 22, a first gate insulating layer 23, a gate 24, a second gate insulating layer 25, an interlayer dielectric layer 26, and a source. Drain 27, where:
  • the buffer layer 21 is provided on, for example, the base substrate 1, and a material thereof is, for example, silicon nitride or silicon oxide or other materials.
  • the active layer 22 is provided on, for example, a surface of the buffer layer 21 facing away from the base substrate 1.
  • the first gate insulating layer 23 covers, for example, the active layer 22 and a region of the buffer layer 21 not covered by the active layer 22.
  • the material of the first gate insulating layer 23 is, for example, silicon oxide.
  • the gate 24 is provided on the surface of the first gate insulating layer 23 facing away from the active layer 22, and more specifically, the orthographic projection of the gate 24 on the buffer layer is covered by the active layer 22; and the gate 24 is, for example, Metal Material.
  • the second gate insulating layer 25 covers, for example, the gate 24 and the area of the first gate insulating layer 23 that is not covered by the gate 24.
  • the material of the second gate insulating layer 25 is, for example, the same as that of the first gate insulating layer 23.
  • the interlayer dielectric layer 26 is provided on, for example, a surface of the second gate insulating layer 25 facing away from the gate 24.
  • the material of the interlayer dielectric layer 26 is, for example, at least one of silicon oxide and silicon nitride. Of course, other materials may be selected instead, for example.
  • the electrode layer is provided, for example, on the surface of the interlayer dielectric layer 26 facing away from the second gate insulating layer 25, and includes a source and a drain 27, and the source and drain 27 specifically include, for example, a source 271 and a drain 272, and the source 271 and the drain
  • Each of 272 is connected to the active layer 22, for example, through a corresponding first via, and each of the first vias is formed to extend through the interlayer dielectric layer 26, the second gate insulating layer 25, the first The gate insulating layer 23 reaches the upper surface of the active layer 22 facing away from the base substrate 1.
  • the driving device layer 2 described above further includes, for example, a capacitor electrode 28, which is also provided on a surface of the second gate insulating layer 25 facing away from the gate 24, and more specifically, the capacitor electrode 28 is insulated at the first gate.
  • the orthographic projection of the layer 23 coincides with the gate electrode 24; the interlayer dielectric layer 26 covers, for example, the capacitor electrode 28 and the area of the second gate insulating layer 25 that is not covered by the capacitor electrode 28.
  • the capacitor electrode 28 can form a storage capacitor with the gate 24, that is, the gate 24 serves not only as a gate of the thin film transistor, but also as an electrode of the storage capacitor.
  • the planarization layer 3 is, for example, an insulating material, and is provided on, for example, a surface of the driving device layer 2 facing away from the substrate substrate 1.
  • the surface of the planarizing layer 3 facing away from the driving device layer 2 has, for example, At least one (e.g., multiple) projections 301 and at least one (e.g., multiple) bases 302.
  • the specific setting of the planarization layer 3, for example, as described above can reduce the conductive layer 4 and the source
  • the capacitance between the drains 27 reduces signal interference.
  • the material of the conductive layer 4 is, for example, metal or other conductive materials.
  • the conductive layer 4 is provided on the surface of the protrusion 301 facing away from the driving device layer 2 and is connected to the driving device layer 2.
  • the conductive layer 4 includes, for example, a plurality of electrode groups, and each electrode group is provided on a surface of each protruding portion 301 facing away from the driving device layer 2 (in other words, each electrode group is on the driving device layer).
  • each electrode group includes, for example, a first electrode 41 and a second electrode 42, the first electrode 41 and the second The electrodes 42 are all located on the corresponding protrusions 301 (more specifically on the surface of the corresponding protrusions 301 facing away from the substrate substrate 1), and the first electrode 41 is then connected to the drain electrode 272 through a second via hole, for example.
  • the material of the spacer layer 5 is, for example, the same as that of the planarization layer 3, and the spacer layer 5 is provided on the surface of the conductive layer 4 facing away from the planarization layer 3, but not Completely cover the electrode group. And because the spacer layer 5 extends at least partially into the planarization layer (for example, into a recessed recess formed between two adjacent protruding portions 301), for example, the spacer layer 5 The layer 5 separates the first electrode 41 and the second electrode 42 of the corresponding electrode group, for example.
  • the spacer layer 5 includes, for example, a plurality of spacer portions, and each spacer portion is provided on a surface of each electrode group facing away from the planarization layer 3 (in other words, each spacer portion is on the driving device layer 2).
  • the orthographic projection on the part overlaps with the orthographic projection of the corresponding electrode group on the driving device layer 2).
  • Each spacer portion separates the corresponding electrode group first electrode 41 and second electrode 42.
  • the spacer portion covers, for example, the spacer. A partial region of the opened first electrode 41 and a partial region of the second electrode 42.
  • the binding layer 6 is, for example, a conductive material such as metal, and it covers, for example, the surface of the spacer layer 5 (including the inclined side surface and the flat top surface) facing away from the conductive layer 4 and the separation of the conductive layer 4.
  • the surface of the layer 3 (and exposed from the black matrix 7 and the insulating layer 8) is planarized.
  • a region of the binding layer 6 that covers the spacer layer 5 is raised, which is convenient for providing a light emitting device on the binding layer 6.
  • the bonding layer 6 includes, for example, a plurality of pads, and the plurality of pads are provided on the surfaces of the spacer portions facing away from the planarization layer 3 (for example, each pad is disposed on a corresponding one).
  • the aforementioned flat top surface of the septum part and is connected to the first electrode 41 and the second electrode 42 of the corresponding electrode group, and for any pad, it is electrically conducted by the separation of the corresponding septum part, for example
  • the surface of the layer 4 extends to the first electrode 41 and the second electrode 42 so as to be connected to the first electrode 41 and the second electrode 42.
  • the pad includes, for example, a first pad body 61 and a second pad body 62 which are disposed at intervals.
  • the first pad body 61 is connected to the first electrode 41 and the second pad body 62 is connected to the second electrode, for example. 42 connections.
  • the black matrix 7 is, for example, a light-shielding material, and is provided on the base portion 302, for example, and the protruding portion 301 is not shielded by the black matrix 7, and thus the protruding portion 301 is protruding to be exposed from the black matrix 7, for example.
  • the black matrix 7 includes, for example, a plurality of light-shielding units, and the light-shielding units are provided on the bases 302 in a one-to-one correspondence (more specifically, the orthographic projection of each light-shielding unit on the driving device layer 2 corresponds to the corresponding The orthographic projection of the base 302 on the driving device layer 2 at least partially overlaps), and the driving backplane is divided into a plurality of pixel areas by a light shielding unit, for example, each pixel area has a pad (for example, only one pad shown in the figure) ), For example, (for example, one or more) light emitting devices are disposed on each pad.
  • the height h of the spacer layer 5 protruding beyond the black matrix 7 is not less than 1 ⁇ m, that is, h ⁇ 1 ⁇ m, for example, h is, for example, 1.7 ⁇ m.
  • the distance between the conductive layer 4 and the bottom of the base 302 (that is, the distance between the lower surface of the conductive layer 4 facing the base substrate and the upper surface of the driving device layer 2 facing away from the base substrate) is, for example, 1 ⁇ m.
  • the thickness of the black matrix 7 is, for example, 1 ⁇ m, and also larger or smaller than 1 ⁇ m.
  • the distance between the conductive layer 4 and the bottom of the base 302 is the same as the thickness of the black matrix 7, and both are 1 ⁇ m.
  • the driving backplane further includes, for example, an insulating layer 8.
  • the insulating layer 8 is provided on the surface of the base 302 facing away from the base substrate and extends to the conductive layer 4.
  • the black matrix 7 is provided on, for example, The surface of the insulating layer 8 facing away from the planarization layer 3.
  • the insulating layer 8 extends to a part of the conductive layer 4 covering a part of the conductive layer 4, and the binding layer 6 covers an area of the insulating layer 8 corresponding to the conductive layer 4 (that is, an area of the insulating layer 8 overlapping the conductive layer 4).
  • a portion of the conductive layer 4 that is not covered by the insulating layer 8 (that is, a portion of the conductive layer 4 exposed from the insulating layer 8) is covered by, for example, the binding layer 6 so as to be connected with the binding layer 6 and the conductive layer 4.
  • An embodiment of the present disclosure provides a manufacturing method of a driving backplane. As shown in FIG. 2, the manufacturing method includes, for example:
  • Step S110 forming a driving device layer on the base substrate
  • Step S120 forming a planarization layer on a surface of the driving device layer facing away from the base substrate;
  • Step S130 A conductive layer is formed on a surface of the planarization layer facing away from the driving device layer, and the conductive layer is connected to the driving device layer;
  • Step S140 etch the conductive material layer to form a pattern of the conductive layer
  • Step S150 etch an area of the planarization layer that is not covered by the conductive layer to form a protrusion and a base, and the conductive layer is located on a surface of the protrusion that faces away from the driving device layer;
  • Step S160 A spacer layer is formed on a surface of the conductive layer facing away from the planarization layer, and the spacer layer is formed to extend into a part of the thickness of the planarization layer (for example, a protrusion extending into the planarization layer). Inside the recessed groove formed in the part);
  • step S170 a binding layer is formed on a surface of the spacer layer facing away from the conductive layer, the binding layer is connected to the conductive layer, and the binding layer is used for setting a light emitting device thereon.
  • the method further includes, for example, step S180: forming a black matrix on the base portion, and the protruding portion protrudes from the black matrix.
  • step S110 a driving device layer is formed on a base substrate.
  • the driving device layer 2 includes, for example, a buffer layer 21, an active layer 22, a first gate insulating layer 23, a gate 24, a second gate insulating layer 25, an interlayer dielectric layer 26, and a source and drain electrode 27,
  • step S110 includes, for example:
  • step S1110 a buffer layer 21 is formed on the base substrate 1.
  • Step S1120 An active layer 22 is formed on a surface of the buffer layer 21 facing away from the base substrate 1.
  • a first gate insulating layer 23 is formed to cover the active layer 22 and the buffer layer 21 in a region not covered by the active layer 22.
  • a gate electrode 24 is formed on a surface of the first gate insulating layer 23 facing away from the buffer layer 21, and more specifically, for example, the orthographic projection of the gate electrode 24 on the buffer layer is covered by the active layer 22.
  • a second gate insulating layer 25 is formed to cover the gate 24 and the first gate insulating layer 23 and the region not covered by the gate 24.
  • Step S1160 An interlayer dielectric layer 26 is formed on a surface of the second gate insulating layer 25 facing away from the gate 24.
  • Step S1170 forming a first via hole, the first via hole penetrates the first gate insulating layer 23, the second gate insulating layer 25, and the interlayer dielectric layer 26 to reach the upper surface of the active layer 22 facing away from the substrate substrate 1, And exposed the active layer 22.
  • Step S1180 A source / drain 27 is formed on a surface of the interlayer dielectric layer 26 facing away from the second gate insulating layer 25, and the source / drain 27 is connected to the active layer 22 through the first via hole.
  • step S110 also includes step S1190, forming a capacitor electrode 28 on a surface of the second gate insulating layer 25 facing away from the gate 24, and the orthographic projection of the capacitor electrode 28 on the first gate insulating layer 23 coincides with the gate 24, for example, so that A storage capacitor may be formed with the gate 24.
  • This step S1190 is performed, for example, between step S1140 and step S1150.
  • the interlayer dielectric layer 26 covers, for example, the capacitor electrode 28 and the area of the second gate insulating layer 25 that is not covered by the capacitor electrode 28.
  • step S120 a planarization layer is formed on a surface of the driving device layer facing away from the base substrate.
  • the planarization layer 3 is formed by, for example, photolithography or other processes.
  • the planarization 3 has a through hole of the drain 272.
  • the surface of the planarization layer 3 formed in step S120 facing away from the base substrate 1 is, for example, a flat surface.
  • Step S130 A conductive layer is formed on a surface of the planarization layer facing away from the driving device layer, and the conductive layer is connected to the driving device layer.
  • the conductive layer 4 completely covers the planarization layer 3 formed in step S120, and the second via hole formed through the planarization layer 3 is connected to the drain electrode 272.
  • step S140 the conductive layer is etched to form a pattern of the conductive layer.
  • the conductive layer 4 is etched by a physical or chemical etching process to form a pattern of the conductive layer 4.
  • the conductive layer 4 is formed into an electrode group, and each electrode group includes, for example, two electrodes disposed at intervals, that is, a first electrode 41 and a second electrode 42.
  • the second electrodes 42 are spaced apart from each other, for example, by recessed recesses that penetrate the conductive layer 4 and extend to a portion of the thickness within the planarization layer; the electrode group covers the planarization layer 3, and areas other than the electrode group are exposed to planarization.
  • Layer 3 ie, the grooves of the planarization layer 3 are exposed).
  • Step S150 Etching an area of the planarization layer not covered by the conductive layer to form a protruding portion and a base portion, and the conductive layer is located on a surface of the protruding portion facing away from the driving device layer.
  • dry etching is used to etch the area of the planarization layer 3 that is not covered by the conductive layer 4.
  • a gas including oxygen is used in the etching, and the specific composition depends on the process conditions. Make special restrictions.
  • the etch depth is, for example, among them
  • the planarization layer 3 is also etched by other means, for example.
  • a region of the planarization layer not covered by the conductive layer is formed as a base portion, and a region covered by the conductive layer is formed as a protrusion.
  • Step S160 A spacer layer is formed on a surface of the conductive layer facing away from the planarization layer.
  • the method for forming the spacer layer 5 is referred to, for example, the planarization layer 3, and the specific structure of the spacer layer 5 is referred to, for example, the spacer layer 5 in the implementation of the driving backplane, which is not described in detail here.
  • the spacer layer 5 is provided on the surface of the conductive layer 4 facing away from the planarization layer 3, but does not completely cover the electrode group.
  • the spacer layer 5 at least partially extends into the planarization layer as shown in the figure (for example, it extends into a recessed groove formed between two adjacent protruding portions 301, the spacer layer 5 5
  • the first electrode 41 and the second electrode 42 of the corresponding electrode group are separated.
  • Step S170 A binding layer is formed on a surface of the spacer layer facing away from the conductive layer (including an inclined side surface and a flat top surface) and a surface of the conductive layer 4 facing away from the planarization layer 3, and the binding The fixed layer is connected to the conductive layer, and the binding layer is used for setting a light emitting device.
  • a binding layer 6 is formed on the surface of the spacer layer 5 facing away from the conductive layer 4 by, for example, photolithography, printing, or other processes, and the binding layer 6 extends to an area of the conductive layer 4 that is not covered by the spacer layer 5 so as to The conductive layer 4 is connected.
  • Step S180 A black matrix is formed in the base portion, and the protruding portion protrudes from the black matrix.
  • the manufacturing method of the embodiment of the present disclosure further includes, for example:
  • Step S190 An insulating layer is formed in the base portion, and the insulating portion extends toward the conductive layer and covers a part of the conductive layer.
  • the black matrix 7 is provided on, for example, a surface of the insulating layer 8 facing away from the planarization layer 3, and the binding layer 6 covers, for example, a region corresponding to the conductive layer 4 and the insulating layer 8.
  • the display panel includes, for example, a light emitting device 100 and the driving backplane of the foregoing embodiment, wherein:
  • the light emitting devices 100 are, for example, disposed on a surface of the binding layer 6 facing away from the conductive layer 4.
  • the number of the light emitting devices 100 is, for example, multiple, and one-to-one correspondence is provided on a plurality of pads of the binding layer 6
  • each light-emitting device 100 is connected to a plurality of driving devices of the driving device layer 2 through a one-to-one correspondence with each pad, for example, to independently control light emission to display an image, for example.
  • An embodiment of the present disclosure also provides an electronic device including, for example, the display panel of the above-mentioned embodiment.
  • the electronic device is, for example, a device with a display panel, such as a mobile phone, a tablet computer, or an electronic watch, and will not be enumerated here.
  • the planarization layer has a protrusion and a base
  • the black matrix is located at the base
  • the binding layer is located at the protrusion
  • the binding layer is separated.
  • the cushion layer and the conductive layer are cushioned, thereby increasing the height of the binding layer.
  • the binding layer protrudes from the black matrix, which is convenient for connecting the light-emitting device layer to the binding layer.
  • a part of the planarization layer can be made through the base The thickness is reduced, thereby reducing the amount of gas stored, which is beneficial to reduce the amount of exhaust gas and ensure product quality.

Abstract

一种驱动背板、显示面板、电子设备、及驱动背板的制造方法，涉及显示技术领域。驱动背板包括衬底基板(1)、驱动器件层(2)、平坦化层(3)、导电层(4)、隔垫层(5)、绑定层(6)。驱动器件层(2)设于衬底基板(1)，包括电极层；平坦化层(3)设于驱动器件层(2)的背离衬底基板(1)的表面，且平坦化层(3)的背离驱动器件层(2)的表面上设有至少一个凸出部(301)和与凸出部(301)紧邻设置的至少一个基部(302)，其中每个凸出部(301)具备比每个基部(302)更大厚度；导电层(4)设于每个凸出部(301)的背离驱动器件层(2)的表面，且与驱动器件层(2)的电极层成导电连接；隔垫层(5)设于导电层(4)的背离平坦化层(3)的表面；绑定层(6)覆盖隔垫层(5)的背离导电层(4)的表面以及导电层(4)的背离平坦化层(3)的表面，绑定层(6)用于设置发光器件(100)。

Description

驱动背板、显示面板、电子设备及驱动背板的制造方法
相关申请的交叉引用
本公开实施例要求于2018年9月21日递交中国专利局的、申请号为201811110064.1的中国专利申请的权益，该申请的全部内容以引用方式并入本文。
技术领域
本公开涉及显示技术领域，具体而言，涉及一种驱动背板、电子设备、显示面板及驱动背板的制造方法。
背景技术
随着显示技术的发展，人们对显示面板的要求也越来越高，目前，Micro LED显示技术，即LED微缩化和矩阵化技术，正在获得越来越广泛的关注。相关Micro LED显示面板一般包括驱动基板和设于驱动基板的发光器件层，发光器件层包括阵列分布的LED，通过驱动基板驱动发光器件层的各LED独立发光，从而实现相关的Micro LED显示面板显示图像。但是，相关的驱动基板难以安装LED，且相关驱动基板的平坦化层储气量较大，相应的，平坦化层排气量也较大，会降低产品的可靠性。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的相关技术的信息。
发明内容
为至少部分地克服上述相关技术中的缺陷和/或不足，本公开的实施例提供了一种显示面板。
本公开实施例提供一种电子设备、显示面板、驱动背板及驱动背板的制造方法，便于安装发光器件，且有利于减小平坦化层的排气量。
本公开的实施例提供技术方案如下：
根据本公开的一个方面，提供一种驱动背板，包括：
衬底基板；
驱动器件层，设于所述衬底基板上，包括电极层；
平坦化层，设于所述驱动器件层的背离所述衬底基板的表面，且所述平坦化层的 背离所述驱动器件层的表面上设有至少一个凸出部和与所述至少一个凸出部相邻的至少一个基部，其中，在垂直于所述衬底基板所在平面的方向上，每个凸出部具备比每个基部更大厚度；
导电层，设于每个凸出部的背离所述驱动器件层的表面，且与所述驱动器件层的电极层连接；
隔垫层，设于所述导电层的背离所述平坦化层的表面；
绑定层，覆盖所述隔垫层的背离所述导电层的表面以及所述导电层的背离所述平坦化层的表面，所述绑定层用于设置发光器件。
在本公开的一种示例性实施例中，所述驱动背板还包括黑矩阵，所述黑矩阵设于每个基部，相应凸出部未被所述黑矩阵遮蔽。
在本公开的一种示例性实施例中，所述隔垫层至少部分地覆盖导电层的背离平坦化层的表面，并且延伸到平坦化层的相邻的凸出部之间所形成的凹槽内。
在本公开的一种示例性实施例中，所述隔垫层凸出超出所述黑矩阵的高度不小于1μm。
在本公开的一种示例性实施例中，所述驱动背板还包括：
绝缘层，设于所述基部的背离衬底基板的表面且延伸至所述导电层，并覆盖所述导电层的部分区域，所述黑矩阵设于所述绝缘层的背离所述平坦化层的表面。
在本公开的一种示例性实施例中，所述绑定层覆盖所述绝缘层的与导电层叠置的区域。
在本公开的一种示例性实施例中，所述导电层与所述基部的底部之间的距离和所述黑矩阵的厚度相同。
在本公开的一种示例性实施例中，所述驱动器件层还包括：
缓冲层，设于衬底基板；
有源层，设于所述缓冲层的背离所述衬底基板的表面；
第一栅绝缘层，覆盖所述有源层、和所述缓冲层的未被有源层覆盖的区域；
栅极，设于所述第一栅绝缘层的背离所述有源层的表面；
第二栅绝缘层，覆盖所述栅极和所述第一栅绝缘层的未被栅极覆盖的区域；以及
层间介质层，设于所述第二栅绝缘层的背离所述栅极的表面；
其中电极层设于所述层间介质层的背离所述第二栅绝缘层的表面，且包括源极和漏极，所述源极和所述漏极分别均通过各自相应的第一过孔与所述有源层连接，所述 各自相应的第一过孔延伸穿过所述层间介质层、第二栅绝缘层、第一栅绝缘层而达到有源层的背离衬底基板的表面。
在本公开的一种示例性实施例中，所述驱动器件层包括：
电容电极，设于所述第一栅绝缘层的背离所述栅极的表面，且所述电容电极在所述第一栅绝缘层的正投影与所述栅极重合，所述层间介质层覆盖所述电容电极、和第二栅绝缘层的未被电容电极覆盖的区域，所述电容电极与所述栅极能形成存储电容。
在本公开的一种示例性实施例中，所述至少一个凸出部包括多个凸出部，和所述至少一个基部包括多个基部；
所述导电层包括多个电极组，各所述电极组一一对应的设于各所述凸出部的背离所述驱动器件层的表面，每个所述电极组均包括第一电极和第二电极，且第一电极通过第二过孔与漏极连接；
所述隔垫层包括多个隔垫部，各所述隔垫部一一对应的设于各所述电极组的背离所述平坦化层的表面，每个所述隔垫部隔开对应的第一电极和第二电极；
所述绑定层包括多个焊盘，各所述焊盘一一对应的设于各所述隔垫部的背离所述平坦化层的表面，且与对应的第一电极和第二电极连接；
所述黑矩阵包括多个遮光单元，各所述遮光单元一一对应的设于各所述基部内。
在本公开的一种示例性实施例中，每个电极组在驱动器件层上的正投影与相应凸出部在驱动器件层上的正投影至少部分地重叠；或
每个隔垫部在驱动器件层上的正投影与相应电极组在驱动器件层上的正投影部分地重叠；或
每个遮光单元在驱动器件层上的正投影与相应的基部在驱动器件层上的正投影至少部分重叠。
根据本公开的一个方面，提供一种驱动背板的制造方法，其中，包括：
在衬底基板上形成驱动器件层；
在所述驱动器件层的背离所述衬底基板的表面形成平坦化层；
在所述平坦化层的背离所述驱动器件层的表面形成导电层，且所述导电层与所述驱动器件层中的电极层连接；
对所述导电层刻蚀，以形成导电层的图案；
对所述平坦化层未被所述导电层覆盖的区域进行刻蚀，以形成凸出部和基部，所述导电层位于所述凸出部的背离所述驱动器件层的表面；
在所述导电层的背离所述平坦化层的表面形成隔垫层，且所述隔垫层形成为延伸到平坦化层内的一部分厚度内；
在所述隔垫层的背离所述导电层的表面形成绑定层，所述绑定层与所述导电层连接，所述绑定层用于设置发光器件。
在本公开的一种示例性实施例中，在步骤“在所述隔垫层的背离所述导电层的表面形成绑定层”之后，所述方法还包括：
在所述基部内形成黑矩阵，所述凸出部凸出于所述黑矩阵。
在本公开的一种示例性实施例中，在衬底基板上形成驱动器件层包括：
在衬底基板上形成缓冲层；
在缓冲层的背离衬底基板的表面形成有源层；
形成覆盖有源层、和缓冲层的未被有源层覆盖的区域的第一栅绝缘层；
在第一栅绝缘层的背离缓冲层的表面形成栅极，栅极在缓冲层上的正投影被有源层所覆盖；
形成覆盖栅极和第一栅绝缘层的未被栅极覆盖的区域的第二栅绝缘层；
在第二栅绝缘层的背离栅极的表面形成层间介质层；
形成第一过孔，第一过孔穿透第一栅绝缘层、第二栅绝缘层和层间介质层以达到有源层的背离衬底基板的上表面，并露出有源层。
在层间介质层的背离第二栅绝缘层的表面形成源漏极，源漏极通过各自相应的第一过孔与有源层连接。
在本公开的一种示例性实施例中，在步骤“在第一栅绝缘层的背离缓冲层的表面形成栅极”之后、且在步骤“形成覆盖栅极和第一栅绝缘层的未被栅极覆盖的区域的第二栅绝缘层”之前，所述步骤“在衬底基板上形成驱动器件层”还包括：
在第二栅绝缘层的背离栅极的表面形成电容电极，电容电极在第一栅绝缘层上的正投影与栅极重合以与栅极形成存储电容。
在本公开的一种示例性实施例中，所述步骤“对所述导电材料层刻蚀，以形成导电层的图案”包括：
通过对导电层的刻蚀来使导电层形成电极组，每个电极组包括间隔设置的第一电极和第二电极，所述第一电极和所述第二电极由贯穿导电层且延伸到到平坦化层内的一部分厚度内的下凹的凹槽而彼此间隔开，且第一电极通过第二过孔与漏极连接；电极组覆盖平坦化层，电极组以外的区域露出平坦化层的凹槽。
在本公开的一种示例性实施例中，所述步骤“在所述隔垫层的背离所述导电层的表面形成绑定层，所述绑定层与所述导电层连接，所述绑定层用于设置发光器件”包括：
通过光刻、印刷在隔垫层的背离导电层的表面形成绑定层，且绑定层延伸至导电层未被隔垫层覆盖的区域以与导电层连接。
根据本公开的一个方面，提供一种显示面板，包括：
上述任意一项所述的驱动背板；
发光器件，设于所述绑定层。
根据本公开的一个方面，提供一种电子设备，包括上述任意一项所述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施方式驱动背板的结构示意图。
图2为本公开实施方式驱动背板的制造方法的流程图。
图3为完成图2中步骤S110后的结构示意图。
图4为完成图2中步骤S120后的结构示意图。
图5为完成图2中步骤S130后的结构示意图。
图6为完成图2中步骤S140后的结构示意图。
图7为完成图2中步骤S150后的结构示意图。
图8为完成图2中步骤S160后的结构示意图。
图9为本公开实施方式显示面板的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本 发明将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”等仅作为标记使用，不是对其对象的数量限制。
附图中各部件的形状和大小不反映本公开实施例的显示面板的各个膜层和部件的真实比例，目的只是示意说明本公开实施例内容。
根据本公开实施例的总体技术构思，本公开实施方式提供了一种驱动背板，适用于显示面板，该显示面板例如是Micro LED显示面板。如图1以及图3至图8所示，该驱动背板例如包括衬底基板1、驱动器件层2、平坦化层3、导电层4、隔垫层5、绑定层6；并且例如还包括黑矩阵7，其中：
驱动器件层2例如设于衬底基板1，包括电极层。
平坦化层3例如设于驱动器件层2的背离衬底基板1的表面，且平坦化层3的背离驱动器件层2的表面具有至少一个凸出部301和与凸出部301紧邻设置的至少一个基部302，其中所述凸出具备比基部更大厚度。
导电层4设于凸出部301的背离驱动器件层2的表面，且与驱动器件层2的电极层成导电连接。
隔垫层5设于导电层4的背离平坦化层3的表面，且至少部分地覆盖导电层4的背离平坦化层3的表面；且所述隔垫层5例如图示般至少部分地延伸进入平坦化层内(例如延伸进入介于相邻两个凸出部301之间所形成的下凹的凹槽内)。
绑定层6至少部分地覆盖隔垫层5的背离导电层4的表面、以及导电层4的背离平坦化层3的表面的未被隔垫层5覆盖的部分，绑定层6用于设置发光器件。
并且，例如，黑矩阵7设于基部302，凸出部301未被黑矩阵7遮蔽，由此凸出 部301凸出为呈从黑矩阵暴露。
本公开实施方式的显示面板，例如由于平坦化层3具有凸出部301和基部302，黑矩阵7位于基部302上方，绑定层6位于凸出部301上方，且绑定层6被隔垫层5和导电层4所支承，从而增大了绑定层6的高度，便于实现发光器件与绑定层6之间的连接；同时，例如通过设置基部302使平坦化层3的凸出部301(其上设置待与导电层4连接的所述绑定层6)相比于基部302高出的竖向尺寸减薄、由此使所需的平坦化层3的局部厚度降低，从而减少储气量，有利于使排气量降低，保证产品质量。
下面对本公开实施方式的显示面板的各部分进行详细说明：
衬底基板1例如是玻璃或其它透明材质，其形状例如是矩形、圆形等，在此不做特殊限定。
如图3所示，驱动器件层2例如设于衬底基板1上，其例如包括多个驱动器件，所述多个驱动器件配置成分别驱动设于驱动背板上的发光器件，驱动器件例如是薄膜晶体管。
如图3所示，举例而言，驱动器件层2例如包括缓冲层21、有源层22、第一栅绝缘层23、栅极24、第二栅绝缘层25、层间介质层26和源漏极27，其中：
缓冲层21例如设于衬底基板1，其材料例如是氮化硅或氧化硅或其它材料。有源层22例如设于缓冲层21的背离衬底基板1的表面。第一栅绝缘层23例如覆盖有源层22、和缓冲层21未被有源层22覆盖的区域，第一栅绝缘层23的材料例如为氧化硅。栅极24例如设于第一栅绝缘层23的背离有源层22的表面，且更具体地，栅极24在缓冲层上的正投影被有源层22所覆盖；且栅极24例如为金属材质。第二栅绝缘层25例如覆盖栅极24、和第一栅绝缘层23未被栅极24覆盖的区域，其材料例如与第一栅绝缘层23的材料相同。层间介质层26例如设于第二栅绝缘层25的背离栅极24的表面，其材料例如是氧化硅、氮化硅中至少一个，当然，也例如替代地选择为其它材料。电极层例如设于层间介质层26的背离第二栅绝缘层25的表面，且包括源漏极27，源漏极27具体地例如包括源极271和漏极272，源极271和漏极272中每个均例如通过相应第一过孔与有源层22连接，每个所述第一过孔例如形成为延伸穿过所述层间介质层26、第二栅绝缘层25、第一栅绝缘层23达到有源层22的背离衬底基板1的上表面。
此外，上述的驱动器件层2还例如包括电容电极28，该电容电极28例如也设于第二栅绝缘层25的背离栅极24的表面，且更具体地，电容电极28在第一栅绝缘层23的正投影与栅极24重合；层间介质层26例如覆盖电容电极28、和第二栅绝缘层 25的未被电容电极28覆盖的区域。
电容电极28例如与栅极24能形成存储电容，也就是说，栅极24不仅充当薄膜晶体管的栅极，而且充当存储电容的一个电极。
如图1和图7所示，平坦化层3例如为绝缘材质，且其例如设于驱动器件层2的背离衬底基板1的表面，平坦化层3的背离驱动器件层2的表面例如具有至少一个(例如多个)凸出部301和至少一个(例如多个)基部302。平坦化层3的例如如前所述的具体设置(通过凸出部的设置来抬高源漏极，便利了增加导电层4和源漏极27间的距离)可减小导电层4和源漏极27间的电容，减小信号干扰。
如图1和图7所示，导电层4的材料例如为金属或其它导电材料，导电层4例如设于凸出部301的背离驱动器件层2的表面，且与驱动器件层2连接。举例而言，具体地，导电层4例如包括多个电极组，各电极组一一对应的设于各凸出部301的背离驱动器件层2的表面(换言之，每个电极组在驱动器件层2上的正投影与相应凸出部301在驱动器件层2上的正投影至少部分地重叠)，每个电极组均例如包括第一电极41和第二电极42，第一电极41和第二电极42均位于相应凸出部301上(更具体地位于相应凸出部301的背离衬底基板1的表面上)，第一电极41例如继而通过第二过孔与漏极272连接。
如图1和图7、图8所示，隔垫层5的材料例如与平坦化层3的材料相同，且隔垫层5例如设于导电层4的背离平坦化层3的表面，但不完全覆盖电极组。且由于所述隔垫层5例如图示般至少部分地延伸进入平坦化层内(例如延伸进入介于相邻两个凸出部301之间所形成的下凹的凹槽内)，隔垫层5例如将相应电极组的第一电极41和第二电极42隔开。举例而言，隔垫层5例如包括多个隔垫部，各隔垫部一一对应的设于各电极组的背离平坦化层3的表面(换言之，每个隔垫部在驱动器件层2上的正投影与相应电极组在驱动器件层2上的正投影部分地重叠)，每个隔垫部隔开对应的电极组第一电极41和第二电极42，隔垫部例如覆盖其隔开的第一电极41的部分区域和第二电极42的部分区域。
如图1所示，绑定层6例如为金属等导电材质，且其例如覆盖隔垫层5的背离导电层4的表面(包括倾斜的侧表面和平坦的顶面)以及导电层4的背离平坦化层3的(且从黑矩阵7和绝缘层8暴露的)表面。并且，由于隔垫层5的存在，例如使绑定层6的覆盖隔垫层5的区域凸起，便利于在绑定层6上设置发光器件。
举例而言，绑定层6例如包括多个焊盘，多个焊盘例如一一对应的设于多个隔垫 部的背离平坦化层3的表面(例如，每个焊盘设置在相应的隔垫部的前述的平坦的顶面上)，且与对应的电极组的第一电极41和第二电极42连接，对于任一焊盘而言，其例如由对应的隔垫部的背离导电层4的表面(从其平坦的顶面经过倾斜的侧表面)延伸至第一电极41和第二电极42，从而与第一电极41和第二电极42连接。具体而言，焊盘例如包括间隔设置的第一焊盘体61和第二焊盘体62，第一焊盘体61例如与第一电极41连接，第二焊盘体62例如与第二电极42连接。
如图1所示，黑矩阵7例如为遮光材质，且例如设于基部302，且凸出部301未被黑矩阵7遮蔽，由此凸出部301例如凸出为呈从黑矩阵7暴露。举例而言，黑矩阵7例如包括多个遮光单元，多个遮光单元例如一一对应的设于多个基部302(更具体地，每个遮光单元在驱动器件层2上的正投影例如与相应的基部302在驱动器件层2上的正投影至少部分重叠)，通过遮光单元例如将驱动背板划分出多个像素区域，每个像素区域均具有一个焊盘(例如图示的仅一个焊盘)，每个焊盘上均例如设置(例如一个或多个)发光器件。
如图1所示，隔垫层5凸出超出黑矩阵7的高度h不小于1μm，即h≥1μm，例如h例如为1.7μm等。导电层4与基部302的底部之间的距离(即导电层4的朝向衬底基板的下表面与驱动器件层2的背离衬底基板的上表面之间的距离)例如为1μm，当然，也替代地例如更大或更小，黑矩阵7的厚度例如为1μm，也以大于或小于1μm。举例而言，导电层4与基部302的底部之间的距离和黑矩阵7的厚度相同，且均为1μm。
如图1所示，本公开实施方式的驱动背板还例如包括绝缘层8，绝缘层8例如设于基部302的背离衬底基板的表面，并延伸至导电层4，黑矩阵7例如设于绝缘层8的背离平坦化层3的表面。绝缘层8延伸至导电层4的部分覆盖导电层4的部分区域，绑定层6覆盖绝缘层8的与导电层4对应的区域(即，绝缘层8的与导电层4叠置的区域)，即导电层4未被绝缘层8覆盖的部分(也就是，导电层4的从绝缘层8暴露的部分)例如被绑定层6覆盖，以便与绑定层6与导电层4连接。
本公开实施方式提供一种驱动背板的制造方法，如图2所示，该制造方法例如包括：
步骤S110、在衬底基板上形成驱动器件层；
步骤S120、在所述驱动器件层的背离所述衬底基板的表面形成平坦化层；
步骤S130、在所述平坦化层的背离所述驱动器件层的表面形成导电层，且所述导 电层与所述驱动器件层连接；
步骤S140、对所述导电材料层刻蚀，以形成导电层的图案；
步骤S150、对所述平坦化层未被所述导电层覆盖的区域进行刻蚀，以形成凸出部和基部，所述导电层位于所述凸出部的背离所述驱动器件层的表面；
步骤S160、在所述导电层的背离所述平坦化层的表面形成隔垫层，且所述隔垫层形成为延伸到平坦化层内的一部分厚度内(例如延伸进入平坦化层的凸出部中所形成的下凹的凹槽内)；
步骤S170、在所述隔垫层的背离所述导电层的表面形成绑定层，所述绑定层与所述导电层连接，所述绑定层用于在其上设置发光器件。
并且，所述方法例如还包括：步骤S180、在所述基部上形成黑矩阵，所述凸出部凸出于所述黑矩阵。
下面对本公开实施方式的制造方法的各步骤进行详细说明：
在步骤S110中，在衬底基板上形成驱动器件层。
如图3所示，驱动器件层2例如包括缓冲层21、有源层22、第一栅绝缘层23、栅极24、第二栅绝缘层25、层间介质层26和源漏极27，举例而言，步骤S110例如包括：
步骤S1110、在衬底基板1上形成缓冲层21。
步骤S1120、在缓冲层21的背离衬底基板1的表面形成有源层22。
步骤S1130、形成覆盖有源层22、和缓冲层21的未被有源层22覆盖的区域的第一栅绝缘层23。
步骤S1140、在第一栅绝缘层23的背离缓冲层21的表面形成栅极24，且更具体地，例如，栅极24在缓冲层上的正投影被有源层22所覆盖。
步骤S1150、形成覆盖栅极24和第一栅绝缘层23的未被栅极24覆盖的区域的第二栅绝缘层25。
步骤S1160、在第二栅绝缘层25的背离栅极24的表面形成层间介质层26。
步骤S1170、形成第一过孔，第一过孔穿透第一栅绝缘层23、第二栅绝缘层25和层间介质层26以达到有源层22的背离衬底基板1的上表面，并露出有源层22。
步骤S1180、在层间介质层26的背离第二栅绝缘层25的表面形成源漏极27，源漏极27通过第一过孔与有源层22连接。
驱动器件层2详细结构可参考上述驱动背板的实施方式，在此不再赘述。
此外，步骤S110还包括步骤S1190、在第二栅绝缘层25的背离栅极24的表面形成电容电极28，电容电极28在第一栅绝缘层23上的正投影例如与栅极24重合，从而可与栅极24形成存储电容。该步骤S1190例如在步骤S1140和步骤S1150之间进行，层间介质层26例如覆盖电容电极28、和第二栅绝缘层25的未被电容电极28覆盖的区域。
在步骤S120中，在所述驱动器件层的背离所述衬底基板的表面形成平坦化层。
如图4所示，例如通过光刻或其它工艺形成平坦化层3。平坦化3具有漏极272的通孔。通过步骤S120形成的平坦化层3的背离衬底基板1的表面例如为平面。
步骤S130、在所述平坦化层的背离所述驱动器件层的表面形成导电层，且所述导电层与所述驱动器件层连接。
如图5所示，导电层4例如完整覆盖步骤S120中形成的平坦化层3，且通过贯穿平坦化层3而形成的第二过孔与漏极272连接。
步骤S140、对所述导电层刻蚀，以形成导电层的图案。
如图6所示，例如通过物理或化学刻蚀工艺对导电层4进行刻蚀，以形成导电层4的图案。通过对导电层4的刻蚀，例如使导电层4形成电极组，每个电极组例如包括两个间隔设置的电极，即第一电极41和第二电极42，所述第一电极41和所述第二电极42例如由贯穿导电层4且延伸到到平坦化层内的一部分厚度内的下凹的凹槽而彼此间隔开；电极组覆盖平坦化层3，电极组以外的区域露出平坦化层3(即，暴露出平坦化层3的凹槽)。
步骤S150、对所述平坦化层未被所述导电层覆盖的区域进行刻蚀，以形成凸出部和基部，所述导电层位于所述凸出部的背离所述驱动器件层的表面。
如图7所示，例如采用干法刻蚀对平坦化层3未被导电层4覆盖的区域进行刻蚀，刻蚀中例如采用包括氧气的气体，具体组成随工艺条件而定，在此不做特殊限定。刻蚀深度例如为
Figure PCTCN2019106183-appb-000001
其中
Figure PCTCN2019106183-appb-000002
当然，也例如通过其它方式刻蚀平坦化层3。平坦化层的未被导电层覆盖的区域形成为基部，而被导电层覆盖的区域形成为凸出部。
步骤S160、在所述导电层的背离所述平坦化层的表面形成隔垫层。
如图8所示，隔垫层5的形成方法例如参考平坦化层3，隔垫层5的具体结构例如参考驱动背板实施方式中的隔垫层5，在此不再详述。换言之，隔垫层5例如设于导电层4的背离平坦化层3的表面，但不完全覆盖电极组。且由于所述隔垫层5例如 图示般至少部分地延伸进入平坦化层内(例如延伸进入介于相邻两个凸出部301之间所形成的下凹的凹槽内，隔垫层5例如将相应电极组的第一电极41和第二电极42隔开。
步骤S170、在所述隔垫层的背离所述导电层的表面(包括倾斜的侧表面和平坦的顶面)、以及导电层4的背离平坦化层3的表面形成绑定层，所述绑定层与所述导电层连接，所述绑定层用于设置发光器件。
例如通过光刻、印刷或其它工艺在隔垫层5的背离导电层4的表面形成绑定层6，且绑定层6例如延伸至导电层4未被隔垫层5覆盖的区域，从而与导电层4连接。
步骤S180、在所述基部内形成黑矩阵，所述凸出部凸出于所述黑矩阵。
如图1所示，黑矩阵7的结构例如参考参考驱动背板实施方式中的黑矩阵7，在此不再详述。
本公开实施方式的制造方法还例如包括：
步骤S190、在所述基部内形成绝缘层，所述绝缘部向所述导电层延伸，并覆盖所述导电层的部分区域。
如图1所示，黑矩阵7例如设于绝缘层8的背离平坦化层3的表面，绑定层6例如覆盖绝缘层8与导电层4对应的区域。
本公开实施方式提供一种显示面板，如图9所示，该显示面板例如包括发光器件100和上述实施方式的驱动背板，其中：
驱动背板的结构例如参考上述驱动背板的实施方式，在此不再详述。
发光器件100例如设于绑定层6的背离导电层4的表面，举例而言，发光器件100的数量例如为多个，且一一对应的设于绑定层6的多个焊盘上，同时，各发光器件100例如通过各焊盘一一对应的与驱动器件层2的多个驱动器件连接，从而例如分别独立控制发光，以便显示图像。
本公开实施方式还提供一种电子设备，该电子设备例如包括上述实施方式的显示面板。该电子设备例如是手机、平板电脑、电子手表等具有显示面板的设备，在此不再一一列举。
本公开的驱动背板、显示面板、电子设备及驱动背板的制造方法，由于平坦化层具有凸出部和基部，黑矩阵位于基部，绑定层位于凸出部，且绑定层被隔垫层和导电层垫起，从而增大了绑定层的高度，是绑定层凸出于黑矩阵，便于将发光器件层与绑 定层连接；同时，可通过基部使平坦化层的局部厚度降低，从而减少储气量，有利于使排气量降低，保证产品质量。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (20)

  1. 一种驱动背板，包括：
    衬底基板；
    驱动器件层，设于所述衬底基板上，包括电极层；
    平坦化层，设于所述驱动器件层的背离所述衬底基板的表面，且所述平坦化层的背离所述驱动器件层的表面上设有至少一个凸出部和与所述至少一个凸出部相邻的至少一个基部，其中，在垂直于所述衬底基板所在平面的方向上，每个凸出部具备比每个基部更大厚度；
    导电层，设于每个凸出部的背离所述驱动器件层的表面，且与所述驱动器件层的电极层连接；
    隔垫层，设于所述导电层的背离所述平坦化层的表面；
    绑定层，覆盖所述隔垫层的背离所述导电层的表面以及所述导电层的背离所述平坦化层的表面，所述绑定层用于设置发光器件。
  2. 根据权利要求1所述的驱动背板，其中，所述驱动背板还包括黑矩阵，所述黑矩阵设于每个基部，相应凸出部未被所述黑矩阵遮蔽。
  3. 根据权利要求1所述的驱动背板，其中，所述隔垫层至少部分地覆盖导电层的背离平坦化层的表面，并且延伸到平坦化层的相邻的凸出部之间所形成的凹槽内。
  4. 根据权利要求2所述的驱动背板，其中，所述隔垫层凸出超出所述黑矩阵的高度不小于1μm。
  5. 根据权利要求2所述的驱动背板，其中，所述驱动背板还包括：
    绝缘层，设于所述基部的背离衬底基板的表面且延伸至所述导电层，并覆盖所述导电层的部分区域，所述黑矩阵设于所述绝缘层的背离所述平坦化层的表面。
  6. 根据权利要求5所述的驱动背板，其中，所述绑定层覆盖所述绝缘层的与导电层叠置的区域。
  7. 根据权利要求2所述的驱动背板，其中，所述导电层与所述基部的底部之间的距离和所述黑矩阵的厚度相同。
  8. 根据权利要求1所述的驱动背板，其中，所述驱动器件层还包括：
    缓冲层，设于衬底基板；
    有源层，设于所述缓冲层的背离所述衬底基板的表面；
    第一栅绝缘层，覆盖所述有源层、和所述缓冲层的未被有源层覆盖的区域；
    栅极，设于所述第一栅绝缘层的背离所述有源层的表面；
    第二栅绝缘层，覆盖所述栅极和所述第一栅绝缘层的未被栅极覆盖的区域；以及
    层间介质层，设于所述第二栅绝缘层的背离所述栅极的表面；
    其中电极层设于所述层间介质层的背离所述第二栅绝缘层的表面，且包括源极和漏极，所述源极和所述漏极分别均通过各自相应的第一过孔与所述有源层连接，所述各自相应的第一过孔延伸穿过所述层间介质层、第二栅绝缘层、第一栅绝缘层而达到有源层的背离衬底基板的表面。
  9. 根据权利要求6所述的驱动背板，其中，所述驱动器件层包括：
    电容电极，设于所述第一栅绝缘层的背离所述栅极的表面，且所述电容电极在所述第一栅绝缘层的正投影与所述栅极重合，所述层间介质层覆盖所述电容电极、和第二栅绝缘层的未被电容电极覆盖的区域，所述电容电极与所述栅极能形成存储电容。
  10. 根据权利要求2-9任一项所述的驱动背板，其中，所述至少一个凸出部包括多个凸出部，和所述至少一个基部包括多个基部；
    所述导电层包括多个电极组，各所述电极组一一对应的设于各所述凸出部的背离所述驱动器件层的表面，每个所述电极组均包括第一电极和第二电极，且第一电极通过第二过孔与漏极连接；
    所述隔垫层包括多个隔垫部，各所述隔垫部一一对应的设于各所述电极组的背离所述平坦化层的表面，每个所述隔垫部隔开对应的第一电极和第二电极；
    所述绑定层包括多个焊盘，各所述焊盘一一对应的设于各所述隔垫部的背离所述平坦化层的表面，且与对应的第一电极和第二电极连接；
    所述黑矩阵包括多个遮光单元，各所述遮光单元一一对应的设于各所述基部内。
  11. 根据权利要求10所述的驱动背板，其中，每个电极组在驱动器件层上的正投影与相应凸出部在驱动器件层上的正投影至少部分地重叠；或
    每个隔垫部在驱动器件层上的正投影与相应电极组在驱动器件层上的正投影部分地重叠；或
    每个遮光单元在驱动器件层上的正投影与相应的基部在驱动器件层上的正投影至少部分重叠。
  12. 一种驱动背板的制造方法，其中，包括：
    在衬底基板上形成驱动器件层；
    在所述驱动器件层的背离所述衬底基板的表面形成平坦化层；
    在所述平坦化层的背离所述驱动器件层的表面形成导电层，且所述导电层与所述驱动器件层中的电极层连接；
    对所述导电层刻蚀，以形成导电层的图案；
    对所述平坦化层未被所述导电层覆盖的区域进行刻蚀，以形成凸出部和基部，所述导电层位于所述凸出部的背离所述驱动器件层的表面；
    在所述导电层的背离所述平坦化层的表面形成隔垫层，且所述隔垫层形成为延伸到平坦化层内的一部分厚度内；
    在所述隔垫层的背离所述导电层的表面形成绑定层，所述绑定层与所述导电层连接，所述绑定层用于设置发光器件。
  13. 根据权利要求12所述的方法，其中，在步骤“在所述隔垫层的背离所述导电层的表面形成绑定层”之后，所述方法还包括：
    在所述基部内形成黑矩阵，所述凸出部凸出于所述黑矩阵。
  14. 根据权利要求12所述的方法，其中，在衬底基板上形成驱动器件层包括：
    在衬底基板上形成缓冲层；
    在缓冲层的背离衬底基板的表面形成有源层；
    形成覆盖有源层、和缓冲层的未被有源层覆盖的区域的第一栅绝缘层；
    在第一栅绝缘层的背离缓冲层的表面形成栅极，栅极在缓冲层上的正投影被有源层所覆盖；
    形成覆盖栅极和第一栅绝缘层的未被栅极覆盖的区域的第二栅绝缘层；
    在第二栅绝缘层的背离栅极的表面形成层间介质层；
    形成第一过孔，第一过孔穿透第一栅绝缘层、第二栅绝缘层和层间介质层以达到有源层的背离衬底基板的上表面，并露出有源层。
    在层间介质层的背离第二栅绝缘层的表面形成源漏极，源漏极通过各自相应的第一过孔与有源层连接。
  15. 根据权利要求12所述的方法，其中，在步骤“在第一栅绝缘层的背离缓冲层的表面形成栅极”之后、且在步骤“形成覆盖栅极和第一栅绝缘层的未被栅极覆盖的区域的第二栅绝缘层”之前，所述步骤“在衬底基板上形成驱动器件层”还包括：
    在第二栅绝缘层的背离栅极的表面形成电容电极，电容电极在第一栅绝缘层上的正投影与栅极重合以与栅极形成存储电容。
  16. 根据权利要求12所述的方法，其中，所述步骤“对所述导电材料层刻蚀，以形成导电层的图案”包括：
    通过对导电层的刻蚀来使导电层形成电极组，每个电极组包括间隔设置的第一电极和第二电极，所述第一电极和所述第二电极由贯穿导电层且延伸到到平坦化层内的一部分厚度内的下凹的凹槽而彼此间隔开，且第一电极通过第二过孔与漏极连接；电极组覆盖平坦化层，电极组以外的区域露出平坦化层的凹槽。
  17. 根据权利要求12所述的方法，其中，所述步骤“在所述隔垫层的背离所述导电层的表面形成绑定层，所述绑定层与所述导电层连接，所述绑定层用于设置发光器件”包括：
    通过光刻、印刷在隔垫层的背离导电层的表面形成绑定层，且绑定层延伸至导电层未被隔垫层覆盖的区域以与导电层连接。
  18. 根据权利要求12所述的方法，还包括：
    在所述基部内形成绝缘层，所述绝缘部向所述导电层延伸，并覆盖所述导电层的部分区域。
  19. 一种显示面板，其中，包括：
    权利要求1-11任一项所述的驱动背板；
    发光器件，设于所述绑定层。
  20. 一种电子设备，其中，包括权利要求19所述的显示面板。
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