WO2021031821A1 - 像素驱动电路、阵列基板和显示装置 - Google Patents

像素驱动电路、阵列基板和显示装置 Download PDF

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Publication number
WO2021031821A1
WO2021031821A1 PCT/CN2020/105843 CN2020105843W WO2021031821A1 WO 2021031821 A1 WO2021031821 A1 WO 2021031821A1 CN 2020105843 W CN2020105843 W CN 2020105843W WO 2021031821 A1 WO2021031821 A1 WO 2021031821A1
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Prior art keywords
driving circuit
transistor
layer
pixel driving
via hole
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PCT/CN2020/105843
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English (en)
French (fr)
Inventor
李盼
郝学光
许晨
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京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2021538685A priority Critical patent/JP2022544726A/ja
Priority to EP20853768.8A priority patent/EP4016518A4/en
Priority to US17/278,692 priority patent/US11386841B2/en
Publication of WO2021031821A1 publication Critical patent/WO2021031821A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel driving circuit, an array substrate and a display device.
  • some gate layer leads and some source and drain layer leads need to be connected through via holes.
  • the present disclosure provides a pixel driving circuit, an array substrate and a display device.
  • a pixel driving circuit including:
  • the lead of the gate layer is arranged on one side of the base substrate;
  • the source-drain layer leads are electrically connected to the gate layer leads; the position where the source-drain layer leads are electrically connected to the gate layer leads further includes:
  • the first interlayer dielectric layer is arranged on a side of the gate layer lead away from the base substrate, and a first via hole is formed to expose the gate layer lead;
  • the second interlayer dielectric layer is provided on the side of the first interlayer dielectric layer away from the base substrate, and is formed with a second via hole exposing the first via hole; the source and drain layer leads are provided On the side of the second interlayer dielectric layer away from the base substrate, and electrically connected to the gate layer lead through the first via hole and the second via hole.
  • the slope angle of the first via is smaller than the slope angle of the second via.
  • the slope angle of the first via is 20-45°, and/or the slope angle of the second via is 45-90°.
  • the first via hole is away from the edge of the base substrate and coincides with the edge of the second via hole close to the base substrate.
  • the orthographic projection of the second via hole close to the edge of the base substrate on the first interlayer dielectric layer surrounds the first via hole away from the The edge of the base substrate.
  • the slope angle of the first via is equal to the slope angle of the second via.
  • the slope angle of the first via is 45-90°, and/or the slope angle of the second via is 45-90°.
  • the material of the first interlayer dielectric layer or the second interlayer dielectric layer includes silicon nitride, silicon oxide, or silicon oxynitride.
  • the pixel driving circuit further includes: a transistor provided on one side of the base substrate; and the gate layer lead is electrically connected to the transistor.
  • the transistor is a driving transistor, and the gate of the transistor is electrically connected to the gate layer lead;
  • the pixel driving circuit further includes a storage capacitor, and the storage capacitor includes a first electrode plate; the first electrode plate is electrically connected to the source and drain layer leads.
  • the first electrode plate and the active layer of the driving transistor are arranged in the same layer and have the same material.
  • the storage capacitor further includes a second electrode plate, and the second electrode plate and the gate layer of the driving transistor are arranged in the same layer and have the same material.
  • the transistor is a compensation transistor, and the source of the transistor is electrically connected to the gate layer lead;
  • the pixel driving circuit further includes a storage capacitor including a second electrode plate; the second electrode plate is electrically connected to the drain of the transistor.
  • an array substrate including a plurality of pixels, each pixel including the above-mentioned pixel driving circuit, and a light-emitting element connected to the pixel driving circuit.
  • the plurality of pixels share the same base substrate.
  • the light-emitting element is an organic light-emitting diode (OLED).
  • OLED organic light-emitting diode
  • a display device including the above-mentioned array substrate and a driving circuit for driving pixels in the array substrate.
  • FIG. 1 is a schematic diagram of a cross-sectional structure of a pixel driving circuit in an embodiment of the present disclosure at a position where the source and drain layer leads are connected to the gate layer leads.
  • FIG. 2 is a schematic cross-sectional structure diagram of a first via hole and a second via hole according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic cross-sectional structure diagram of a pixel driving circuit of an embodiment of the present disclosure at a position where the source and drain layer leads are connected to the gate layer leads.
  • FIG. 4 is a schematic cross-sectional structure diagram of a first via hole and a second via hole in an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a hierarchical structure of a pixel driving circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of an active material layer pattern of a pixel driving circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a gate material layer pattern of a pixel driving circuit according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a source and drain material layer pattern of a pixel driving circuit according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of an electrode material layer pattern of a pixel driving circuit according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • first and second are only used as markers and are not limited to the number of objects.
  • some gate layer leads and some source and drain layer leads need to be connected through via holes.
  • the thickness of the interlayer insulating layer between the gate layer leads and the source and drain layer leads is relatively large and the slope angle of the via hole is relatively large, which causes the source and drain layer leads to be easily broken, which in turn reduces the yield of the display device.
  • Embodiments of the present disclosure provide a pixel driving circuit. As shown in FIGS. 1 to 6, the pixel driving circuit includes a base substrate 110, a gate layer lead 130 and a source drain layer lead 160.
  • the gate layer lead 130 is provided on one side of the base substrate 110; the source and drain layer leads 160 are electrically connected to the gate layer lead 130.
  • the position A where the source-drain layer lead 160 and the gate layer lead 130 are electrically connected also includes:
  • the first interlayer dielectric layer 140 is disposed on a side of the gate layer lead 130 away from the base substrate 110, and a first via 141 exposing the gate layer lead 130 is formed.
  • the second interlayer dielectric layer 150 is disposed on the side of the first interlayer dielectric layer 140 away from the base substrate 110, and is formed with a second via 151 exposing the first via 141; the source and drain layer leads 160 are disposed on the first via
  • the second interlayer dielectric layer 150 is away from the side of the base substrate 110 and is electrically connected to the gate layer lead 130 through the first via 141 and the second via 151.
  • two vias communicating with each other are provided between the source and drain layer leads 160 and the gate layer leads 130 to connect the source and drain layer leads 160 and the gate layer leads 130, which reduces
  • the depth of a single via avoids the defect that the depth of a single via is too large. For example, it is possible to avoid the problem of breakage of the source and drain layer leads 160 when the depth of a single via is too large and the slope angle is too large, and the yield rate of the pixel driving circuit can be improved.
  • the first interlayer dielectric layer 140 and the second interlayer dielectric layer 150 may be provided between the source and drain layer leads 160 and the gate layer leads 130, and the materials of the two may be the same or different.
  • the material of the first interlayer dielectric layer 140 may include silicon nitride, silicon oxide, or silicon oxynitride.
  • the material of the first interlayer dielectric layer 140 may include silicon nitride, silicon oxide, or silicon oxynitride.
  • the size of the first via 141 near the edge of the base substrate 110 is smaller than that of the first via 141 away from the substrate.
  • the size of the edge of the substrate 110 makes the first via hole 141 have a certain slope angle.
  • the slope angle ⁇ of the first via hole 141 may be the angle between the sidewall of the first via hole 141 and the plane where the base substrate 110 is located. That is, when the sidewall of the first via 141 is perpendicular to the plane of the base substrate 110, the slope angle ⁇ of the first via 141 is 90°.
  • the size of the second via 151 near the edge of the base substrate 110 is smaller than the second via 151
  • the size of the edge away from the base substrate 110 makes the second via hole 151 have a certain slope angle.
  • the slope angle ⁇ of the second via hole 151 may be the angle between the sidewall of the second via hole 151 and the plane where the base substrate 110 is located. That is, when the sidewall of the second via 151 is perpendicular to the plane where the base substrate 110 is located, the slope angle ⁇ of the second via 151 is 90°.
  • the slope angle ⁇ of the first via 141 is smaller than the slope angle ⁇ of the second via 151.
  • the slope angle ⁇ of the first via 141 can be prevented from being too large, thereby avoiding the problem of excessive depth and too large slope angle of the first via 141, thereby avoiding the source and drain layer leads 160 in the first via. 141 There was a fracture problem.
  • the slope angle ⁇ of the second via hole 151 is greater than the slope angle ⁇ of the first via hole 141, which avoids the problem that the slope angle ⁇ of the second via hole 151 is too small and the size of the second via hole 151 is too large. .
  • the problem that the size of the second via 151 on the surface of the second interlayer dielectric layer 150 away from the base substrate 110 is too large is avoided, and the size of the pixel driving circuit can be made smaller, which is convenient for improving the application of the pixel driving circuit.
  • the slope angle ⁇ of the first via 141 is 20-45° to have a smaller slope angle.
  • the first via hole 141 may be formed on the first interlayer dielectric layer 140 by using a dry etching process to ensure that the slope angle ⁇ of the first via hole 141 is small.
  • the slope angle ⁇ of the second via hole 151 is 45-90° to have a larger slope angle.
  • the second via hole 151 may be formed on the second interlayer dielectric layer 150 by a wet etching process to ensure that the slope angle ⁇ of the second via hole 151 is relatively large.
  • the first interlayer dielectric layer 140 is formed by a low temperature process
  • the second interlayer dielectric layer 150 is formed by a high temperature process.
  • the density of the first interlayer dielectric layer 140 and the second interlayer dielectric layer 150 are different, and the slope angles of the formed first via hole 141 and the second via hole 151 are also different.
  • the first via hole 141 is away from the edge of the base substrate 110 and coincides with the edge of the second via hole 151 close to the base substrate 110. In this way, it can be further ensured that the second via 151 has a smaller size, thereby reducing the pixel driving circuit to have a smaller size.
  • the orthographic projection of the second via hole 151 on the first interlayer dielectric layer 140 close to the edge of the base substrate 110 is in the first via hole 141 is far away from the edge of the base substrate 110. That is, the orthographic projection of the edge of the second via 151 close to the base substrate 110 on the first interlayer dielectric layer 140 surrounds the first via 141 away from the edge of the base substrate 110. As such, the second via hole 151 exposes the first via hole 141 and the annular buffer surface 142 surrounding the first via hole 141.
  • the ring buffer surface 142 is a part of the surface of the first interlayer dielectric layer 140 away from the base substrate 110, and the outer edge of the ring buffer surface 142 is the edge of the second via 151 close to the base substrate 110.
  • the ring buffer surface The inner edge of 142 is the edge of the first via 141 away from the base substrate 110.
  • the source and drain layer leads 160 sequentially cover the surface of the second via 151, the ring buffer surface 142, the surface of the first via 141, and the exposed gate layer leads 130.
  • the source and drain layer leads 160 can cover the ring buffer surface 142, the source and drain layer leads 160 are prevented from passing through deep via holes, and the stability of the source and drain layer leads 160 can be improved, and the yield of the pixel driving circuit can be improved.
  • the yield rate of the array substrate to which the pixel driving circuit is applied is improved.
  • the slope angle ⁇ of the first via 141 is 45° to 90°.
  • the first via hole 141 may have a larger slope angle to reduce the size of the first via hole 141, that is, to reduce the size of the edge of the first via hole 141 away from the base substrate 110.
  • the size of the second via 151 can be reduced correspondingly, so as to reduce the size of the pixel driving circuit.
  • the area of the ring buffer surface 142 can be increased to further improve the buffer effect of the ring buffer surface 142, thereby further enhancing the stability of the source and drain layer leads 160 and improving the pixels.
  • the yield of the drive circuit Still alternatively, the area of the annular buffer surface 142 may be increased while reducing the size of the second via 151.
  • the slope angle ⁇ of the second via 151 is 45-90°. In this way, it is possible to ensure that the second via hole 151 has a small size, and avoid the problem that the slope angle ⁇ of the second via hole 151 is too small and the size of the second via hole 151 is too large.
  • the slope angle ⁇ of the first via 141 and the second via 151 may be the same to reduce the difficulty of preparing the first via 141 and the second via 151.
  • the first via hole 141 and the second via hole 151 can be simultaneously formed by a halftone mask.
  • the pixel driving circuit provided by the present disclosure further includes a transistor, the transistor is located on one side of the base substrate 110, and the gate layer lead 130 is electrically connected to the transistor.
  • the pixel driving circuit may include a data writing transistor 500, a storage capacitor 300, and a driving transistor 200.
  • the storage capacitor 300 includes a first electrode plate 310 and a second electrode plate 320 that are arranged oppositely.
  • the source 510 of the data writing transistor 500 is electrically connected to the data line 162
  • the drain 520 of the data writing transistor 500 is electrically connected to the first electrode plate 310 of the storage capacitor 300
  • the gate 530 of the data writing transistor 500 is electrically connected to the first electrode plate 310 of the storage capacitor 300.
  • the gate line 132 is electrically connected.
  • the gate 230 of the driving transistor 200 is electrically connected to the first electrode plate 310 of the storage capacitor 300, the source 210 of the driving transistor 200 is electrically connected to the power line 163, and the drain 220 of the driving transistor 200 is electrically connected to the pixel electrode 191.
  • the pixel driving circuit may further include a compensation transistor 400.
  • the drain 420 of the compensation transistor 400 is electrically connected to the second electrode plate 320 of the storage capacitor 300
  • the gate 430 of the compensation transistor 400 is electrically connected to the second gate line 133
  • the source 410 of the compensation transistor 400 is electrically connected to the compensation line 164. Electric connection.
  • the compensation transistor 400, the driving transistor 200, the data writing transistor 500 and the storage capacitor 300 are arranged on the same side of the base substrate 110.
  • the gate layer lead 130 is a gate layer connection line 131, and the gate layer connection line 131 is electrically connected to the gate 230 of the driving transistor 200;
  • the source-drain layer wiring 160 is a source-drain layer connection line 161, and the source-drain layer connection line 161 is electrically connected to the first electrode plate 310, the gate layer connection line 131 and the drain 520 of the data writing transistor 500.
  • the gate layer lead 130 is a compensation connection lead 134, and the compensation connection lead 134 is electrically connected to the source 410 of the compensation transistor 400; the source and drain layer lead 160 is a compensation line 164, and the compensation The line 164 is electrically connected to the compensation connecting lead 134.
  • the driving transistor 200 may include a source 210, a gate 230 and a drain 220.
  • the source 210 of the driving transistor 200 and the drain 220 of the driving transistor 200 may have the same structure. Therefore, in other cases, the connection relationship between the source 210 of the driving transistor 200 and the drain 220 of the driving transistor 200 may be interchanged.
  • the driving transistor 200 may have a first connection terminal, a second connection terminal, and a control terminal. Among them, one of the first connection terminal and the second connection terminal may be used as the source 210 of the driving transistor 200, the other may be used as the drain 220 of the driving transistor 200, and the control terminal may be the gate 230 of the driving transistor 200.
  • the driving transistor 200 may also include The active layer 240 of the driving transistor 200 on the side of the substrate 110, the active layer 240 provided on the side of the driving transistor 200 away from the base substrate 110, the gate insulating layer of the driving transistor 200, and the gate insulating layer provided on the driving transistor 200 The gate layer 231 of the driving transistor 200 on the side away from the base substrate 110 (as the gate 230 of the driving transistor 200), and the source 210 of the driving transistor 200 connected to and insulated from the active layer 240 of the driving transistor 200 And the drain 220 of the driving transistor 200.
  • the active layer 240 of the driving transistor 200 may include a channel region 241 of the driving transistor 200 and source contact regions 242 of the driving transistor 200 located on both sides of the channel region 241 of the driving transistor 200. And the drain contact area 243 of the driving transistor 200.
  • the gate insulating layer of the driving transistor 200 covers the channel region 241 of the driving transistor 200 and at least partially exposes the source contact region 242 of the driving transistor 200 and the drain contact region 243 of the driving transistor 200.
  • the first interlayer dielectric layer 140 may be disposed on a side of the gate layer 231 of the driving transistor 200 away from the base substrate 110.
  • the second interlayer dielectric layer 150 may be disposed on the side of the first interlayer dielectric layer 140 away from the base substrate 110.
  • the source 210 of the driving transistor 200 is arranged on a side of the second interlayer dielectric layer 150 away from the base substrate 110 and is connected to the source contact area 242 of the driving transistor 200 through a via hole.
  • the drain 220 of the driving transistor 200 is provided on a side of the second interlayer dielectric layer 150 away from the base substrate 110 and is connected to the drain contact area 243 of the driving transistor 200 through a via hole.
  • the pixel driving circuit of the present disclosure may include a base substrate 110, an active material layer, an insulating material layer 120, a gate material layer, a first interlayer dielectric layer 140, a second interlayer dielectric layer 150 and Source and drain material layer.
  • the active material layer is formed with the active layer 240 of the driving transistor 200.
  • the insulating material layer 120 is formed with a gate insulating layer of the driving transistor 200.
  • the gate material layer is formed with the gate layer 231 of the driving transistor 200, the gate layer connection line 131, the first gate line 132, the second gate line 133 and the compensation connection lead 134.
  • the first interlayer dielectric layer 140 is formed with a first via hole 141
  • the second interlayer dielectric layer 150 is formed with a second via hole 151.
  • the source-drain material layer is formed with the source 210 of the driving transistor 200, the drain 220 of the driving transistor 200, the source-drain layer connection line 161, the data line 162, the power line 163, and the compensation line 164.
  • the storage capacitor 300 may include a first electrode plate 310 arranged on the side of the base substrate 110, and a storage capacitor arranged on the side of the first electrode plate 310 away from the base substrate 110.
  • the dielectric layer 300 and the dielectric layer provided on the storage capacitor 300 are away from the second electrode plate 320 on the side of the base substrate 110.
  • the first electrode plate 310 may be provided in the same layer as the active layer 240 of the driving transistor 200 and may be of the same material.
  • the second electrode plate 320 may be provided in the same layer and the same material as the gate layer 231 of the driving transistor 200.
  • the dielectric layer of the storage capacitor 300 and the gate insulating layer of the driving transistor 200 may be provided in the same layer and have the same material.
  • the active material layer may also be formed with the first electrode plate 310
  • the insulating material layer 120 may also be formed with the dielectric layer of the storage capacitor 300
  • the gate material layer may also be formed with the second electrode plate 320.
  • the pixel driving circuit may also be provided with a planarization layer 180 and an electrode material layer.
  • the planarization layer 180 is provided on the side of the driving transistor 200 away from the base substrate 110, that is, the planarization layer 180 is provided on the side of the source and drain material layers away from the base substrate 110.
  • the electrode material layer is provided on the side of the planarization layer 180 away from the base substrate 110.
  • a pattern of a pixel electrode 191 is formed on the electrode material layer, and the pixel electrode 191 may be connected to the drain 220 of the driving transistor 200 through a via hole.
  • a protective layer 170 PVX
  • the compensation transistor 400 may include an active layer 440 of the compensation transistor 400 provided on the side of the base substrate 110, and the active layer 440 provided on the compensation transistor 400 away from the base substrate.
  • the active layer 440 of the compensation transistor 400 may include the channel region 441 of the compensation transistor 400, and the source contact region 442 of the compensation transistor 400 and the drain contact region 442 of the compensation transistor 400 located on both sides of the channel region 441 of the compensation transistor 400. District 443.
  • the gate insulating layer of the compensation transistor 400 covers the channel region 441 of the compensation transistor 400 and at least partially exposes the source contact region 442 of the compensation transistor 400 and the drain contact region 443 of the compensation transistor 400.
  • the source contact area 442 of the compensation transistor 400 can be used as the source 410 of the compensation transistor 400 to be electrically connected to the compensation connection lead 134, and the compensation connection lead 134 can be electrically connected to the compensation line 164 through the first via and the second via .
  • the drain contact area 443 of the compensation transistor 400 can be used as the drain 420 of the compensation transistor 400 for connecting with the second electrode plate 320 through a via hole.
  • the active material layer may also be formed with the active layer 440 of the compensation transistor 400
  • the insulating material layer 120 may also be formed with the gate 430 insulating layer of the compensation transistor 400
  • the gate material layer may also be formed with the gate of the compensation transistor 400. ⁇ 431.
  • the data writing transistor 500 may include an active layer 540 of the data writing transistor 500 provided on the side of the base substrate 110, and an active layer 540 provided on the data writing transistor 500.
  • the layer 540 is away from the gate insulating layer of the data writing transistor 500 on the side of the base substrate 110, and the gate insulating layer provided on the data writing transistor 500 is away from the gate layer of the data writing transistor 500 on the side of the base substrate 110 531 (as the gate 530 of the data writing transistor 500), and the source 510 of the data writing transistor 500 and the drain 520 of the data writing transistor 500 connected to the active layer 540 of the data writing transistor 500 and insulated from each other .
  • the active layer 540 of the data writing transistor 500 may include a channel region 541 of the data writing transistor 500 and source contacts of the data writing transistor 500 located on both sides of the channel region 541 of the data writing transistor 500 The area 542 and the drain contact area 543 of the data writing transistor 500.
  • the insulating layer of the gate 530 of the data writing transistor 500 covers the channel region 541 of the data writing transistor 500 and at least partially exposes the source contact area 542 of the data writing transistor 500 and the drain contact area of the data writing transistor 500 543.
  • the first interlayer dielectric layer 140 and the second interlayer dielectric layer 150 are disposed on a side of the gate layer 531 of the data writing transistor 500 away from the base substrate 110.
  • the source 510 of the data writing transistor 500 is disposed on a side of the second interlayer dielectric layer 150 away from the base substrate 110 and is connected to the source contact area 542 of the data writing transistor 500 through a via hole.
  • the drain 520 of the data writing transistor 500 is provided on a side of the second interlayer dielectric layer 150 away from the base substrate 110 and is connected to the drain contact area 543 of the data writing transistor 500 through a via hole.
  • the active material layer may also be formed with the active layer 540 of the data writing transistor 500, and the insulating material layer 120 may also be formed with the gate insulating layer of the data writing transistor 500.
  • the gate material layer may also be formed with the gate layer 531 of the data writing transistor 500.
  • the source-drain material layer may also be formed with the source electrode 510 of the data writing transistor 500 and the drain electrode 520 of the data writing transistor 500.
  • the embodiments of the present disclosure also provide an array substrate.
  • the array substrate includes a plurality of pixels 01, and each pixel 01 includes any one of the pixel driving circuits 011 described in the above pixel driving circuit embodiments, and The light-emitting element 012 connected to the pixel driving circuit 011.
  • the light-emitting element 012 may be an OLED.
  • each pixel 01 of the array substrate may share the same base substrate 110. Since the array substrate has any one of the pixel driving circuits described in the above-mentioned pixel driving circuit embodiments, it has the same beneficial effects, and this disclosure will not be repeated here.
  • the embodiments of the present disclosure also provide a display device.
  • the display device includes any one of the array substrates 1000 described in the above-mentioned array substrate embodiment, and a driver for driving the pixels 01 in the array substrate 1000.
  • the driving circuit may include a gate driving circuit 2000 and a source driving circuit 3000.
  • the gate driving circuit 2000 can be connected to each row of pixels 01 for providing gate driving signals for each row of pixels 01.
  • the source driving circuit 3000 is connected to each column of pixels 01 for providing data signals for each column of pixels 01.
  • the display device may be an OLED display device, an LCD or other types of display devices. Since the display device has any one of the array substrates described in the above-mentioned array substrate embodiments, it has the same beneficial effects, which will not be repeated in this disclosure.
  • the present disclosure does not limit its application to the detailed structure and arrangement of the components proposed in this specification.
  • the present disclosure can have other embodiments, and can be implemented and executed in various ways.
  • the aforementioned deformations and modifications fall within the scope of the present disclosure.
  • the present disclosure disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or obvious in the text and/or drawings. All these different combinations constitute multiple alternative aspects of the present disclosure.
  • the embodiments described in this specification illustrate exemplary ways known to implement the present disclosure, and will enable those skilled in the art to utilize the present disclosure.

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Abstract

一种像素驱动电路、阵列基板和显示装置，属于显示技术领域。该像素驱动电路包括第一层间介质层（140）和第二层间介质层（150）；第一层间介质层（140）设于栅极层引线（130）远离衬底基板（110）的一侧，且形成有暴露栅极层引线（130）的第一过孔（141）；第二层间介质层（150）设于第一层间介质层（140）远离衬底基板（110）的一侧，且形成有暴露第一过孔（141）的第二过孔（151）；源漏层引线（160）设于第二层间介质层（150）远离衬底基板（110）的一侧，且通过第一过孔（141）和第二过孔（151）与栅极层引线（130）电连接。该像素驱动电路能够提高像素驱动电路的良率。

Description

像素驱动电路、阵列基板和显示装置
本公开要求于2019年8月16日提交的申请号为201921333600.4、实用新型名称为“像素驱动电路、阵列基板和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路、阵列基板和显示装置。
背景技术
显示装置的像素驱动电路中，某些栅极层引线与某些源漏层引线需要通过过孔连接。
所述背景技术部分公开的上述信息仅用于加强对本公开的背景的理解，因此它可以包括不构成对本领域普通技术人员已知的现有技术的信息。
实用新型内容
本公开提供了一种像素驱动电路、阵列基板和显示装置。
根据本公开的一个方面，提供一种像素驱动电路，包括：
衬底基板；
栅极层引线，设于所述衬底基板的一侧；
源漏层引线，与所述栅极层引线电连接；所述源漏层引线与所述栅极层引线电连接的位置还包括：
第一层间介质层，设于所述栅极层引线远离所述衬底基板的一侧，且形成有暴露所述栅极层引线的第一过孔；
第二层间介质层，设于所述第一层间介质层远离所述衬底基板的一侧，且形成有暴露所述第一过孔的第二过孔；所述源漏层引线设于所述第二层间介质层远离所述衬底基板的一侧，且通过所述第一过孔和所述第二过孔与所述栅极层引线电连接。
在本公开的一种示例性实施例中，所述第一过孔的坡度角小于所述第二过孔的坡度角。
在本公开的一种示例性实施例中，所述第一过孔的坡度角为20～45°，和/或所述第二过孔的坡度角为45～90°。
在本公开的一种示例性实施例中，所述第一过孔远离所述衬底基板的边缘，与所述第二过孔靠近所述衬底基板的边缘重合。
在本公开的一种示例性实施例中，所述第二过孔靠近所述衬底基板的边缘在所述第一层间介质层上的正投影，包围所述第一过孔远离所述衬底基板的边缘。
在本公开的一种示例性实施例中，所述第一过孔的坡度角等于所述第二过孔的坡度角。
在本公开的一种示例性实施例中，所述第一过孔的坡度角为45～90°，和/或所述第二过孔的坡度角为45～90°。
在本公开的一种示例性实施例中，所述第一层间介质层或所述第二层间介质层的材料包括氮化硅、氧化硅或者氮氧化硅。
在本公开的一种示例性实施例中，所述像素驱动电路还包括：晶体管，设于所述衬底基板的一侧；所述栅极层引线与所述晶体管电连接。
在本公开的一种示例性实施例中，所述晶体管为驱动晶体管，且所述晶体管的栅极与所述栅极层引线电连接；
所述像素驱动电路还包括存储电容，所述存储电容包括第一电极板；所述第一电极板与所述源漏层引线电连接。
在本公开的一种示例性实施例中，所述第一电极板与所述驱动晶体管的有源层同层设置且材料相同。
在本公开的一种示例性实施例中，所述存储电容还包括第二电极板，所述第二电极板与所述驱动晶体管的栅极层同层设置且材料相同。
在本公开的一种示例性实施例中，所述晶体管为补偿晶体管，且所述晶体管的源极与所述栅极层引线电连接；
所述像素驱动电路还包括存储电容，所述存储电容包括第二电极板；所述第二电极板与所述晶体管的漏极电连接。
根据本公开的另一个方面，提供一种阵列基板，包括多个像素，每个像素 均包括上述的像素驱动电路，以及与所述像素驱动电路连接的发光元件。
在本公开的一种示例性实施例中，所述多个像素共用同一个衬底基板。
在本公开的一种示例性实施例中，所述发光元件为有机发光二极管(organic light-emitting diode，OLED)。
根据本公开的又一个方面，提供一种显示装置，包括上述的阵列基板，以及用于驱动所述阵列基板中的像素的驱动电路。
附图说明
通过参照附图详细描述其示例实施方式，本公开的上述和其它特征及优点将变得更加明显。
图1是本公开一实施方式的像素驱动电路在源漏层引线与栅极层引线连接的位置处的剖面结构示意图。
图2是本公开一实施方式的第一过孔和第二过孔的剖面结构示意图。
图3是本公开一实施方式的像素驱动电路在源漏层引线与栅极层引线连接的位置处的剖面结构示意图。
图4是本公开一实施方式的第一过孔和第二过孔的剖面结构示意图。
图5是本公开一实施方式的像素驱动电路的等效电路示意图。
图6是本公开一实施方式的像素驱动电路的层级结构示意图。
图7是本公开一实施方式的像素驱动电路的有源材料层图案示意图。
图8是本公开一实施方式的像素驱动电路的栅极材料层图案示意图。
图9是本公开一实施方式的像素驱动电路的源漏材料层图案示意图。
图10是本公开一实施方式的像素驱动电路的电极材料层图案示意图。
图11是本公开一实施方式的阵列基板的结构示意图。
图12是本公开一实施方式的显示装置的结构示意图。
图中主要元件附图标记说明如下：
110、衬底基板；120、绝缘材料层；130、栅极层引线；131、栅极层连接线；132、第一栅极线；133、第二栅极线；134、补偿连接引线；140、第一层间介质层；141、第一过孔；142、环形缓冲表面；150、第二层间介质层；151、第二过孔；160、源漏层引线；161、源漏层连接线；162、数据线；163、电源线；164、补偿线；170、保护层；180、平坦化层；191、像素电极；200、驱动 晶体管；210、驱动晶体管的源极；220、驱动晶体管的漏极；230、驱动晶体管的栅极；231、驱动晶体管的栅极层；240、驱动晶体管的有源层；241、驱动晶体管的沟道区；242、驱动晶体管的源极接触区；243、驱动晶体管的漏极接触区；300、存储电容；310、第一电极板；320、第二电极板；400、补偿晶体管；410、补偿晶体管的源极；420、补偿晶体管的漏极；430、补偿晶体管的栅极；431、补偿晶体管的栅极层；440、补偿晶体管的有源层；441、补偿晶体管的沟道区；442、补偿晶体管的源极接触区；443、补偿晶体管的漏极接触区；500、数据写入晶体管；510、数据写入晶体管的源极；520、数据写入晶体管的漏极；530、数据写入晶体管的栅极；531、数据写入晶体管的栅极层；540、数据写入晶体管的有源层；541、数据写入晶体管的沟道区；542、数据写入晶体管的源极接触区；543、数据写入晶体管的漏极接触区；01、像素；011、像素驱动电路；012、发光元件；1000、阵列基板；2000、栅极驱动电路；3000、源极驱动电路。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
显示装置的像素驱动电路中，某些栅极层引线与某些源漏层引线需要通过过孔连接。然而，栅极层引线与源漏层引线之间的层间绝缘层厚度比较大且过孔的坡度角比较大，这导致源漏层引线容易发生断裂，进而导致显示装置的良率降低。
本公开实施方式中提供一种像素驱动电路，如图1至图6所示，该像素驱动电路包括衬底基板110、栅极层引线130和源漏层引线160。
其中，栅极层引线130设于衬底基板110的一侧；源漏层引线160与栅极层引线130电连接。源漏层引线160与栅极层引线130电连接的位置A还包括：
第一层间介质层140，设于栅极层引线130远离衬底基板110的一侧，且形成有暴露栅极层引线130的第一过孔141。
第二层间介质层150，设于第一层间介质层140远离衬底基板110的一侧，且形成有暴露第一过孔141的第二过孔151；源漏层引线160设于第二层间介质层150远离衬底基板110的一侧，且通过第一过孔141和第二过孔151与栅极层引线130电连接。
在本公开的像素驱动电路中，在源漏层引线160和栅极层引线130之间设置有相互连通的两个过孔以使得源漏层引线160和栅极层引线130连接，减小了单个过孔的深度，避免了单个过孔的深度过大的缺陷。例如，可以避免单个过孔深度过大且坡度角过大时导致的源漏层引线160断裂问题，可以提高像素驱动电路的良率。
下面结合附图对本公开实施方式提供的像素驱动电路的各部件进行详细说明：
本公开提供的像素驱动电路中，第一层间介质层140和第二层间介质层150可以设于源漏层引线160和栅极层引线130之间，两者的材料可以相同或者不同。
可选的，第一层间介质层140的材料可以包含氮化硅、氧化硅或者氮氧化硅。
可选的，第一层间介质层140的材料可以包含氮化硅、氧化硅或者氮氧化硅。
如图2和图4所示，当在第一层间介质层140上开设第一过孔141时，第一过孔141靠近衬底基板110的边缘的尺寸小于第一过孔141远离衬底基板110的边缘的尺寸，使得第一过孔141具有一定的坡度角。其中，第一过孔141的坡度角α可以为第一过孔141的侧壁与衬底基板110所在平面的夹角。即，当第一过孔141的侧壁垂直于衬底基板110所在平面时，第一过孔141的坡度角α为90°。
同理，如图2和图4所示，当在第二层间介质层150上开设第二过孔151时，第二过孔151靠近衬底基板110的边缘的尺寸小于第二过孔151远离衬底 基板110的边缘的尺寸，使得第二过孔151具有一定的坡度角。其中，第二过孔151的坡度角β可以为第二过孔151的侧壁与衬底基板110所在平面的夹角。即，当第二过孔151的侧壁垂直于衬底基板110所在平面时，第二过孔151的坡度角β为90°。
在本公开的一种实施方式中，如图1和图2所示，第一过孔141的坡度角α小于第二过孔151的坡度角β。一方面，可以避免第一过孔141的坡度角α过大，进而避免了第一过孔141出现深度过大且坡度角过大的问题，进而避免了源漏层引线160在第一过孔141出现断裂的问题。另一方面，第二过孔151的坡度角β大于第一过孔141的坡度角α，避免了第二过孔151的坡度角β过小而导致第二过孔151的尺寸过大的问题。由此，避免了第二过孔151在第二层间介质层150远离衬底基板110的表面的尺寸过大的问题，可以使得像素驱动电路的尺寸更小，便于提高应用该像素驱动电路的阵列基板的分辨率(PPI)。
可选的，第一过孔141的坡度角α为20～45°，以具有较小的坡度角。可以采用干刻工艺在第一层间介质层140上形成该第一过孔141，以保证第一过孔141的坡度角α较小。
可选的，第二过孔151的坡度角β为45～90°，以具有较大的坡度角。可以采用湿刻工艺在第二层间介质层150上形成该第二过孔151，以保证第二过孔151的坡度角β较大。
可选的，第一层间介质层140采用低温工艺形成，且第二层间介质层150采用高温工艺形成。如此，第一层间介质层140和第二层间介质层150的密度不同，所形成的第一过孔141和第二过孔151的坡度角也不相同。
可选的，如图1和图2所示，第一过孔141远离衬底基板110的边缘，与第二过孔151靠近衬底基板110的边缘重合。如此，可以进一步保证第二过孔151具有较小的尺寸，进而减小像素驱动电路具有较小的尺寸。
在本公开的另一种实施方式中，如图3和图4所示，第二过孔151靠近衬底基板110的边缘在第一层间介质层140上的正投影，在第一过孔141远离衬底基板110的边缘以外。也即是，该第二过孔151靠近衬底基板110的边缘在第一层间介质层140上的正投影，包围该第一过孔141远离衬底基板110的边缘以外。如此，第二过孔151暴露了第一过孔141和围绕第一过孔141的环形缓冲表面142。其中，该环形缓冲表面142为第一层间介质层140远离衬底基板 110的表面的一部分，且环形缓冲表面142的外边缘为第二过孔151靠近衬底基板110的边缘，环形缓冲表面142的内边缘为第一过孔141远离衬底基板110的边缘。源漏层引线160依次覆盖第二过孔151的表面、环形缓冲表面142、第一过孔141的表面和暴露的栅极层引线130。由于源漏层引线160可以覆盖环形缓冲表面142，避免了源漏层引线160通过深度过大的过孔，进而可以提高源漏层引线160的稳定性，提高该像素驱动电路的良率，进而提高应用该像素驱动电路的阵列基板的良率。
可选地，第一过孔141的坡度角α为45～90°。如此，第一过孔141可以具有较大的坡度角，以减小第一过孔141的尺寸，即减小第一过孔141远离衬底基板110的边缘的尺寸。如此，这可以相应的减小第二过孔151的尺寸，以便减小像素驱动电路的尺寸。或者，可以在第二过孔151尺寸不变的前提下，增大环形缓冲表面142的面积，进一步提高环形缓冲表面142的缓冲效果，进而可以进一步增强源漏层引线160的稳定性，提高像素驱动电路的良率。又或者，可以在减小第二过孔151的尺寸的同时增大环形缓冲表面142的面积。
可选地，第二过孔151的坡度角β为45～90°。如此，可以保证第二过孔151具有较小的尺寸，避免第二过孔151的坡度角β过小而导致第二过孔151的尺寸过大的问题。
可选地，第一过孔141和第二过孔151的坡度角β可以相同，以降低第一过孔141和第二过孔151的制备难度。举例而言，可以通过半色调掩膜(halftone mask)同时形成第一过孔141和第二过孔151。
可选地，本公开提供的像素驱动电路还包括晶体管，该晶体管位于衬底基板110的一侧，该栅极层引线130与该晶体管电连接。
如图5和图6所示，像素驱动电路可以包括数据写入晶体管500、存储电容300和驱动晶体管200。其中，存储电容300包括相对设置的第一电极板310和第二电极板320。数据写入晶体管500的源极510与数据线162电连接，数据写入晶体管500的漏极520与存储电容300的第一电极板310电连接，数据写入晶体管500的栅极530与第一栅极线132电连接。驱动晶体管200的栅极230与存储电容300的第一电极板310电连接，驱动晶体管200的源极210与电源线163电连接，驱动晶体管200的漏极220与像素电极191电连接。
可选地，如图5和图6所示，像素驱动电路还可以包括补偿晶体管400。其 中，补偿晶体管400的漏极420与存储电容300的第二电极板320电连接，补偿晶体管400的栅极430与第二栅极线133电连接，补偿晶体管400的源极410与补偿线164电连接。其中，补偿晶体管400、驱动晶体管200、数据写入晶体管500和存储电容300设置于衬底基板110的同一侧。
在本公开的一种实施方式中，如图6至图9所示，栅极层引线130为栅极层连接线131，且栅极层连接线131与驱动晶体管200的栅极230电连接；源漏层引线160为源漏层连接线161，且源漏层连接线161与第一电极板310、栅极层连接线131和数据写入晶体管500的漏极520电连接。
在本公开的另一种实施方式中，栅极层引线130为补偿连接引线134，且补偿连接引线134与补偿晶体管400的源极410电连接；源漏层引线160为补偿线164，且补偿线164与补偿连接引线134电连接。
可选的，如图5所示，驱动晶体管200可以包括源极210、栅极230和漏极220。驱动晶体管200的源极210和驱动晶体管200的漏极220可以为相同的结构，因此，在其他情形下，驱动晶体管200的源极210和驱动晶体管200的漏极220的连接关系可以互换。换言之，驱动晶体管200可以具有第一连接端、第二连接端和控制端。其中，第一连接端和第二连接端中的一个可以作为驱动晶体管200的源极210，另一个可以作为驱动晶体管200的漏极220，控制端为驱动晶体管200的栅极230。
可选的，如图6(仅显示了有源材料层图案、栅极材料层图案、源漏材料层图案和电极材料层图案)至图9所示，驱动晶体管200还可以包括设于衬底基板110一侧的驱动晶体管200的有源层240、设于驱动晶体管200的有源层240远离衬底基板110一侧的驱动晶体管200的栅极绝缘层、设于驱动晶体管200的栅极绝缘层远离衬底基板110一侧的驱动晶体管200的栅极层231(作为驱动晶体管200的栅极230)，以及与驱动晶体管200的有源层240连接且相互绝缘的驱动晶体管200的源极210和驱动晶体管200的漏极220。
可选地，如图7所示，驱动晶体管200的有源层240可以包括驱动晶体管200的沟道区241以及位于驱动晶体管200的沟道区241两侧的驱动晶体管200的源极接触区242和驱动晶体管200的漏极接触区243。其中，驱动晶体管200的栅极绝缘层覆盖驱动晶体管200的沟道区241且至少部分暴露驱动晶体管200的源极接触区242和驱动晶体管200的漏极接触区243。
第一层间介质层140可以设置于驱动晶体管200的栅极层231远离衬底基板110的一侧。第二层间介质层150可以设置于第一层间介质层140远离衬底基板110的一侧。驱动晶体管200的源极210设于第二层间介质层150远离衬底基板110的一侧且与驱动晶体管200的源极接触区242通过过孔连接。驱动晶体管200的漏极220设于第二层间介质层150远离衬底基板110的一侧且与驱动晶体管200的漏极接触区243通过过孔连接。
换言之，本公开的像素驱动电路可以包括依次层叠设置的衬底基板110、有源材料层、绝缘材料层120、栅极材料层、第一层间介质层140、第二层间介质层150和源漏材料层。其中，有源材料层形成有驱动晶体管200的有源层240。绝缘材料层120形成有驱动晶体管200的栅极绝缘层。栅极材料层形成有驱动晶体管200的栅极层231、栅极层连接线131、第一栅极线132、第二栅极线133和补偿连接引线134。第一层间介质层140形成有第一过孔141，第二层间介质层150形成有第二过孔151。源漏材料层形成有驱动晶体管200的源极210、驱动晶体管200的漏极220、源漏层连接线161、数据线162、电源线163和补偿线164。
可选的，如图6至图8所示，存储电容300可以包括设于衬底基板110一侧的第一电极板310、设于第一电极板310远离衬底基板110一侧的存储电容300的电介质层以及设于存储电容300的电介质层远离衬底基板110一侧的第二电极板320。
可选地，如图6至图8所示，第一电极板310可以与驱动晶体管200的有源层240同层设置，且可以材料相同。第二电极板320可以与驱动晶体管200的栅极层231同层设置且材料相同。存储电容300的电介质层可以与驱动晶体管200的栅极绝缘层同层设置且材料相同。换言之，有源材料层还可以形成有第一电极板310，绝缘材料层120还可以形成有存储电容300的电介质层，栅极材料层还可以形成有第二电极板320。
可选的，如图1和图3所示，像素驱动电路还可以设置有平坦化层180和电极材料层。其中，平坦化层180设于驱动晶体管200远离衬底基板110的一侧，即平坦化层180设于源漏材料层远离衬底基板110的一侧。电极材料层设于平坦化层180远离衬底基板110一侧。如图10所示，电极材料层上形成有像素电极191的图案，且像素电极191可以通过过孔与驱动晶体管200的漏极220 连接。进一步地，在源漏材料层与平坦化层180之间，还可以设置有保护层170(PVX)。
可选的，如图6至图9所示，补偿晶体管400可以包括设于衬底基板110一侧的补偿晶体管400的有源层440、设于补偿晶体管400的有源层440远离衬底基板110一侧的补偿晶体管400的栅极绝缘层、设于补偿晶体管400的栅极绝缘层远离衬底基板110一侧的补偿晶体管400的栅极层431(作为补偿晶体管400的栅极430)。其中，补偿晶体管400的有源层440可以包括补偿晶体管400的沟道区441以及位于补偿晶体管400的沟道区441两侧的补偿晶体管400的源极接触区442和补偿晶体管400的漏极接触区443。其中，补偿晶体管400的栅极绝缘层覆盖补偿晶体管400的沟道区441且至少部分暴露补偿晶体管400的源极接触区442和补偿晶体管400的漏极接触区443。补偿晶体管400的源极接触区442可以作为补偿晶体管400的源极410，用于与补偿连接引线134电连接，补偿连接引线134可以通过第一过孔和第二过孔与补偿线164电连接。补偿晶体管400的漏极接触区443可以作为补偿晶体管400的漏极420，用于与第二电极板320通过过孔连接。
如此，有源材料层还可以形成有补偿晶体管400的有源层440，绝缘材料层120还可以形成有补偿晶体管400的栅极430绝缘层，栅极材料层还可以形成有补偿晶体管400的栅极层431。
可选的，如图6～图9所示，数据写入晶体管500可以包括设于衬底基板110一侧的数据写入晶体管500的有源层540、设于数据写入晶体管500的有源层540远离衬底基板110一侧的数据写入晶体管500的栅极绝缘层、设于数据写入晶体管500的栅极绝缘层远离衬底基板110一侧的数据写入晶体管500的栅极层531(作为数据写入晶体管500的栅极530)，以及与数据写入晶体管500的有源层540连接且相互绝缘的数据写入晶体管500的源极510和数据写入晶体管500的漏极520。
可选地，数据写入晶体管500的有源层540可以包括数据写入晶体管500的沟道区541以及位于数据写入晶体管500的沟道区541两侧的数据写入晶体管500的源极接触区542和数据写入晶体管500的漏极接触区543。其中，数据写入晶体管500的栅极530绝缘层覆盖数据写入晶体管500的沟道区541且至少部分暴露数据写入晶体管500的源极接触区542和数据写入晶体管500的漏 极接触区543。第一层间介质层140和第二层间介质层150设于数据写入晶体管500的栅极层531远离衬底基板110的一侧。数据写入晶体管500的源极510设于第二层间介质层150远离衬底基板110的一侧且与数据写入晶体管500的源极接触区542通过过孔连接。数据写入晶体管500的漏极520设于第二层间介质层150远离衬底基板110的一侧且与数据写入晶体管500的漏极接触区543通过过孔连接。
换言之，有源材料层还可以形成有数据写入晶体管500的有源层540，绝缘材料层120还可以形成有数据写入晶体管500的栅极绝缘层。栅极材料层还可以形成有数据写入晶体管500的栅极层531。源漏材料层还可以形成有数据写入晶体管500的源极510和数据写入晶体管500的漏极520。
本公开实施方式还提供一种阵列基板，如图11所示，该阵列基板包括多个像素01，每个像素01均包括上述像素驱动电路实施方式所描述的任意一种像素驱动电路011，以及与该像素驱动电路011连接的发光元件012。
可选地，该发光元件012可以为OLED。
可选地，参考图11，阵列基板的各个像素01可以共用同一衬底基板110。由于该阵列基板具有上述像素驱动电路实施方式所描述的任意一种像素驱动电路，因此具有相同的有益效果，本公开在此不再赘述。
本公开实施方式还提供一种显示装置，如图12所示，该显示装置包括上述阵列基板实施方式所描述的任意一种阵列基板1000，以及用于驱动该阵列基板1000中的像素01的驱动电路。如图12所示，该驱动电路可以包括栅极驱动电路2000，以及源极驱动电路3000。
其中，该栅极驱动电路2000可以与各行像素01连接，用于为各行像素01提供栅极驱动信号。该源极驱动电路3000与各列像素01连接，用于为各列像素01提供数据信号。
可选地，该显示装置可以为OLED显示装置、LCD或者其他类型的显示装置。由于该显示装置具有上述阵列基板实施方式所描述的任意一种阵列基板，因此具有相同的有益效果，本公开在此不再赘述。
应当理解的是，在本文中提及的“和/或”，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
相应可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置方式。本公开能够具有其他实施方式，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本公开的范围内。应可理解的是，本说明书公开和限定的本公开延伸到文中和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本公开的多个可替代方面。本说明书所述的实施方式说明了已知用于实现本公开的示例性方式，并且将使本领域技术人员能够利用本公开。

Claims (20)

  1. 一种像素驱动电路，包括：
    衬底基板；
    栅极层引线，设于所述衬底基板的一侧；
    第一层间介质层，设于所述栅极层引线远离所述衬底基板的一侧，且形成有暴露所述栅极层引线的第一过孔；
    第二层间介质层，设于所述第一层间介质层远离所述衬底基板的一侧，且形成有暴露所述第一过孔的第二过孔；
    以及源漏层引线，设于所述第二层间介质层远离所述衬底基板的一侧，且通过所述第一过孔和所述第二过孔与所述栅极层引线电连接。
  2. 根据权利要求1所述的像素驱动电路，其中，所述第一过孔的坡度角小于所述第二过孔的坡度角。
  3. 根据权利要求2所述的像素驱动电路，其中，所述第一过孔的坡度角为20～45°。
  4. 根据权利要求2或3所述的像素驱动电路，其中，所述第二过孔的坡度角为45～90°。
  5. 根据权利要求2至4任一项所述的像素驱动电路，其中，所述第一过孔远离所述衬底基板的边缘，与所述第二过孔靠近所述衬底基板的边缘重合。
  6. 根据权利要求1所述的像素驱动电路，其中，所述第二过孔靠近所述衬底基板的边缘在所述第一层间介质层上的正投影，包围所述第一过孔远离所述衬底基板的边缘。
  7. 根据权利要求6所述的像素驱动电路，其中，所述第一过孔的坡度角等于所述第二过孔的坡度角。
  8. 根据权利要求6或7所述的像素驱动电路，其中，所述第一过孔和所述第二过孔中至少一个过孔的坡度角为45～90°。
  9. 根据权利要求1至8任一项所述的像素驱动电路，其中，所述第一层间介质层和所述第二层间介质层中至少一个层间介质层的材料包括氮化硅、氧化硅或者氮氧化硅。
  10. 根据权利要求1至9任一项所述的像素驱动电路，其中，所述像素驱动电路还包括：晶体管，设于所述衬底基板的一侧；
    所述栅极层引线与所述晶体管电连接。
  11. 根据权利要求10所述的像素驱动电路，其中，所述晶体管为驱动晶体管，且所述晶体管的栅极与所述栅极层引线电连接。
  12. 根据权利要求11所述的像素驱动电路，其中，所述像素驱动电路还包括存储电容，所述存储电容包括第一电极板；所述第一电极板与所述源漏层引线电连接。
  13. 根据权利要求12所述的像素驱动电路，其中，所述第一电极板与所述驱动晶体管的有源层同层设置且材料相同。
  14. 根据权利要求12或13所述的像素驱动电路，其中，所述存储电容还包括第二电极板，所述第二电极板与所述驱动晶体管的栅极层同层设置且材料相同。
  15. 根据权利要求10所述的像素驱动电路，其中，所述晶体管为补偿晶体管，且所述晶体管的源极与所述栅极层引线电连接。
  16. 根据权利要求15所述的像素驱动电路，其中，所述像素驱动电路还包 括存储电容，所述存储电容包括第二电极板；所述第二电极板与所述晶体管的漏极电连接。
  17. 一种阵列基板，包括多个像素，每个所述像素均包括如权利要求1至16任一项所述的像素驱动电路，以及与所述像素驱动电路连接的发光元件。
  18. 根据权利要求17所述的阵列基板，其中，所述多个像素共用同一个衬底基板。
  19. 根据权利要求17或18所述的阵列基板，其中，所述发光元件为有机发光二极管。
  20. 一种显示装置，包括如权利要求17至19任一项所述的阵列基板，以及用于驱动所述阵列基板中的像素的驱动电路。
PCT/CN2020/105843 2019-08-16 2020-07-30 像素驱动电路、阵列基板和显示装置 WO2021031821A1 (zh)

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