WO2020228532A1 - 电子设备、显示面板、驱动背板及其制造方法 - Google Patents

电子设备、显示面板、驱动背板及其制造方法 Download PDF

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Publication number
WO2020228532A1
WO2020228532A1 PCT/CN2020/087594 CN2020087594W WO2020228532A1 WO 2020228532 A1 WO2020228532 A1 WO 2020228532A1 CN 2020087594 W CN2020087594 W CN 2020087594W WO 2020228532 A1 WO2020228532 A1 WO 2020228532A1
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Prior art keywords
layer
substrate
driving
blind hole
pad
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PCT/CN2020/087594
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English (en)
French (fr)
Inventor
李海旭
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京东方科技集团股份有限公司
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Publication of WO2020228532A1 publication Critical patent/WO2020228532A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an electronic device, a display panel, a driving backplane and a manufacturing method thereof.
  • Micro LED is a micron-level light-emitting diode, which can realize image display by driving the micro-light-emitting diodes distributed in the array on the backplane.
  • the driving backplane includes an array of driving device layers and a plurality of film layers covering the driving device layers. However, during the processing process, if the film is heated, outgas will occur. If the gas cannot be discharged in time, the film will bubble and affect the display effect.
  • the purpose of the present disclosure is to overcome the above-mentioned shortcomings of the prior art and provide an electronic device, a display panel, a driving backplane and a manufacturing method thereof, which can prevent bubbling and ensure the display effect.
  • a drive backplane including:
  • the driving layer is provided on one side of the substrate
  • a plurality of pads arranged on the surface of the flat layer away from the substrate, and connected with the driving layer;
  • the passivation layer is composed of a plurality of sub-regions, each of the sub-regions has the same shape and size, and the sub-region is larger than the pad, and each sub-region has at least One said blind hole is provided.
  • the sub-region is a square region with a side length of 200 ⁇ m;
  • the blind hole is a square hole with a side length of 7 ⁇ m or a circular hole with a diameter of 7 ⁇ m.
  • the blind hole is located outside the pad, and the distance between the blind hole and the pad is not less than 5 ⁇ m.
  • the thickness of the flat layer is greater than 1 ⁇ m; the depth of the blind hole in the flat layer is not less than 0.5 ⁇ m and not more than 1 ⁇ m.
  • the surface of the drive layer away from the substrate has a peripheral wire, and the flat layer covers the peripheral wire; at least one of the blind holes is formed on the drive layer The projection and the peripheral wire at least partially overlap.
  • a manufacturing method of a driving backplane including:
  • a plurality of hollow areas and a plurality of blind holes are formed on the passivation layer, and the hollow areas expose each of the pads one by one, and the bottom of the blind holes extends into the flat layer and covers the Drive layer.
  • the hollow area and the blind hole are formed by one patterning process.
  • the passivation layer is composed of a plurality of sub-regions, each sub-region has the same shape and size, and the sub-region is larger than the pad, and each sub-region has at least One said blind hole.
  • the sub-region is a square region with a side length of 200 ⁇ m;
  • the blind hole is a square hole with a side length of 7 ⁇ m or a circular hole with a diameter of 7 ⁇ m.
  • the blind hole is located outside the pad, and the distance between the blind hole and the pad is not less than 5 ⁇ m.
  • the surface of the drive layer away from the substrate has a peripheral wire, and the flat layer covers the peripheral wire; at least one of the blind holes is formed on the drive layer The projection and the peripheral wire at least partially overlap.
  • a display panel including the driving backplane described in any one of the above.
  • an electronic device including the display panel described in any one of the above.
  • the blind hole is provided in the passivation layer, and the bottom of the blind hole penetrates the passivation layer and extends into the flat layer, so that the blind hole can pass through
  • the gas generated during the manufacturing process of the flat layer is discharged to prevent bubbling and ensure the display effect.
  • the pad is exposed by the hollow area of the passivation layer, which is convenient for connection with the micro light emitting diode.
  • FIG. 1 is a schematic diagram of a driving backplane according to an embodiment of the disclosure.
  • FIG. 2 is a schematic diagram of the distribution of the blind holes of the driving backplane on the passivation layer according to the embodiment of the disclosure.
  • FIG. 3 is a flowchart of a manufacturing method of a driving backplane according to an embodiment of the disclosure.
  • step S110 of the manufacturing method of the present disclosure is a schematic diagram of step S110 of the manufacturing method of the present disclosure.
  • FIG. 5 is a schematic diagram of step S120 of the manufacturing method of the present disclosure.
  • FIG. 6 is a schematic diagram of step S130 of the manufacturing method of the present disclosure.
  • FIG. 7 is a schematic diagram of step S140 of the manufacturing method of the present disclosure.
  • FIG. 8 is a schematic diagram of step S1520 of the manufacturing method of the present disclosure.
  • the drive backplane includes a substrate 1, a drive layer 2, a flat layer 3, a pad 4 and a passivation layer 5, where:
  • the driving layer 2 is provided on the side of the substrate 1.
  • the flat layer 3 covers the surface of the driving layer 2 away from the substrate 1.
  • the number of the pads 4 is multiple, and each pad 4 is provided on the surface of the flat layer 3 away from the substrate 1 and connected to the driving layer 2.
  • the passivation layer 5 covers the surface of the flat layer 3 away from the substrate 1.
  • the passivation layer 5 is provided with a plurality of hollow areas 51 and a plurality of blind holes 52.
  • the hollow areas 51 correspond to the pads 4 and the blind holes 52.
  • the bottom extends into the flat layer 3 and covers the driving layer 2.
  • the blind hole 52 is provided in the passivation layer 5, and the bottom of the blind hole 52 passes through the passivation layer 5 and extends into the flat layer 3, the flat layer can be discharged through the blind hole 52.
  • the gas generated in the manufacturing process of layer 3 prevents bubbling and ensures the display effect.
  • the bonding pad 4 is exposed by the hollow area 51 to facilitate connection with the micro light emitting diode.
  • the bottom of the blind hole 52 covers the driving layer 2 to avoid exposing the driving layer 2.
  • the material of the substrate 1 may be transparent materials such as glass, PET (polyethylene terephthalate), etc., and its shape and size are not particularly limited here.
  • the drive layer 2 is provided on the side of the substrate 1.
  • a buffer layer 6 of insulating material can be provided on the substrate 1.
  • the insulating material can be silicon oxide, silicon nitride, etc., and the drive layer 2 can be It is arranged on the surface of the buffer layer 6 away from the substrate 1.
  • the driving layer 2 may include a plurality of driving devices distributed in an array, and a plurality of micro light-emitting diodes may be driven by each driving device.
  • the driving device is a thin film transistor, and the thin film transistor may be a top-gate structure or a bottom-gate structure. Make special restrictions. As shown in FIG. 1, taking the top gate structure as an example: the driving layer 2 includes an active layer 21, a gate insulating layer 22, a gate electrode 23, an interlayer insulating layer 24, a dielectric layer 25, a source electrode 26 and a drain electrode 27. ,among them:
  • the number of active layers 21 is multiple, and they are all distributed in an array on the surface of the buffer layer 6 away from the substrate 1.
  • the material of the active layer 21 can be amorphous silicon, polysilicon, etc., which are not particularly limited here, and each has
  • the source layer 21 includes a channel region and doped regions on both sides of the channel region.
  • the gate insulating layer 22 may cover the active layer 21 and the buffer layer 6, and the gate insulating layer 22 may be silicon oxide or other insulating materials.
  • the number of the gates 23 is multiple, and the arrays are distributed on the surface of the gate insulating layer 22 away from the substrate 1, and correspond to each active layer 21 directly, that is, the gates 23 are on the gate insulating layer 22.
  • the projections are located within the projections of the active layers 21 on the gate insulating layer 22 in a one-to-one correspondence.
  • the material of the interlayer insulating layer 24 can be an insulating material such as silicon oxide, which can cover each gate 23 and the gate insulating layer 22.
  • the dielectric layer 25 can be made of insulating materials such as silicon oxide and silicon nitride, and the dielectric layer 25 covers the interlayer insulating layer 24.
  • the source electrode 26 and the drain electrode 27 may be provided on the surface of the dielectric layer 25 away from the substrate 1.
  • the number of the source electrode 26 and the drain electrode 27 is multiple, and they are divided into multiple groups, each group is in a one-to-one correspondence with each active layer 21, and each group includes a source electrode 26 and a drain electrode 27, the same group
  • the source electrode 26 and the drain electrode 27 are respectively connected to the two doped regions of the opposite active layer 21 through via holes penetrating the dielectric layer 25, the interlayer insulating layer 24 and the gate insulating layer 22.
  • the driving layer 2 may further include a peripheral wire 28, which is provided on the surface of the driving layer 2 away from the substrate 1.
  • the peripheral wire 28 is provided on the surface of the dielectric layer 25 away from the substrate 1.
  • the material of the source electrode 26 and the drain electrode 27 is the same, so that the source electrode 26, the drain electrode 27 and the peripheral wire 28 are formed by one patterning process.
  • the shape and structure of the peripheral wire 28 are not particularly limited here, and it can be a signal wire or other circuit.
  • the peripheral wire 28 can be a circuit for providing signals to the source 26 and the drain 27.
  • the width of the peripheral wire 28 may be 80 ⁇ m, of course, it may also be greater than or less than 80 ⁇ m, and the extension track and length of the peripheral wire 28 are not specifically limited herein.
  • the flat layer 3 is an insulating material, which can cover the surface of the driving layer 2 away from the substrate 1, and the surface of the flat layer 3 away from the substrate 1 is a flat surface.
  • the flat layer 3 covers the dielectric layer 25, the source electrode 26, the drain electrode 27 and the peripheral wire 28.
  • the pads 4 can be used for mounting micro light emitting diodes.
  • each pad 4 and each drain 27 are arranged in a one-to-one correspondence and are connected to the corresponding drain 27 through a via hole penetrating the flat layer 3.
  • the pad 4 may be copper or other metal materials, and the pad 4 may be a single layer or a multilayer structure stacked in a direction away from the substrate, as long as it can conduct electricity, and there is no special limitation here.
  • the pad 4 can be round or square, and its diameter or side length can be 70 ⁇ m-120 um, for example, 70 ⁇ m, 100 ⁇ m, or 120 um. Of course, the pad 4 can also have other shapes or sizes.
  • the passivation layer 5 covers the surface of the flat layer 3 away from the substrate 1.
  • the passivation layer 5 is provided with a plurality of hollow areas 51 and a plurality of blind holes 52, wherein:
  • Each hollow area 51 penetrates the passivation layer 5 along the thickness direction of the passivation layer 5, and exposes each pad 4 in a one-to-one correspondence, so as to connect the micro light emitting diode to the pad 4.
  • the projections of each hollow area 51 on the flat layer 3 are located within each pad 4 in a one-to-one correspondence, so that the hollow area 51 exposes at most the entire area of the corresponding pad 4 without exposing the flat layer 3.
  • the blind hole 52 penetrates the passivation layer 5 along the thickness direction of the passivation layer 5, and the bottom of the blind hole 52 extends into the flat layer 3, so that the gas in the flat layer 3 can be discharged through the blind hole 52 to avoid bubbling.
  • the bottom of the blind hole 52 covers the driving layer 2, that is, the blind hole 52 does not penetrate the flat layer 3 to avoid exposing the driving layer 2 and prevent other film layers formed on the passivation layer 5 from contacting the driving layer 2.
  • the blind holes 52 should have a certain density, as shown in FIG. Larger than the pad 4, at least one blind hole 52 is provided in each sub-region 501. Further, the sub-region 501 is a square region with a side length of 200 ⁇ m; the blind hole 52 is a square hole with a side length of 7 ⁇ m or a circular hole with a diameter of 7 ⁇ m. As a result, at least one blind hole 52 on the passivation layer 5 can be exhausted in every 200 ⁇ m 2 range. Of course, the density of the blind holes 52 can also be larger or smaller.
  • the blind hole 52 is located outside the pad 4, that is, the blind hole 52 and the pad 4 are spaced apart on the flat layer 3, and there is no overlapping area.
  • the distance L between the blind hole 52 and the pad 4 can be made not more than 5 ⁇ m. Of course, of course, this The distance L can also be less than or greater than 5 ⁇ m.
  • the distance L between the blind hole 52 and the pad 4 is the distance between the edge of the blind hole 52 and the edge of the pad 4 closest to the two points.
  • the blind hole 52 should have a certain depth.
  • the thickness H of the flat layer 3 is greater than 1 ⁇ m, and the depth h of the blind hole 52 in the flat layer 3 is not less than 0.5 ⁇ m.
  • the depth h of the blind hole 52 in the flat layer 3 is not greater than 1 ⁇ m, so as not to penetrate the flat layer 3 and avoid exposing the driving layer 2.
  • the flat layer 3 covers the peripheral wire 28, and among the plurality of blind holes 52, the projection of at least one blind hole 52 on the drive layer 2 and the peripheral wire 28 At least part of the area overlaps, for example, the projection of at least one blind hole 52 on the driving layer 2 is located within the peripheral wire 28. In this way, it is avoided that the gas cannot be discharged in a direction close to the substrate 1 due to the shielding of the peripheral wires 28, but can be discharged in a direction away from the substrate 1.
  • the number of blind holes 52 whose projection on the drive layer 2 overlaps with at least a part of the peripheral wire 28 is multiple, and on the extension track of the peripheral wire 28, there is at least one blind hole 52 every 200 ⁇ m to Improve the exhaust effect.
  • Embodiments of the present disclosure also provide a manufacturing method of a drive backplane, which is the drive backplane of any of the above embodiments. As shown in FIG. 3, the manufacturing method includes:
  • Step S110 forming a driving layer on one side of a substrate
  • Step S120 forming a flat layer on the surface of the driving layer away from the substrate;
  • Step S130 forming a plurality of pads on the surface of the flat layer away from the substrate, and the pads are connected to the driving layer;
  • Step S140 forming a passivation layer on the surface of the flat layer away from the substrate;
  • Step S150 forming a plurality of hollow areas and a plurality of blind holes on the passivation layer, the hollow areas exposing the pads one by one, and the bottom of the blind holes extends into the flat layer and covers The driving layer.
  • the blind hole 52 is provided in the passivation layer 5, and the bottom of the blind hole 52 penetrates the passivation layer 5 and extends into the flat layer 3, the flat layer can be discharged through the blind hole 52 3
  • the gas generated during the manufacturing process prevents bubbling and ensures the display effect.
  • the bonding pad 4 is exposed by the hollow area 51 to facilitate connection with the micro light emitting diode.
  • the bottom of the blind hole 52 covers the driving layer 2 to avoid exposing the driving layer 2.
  • step S110 a driving layer is formed on one side of a substrate.
  • the material of the substrate 1 can be a transparent material such as glass, PET (polyethylene terephthalate), etc., and its shape and size are not particularly limited here.
  • the driving layer 2 is provided on the side of the substrate 1, for example, a buffer layer 6 of insulating material may be provided on the substrate 1, and the driving layer 2 may be provided on the surface of the buffer layer 6 away from the substrate 1.
  • the driving layer 2 may include a plurality of driving devices distributed in an array, and a plurality of micro light-emitting diodes may be driven by each driving device.
  • the driving device is a thin film transistor, and the thin film transistor may be a top-gate structure or a bottom-gate structure. Make special restrictions.
  • step S110 may include step S1110-step S1160, wherein:
  • Step S1110 forming an active layer on one side of the substrate.
  • the buffer layer 6 may be formed on one side of the substrate, and the buffer layer 6 may include insulating materials such as silicon nitride and silicon oxide. Then an active layer 21 is formed on the surface of the buffer layer 6 away from the substrate 1. The number of the active layer 21 is multiple, and the array is distributed on the surface of the buffer layer 6 away from the substrate 1.
  • the material of the active layer 21 can be amorphous silicon, polysilicon, etc., which are not particularly limited here, and each active layer
  • the layer 21 includes a channel region and doped regions on both sides of the channel region.
  • Step S1120 forming a gate insulating layer covering the active layer.
  • the gate insulating layer 22 may cover the active layer 21 and the buffer layer 6, and the gate insulating layer 22 may be silicon oxide or other insulating materials.
  • Step S1130 forming a gate on the surface of the gate insulating layer away from the substrate.
  • the number of the gates 23 is multiple, and the arrays are distributed on the surface of the gate insulating layer 22 away from the substrate 1, and correspond to each active layer 21 directly, that is, the gates 23 are on the gate insulating layer 22.
  • the projection is located within the projection of each active layer 21 on the gate insulating layer 22 in a one-to-one correspondence.
  • Step S1140 forming an interlayer insulating layer covering the gate and the gate insulating layer.
  • the material of the interlayer insulating layer 24 can be an insulating material such as silicon oxide, which can cover each gate 23 and the gate insulating layer 22.
  • Step S1150 forming a dielectric layer covering the interlayer insulating layer.
  • the dielectric layer 25 can be made of insulating materials such as silicon oxide and silicon nitride, and the dielectric layer 25 covers the interlayer insulating layer 24.
  • Step S1160 forming a source electrode and a drain electrode on the surface of the dielectric layer away from the substrate.
  • the source electrode 26 and the drain electrode 27 may be provided on the surface of the dielectric layer 25 away from the substrate 1.
  • the number of the source electrode 26 and the drain electrode 27 is multiple, and they are divided into multiple groups, each group is in a one-to-one correspondence with each active layer 21, and each group includes a source electrode 26 and a drain electrode 27, the same group
  • the source electrode 26 and the drain electrode 27 are respectively connected to the two doped regions of the opposite active layer 21 through via holes penetrating the dielectric layer 25, the interlayer insulating layer 24 and the gate insulating layer 22.
  • step S1160 further includes: forming a peripheral wire on the surface of the dielectric layer away from the substrate.
  • the peripheral wire 28 is provided on the surface of the driving layer 2 away from the substrate 1.
  • the peripheral wire 28 is provided on the surface of the dielectric layer 25 away from the substrate 1, and is connected to the material of the source 26 and the drain 27.
  • the shape and structure of the peripheral wire 28 are not particularly limited here, and it may be a signal wire or other circuit.
  • the width of the peripheral wire 28 may be 80 ⁇ m, of course, it may also be greater than or less than 80 ⁇ m, and the extension track and length of the peripheral wire 28 are not specifically limited herein.
  • step S120 a flat layer is formed on the surface of the driving layer away from the substrate.
  • the flat layer 3 is made of an insulating material, which can cover the surface of the driving layer 2 away from the substrate 1, and the surface of the flat layer 3 away from the substrate 1 is a flat surface.
  • the flat layer 3 covers the dielectric layer 25, the source electrode 26, the drain electrode 27 and the peripheral wire 28.
  • Step S130 forming a plurality of pads on the surface of the flat layer away from the substrate, and the pads are connected to the driving layer.
  • the bonding pads 4 can be used for mounting micro light-emitting diodes.
  • Each bonding pad 4 is provided on the surface of the flat layer 3 away from the substrate 1 and connected to the driving layer 2.
  • the pads 4 and the drains 27 are arranged in one-to-one correspondence and are directly opposite to each other, and are connected to the corresponding drains 27 through vias penetrating the planarization layer 3.
  • the pad 4 may be copper or other metal materials, and the pad 4 may be a single layer or a multilayer structure stacked in a direction away from the substrate, as long as it can conduct electricity, and there is no special limitation here.
  • the pad 4 can be round or square, and its diameter or side length can be 70 ⁇ m-120 um, for example, 70 ⁇ m, 100 ⁇ m, or 120 um. Of course, the pad 4 can also have other shapes or sizes.
  • step S140 a passivation layer is formed on the surface of the flat layer away from the substrate.
  • the material of the passivation layer 5 may include metal, which can be formed by passivating the metal with a passivation agent, and the passivation layer 5 covers the surface of the flat layer 3 away from the substrate 1.
  • Step S150 forming a plurality of hollow areas and a plurality of blind holes on the passivation layer, the hollow areas exposing the pads one by one, and the bottom of the blind holes extends into the flat layer and covers The driving layer.
  • Each hollow area 51 penetrates the passivation layer 5 along the thickness direction of the passivation layer 5, and exposes each pad 4 in a one-to-one correspondence, so as to connect the micro light emitting diode to the pad 4.
  • the projections of each hollow area 51 on the flat layer 3 are located within each pad 4 in a one-to-one correspondence, so that the hollow area 51 exposes at most the entire area of the corresponding pad 4 without exposing the flat layer 3.
  • the blind hole 52 penetrates the passivation layer 5 along the thickness direction of the passivation layer 5, and the bottom of the blind hole 52 extends into the flat layer 3, so that the gas in the flat layer 3 can be discharged through the blind hole 52 to avoid bubbling.
  • the bottom of the blind hole 52 covers the driving layer 2, that is, the blind hole 52 does not penetrate the flat layer 3 to avoid exposing the driving layer 2 and prevent other film layers formed on the passivation layer 5 from contacting the driving layer 2.
  • the blind holes 52 should have a certain density, as shown in FIG. Larger than the pad 4, at least one blind hole 52 is provided in each sub-region 501. Further, the sub-region 501 is a square region with a side length of 200 ⁇ m; the blind hole 52 is a square hole with a side length of 7 ⁇ m or a circular hole with a diameter of 7 ⁇ m. As a result, at least one blind hole 52 on the passivation layer 5 can be exhausted in every 200 ⁇ m 2 range. Of course, the density of the blind holes 52 can also be larger or smaller.
  • the blind hole 52 is located outside the pad 4, that is, the blind hole 52 and the pad 4 are spaced apart on the flat layer 3, and there is no overlapping area.
  • the distance L between the blind hole 52 and the pad 4 can be made not more than 5 ⁇ m. Of course, of course, this The distance L can also be less than or greater than 5 ⁇ m.
  • the distance L between the blind hole 52 and the pad 4 is the distance between the edge of the blind hole 52 and the edge of the pad 4 closest to the two points.
  • the blind hole 52 should have a certain depth.
  • the thickness H of the flat layer 3 is greater than 1 ⁇ m, and the depth h of the blind hole 52 in the flat layer 3 is not less than 0.5 ⁇ m.
  • the depth h of the blind hole 52 in the flat layer 3 is not greater than 1 ⁇ m, so as not to penetrate the flat layer 3 and avoid exposing the driving layer 2.
  • the flat layer 3 covers the peripheral wire 28, and among the plurality of blind holes 52, the projection of at least one blind hole 52 on the drive layer 2 and the peripheral wire 28 At least part of the area overlaps, for example, the projection of at least one blind hole 52 on the driving layer 2 is located within the peripheral wire 28. In this way, it is avoided that the gas cannot be discharged in a direction close to the substrate 1 due to the shielding of the peripheral wires 28, but can be discharged in a direction away from the substrate 1.
  • the number of blind holes 52 whose projection on the drive layer 2 overlaps with at least a part of the peripheral wire 28 is multiple, and on the extension track of the peripheral wire 28, there is at least one blind hole 52 every 200 ⁇ m to Improve the exhaust effect.
  • the hollow area 51 and the blind hole 52 can be formed by one patterning process.
  • the hollow area 51 and the blind hole 52 are formed on the passivation layer 5, that is, step S150 includes step S1510 to step S1530, wherein:
  • Step S1510 covering the passivation layer with a photoresist layer.
  • the material of the photoresist layer 7 can be positive or negative photoresist, which is not specifically limited here.
  • Step S1520 exposing and developing the photoresist layer.
  • each developing area is used to form hollow areas 51 and blind holes 52.
  • Step S1530 etching the developing area to form multiple hollow areas and multiple blind holes.
  • hollow area 51 and the blind hole 52 please refer to the hollow area 51 and the blind hole 52 above, which will not be repeated here.
  • the hollow area 51 and the blind hole 52 can also be formed independently.
  • the embodiments of the present disclosure provide a display panel including the driving backplane of any of the above embodiments.
  • the structure of the driving backplane and the beneficial effects of the display panel can be referred to the above driving backplane embodiments, which will not be repeated here.
  • the display panel may also include a plurality of micro light emitting diodes, each of which is connected to each bonding pad 4 in a one-to-one correspondence.
  • the embodiments of the present disclosure also provide an electronic device including the display panel of the above-mentioned embodiment.
  • the electronic device may be a device with a display panel such as a mobile phone, a tablet computer, etc., which will not be listed here.

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Abstract

本公开提供一种电子设备、显示面板、驱动背板及其制造方法，涉及显示技术领域。该驱动背板包括衬底、平坦层、焊盘和钝化层，驱动层设于衬底一侧；平坦层覆盖于驱动层远离衬底的表面；焊盘数量为多个，且设于平坦层远离衬底的表面，并与驱动层连接；钝化层覆盖于平坦层远离衬底的表面，钝化层设有多个镂空区和多个盲孔，镂空区一一对应地露出各焊盘，盲孔的底部延伸至平坦层内并覆盖驱动层。本公开的驱动背板可防止鼓泡，保证显示效果。 (图1)

Description

电子设备、显示面板、驱动背板及其制造方法 技术领域
本公开涉及显示技术领域，具体而言，涉及一种电子设备、显示面板、驱动背板及其制造方法。
背景技术
微发光二极管(Micro LED)是微米级的发光二极管，通过驱动背板驱动阵列分布的微发光二极管可实现图像显示。驱动背板包括阵列分布的驱动器件层和覆盖驱动器件层的多个膜层。但是，在加工过程中，若膜层受热，会出现放气(Outgas)现象，如果气体无法及时排出，则会使膜层鼓泡，影响显示效果。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服上述现有技术的不足，提供一种电子设备、显示面板、驱动背板及其制造方法，可防止鼓泡，保证显示效果。
根据本公开的一个方面，提供一种驱动背板，包括：
衬底；
驱动层，设于所述衬底一侧；
平坦层，覆盖于所述驱动层远离所述衬底的表面；
多个焊盘，设于所述平坦层远离所述衬底的表面，并与所述驱动层连接；
钝化层，覆盖于所述平坦层远离所述衬底的表面，所述钝化层设有多个镂空区和多个盲孔，所述镂空区一一对应地露出各所述焊盘，所述盲孔的底部延伸至所述平坦层内并覆盖所述驱动层。
在本公开的一种示例性实施例中，所述钝化层由多个子区域组成，各个所述子区域的形状和尺寸相同，且所述子区域大于所述焊盘，每个子区域内至少设有一个所述盲孔。
在本公开的一种示例性实施例中，所述子区域为边长为200μm的正方形区域；所述盲孔为边长为7μm的正方形孔或直径为7μm的圆孔。
在本公开的一种示例性实施例中，所述盲孔位于所述焊盘以外，且所述盲孔与所述焊盘的距离不小于5μm。
在本公开的一种示例性实施例中，所述平坦层的厚度大于1μm；所述盲孔在所述平坦层内的深度不小于0.5μm，且不大于1μm。
在本公开的一种示例性实施例中，所述驱动层远离所述衬底的表面具有外围导线，所述平坦层覆盖所述外围导线；至少一个所述盲孔在所述驱动层上的投影与所述外围导线至 少部分重合。
根据本公开的一个方面，提供一种驱动背板的制造方法，包括：
在一衬底一侧形成驱动层；
在所述驱动层远离所述衬底的表面形成平坦层；
在所述平坦层远离所述衬底的表面形成多个焊盘，且所述焊盘与所述驱动层连接；
在所述平坦层远离所述衬底的表面形成钝化层；
在所述钝化层上形成多个镂空区和多个盲孔，所述镂空区一一对应地露出各所述焊盘，所述盲孔的底部延伸至所述平坦层内并覆盖所述驱动层。
在本公开的一种示例性实施例中，所述镂空区和所述盲孔通过一次构图工艺形成。
在本公开的一种示例性实施例中，所述钝化层由多个子区域组成，各个子区域的形状和尺寸相同，且所述子区域大于所述焊盘，每个子区域内至少设有一个所述盲孔。
在本公开的一种示例性实施例中，所述子区域为边长为200μm的正方形区域；所述盲孔为边长为7μm的正方形孔或直径为7μm的圆孔。
在本公开的一种示例性实施例中，所述盲孔位于所述焊盘以外，且所述盲孔与所述焊盘的距离不小于5μm。
在本公开的一种示例性实施例中，所述驱动层远离所述衬底的表面具有外围导线，所述平坦层覆盖所述外围导线；至少一个所述盲孔在所述驱动层上的投影与所述外围导线至少部分重合。
根据本公开的一个方面，提供一种显示面板，包括上述任意一项所述的驱动背板。
根据本公开的一个方面，提供一种电子设备，包括上述任意一项所述的显示面板。
本公开的电子设备、显示面板、驱动背板及其制造方法，由于在钝化层设置了盲孔，且盲孔的底部穿过钝化层并延伸至平坦层内，在从而可通过盲孔排出平坦层在制造过程中产生的气体，防止鼓泡，保证显示效果。同时，焊盘被钝化层的镂空区露出，便于与微发光二极管连接。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施方式驱动背板的示意图。
图2为本公开实施方式驱动背板的盲孔在钝化层上的分布示意图。
图3为本公开实施方式驱动背板的制造方法的流程图。
图4为本公开制造方法的步骤S110的示意图。
图5为本公开制造方法的步骤S120的示意图。
图6为本公开制造方法的步骤S130的示意图。
图7为本公开制造方法的步骤S140的示意图。
图8为本公开制造方法的步骤S1520的示意图。
附图标记说明：
1、衬底；2、驱动层；21、有源层；22、栅绝缘层；23、栅极；24、层间绝缘层；25、介电层；26、源极；27、漏极；28、外围导线；3、平坦层；4、焊盘；5、钝化层；501、子区域；51、镂空区；52、盲孔；6、缓冲层；7、光刻胶层。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
本公开实施方式提供了一种驱动背板，用于驱动微发光二极管。如图1所示，该驱动背板包括衬底1、驱动层2、平坦层3、焊盘4和钝化层5，其中：
驱动层2设于衬底1一侧。平坦层3覆盖于驱动层2远离衬底1的表面。焊盘4的数量为多个，各焊盘4设于平坦层3远离衬底1的表面，并与驱动层2连接。
钝化层5覆盖于平坦层3远离衬底1的表面，钝化层5设有多个镂空区51和多个盲孔52，镂空区51一一对应地露出焊盘4，盲孔52的底部延伸至平坦层3内且覆盖驱动层2。
本公开实施方式的驱动背板，由于在钝化层5设置了盲孔52，且盲孔52的底部穿过钝化层5并延伸至平坦层3内，在从而可通过盲孔52排出平坦层3在制造过程中产生的气体，防止鼓泡，保证显示效果。同时，焊盘4被镂空区51露出，便于与微发光二极管 连接。此外，盲孔52的底部覆盖驱动层2，从而避免露出驱动层2。
下面对本公开实施方式驱动背板的各部分进行详细说明：
如图1所示，衬底1的材料可以是玻璃、PET(聚对苯二甲酸乙二酯)等透明材料，其形状和尺寸在此不做特殊限定。
如图1所示，驱动层2设于衬底1一侧，例如，可在衬底1上设置绝缘材料的缓冲层6，该绝缘材料可以是氧化硅、氮化硅等，驱动层2可设于缓冲层6远离衬底1的表面。
驱动层2可包括多个阵列分布的驱动器件，可通过各个驱动器件驱动多个微发光二极管，该驱动器件为薄膜晶体管，该薄膜晶体管可以是顶栅型结构或底栅型结构，在此不做特殊限定。如图1所示，以顶栅型结构为例：驱动层2包括有源层21、栅绝缘层22、栅极23、层间绝缘层24、介电层25、源极26和漏极27，其中：
有源层21的数量为多个，且均阵列分布于缓冲层6远离衬底1的表面，有源层21的材料可以是非晶硅、多晶硅等，在此不做特殊限定，且每个有源层21包括沟道区和沟道区两侧的掺杂区。
栅绝缘层22可覆盖有源层21和缓冲层6，栅绝缘层22可以是氧化硅或其它绝缘材料。
栅极23的数量为多个，且阵列分布于栅绝缘层22远离衬底1的表面，且一一对应地与各有源层21正对，即各栅极23在栅绝缘层22上的投影一一对应地位于各有源层21在栅绝缘层22的投影以内。
层间绝缘层24的材料可为氧化硅等绝缘材料，其可覆盖各栅极23和栅绝缘层22。
介电层25的材料可氧化硅、氮化硅等绝缘材料，且介电层25覆盖层间绝缘层24。
源极26和漏极27可设于介电层25远离衬底1的表面。源极26和漏极27的数量为多个，且分为多组，各组与各有源层21一一对应的正对，且每组包括一个源极26和一个漏极27，同一组源极26和漏极27分别通过贯穿介电层25、层间绝缘层24和栅绝缘层22的过孔与正对的有源层21的两个掺杂区连接。
此外，如图1所示，驱动层2还可包括外围导线28，外围导线28设于驱动层2远离衬底1的表面，例如，外围导线28设于介电层25远离衬底1的表面，且与源极26和漏极27的材料相同，以便通过一次构图工艺形成源极26、漏极27和外围导线28。外围导线28的形状和结构在此不做特殊限定，其可以是信号线或其它线路，例如外围导线28可以是用于向源极26和漏极27提供信号的线路。外围导线28的宽度可为80μm，当然也可大于或小于80μm，外围导线28的延伸轨迹和长度在此不做特殊限定。
如图1所示，平坦层3为绝缘材质，其可覆盖于驱动层2远离衬底1的表面，且平坦层3远离衬底1的表面为平面。举例而言，平坦层3覆盖介电层25、源极26、漏极27和外围导线28。
如图1所示，焊盘4可用于安装微发光二极管，焊盘4的数量为多个，各焊盘4设于 平坦层3远离衬底1的表面，并与驱动层2连接。举例而言，各焊盘4与各漏极27一一对应地正对设置，并通过贯穿平坦层3的过孔与对应的漏极27连接。焊盘4可为铜或其它的金属材料，且焊盘4可为单层或向远离衬底的方向依次层叠的多层结构，只要能够导电即可，在此不做特殊限定。焊盘4可为圆形或正方形，其直径或边长可为70μm-120um，例如，70μm、100μm或120um等，当然，焊盘4也可采用其它形状或尺寸。
如图1所示，钝化层5覆盖于平坦层3远离衬底1的表面，钝化层5设有多个镂空区51和多个盲孔52，其中：
各镂空区51沿钝化层5的厚度方向贯穿钝化层5，且一一对应地露出各焊盘4，以便将微发光二极管与焊盘4连接。同时，各个镂空区51在平坦层3上的投影一一对应的位于各焊盘4以内，使得镂空区51至多露出对应焊盘4的全部区域，而不会露出平坦层3。
盲孔52沿钝化层5的厚度方向贯穿钝化层5，且盲孔52的底部延伸至平坦层3内，从而可通过盲孔52排出平坦层3内的气体，避免出现鼓泡。同时，盲孔52的底部覆盖驱动层2，即盲孔52未贯穿平坦层3，避免露出驱动层2，防止在钝化层5上形成的其它膜层与驱动层2接触。
为了保证排气效果，盲孔52应具有一定的密度，如图2所示，举例而言，钝化层5可由多个子区域501组成，各个子区域501的形状和尺寸相同，且子区域501大于焊盘4，每个子区域501内至少设有一个盲孔52。进一步的，子区域501为正方形区域，其边长为200μm；盲孔52为边长为7μm的正方形孔或直径为7μm的圆孔。由此，钝化层5上的每200μm 2的范围内至少有一个盲孔52可进行排气。当然，盲孔52的密度也可更大或更小。
如图1所示，盲孔52位于焊盘4以外，即盲孔52和焊盘4在平坦层3上相互间隔，没有重合区域。为了避免在焊盘4进行焊接时，锡膏等焊料进入盲孔52，造成焊料流失，防止堵塞盲孔52，可使盲孔52与焊盘4的距离L不大于5μm，当然，当然，该距离L也可以小于或大于5μm。其中，盲孔52与焊盘4的距离L为盲孔52边缘与焊盘4边缘最近的两点间的距离。
为了保证排气效果，如图1所示，盲孔52应具有一定的深度，举例而言，平坦层3的厚度H大于1μm，盲孔52在平坦层3内的深度h不小于0.5μm，以保证排出平坦层3内的气体，同时，盲孔52在平坦层3内的深度h不大于1μm，从而不贯穿平坦层3，避免露出驱动层2。
此外，如图1所示，若驱动层2具有外围导线28，则平坦层3覆盖外围导线28，且多个盲孔52中，至少一个盲孔52在驱动层2上的投影与外围导线28的至少部分区域重合，例如，至少一个盲孔52在驱动层2上的投影位于外围导线28以内。由此，避免因外围导线28的遮挡而使气体无法向靠近衬底1的方向排出，而可向远离衬底1的方向排出。
进一步的，在驱动层2上的投影与外围导线28的至少部分区域重合的盲孔52的数量为多个，且在外围导线28的延伸轨迹上，每隔200μm至少有一个盲孔52，以提高排气效 果。
本公开实施方式还提供一种驱动背板的制造方法，该驱动背板为上述任意实施方式的驱动背板，如图3所示，该制造方法包括：
步骤S110、在一衬底一侧形成驱动层；
步骤S120、在所述驱动层远离所述衬底的表面形成平坦层；
步骤S130、在所述平坦层远离所述衬底的表面形成多个焊盘，且所述焊盘与所述驱动层连接；
步骤S140、在所述平坦层远离所述衬底的表面形成钝化层；
步骤S150、在所述钝化层上形成多个镂空区和多个盲孔，所述镂空区一一对应地露出所述焊盘，所述盲孔的底部延伸至所述平坦层内并覆盖所述驱动层。
本公开实施方式的制造方法，由于在钝化层5设置了盲孔52，且盲孔52的底部穿过钝化层5并延伸至平坦层3内，在从而可通过盲孔52排出平坦层3在制造过程中产生的气体，防止鼓泡，保证显示效果。同时，焊盘4被镂空区51露出，便于与微发光二极管连接。此外，盲孔52的底部覆盖驱动层2，从而避免露出驱动层2。
下面对本公开实施方式制造方法的各步骤进行详细说明：
在步骤S110中，在一衬底一侧形成驱动层。
如图4所示，衬底1的材料可以是玻璃、PET(聚对苯二甲酸乙二酯)等透明材料，其形状和尺寸在此不做特殊限定。驱动层2设于衬底1一侧，例如，可在衬底1上设置绝缘材质的缓冲层6，驱动层2可设于缓冲层6远离衬底1的表面。
驱动层2可包括多个阵列分布的驱动器件，可通过各个驱动器件驱动多个微发光二极管，该驱动器件为薄膜晶体管，该薄膜晶体管可以是顶栅型结构或底栅型结构，在此不做特殊限定。
如图4所示，以顶栅型结构为例：在衬底1一侧形成驱动层2，即步骤S110可包括步骤S1110-步骤S1160，其中：
步骤S1110、在衬底的一侧形成有源层。
可在衬底的一侧形成缓冲层6，缓冲层6可包括氮化硅、氧化硅等绝缘材料。再在缓冲层6远离衬底1的表面形成有源层21。有源层21的数量为多个，且阵列分布于缓冲层6远离衬底1的表面，有源层21的材料可以是非晶硅、多晶硅等，在此不做特殊限定，且每个有源层21包括沟道区和沟道区两侧的掺杂区。
步骤S1120、形成覆盖有源层的栅绝缘层。
栅绝缘层22可覆盖有源层21和缓冲层6，栅绝缘层22可以是氧化硅或其它绝缘材料。
步骤S1130、在栅绝缘层远离衬底的表面形成栅极。
栅极23的数量为多个，且阵列分布于栅绝缘层22远离衬底1的表面，且一一对应地 与各有源层21正对，即各栅极23在栅绝缘层22上的投影位于一一对应地位于各有源层21在栅绝缘层22的投影以内。
步骤S1140、形成覆盖栅极和栅绝缘层的层间绝缘层。
层间绝缘层24的材料可为氧化硅等绝缘材料，其可覆盖各栅极23和栅绝缘层22。
步骤S1150、形成覆盖层间绝缘层的介电层。
介电层25的材料可氧化硅、氮化硅等绝缘材料，且介电层25覆盖层间绝缘层24。
步骤S1160、在介电层远离衬底的表面形成源极和漏极。
源极26和漏极27可设于介电层25远离衬底1的表面。源极26和漏极27的数量为多个，且分为多组，各组与各有源层21一一对应的正对，且每组包括一个源极26和一个漏极27，同一组源极26和漏极27分别通过贯穿介电层25、层间绝缘层24和栅绝缘层22的过孔与正对的有源层21的两个掺杂区连接。
此外，步骤S1160还包括：在介电层远离衬底的表面形成外围导线。
如图4所示，外围导线28设于驱动层2远离衬底1的表面，例如，外围导线28设于介电层25远离衬底1的表面，且与源极26和漏极27的材料相同，并可通过一次构图工艺形成。外围导线28的形状和结构在此不做特殊限定，其可以是信号线或其它线路。外围导线28的宽度可为80μm，当然也可大于或小于80μm，外围导线28的延伸轨迹和长度在此不做特殊限定。
在步骤S120中，在所述驱动层远离所述衬底的表面形成平坦层。
如图5所示，平坦层3为绝缘材质，其可覆盖于驱动层2远离衬底1的表面，且平坦层3远离衬底1的表面为平面。举例而言，平坦层3覆盖介电层25、源极26、漏极27和外围导线28。
步骤S130、在所述平坦层远离所述衬底的表面形成多个焊盘，且所述焊盘与所述驱动层连接。
如图6所示，焊盘4可用于安装微发光二极管，焊盘4的数量为多个，各焊盘4设于平坦层3远离衬底1的表面，并与驱动层2连接。举例而言，各焊盘4与各漏极27一一对应地正对设置，并通过贯穿平坦层3的过孔与对应的漏极27连接。焊盘4可为铜或其它的金属材料，且焊盘4可为单层或向远离衬底的方向依次层叠的多层结构，只要能够导电即可，在此不做特殊限定。焊盘4可为圆形或正方形，其直径或边长可为70μm-120um，例如，70μm、100μm或120um等，当然，焊盘4也可采用其它形状或尺寸。
在步骤S140中，在所述平坦层远离所述衬底的表面形成钝化层。
如图7所示，钝化层5的材料可包括金属，可通过钝化剂对金属进行钝化处理而形成，且钝化层5覆盖于平坦层3远离衬底1的表面。
步骤S150、在所述钝化层上形成多个镂空区和多个盲孔，所述镂空区一一对应地露出所述焊盘，所述盲孔的底部延伸至所述平坦层内并覆盖所述驱动层。
各镂空区51沿钝化层5的厚度方向贯穿钝化层5，且一一对应地露出各焊盘4，以便将微发光二极管与焊盘4连接。同时，各个镂空区51在平坦层3上的投影一一对应的位于各焊盘4以内，使得镂空区51至多露出对应焊盘4的全部区域，而不会露出平坦层3。
盲孔52沿钝化层5的厚度方向贯穿钝化层5，且盲孔52的底部延伸至平坦层3内，从而可通过盲孔52排出平坦层3内的气体，避免出现鼓泡。同时，盲孔52的底部覆盖驱动层2，即盲孔52未贯穿平坦层3，避免露出驱动层2，防止在钝化层5上形成的其它膜层与驱动层2接触。
为了保证排气效果，盲孔52应具有一定的密度，如图2所示，举例而言，钝化层5可由多个子区域501组成，各个子区域501的形状和尺寸相同，且子区域501大于焊盘4，每个子区域501内至少设有一个盲孔52。进一步的，子区域501为正方形区域，其边长为200μm；盲孔52为边长为7μm的正方形孔或直径为7μm的圆孔。由此，钝化层5上的每200μm 2的范围内至少有一个盲孔52可进行排气。当然，盲孔52的密度也可更大或更小。
如图1所示，盲孔52位于焊盘4以外，即盲孔52和焊盘4在平坦层3上相互间隔，没有重合区域。为了避免在焊盘4进行焊接时，锡膏等焊料进入盲孔52，造成焊料流失，防止堵塞盲孔52，可使盲孔52与焊盘4的距离L不大于5μm，当然，当然，该距离L也可以小于或大于5μm。其中，盲孔52与焊盘4的距离L为盲孔52边缘与焊盘4边缘最近的两点间的距离。
为了保证排气效果，如图1所示，盲孔52应具有一定的深度，举例而言，平坦层3的厚度H大于1μm，盲孔52在平坦层3内的深度h不小于0.5μm，以保证排出平坦层3内的气体，同时，盲孔52在平坦层3内的深度h不大于1μm，从而不贯穿平坦层3，避免露出驱动层2。
此外，如图1所示，若驱动层2具有外围导线28，则平坦层3覆盖外围导线28，且多个盲孔52中，至少一个盲孔52在驱动层2上的投影与外围导线28的至少部分区域重合，例如，至少一个盲孔52在驱动层2上的投影位于外围导线28以内。由此，避免因外围导线28的遮挡而使气体无法向靠近衬底1的方向排出，而可向远离衬底1的方向排出。
进一步的，在驱动层2上的投影与外围导线28的至少部分区域重合的盲孔52的数量为多个，且在外围导线28的延伸轨迹上，每隔200μm至少有一个盲孔52，以提高排气效果。
镂空区51和盲孔52可通过一次构图工艺形成，举例而言，在钝化层5上形成镂空区51和盲孔52，即步骤S150包括步骤S1510-步骤S1530，其中：
步骤S1510、在钝化层上覆盖光刻胶层。
如图7所示，光刻胶层7的材料可以是正性或负性光刻胶，在此不做特殊限定。
步骤S1520、对光刻胶层进行曝光并显影。
如图7所示，显影后得到露出钝化层5的多个显影区，各个显影区用于形成镂空区 51和盲孔52。
步骤S1530、对显影区进行刻蚀，形成多个镂空区和多个盲孔。
镂空区51和盲孔52可参考上文中的镂空区51和盲孔52，在此不再赘述。
当然，镂空区51和盲孔52也可分别独立形成。
需要说明的是，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本公开实施方式提供一种显示面板，包括上述任意实施方式的驱动背板，该驱动背板的结构及显示面板的有益效果可参考上文驱动背板的实施方式，在此不再赘述。同时，该显示面板还可包括多个微发光二极管，各个微发光二极管一一对应的与各焊盘4连接。
本公开实施方式还提供一种电子设备，该电子设备包括上述实施方式的显示面板。该电子设备可以是手机、平板电脑等具有显示面板的设备，在此不再一一列举。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (16)

  1. 一种驱动背板，其特征在于，包括：
    衬底；
    驱动层，设于所述衬底一侧；
    平坦层，覆盖于所述驱动层远离所述衬底的表面；
    多个焊盘，设于所述平坦层远离所述衬底的表面，并与所述驱动层连接；
    钝化层，覆盖于所述平坦层远离所述衬底的表面，所述钝化层设有多个镂空区和多个盲孔，所述镂空区一一对应地露出各所述焊盘，所述盲孔的底部延伸至所述平坦层内并覆盖所述驱动层。
  2. 根据权利要求1所述的驱动背板，其特征在于，所述钝化层由多个子区域组成，各个所述子区域的形状和尺寸相同，且所述子区域大于所述焊盘，每个子区域内至少设有一个所述盲孔。
  3. 根据权利要求2所述的驱动背板，其特征在于，所述子区域为边长为200μm的正方形区域；所述盲孔为边长为7μm的正方形孔或直径为7μm的圆孔。
  4. 根据权利要求1所述的驱动背板，其特征在于，所述盲孔位于所述焊盘以外，且所述盲孔与所述焊盘的距离不小于5μm。
  5. 根据权利要求1所述的驱动背板，其特征在于，所述平坦层的厚度大于1μm；所述盲孔在所述平坦层内的深度不小于0.5μm，且不大于1μm。
  6. 根据权利要求1所述的驱动背板，其特征在于，所述驱动层远离所述衬底的表面具有外围导线，所述平坦层覆盖所述外围导线；至少一个所述盲孔在所述驱动层上的投影与所述外围导线至少部分重合。
  7. 根据权利要求1至6中任一项所述的驱动背板，其特征在于，所述驱动层包括多个阵列分布的驱动器件，所述多个驱动器件用于驱动多个微发光二极管。
  8. 一种驱动背板的制造方法，其特征在于，包括：
    在一衬底一侧形成驱动层；
    在所述驱动层远离所述衬底的表面形成平坦层；
    在所述平坦层远离所述衬底的表面形成多个焊盘，且所述焊盘与所述驱动层连接；
    在所述平坦层远离所述衬底的表面形成钝化层；
    在所述钝化层上形成多个镂空区和多个盲孔，所述镂空区一一对应地露出各所述焊盘，所述盲孔的底部延伸至所述平坦层内并覆盖所述驱动层。
  9. 根据权利要求8所述的制造方法，其特征在于，所述镂空区和所述盲孔通过一次构图工艺形成。
  10. 根据权利要求8所述的制造方法，其特征在于，所述钝化层由多个子区域 组成，各个子区域的形状和尺寸相同，且所述子区域大于所述焊盘，每个子区域内至少设有一个所述盲孔。
  11. 根据权利要求10所述的制造方法，其特征在于，所述子区域为边长为200μm的正方形区域；所述盲孔为边长为7μm的正方形孔或直径为7μm的圆孔。
  12. 根据权利要求8所述的制造方法，其特征在于，所述盲孔位于所述焊盘以外，且所述盲孔与所述焊盘的距离不小于5μm。
  13. 根据权利要求8所述的制造方法，其特征在于，所述驱动层远离所述衬底的表面具有外围导线，所述平坦层覆盖所述外围导线；至少一个所述盲孔在所述驱动层上的投影与所述外围导线至少部分重合。
  14. 根据权利要求8至13中任一项所述的制造方法，其特征在于，在一衬底一侧形成驱动层，包括：
    在所述衬底的一侧形成多个阵列分布的驱动器件，所述多个驱动器件用于驱动多个微发光二极管。
  15. 一种显示面板，其特征在于，包括权利要求1-7任一项所述的驱动背板。
  16. 一种电子设备，其特征在于，包括权利要求15所述的显示面板。
PCT/CN2020/087594 2019-05-15 2020-04-28 电子设备、显示面板、驱动背板及其制造方法 WO2020228532A1 (zh)

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