TWI602306B - 陣列基板結構與顯示裝置 - Google Patents

陣列基板結構與顯示裝置 Download PDF

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TWI602306B
TWI602306B TW105121191A TW105121191A TWI602306B TW I602306 B TWI602306 B TW I602306B TW 105121191 A TW105121191 A TW 105121191A TW 105121191 A TW105121191 A TW 105121191A TW I602306 B TWI602306 B TW I602306B
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transistor
gate
substrate
semiconductor layer
display device
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TW105121191A
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TW201803128A (zh
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Kuanfeng Lee
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Innolux Corp
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Priority to TW105121191A priority Critical patent/TWI602306B/zh
Priority to US15/629,912 priority patent/US10504982B2/en
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Publication of TWI602306B publication Critical patent/TWI602306B/zh
Publication of TW201803128A publication Critical patent/TW201803128A/zh
Priority to US16/679,702 priority patent/US10978533B2/en
Priority to US17/249,801 priority patent/US11631728B2/en
Priority to US18/188,009 priority patent/US20230230980A1/en

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    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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Description

陣列基板結構與顯示裝置
本揭露關於顯示裝置，更特別關於具有多種電晶體之顯示裝置。
驅動畫素單元的薄膜電晶體，主要分為多晶矽電晶體如低溫多晶矽電晶體(LTPS電晶體)，與金屬氧化物電晶體(比如IGZO電晶體)。前者具有高開啟電流(Ion)與高載子遷移率，而後者具有低關閉電流(Ioff)與好的均勻度。兩者各自有其優點，但無一種電晶體可同時兼具兩者之優點。
為了兼具上述兩種電晶體的優點，目前已有電路設計如2T1C或4T2C，其採用兩種以上的電晶體驅動單一畫素單元。然而在顯示器的領域中，電晶體所占的面積越大，則顯示區的相對面積越小，即降低顯示影像的解析度。換言之，目前採用多個電晶體的電路設計將導致解析度降低的問題。
綜上所述，目前亟需新的結構，以解決多個電晶體所占面積過大而降低解析度的問題。
本揭露一實施例提供之陣列基板結構，包括：基板，具有相對設置的第一表面與第二表面，且基板具有穿孔；第一薄膜電晶體，位於基板的第一表面上；以及第二薄膜電晶體，位於 基板的第二表面上，其中第一薄膜電晶體經由穿孔電性連接至第二薄膜電晶體。
本揭露一實施例提供之顯示裝置，包括：基板，具有相對設置的第一表面與第二表面，且基板具有穿孔；第一薄膜電晶體，位於基板的第一表面上；第二薄膜電晶體，位於基板的第二表面上；以及發光單元，位於基板的第二表面上，其中第一薄膜電晶體經由穿孔電性連接至第二薄膜電晶體，且發光單元電性連接至第二薄膜電晶體。
11‧‧‧資料線
13‧‧‧掃描線
15‧‧‧驅動電壓線
17‧‧‧開關電晶體
17a、19c、21b‧‧‧半導體層
17c‧‧‧通道區
17d‧‧‧汲極區
17g、19g‧‧‧閘極
17s‧‧‧源極區
19‧‧‧驅動電晶體
19a、41、47、59‧‧‧接點
19d‧‧‧汲極
19s‧‧‧源極
21‧‧‧儲存電容
23‧‧‧發光單元
23a‧‧‧電極
23c‧‧‧共同電極
25‧‧‧基板
27‧‧‧緩衝層
29、29’、31‧‧‧閘極絕緣層
31'、37、48‧‧‧絕緣層
33‧‧‧橋接線
35‧‧‧有機絕緣層
39、53‧‧‧保護層
43、43'、57‧‧‧穿孔
45‧‧‧外部電路
46、49‧‧‧觸控電極層
51‧‧‧遮光層
55‧‧‧觸控單元
第1圖係本揭露一實施例中，採用多個電晶體驅動單一發光單元之電路圖。
第2圖係本揭露一實施例中，對應第1圖之電路圖的顯示裝置其部份剖視圖。
第3A至3E圖係本揭露一實施例中，對應第1圖之電路圖的顯示裝置其製程的部份剖視圖。
第4至5圖係本揭露實施例中，對應第1圖之電路圖的顯示裝置其部份剖視圖。
第6至9圖係本揭露實施例中，觸控顯示裝置的部份剖視圖。
第1圖係本揭露一實施例中，採用多個電晶體驅動單一發光單元之電路圖。資料線11與掃描線13互相垂直以定義畫素，而畫素中具有開關電晶體17與驅動電晶體19以驅動發光單元23。在一實施例中，開關電晶體17為多晶矽電晶體(如LTPS電晶 體)，而驅動電晶體19為金屬氧化物電晶體(如IGZO電晶體)。在其他實施例中，開關電晶體17與驅動電晶體19為相同電晶體。如第1圖所示，掃描線13連接至開關電晶體17之閘極，而資料線11連接至開關電晶體17之源極。開關電晶體17之汲極連接至驅動電晶體19之閘極，而驅動電壓線15連接至驅動電晶體19之源極。驅動電晶體19之汲極連接至儲存電容21之極板與發光單元23的電極，而開關電晶體17之汲極與驅動電晶體19之閘極連接至儲存電容21的另一極板。至於發光單元23的另一電極則為共同電極。
第2圖係本揭露一實施例中，對應第1圖之電路圖的顯示裝置其部份剖視圖。如第2圖所示，在基板25上形成緩衝層27。在一實施例中，基板25可為玻璃基板，而緩衝層27可為氧化矽、氮化矽、或上述之多層結構。接著在預定形成開關電晶體17之區域形成半導體層17a，並在預定形成驅動電晶體19之區域形成半導體層21b。在一實施例中，半導體層17a與21b之材料可為低溫多晶矽。半導體層17a可分為通道區17c與通道區兩側之源極區17s與汲極區17d。接著形成閘極絕緣層29於半導體層17a與21b及緩衝層27上。在一實施例中，閘極絕緣層29為氧化矽。接著在對應通道區17c之閘極絕緣層29上形成閘極17g，並在對應半導體層21b之閘極絕緣層29上形成閘極19g。在一實施例中，閘極17g與19g之材料為金屬。至此已形成開關電晶體17之主要結構，且半導體層21b、閘極19g、與夾設於兩者之間的閘極絕緣層29組成儲存電容21。
接著形成閘極絕緣層31於閘極17g與19g及閘極絕緣層29上。在一實施例中，閘極絕緣層31可為氧化矽。接著形成半 導體層19c於對應閘極19g之閘極絕緣層31上。在一實施例中，半導體層19c為金屬氧化物半導體如IGZO。接著以微影蝕刻定義多個通孔穿過閘極絕緣層29與31，再沉積導電物於通孔中並成層於閘極絕緣層31上。之後以微影蝕刻等製程圖案化導電層，以定義經通孔連接至源極區17s之資料線11、經通孔連接至閘極17g之掃描線(未圖示)、經通孔連接汲極區17d與閘極19g之橋接線33、連接至源極19s之驅動電壓線(未圖示)與源極19s、以及連接至半導體層21b之汲極19d。源極19s與汲極19d分別接觸半導體層19c的兩側。至此已形成驅動電晶體19之主要結構。接著形成有機絕緣層35於上述導電線路/結構與閘極絕緣層31上，再以微影蝕刻定義通孔穿過有機絕緣層35。之後沉積導電物於通孔中與有機絕緣層35上，再以微影蝕刻等製程圖案化導電層，以定義經通孔連接至汲極19d之電極23a。之後形成絕緣層37於電極23a上，再微影蝕刻形成開口露出部份電極23a。在一實施例中，絕緣層37之材料為有機絕緣層材料。之後形成發光單元23於開口中的電極23a上，再形成共同電極23c於發光單元23與絕緣層37上。
在第2圖之結構中，開關電晶體17與驅動電晶體19均位於基板25的上表面上(同一側)，因此電晶體區所占面積較大而降低影像解析度。
第3A至3E圖係本揭露一實施例中，對應第1圖之電路圖的顯示裝置其製程的部份剖視圖。在下述實施例中，若無特別說明，則相同標號之單元之材料與形成方法與前述實施例之類似單元類似而不贅述。如第3A圖所示，在基板25上形成緩衝層27。接著在預定形成開關電晶體17之區域形成半導體層17a。在一實施 例中，半導體層17a之材料可為低溫多晶矽。半導體層17a可分為通道區17c與通道區兩側之源極區17s與汲極區17d。接著形成閘極絕緣層29於半導體層17a及緩衝層27上。接著在對應通道區17c之閘極絕緣層29上形成閘極17g與掃描線13。在第3A圖中，閘極17g繞線後接觸掃描線13。至此已形成開關電晶體17之主要結構。
接著形成絕緣層31'於閘極17g、掃描線13、及閘極絕緣層29上。在一實施例中，絕緣層31'與前述之閘極絕緣層31之材料類似。接著以微影蝕刻定義多個通孔穿過閘極絕緣層29與絕緣層31'，再沉積導電物於通孔中與成層於絕緣層31'上。之後以微影蝕刻等製程圖案化導電層，以定義經通孔連接至源極區17s之資料線11、以及經通孔連接至掃描線13之接點。之後形成保護層39於資料線11、接點、與絕緣層31'上。在一實施例中，保護層39之材料可為有機或無機材料，或是先沉積無機材料(氧化矽，氮化矽)後在其上方再沉積有機材料進行保護。之後微影蝕刻形成通孔穿過保護層39，將導電物填入通孔並成層於保護層39上，再微影蝕刻定義分別經通孔接觸資料線11與接點之接點41。
接著如第3B圖所示，形成穿孔43穿過緩衝層27與基板25，以露出部份汲極區17d。在另一實施例中，可先形成穿孔43穿過基板25與緩衝層27後，再形成半導體層17a與其上之層狀結構。
接著如第3C圖所示，將導電物填入穿孔43後，成層於基板25的下表面上。接著微影蝕刻導電層以定義經穿孔43連接至開關電晶體17之汲極區17d的閘極19g。之後形成閘極絕緣層29'於閘極19g與基板25上。在一實施例中，閘極絕緣層29'之材料選 擇與閘極絕緣層29類似。接著形成半導體層19c於對應閘極19g之閘極絕緣層29'上。
如第3D圖所示，接著形成源極19s與汲極19d於半導體層19c之兩側上，以及連接至源極19s之驅動電壓線(未圖示)。之後形成有機絕緣層35於閘極絕緣層29'、源極19s、汲極19d、與半導體層19c上。至此已完成驅動電晶體19的主要部份。閘極19g、汲極19d、與夾設於兩者之間的閘極絕緣層29'組成儲存電容21。接著以微影蝕刻形成通孔穿過有機絕緣層35，並將導電物填入通孔並成層於有機絕緣層35上。之後微影蝕刻導電層以定義經通孔接觸汲極19d之電極23a，再形成絕緣層37於電極23a與有機絕緣層35上，並以微影蝕刻形成開口露出部份電極23a。之後形成發光單元23於開口中的電極23a上，再形成共同電極23c於發光單元23上。在某些實施例中，發光單元23可為有機發光二極體(OLED)或無機層狀物堆疊的發光二極體(LED)。
在第3D圖中，開關電晶體17與驅動電晶體19在垂直於基板25之表面的方向上重疊，可減少電晶體所占的面積而增加影像解析度。此外，發光單元23在垂直於基板25之表面的方向上，並未與上述電晶體重疊。如此一來，當電極23a與共同電極23c採用透明導電材料如ITO，且有機絕緣層35、閘極絕緣層29'、基板25、緩衝層27、閘極絕緣層29、絕緣層31'、與保護層39之材料與厚度可透光時，上述發光單元23發出的光將可朝上與朝下穿出顯示裝置。在此實施例中，顯示裝置屬兩側發光的顯示裝置。在另一實施例中，電極23a、有機絕緣層35、閘極絕緣層29'、基板25、緩衝層27、閘極絕緣層29、絕緣層31'、與保護層39之材料與厚度 可透光，而共同電極23c屬不透光的導電材料如金屬。此時顯示裝置屬單側(上側)發光的顯示裝置。在另一實施例中，電極23a、有機絕緣層35、閘極絕緣層29'、基板25、緩衝層27、閘極絕緣層29、絕緣層31'、與保護層39中至少一者不可透光，而共同電極23c屬透光的導電材料如ITO。此時顯示裝置屬單側(下側)發光的顯示裝置。
如第3E圖所示，接著將外部電路45接合至接點41。在一實施例中，外部電路45可為印刷電路板(PCB)或積體電路(IC)。在此實施例中，外部電路45與開關電晶體17同側，而與驅動電晶體19及發光單元23不同側。
在另一實施例中，可在第一膜材上形成開關電晶體17與貫穿第一膜材之第一穿孔(填有導電材料)。此外，可在第二膜材上形成驅動電晶體19與發光單元23，以及貫穿第二膜材的第二穿孔(填有導電材料)。在一實施例中，上述膜材之材料可為高分子薄膜。接著將兩張膜材黏合，使第一穿孔對準第二穿孔，以形成第3E圖所示之結構。此種製程的優點在於開關電晶體17的製程良率，與驅動電晶體19及發光單元23的製程良率不會互相影響。
第4圖係本揭露一實施例中，對應第1圖之電路圖的顯示裝置其部份剖視圖。如第4圖所示，在基板25上形成緩衝層27。接著在預定形成開關電晶體17之區域形成半導體層17a。半導體層17a可分為通道區17c與通道區兩側之源極區17s與汲極區17d。接著形成閘極絕緣層29於半導體層17a及緩衝層27上。接著在閘極絕緣層29上形成掃描線13與閘極17g，且閘極17g對應通道區17c。至此已形成開關電晶體17之主要結構。
接著形成絕緣層31'於閘極17g、掃描線13、及閘極絕緣層29上。接著以微影蝕刻定義多個通孔穿過閘極絕緣層29與絕緣層31'，再沉積導電物於通孔中與成層於絕緣層31'上。之後以微影蝕刻等製程圖案化導電層，以定義經通孔連接至源極區17s與接觸基板25之資料線11。在第4圖中，閘極17g繞線後再接觸掃描線13。之後形成保護層39於資料線11與絕緣層31'上。
接著形成穿孔43'穿過基板25、緩衝層27、與閘極絕緣層29，以露出汲極區17d、連接至資料線11之通孔、以及掃描線13。接著將導電物填入上述穿孔並成層於基板25之下表面上，再微影蝕刻導電層以定義閘極19g與接點19a。之後形成閘極絕緣層29'於閘極19g與接點19a上。接著形成半導體層19c於對應閘極19g之閘極絕緣層29'上。
接著形成源極19s與汲極19d於半導體層19c之兩側上，以及連接至源極19s之驅動電壓線(未圖示)。之後形成有機絕緣層35於閘極絕緣層29'、源極19s、汲極19d、與半導體層19c上。至此已完成驅動電晶體19的主要部份。閘極19g、汲極19d、與夾設於兩者之間的閘極絕緣層29'組成儲存電容21。接著以微影蝕刻形成通孔穿過有機絕緣層35，以及開口穿過有機絕緣層35與閘極絕緣層29'。將導電物填入通孔，並成層於開口之側壁與有機絕緣層35上。之後微影蝕刻導電層以定義經通孔接觸汲極19d之電極23a，以及位於開口之底部與側壁及部份有機絕緣層35上(並接觸接點19a)的接點47。
之後形成絕緣層37於電極23a與有機絕緣層35上，並以微影蝕刻形成開口露出部份電極23a。接著形成發光單元23於開 口中的電極23a上，再形成共同電極23c於發光單元23上。此外，可將外部電路45接合至接點47。
在第4圖中，開關電晶體17與驅動電晶體19分別位於基板25之上表面與下表面上，且開關電晶體17與驅動電晶體19在垂直於基板25之表面的方向上重疊，以減少電晶體所占面積。在此實施例中，發光單元23在垂直於基板25之表面的方向上，未與開關電晶體17與驅動電晶體19重疊，因此其亦可為單側發光或雙側發光，端視層狀物的材料與厚度是否透光而定。第4圖與第3E圖之差異在於，第4圖之外部電路45係與驅動電晶體19及發光單元23位於同側。
第5圖與第3E圖之結構類似，差異在於第5圖之發光單元23在與基板25表面垂直之方向上，與開關電晶體17及驅動電晶體19重疊。如此一來，可進一步縮小畫素而增加影像解析度。不過在此實施例中，發光單元23必然為單側(下側)發光，因此共同電極23c必需是透明導電材料，比如ITO。
上述顯示裝置可進一步與觸控單元整合，以形成觸控顯示裝置如第6圖所示。舉例來說，可在第4圖之保護層39之上下兩側各自形成觸控電極層46與49對應發光單元23，以定義所謂的觸控單元55。在此實施例中，顯示裝置為單側(上側)顯示裝置。為避免電晶體之金屬反射環境光，可進一步形成遮光層51於保護層39上，以對應發光單元23以外的電晶體區與外部電路45。接著可形成保護層53於遮光層51、觸控電極層49、與保護層39上。在一實施例中，保護層53之材料可為有機或無機絕緣層材料。當保護層53為覆蓋保護玻璃(未圖示)時，保護層53同時包含與保護玻 璃黏貼之黏著劑。在其他實施例中，可採用單層的觸控電極層，其可位於保護層39之上表面或下表面上。
第7圖與第6圖類似，差別在於第7圖的觸控電極層46與49之位置位於基板25之兩側上。一般而言，可先形成觸控電極層46與49於基板25之上表面與下表面上，以定義觸控單元55後，再形成緩衝層27與其上之其他層狀物。在一實施例中，可在形成觸控電極層46與49之前或之後形成穿孔43，再進行後續製程。在其他實施例中，可採用單層的觸控電極層，其可位於基板25之上表面或下表面上。上述顯示裝置為單側(上側)發光的裝置。
上述顯示裝置可進一步與觸控單元整合，以形成觸控顯示裝置如第8圖所示。舉例來說，可將第2圖之發光單元23改為在與基板25之表面垂直之方向，不與開關電晶體17與驅動電晶體19重疊的位置。此外，在形成緩衝層27前，先形成遮光層51於基板25上，且遮光層51對應之後形成開關電晶體17與驅動電晶體19。穿孔57穿過閘極絕緣層31、閘極絕緣層29、緩衝層27、與基板25。絕緣層37未覆蓋對應穿孔57與資料線11之有機絕緣層35。形成開口露出穿孔57與資料線11，且形成電極23a之步驟亦形成導電物覆蓋開口之底部與側壁以定義接點59。外部電路45接合至接點59。觸控電極層46位於基板25之下表面上，且經由穿孔57與接點59電性連接至外部電路45。絕緣層48位於觸控電極層46與基板25之下表面上，觸控電極層49位於絕緣層48上，且保護層53位於觸控電極層49與絕緣層48上。在一實施例中，絕緣層48之材料為無機或有機材料。在一實施例中，保護層53之材料為有機或無機絕緣層材料。當保護層53為覆蓋保護玻璃時(未圖示)，保護層53 同時包含與保護玻璃黏貼之黏著劑。觸控電極層46、觸控電極層49、與夾設於兩者之間的絕緣層48即觸控單元55。在其他實施例中，可採用單層的觸控電極層，其可位於絕緣層48之上表面或下表面上。上述顯示裝置為單側(下側)顯示的裝置。
第9圖與第8圖類似，差別在於第9圖的觸控電極層46與49之位置位於基板25之兩側上。在其他實施例中，可採用單層的觸控電極層，其可位於基板25之上表面或下表面上。上述顯示裝置為單側(下側)顯示的裝置。
雖然本揭露已以數個實施例揭露如上，然其並非用以限定本發明，任何本技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
11‧‧‧資料線
13‧‧‧掃描線
17‧‧‧開關電晶體
17a、19c‧‧‧半導體層
17c‧‧‧通道區
17d‧‧‧汲極區
17g、19g‧‧‧閘極
17s‧‧‧源極區
19‧‧‧驅動電晶體
19a、41‧‧‧接點
19d‧‧‧汲極
19s‧‧‧源極
21‧‧‧儲存電容
23‧‧‧發光單元
23a‧‧‧電極
23c‧‧‧共同電極
25‧‧‧基板
27‧‧‧緩衝層
29、29’‧‧‧閘極絕緣層
31'、37‧‧‧絕緣層
35‧‧‧有機絕緣層
39‧‧‧保護層
43‧‧‧穿孔
45‧‧‧外部電路

Claims (16)

  1. 一種陣列基板結構，包括：一基板，具有相對設置的一第一表面與一第二表面，且該基板具有一穿孔；一第一薄膜電晶體，位於該基板的該第一表面上；以及一第二薄膜電晶體，位於該基板的該第二表面上，其中該第一薄膜電晶體經由該穿孔電性連接至該第二薄膜電晶體。
  2. 如申請專利範圍第1項所述之陣列基板結構，其中該第一薄膜電晶體係一多晶矽電晶體，包括：一多晶矽半導體層，具有一通道區夾設於一源極區與一汲極區之間；一第一閘極，對應該通道區；以及一閘極絕緣層，位於該多晶矽半導體層與該第一閘極之間，其中該多晶矽半導體層之源極區連接至一資料線，該多晶矽半導體層之汲極區連接至該穿孔，且該第一閘極連接至一掃描線。
  3. 如申請專利範圍第1項所述之陣列基板結構，其中該第二薄膜電晶體係一金屬氧化物電晶體，包括：一第二閘極；一金屬氧化物半導體層，對應該閘極； 一閘極絕緣層，位於該第二閘極與該金屬氧化物半導體層之間；以及一源極與一汲極，分別接觸該金屬氧化物半導體層的兩側，其中該源極連接至一驅動電壓線，且該第二閘極連接至該穿孔。
  4. 如申請專利範圍第1項所述之陣列基板結構，其中該第一電晶體與該第二電晶體在垂直於該第一表面之方向重疊。
  5. 如申請專利範圍第1項所述之陣列基板結構，其中該基板包括直接接觸的一第一膜材與一第二膜材，該第一電晶體位於該第一膜材上，且該第二電晶體位於該第二膜材上。
  6. 如申請專利範圍第1項所述之陣列基板結構，更包括一觸控電極層直接接觸該基板之該第一表面或該第二表面。
  7. 一種顯示裝置，包括：一基板，具有相對設置的一第一表面與一第二表面，且該基板具有一穿孔；一第一薄膜電晶體，位於該基板的該第一表面上；一第二薄膜電晶體，位於該基板的該第二表面上；以及一發光單元，位於該基板的該第二表面上，其中該第一薄膜電晶體經由該穿孔電性連接至該第二薄膜電晶體，且該發光單元電性連接至該第二薄膜電晶體。
  8. 如申請專利範圍第7項所述之顯示裝置，其中該第一薄膜電晶體係一多晶矽電晶體，包括：一多晶矽半導體層，具有一通道區夾設於一源極區與一汲極區之間；一第一閘極，對應該通道區；以及一閘極絕緣層，位於該多晶矽半導體層與該第一閘極之間，其中該多晶矽半導體層之源極區連接至一資料線，該多晶矽半導體層之汲極區連接至該穿孔，且該第一閘極連接至一掃描線。
  9. 如申請專利範圍第7項所述之顯示裝置，其中該第二薄膜電晶體係一金屬氧化物電晶體，包括：一第二閘極；一金屬氧化物半導體層，對應該閘極；一閘極絕緣層，位於該第二閘極與該金屬氧化物半導體層之間；一源極與一汲極，分別接觸該金屬氧化物半導體層的兩側，其中該源極連接至一驅動電壓線，該第二閘極連接至該穿孔，且該汲極連接至該發光單元。
  10. 如申請專利範圍第7項所述之顯示裝置，其中該第一電晶體與該第二電晶體在垂直於該第一表面之方向重疊。
  11. 如申請專利範圍第10項所述之顯示裝置，其中該發光單元與該第二電晶體在垂直於該第一表面之方向重疊。
  12. 如申請專利範圍第11項所述之顯示裝置，更包括一外部電路接合至該第一電晶體，且該外部電路位於該基板之該第一表面上。
  13. 如申請專利範圍第10項所述之顯示裝置，其中該發光單元與該第二電晶體在垂直於該第一表面之方向不重疊。
  14. 如申請專利範圍第13項所述之顯示裝置，更包括一外部電路接合至該第一電晶體，且該外部電路位於該基板之該第二表面上。
  15. 如申請專利範圍第7項所述之顯示裝置，其中該基板包括直接接觸的一第一膜材與一第二膜材，該第一電晶體位於該第一膜材上，且該第二電晶體與該發光單元位於該第二膜材上。
  16. 如申請專利範圍第7項所述之顯示裝置，更包括一觸控電極層接觸該基板之該第一表面或該第二表面。
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