WO2020038362A1 - 移位寄存器及其驱动方法、栅极驱动电路、显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路、显示装置 Download PDF

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Publication number
WO2020038362A1
WO2020038362A1 PCT/CN2019/101590 CN2019101590W WO2020038362A1 WO 2020038362 A1 WO2020038362 A1 WO 2020038362A1 CN 2019101590 W CN2019101590 W CN 2019101590W WO 2020038362 A1 WO2020038362 A1 WO 2020038362A1
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Prior art keywords
terminal
node
transistor
level
pull
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PCT/CN2019/101590
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English (en)
French (fr)
Inventor
郑灿
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京东方科技集团股份有限公司
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Priority to US16/645,697 priority Critical patent/US10964359B2/en
Publication of WO2020038362A1 publication Critical patent/WO2020038362A1/zh
Priority to US17/179,699 priority patent/US11468922B2/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1036—Read-write modes for single port memories, i.e. having either a random port or a serial port using data shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present application relates to the field of display technology, and in particular, to a shift register and a driving method thereof, a gate driving circuit, and a display device.
  • each shift register When the display device performs display, a plurality of shift registers of the gate driving unit sequentially provide scanning signals to corresponding gate lines. Among them, each shift register outputs a valid signal in the output stage of its work, and outputs an invalid signal after the output stage. It is desirable that there is no threshold loss for invalid signals output after the output phase.
  • the present disclosure proposes a shift register, a driving method thereof, a gate driving circuit, and a display device.
  • the present disclosure provides a shift register including: an input sub-circuit connected to an input terminal, a first clock terminal, and a first node of the shift register, for responding to the first in an input stage.
  • a first level signal provided by a clock terminal, electrically connecting the input terminal to the first node; a control sub-circuit, and the first node, an intermediate output terminal of the shift register, a second clock terminal,
  • the third node, the third clock terminal, the second level terminal that provides the second level signal and the first level terminal that provides the first level signal are connected to each other according to the level of the first node.
  • the phase, the output phase, and the reset phase transmit the signal provided by the second clock terminal to the intermediate output terminal, and control the third node's voltage according to the potential of the intermediate output terminal and the signal provided by the third clock terminal.
  • Potential a pull-up sub-circuit is connected to the intermediate output terminal, the final output terminal of the shift register, and the second level terminal, and is configured to respond to the potential of the intermediate output terminal in the output stage, Describe A two-level terminal is electrically connected to the final output terminal; a first voltage regulator sub-circuit is connected to a lower node connection terminal, the final output terminal and the third node are used for the output phase and the reset phase In response to the first level signal provided by the connection node of the lower node, stabilize the voltage between the final output terminal and the third node; the pull-down transistor, the gate of which is connected to the third node, and the first electrode It is connected to the first level terminal, and the second pole is connected to the final output terminal.
  • the first voltage regulator circuit reduces the potential of the third no
  • the first voltage regulator circuit is further configured to stabilize the final output in response to a first level signal provided by the connection node of the lower node in a first pull-down phase after the reset phase. The voltage between the terminal and the third node.
  • control sub-circuit includes: a second voltage regulator sub-circuit, connected to the first node, the second node, and the intermediate output terminal, and configured to connect the first node during the input stage.
  • a node is electrically connected to the second node, and stabilizes the voltage between the second node and the intermediate output terminal; a first pull-up control sub-circuit, and the intermediate output terminal, the second node, and all nodes
  • the second clock terminal is connected and is used to transmit a second level signal provided by the second clock terminal to the intermediate output terminal in response to the potential of the second node during the input phase and the reset phase.
  • the shift register further includes: a second pull-up control sub-circuit, connected to the first clock terminal, the first node, the first level terminal, and a fourth node, for In response to the potential of the first node in the output stage, transmitting a second level signal provided by the first clock terminal to the fourth node, and in response to the first pull-down stage
  • the control of the first level signal provided by the first clock end electrically connects the first level end to the fourth node
  • the third pull-up control sub-circuit is connected to the fourth node and the second power
  • the flat terminal is connected to the intermediate output terminal, and is configured to electrically connect the second level terminal to the intermediate output terminal in response to the potential of the fourth node in the first pull-down phase and the second pull-down phase
  • a two pull-down control sub-circuit is connected to the intermediate output terminal, the third node, and a fourth clock terminal, and is responsive to the potential of the fourth node and the intermediate output terminal, and is configured to provide the fourth clock terminal Signal from the second level
  • the input sub-circuit includes a first transistor, a gate of the first transistor is connected to the first clock terminal, and a first pole of the first transistor is connected to an input of the shift register. Terminals are connected, and a second pole of the first transistor is connected to the first node.
  • the second voltage regulator circuit includes a first capacitor and a second transistor, a first terminal of the first capacitor is connected to the second node, and a second terminal of the first capacitor is connected to The intermediate output terminal is connected; the gate of the second transistor is connected to the first level terminal, the first pole of the second transistor is connected to the second node, and the second electrode of the second transistor Connected to the first node.
  • the first pull-up control sub-circuit includes a third transistor, a gate of the third transistor is connected to the second node, and a first electrode of the third transistor is connected to the intermediate output.
  • the second terminal of the third transistor is connected to the second clock terminal.
  • the pull-up sub-circuit includes a fourth transistor, a gate of the fourth transistor is connected to the intermediate output terminal, and a first pole of the fourth transistor is connected to the second level terminal The second pole of the fourth transistor is connected to the final output terminal.
  • the first pull-down control sub-circuit includes a fifth transistor and a sixth transistor.
  • the gate of the fifth transistor is connected to the intermediate output terminal, the first electrode of the fifth transistor is connected to the second level terminal, and the second electrode of the fifth transistor is connected to the third node.
  • the gate of the sixth transistor is connected to the third clock terminal, the first electrode of the sixth transistor is connected to the third node, and the second electrode of the sixth transistor is connected to the first level terminal. Connected.
  • the first voltage regulator circuit includes a second capacitor and a seventh transistor, a gate of the seventh transistor is connected to the connection node of the lower node, and a first electrode of the seventh transistor is connected to The final output terminal is adjacent, the second electrode of the seventh transistor is connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is connected to the third node.
  • the second pull-up control sub-circuit includes an eighth transistor and a ninth transistor, a gate of the eighth transistor is connected to the first clock terminal, and a first electrode of the eighth transistor Connected to the first level terminal, the second pole of the eighth transistor is connected to the fourth node; the gate of the ninth transistor is connected to the first node, and the first of the ninth transistor A pole is connected to the fourth node, and a second pole of the ninth transistor is connected to the first clock terminal.
  • the shift register further includes a third voltage regulator sub-circuit, connected to the second level terminal and the fourth node, for stabilizing the second level terminal and the fourth node Voltage.
  • the third voltage regulator circuit includes a third capacitor, a first end of the third capacitor is connected to the fourth node, and a second end of the third capacitor is connected to the second capacitor.
  • the level terminals are connected.
  • the third pull-up control sub-circuit includes a tenth transistor, a gate of the tenth transistor is connected to the fourth node, and a first pole of the tenth transistor is connected to the second node.
  • the level terminal is connected, and the second pole of the tenth transistor is connected to the intermediate output terminal.
  • the second pull-down control sub-circuit includes an eleventh transistor, a twelfth transistor, and a fourth capacitor, a gate of the eleventh transistor is connected to the fourth node, and the tenth A first pole of a transistor is connected to a first end of the fourth capacitor, a second pole of the eleventh transistor is connected to a first pole of the twelfth transistor; a gate of the twelfth transistor A second terminal connected to the fourth capacitor is connected to the third node, and a second electrode of the twelfth transistor is connected to the fourth clock terminal.
  • the shift register further includes a fourth pull-up control sub-circuit, the fourth pull-up control sub-circuit and the fourth node, the second clock terminal, the first node, and The second level terminal is connected, and is configured to switch the second level terminal in response to the control of the potential of the fourth node and the first level signal provided by the second clock terminal in the second pull-down stage. Electrically connected to the first node.
  • the fourth pull-up control sub-circuit includes a thirteenth transistor and a fourteenth transistor, and a gate of the thirteenth transistor is connected to the fourth node.
  • a first pole is connected to the second level terminal, a second pole of the thirteenth transistor is connected to the first pole of the fourteenth transistor; a gate of the fourteenth transistor is connected to the second clock The second terminal of the fourteenth transistor is connected to the first node.
  • the present disclosure provides a driving method of a shift register.
  • the shift register includes: an input sub-circuit connected to an input terminal of the shift register, a first clock terminal, and a first node; and a control sub-circuit connected to the first node and an intermediate output of the shift register Terminal, the second clock terminal, the third node, the third clock terminal, the second level terminal that provides the second level signal and the first level terminal that provides the first level signal; a pull-up sub-circuit, connected to the middle An output terminal, a final output terminal of the shift register and the second level terminal are connected; a first voltage regulator sub-circuit is connected to a lower node connection terminal, the final output terminal is connected to the third node; a pull-down transistor, The gate is connected to the third node, the first electrode is connected to the first level terminal, and the second electrode is connected to the final output terminal.
  • the driving method includes, in an input stage, providing a first level signal to the first clock terminal, providing a first level signal to the input terminal, and providing a second level signal to the second clock terminal, Providing a first level signal to the third clock terminal, the input sub-circuit electrically connecting the input terminal of the shift register with the first node, and the control sub-circuit connecting the first clock signal provided by the second clock terminal
  • the two-level signal is transmitted to the intermediate output terminal and electrically connects the first level terminal to the third node;
  • the pull-down transistor electrically connects the first level terminal to the final output terminal; in the output stage, A second level signal is provided to the first clock terminal, a first level signal is provided to the second clock terminal, and a second level signal is provided to the third clock terminal, and the control sub-circuit
  • the first level signal provided by the second clock terminal is transmitted to the intermediate output terminal; the pull-up sub-circuit electrically connects the second level terminal with the final output terminal; during the reset phase, it sends to the first clock
  • the first pull-up control sub-circuit transmits the second level signal provided by the second clock terminal to an intermediate output.
  • the first pull-down control sub-circuit electrically connects the first level terminal with the third node; the pull-down transistor electrically connects the first level terminal with the final output terminal; the first voltage regulator The circuit reduces the potential of the third node to a level lower than a first level signal provided by the first level terminal.
  • the shift register further includes: a second pull-up control sub-circuit connected to the first clock terminal, the first node, the first level terminal, and a fourth node; the third A pull-up control sub-circuit is connected to the fourth node, the second level terminal and the intermediate output terminal; a second pull-down control sub-circuit is connected to the intermediate output terminal, the third node, and a fourth clock ⁇ ⁇ End connected.
  • the driving method further includes: in the output stage, the second pull-up control sub-circuit transmits a second level signal provided by the first clock terminal to the fourth node; and in the reset stage After: in a first pull-down phase, a first level signal is provided to the first clock terminal, a second level signal is provided to the second clock terminal, and a first level signal is provided to the third clock terminal
  • the second pull-up control sub-circuit electrically connects the first level terminal to the fourth node; in a second pull-down phase, a second level signal is provided to the first clock terminal, and the first
  • the second clock terminal provides a first level signal
  • the third clock terminal provides a second level signal
  • the third voltage regulator circuit keeps the potential of the fourth node the same as the first pull-down stage;
  • the second pull-down control sub-circuit keeps the voltage between the third node and the fourth clock terminal the same as the previous first pull-down stage.
  • the first pull-down phase and the second pull-down phase are alternately performed.
  • the present disclosure provides a gate driving circuit including N cascaded shift registers, each of which is any one of the above-mentioned shift registers.
  • the intermediate output of each of the first to (N-1) th shift registers is connected to the input of the next-stage shift register, and each of the first to (N-1) th shift registers is connected
  • the connection nodes of the lower-level nodes are all connected to the first node of the next-level shift register.
  • the present disclosure provides a display device including the above gate driving circuit.
  • FIG. 1 is a schematic block diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 2 is a schematic block diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 3 is a schematic circuit diagram of a shift register provided by an embodiment of the present disclosure.
  • FIG. 5 is a flowchart of a method for driving a shift register according to an embodiment of the present disclosure
  • FIG. 6 is a schematic block diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the transistor in the shift register is a P-type transistor and a high-level signal is output during the output stage, after the output stage, the pull-down transistor transmits the signal at the low-level signal terminal to the output of the shift register, but There is a threshold loss when a P-type transistor transmits a low-level signal, resulting in a certain loss of the low-level output after the shift register output stage.
  • FIG. 1 is a schematic block diagram of a shift register according to an embodiment of the present disclosure.
  • the shift register includes an input sub-circuit 1, a first regulator sub-circuit 2, a first pull-up control sub-circuit 3, a pull-up sub-circuit 4, a first pull-down control sub-circuit 5, and a first Two regulator circuits 6 and a pull-down transistor Tp.
  • the first voltage regulator sub-circuit 2, the first pull-up control sub-circuit 3, and the first pull-down control sub-circuit constitute a control sub-circuit, which is used according to the level of the first node N1 in the input phase, the output phase and
  • the reset stage transmits the signal provided by the second clock terminal CB to the intermediate output terminal GOUT, and controls the potential of the third node N3 according to the potential of the intermediate output terminal GOUT and the signal provided by the third clock terminal CLK.
  • the input sub-circuit 1 is connected to the input terminal IN, the first clock terminal CK, and the first node N1 of the shift register, and is configured to shift the input signal in response to the first level signal provided by the first clock terminal CK during the input phase.
  • An input terminal IN of the register is electrically connected to the first node N1.
  • the first node N1 is a connection node between the input sub-circuit 1 and the first regulator sub-circuit 2.
  • the first voltage stabilizing sub-circuit 2 is connected to the first node N1, the second node N2, and the intermediate output terminal GOUT of the shift register, and is used to electrically connect the first node N1 and the second node N2 during the input stage, and is stable.
  • the voltage between the second node N2 and the intermediate output terminal GOUT, so that when the first node N1 has no signal input during the output stage, the voltage between the second node N2 and the intermediate output terminal GOUT can be kept the same as the input stage.
  • the second node N2 is a connection node between the first voltage regulator sub-circuit 2 and the first pull-up control sub-circuit 3; the intermediate output terminal GOUT is used to connect to the input terminal of the next-stage shift register.
  • the first pull-up control sub-circuit 3 is connected to the intermediate output terminal GOUT, the second node N2, and the second clock terminal CB. In response to the potential of the second node N2, it is used to supply the The second level signal is transmitted to the intermediate output terminal GOUT; and the first level signal provided by the second clock terminal CB is transmitted to the intermediate output terminal GOUT in the output stage.
  • the pull-up sub-circuit 4 is connected to the intermediate output terminal GOUT, the final output terminal EOUT of the shift register, and the second level terminal VGH providing a second-level signal, and is configured to respond to the potential of the intermediate output terminal GOUT during the output stage to connect the second
  • the level terminal VGH is electrically connected to the final output terminal EOUT.
  • the final output terminal EOUT is used to connect to the gate line to provide a scanning signal to the gate line.
  • the first pull-down control sub-circuit 5 is connected to the intermediate output terminal GOUT, the third node N3, the third clock terminal CLK, the second level terminal VGH, and the first level terminal VGL that provides a first level signal, and is used in the output stage. In response to the potential of the intermediate output terminal GOUT, electrically connect the second level terminal VGH to the third node N3; and in response to the first level signal provided by the third clock terminal CLK during the input phase and reset phase, connect the first level terminal VGL It is electrically connected to the third node N3.
  • the third node N3 is a connection node between the gate of the pull-down transistor, the second voltage regulator sub-circuit, and the second pull-down control sub-circuit.
  • the second voltage regulator sub-circuit 6 is connected to the next node connection terminal Next, the final output terminal EOUT and the third node N3, and is used to stabilize the final signal in the output phase and the reset phase in response to the first level signal provided by the next node connection terminal Next.
  • the voltage between the output terminal EOUT and the third node N3, that is, the voltage between the final output terminal EOUT and the third node N3 is stored in the output stage, and the stored voltage is kept the same as the output stage in the reset stage.
  • the lower node connection end Next is used to connect to the first node N1 of the next-stage shift register.
  • the gate of the pull-down transistor Tp is connected to the third node N3, the first pole is connected to the first level terminal VGL, and the second pole is connected to the final output terminal EOUT of the shift register.
  • the first and second poles of the pull-down transistor Tp are turned on when a gate of the pull-down transistor Tp receives a first-level signal.
  • Each of the above-mentioned sub-circuits may include a transistor, and the first level signal and the second-level signal may be determined according to the types of the transistors and the pull-down transistor Tp in each sub-circuit.
  • the first-level signal Is a high level signal
  • the second level signal is a low level signal
  • the first level signal is a low level signal
  • the second level signal is a high level signal
  • the first level terminal VGL is a low-level signal terminal
  • the second level terminal VGH is a high-level signal terminal.
  • each transistor in the shift register is a P-type transistor
  • the first level signal is a low level signal
  • the second level signal is a high level signal
  • the final output terminal EOUT of the shift register outputs a high level in the output stage.
  • the level signal is introduced as an example.
  • the reason why the shift register outputs a low-level signal with a threshold loss after the output phase is that in the reset phase after the output phase, the low-level signal received by the gate of the pull-down transistor and the source of the pull-down transistor
  • the potential of the connected low-level signal terminal is the same, but the P-type transistor is fully turned on when the gate is smaller than the source potential and the potential difference is not less than the absolute value of the threshold value of the P-type transistor. Therefore, the current pull-down of the shift register The transistor cannot be fully turned on during the reset stage, causing a threshold loss when a signal at a low-level signal terminal is transmitted to an output terminal of the shift register.
  • the threshold voltage of a pull-down transistor is -1V.
  • the pull-down transistor When the gate potential and source potential of the pull-down transistor are both -7V, the pull-down transistor cannot fully transfer the -7V potential of the source to the drain, and the drain potential will Reached -6V.
  • the N-type transistor will also have a threshold loss when transmitting a high-level signal. Then, for the case where each transistor of the shift register is an N-type transistor and the low-level signal of the shift register is at the output stage, the shift register is at The high-level signal output during the reset phase also has a threshold loss.
  • a first level signal for example, a low level signal
  • the sub-circuit 2 is transmitted to the second node N2; the first pull-up control sub-circuit 3 transmits a second level signal (for example, a high-level signal) provided by the second clock terminal CB to the intermediate output terminal GOUT; the first pull-down
  • the control sub-circuit 5 transmits the first level signal of the first level terminal VGL to the third node N3 under the control of the first level signal of the third clock terminal CLK, so that the pull-down transistor Tp is turned on, and the final output terminal EOUT A low-level signal is received from the first level terminal VGL.
  • the second node N2 keeps a low potential under the voltage regulation action of the first voltage regulator sub-circuit 2, so that the first pull-up control sub-circuit 3 transmits the low-level signal of the second clock terminal CB to the middle
  • the first pull-down control sub-circuit 5 transmits the second level signal (high level signal) of the second level terminal VGH to the third node N3;
  • the pull-up sub-circuit 4 transmits the high-level signal of the second level terminal VGH to the final output terminal EOUT.
  • the first pull-down control sub-circuit 5 transmits the low-level signal of the first level terminal VGL to the third node N3, so that the pull-down transistor Tp is turned on, and the final output terminal EOUT receives the low-level signal of the first level terminal VGL.
  • the third node N3 is further reduced on the basis of the low potential at the beginning of the reset stage, thereby ensuring that the pull-down transistor Tp can be fully turned on, so that the final output terminal EOUT can output a low-level signal without a threshold loss.
  • the first level signal is a -7V signal
  • the second level signal is a + 7V signal
  • the threshold voltage of the pull-down transistor Tp is -1V.
  • the -7V signal provided by the input terminal IN is transmitted to the second node N2 through the input sub-circuit 1 and the first voltage regulator sub-circuit 2; at this time If the input sub-circuit 1 includes a transistor with a threshold voltage of -1V, the potential of the second node N2 reaches -7+
  • -6V.
  • the first pull-down control sub-circuit 5 turns on the second level terminal VGH and the third node N3, and the third node N3 reaches a potential of + 7V; in addition, Under the control of the potential of the intermediate output terminal GOUT, the pull-up sub-circuit 4 turns on the second level terminal VGH and the final output terminal EOUT, and the final output terminal EOUT reaches a potential of + 7V, so that the final output terminal EOUT and the third node N3 The voltage between them is 0V.
  • FIG. 2 is a schematic block diagram of a shift register according to an embodiment of the present disclosure. As shown in FIG. 2, the shift register further includes a second pull-up control sub-circuit compared to the shift register described with reference to FIG. 1. 7. The third voltage regulator sub-circuit 8, the third pull-up control sub-circuit 9 and the second pull-down control sub-circuit 10.
  • the second pull-up control sub-circuit 7 is connected to the first clock terminal CK, the first node N1, the first level terminal VGL, and the fourth node N4, and is used to connect the first clock terminal in response to the potential of the first node N1 in the output stage.
  • the second level signal provided by CK is transmitted to the fourth node N4; in the first pull-down phase, the first level terminal VGL and the fourth node N4 are turned on in response to the first level signal of the first clock terminal CK.
  • the third voltage stabilizing sub-circuit 8 is connected to the second level terminal VGH and the fourth node N4, and is used to stabilize the voltage between the second level terminal VGH and the fourth node N4.
  • the fourth node N4 is a connection node between the second pull-up control sub-circuit 7 and the third voltage stabilizing sub-circuit 8.
  • the third pull-up control sub-circuit 9 is connected to the fourth node N4, the second level terminal VGH, and the intermediate output terminal GOUT, and is configured to respond to the potential of the fourth node N4 during the first pull-down phase and the second pull-down phase,
  • the level terminal VGH is in conduction with the intermediate output terminal GOUT.
  • the second pull-down control sub-circuit 10 is connected to the intermediate output terminal GOUT, the third node N3, and the fourth clock terminal CLB. In response to the potentials of the fourth node N4 and the intermediate output terminal GOUT, the second pull-down control sub-circuit 10 is used for The voltage between the third node N3 and the fourth clock terminal CLB is stored; and the signal provided at the fourth clock terminal CLB is changed from the second level signal in the first pull-down phase to the first level in the second pull-down phase. Signal, stabilize the voltage between the third node N3 and the fourth clock terminal CLB.
  • the working process of the shift register in FIG. 2 is described below by taking the first level signal as a low potential and the second level signal as a high potential as an example.
  • the first node N1 reaches a low potential (see the description above).
  • the second pull-up control sub-circuit 7 sends a high-level signal provided by the first clock terminal CK It is transmitted to the fourth node N4; at this time, the third pull-up control sub-circuit 9 does not electrically connect the second level terminal VGH to the intermediate output terminal GOUT, thereby ensuring the low potential of the intermediate output terminal GOUT in the output stage.
  • the second pull-up control sub-circuit 7 transmits the low-level signal of the first level terminal VGL to the fourth node N4.
  • the third pull-up control sub-circuit 9 sends the first The high-level signal of the two-level terminal VGH is transmitted to the intermediate output terminal GOUT, thereby preventing the final output terminal EOUT from being electrically connected to the second-level terminal VGH through the pull-up sub-circuit 4; in addition, the third node N3 is in the second voltage-regulating sub-circuit.
  • the low potential of the previous stage is maintained under the voltage regulation of 6, and under the common control of the low potential of the third node N3 and the low potential of the fourth node N4, the second pull-down control sub-circuit 10 connects the fourth clock terminal CLB and The voltage between the third node N3 is stabilized to the current state.
  • the third node N3 starts to keep the low potential in the first pull-down phase, and the fourth node N4 keeps the low potential under the voltage regulation action of the third voltage regulator sub-circuit 8;
  • the second pull-down control sub-circuit 10 stabilizes the potential between the fourth clock terminal CLB and the third node N3 to be the same as the first pull-down stage;
  • the signal transitions from a high level in the first pull-down phase to a low-level signal in the second pull-down phase. Therefore, the potential of the third node N3 will decrease accordingly.
  • the first pull-down phase and the second pull-down phase can be alternately performed, so as to periodically pull the third node N3 to a lower potential to prevent the potential of the third node N3 from rising due to the transistor leakage. Therefore, the figure The shift register of 2 can keep the third node N3 at a lower potential than the first level terminal VGL after the reset stage, thereby ensuring that the pull-down transistor Tp is fully turned on, and the final output terminal EOUT outputs a low-level signal without a threshold loss. .
  • the shift register of FIG. 2 can maintain the third node N3 at the same or lower potential than the reset stage to prevent the pull-down transistor Tp from being turned on due to the leakage of the third node N3. The phenomenon.
  • the first-level signal is a signal of -7V
  • the second-level signal is a signal of + 7V
  • the threshold voltage of the pull-down transistor Tp is -1V.
  • the potential of the third node N3 is further reduced to -20V on the basis of -7V, thereby ensuring that the pull-down transistor Tp can be fully turned on.
  • the second pull-up control sub-circuit 7 transmits a signal of -7V of the first level terminal VGL to the fourth node N4.
  • the intermediate output terminal GOUT is received by the third pull-up control sub-circuit 9 To the + 7V signal provided by the second level terminal VGH; in addition, the third node N3 maintains the potential of -20V in the previous stage under the voltage regulation of the second voltage regulator circuit 6; and the third node N3 and the fourth node Under the common control of the low potential of the node N4, the second pull-down control sub-circuit 10 stabilizes the voltage between the fourth clock terminal CLB and the third node N3 to the current state.
  • the signal voltage provided by the fourth clock terminal CLB jumps from + 7V in the first pull-down phase to -7V in the second pull-down phase, thereby further reducing the potential of the third node N3 to reach -20.
  • -(7 + 7) -27V.
  • the shift register further includes a fourth pull-up control sub-circuit 11, the fourth pull-up control sub-circuit 11 and the fourth node N4, the second clock terminal CB, the first node N1, and the second power
  • the flat terminal VGH is connected, and is used to electrically connect the second level terminal VGH to the first node N1 in response to the control of the potential of the fourth node N4 and the first level signal provided by the second clock terminal CB in the second pull-down stage.
  • the fourth pull-up control sub-circuit 11 can ensure that the first node N1 and the second node N2 are at a high potential during the second pull-down stage, thereby ensuring that the second clock terminal CB is disconnected from the intermediate output terminal GOUT, preventing the intermediate output terminal GOUT from being subject to The effect of the low-level signal of the second clock terminal CB.
  • FIG. 3 is a schematic circuit diagram of a shift register according to an embodiment of the present disclosure, which illustrates a specific implementation of the shift register of FIG. 2. The structure of the shift register according to the embodiment of the present disclosure is described below with reference to FIG. 3.
  • the input sub-circuit 1 includes a first transistor T1, a gate of the first transistor T1 is connected to the first clock terminal CK, a first pole of the first transistor T1 is connected to the input terminal IN of the shift register, The second pole is connected to the first node N1.
  • the first voltage regulator circuit 2 includes a first capacitor C1 and a second transistor T2.
  • the first terminal of the first capacitor C1 is connected to the second node N2, and the second terminal is connected to the intermediate output terminal GOUT.
  • the gate of the second transistor T2 is connected to the first level terminal VGL, the first pole of the second transistor T2 is connected to the second node N2, and the second pole of the second transistor T2 is connected to the first node N1.
  • the first pull-up control sub-circuit 3 includes a third transistor T3, the gate of the third transistor T3 is connected to the second node N2, the first electrode of the third transistor T3 is connected to the intermediate output terminal GOUT, and the second of the third transistor T3 is The pole is connected to the second clock terminal CB.
  • the pull-up sub-circuit 4 includes a fourth transistor T4, the gate of the fourth transistor T4 is connected to the intermediate output terminal GOUT, the first pole of the fourth transistor T4 is connected to the second level terminal VGH, and the second pole of the fourth transistor T4 is connected to The final output EOUT is connected.
  • the first pull-down control sub-circuit 5 includes a fifth transistor T5 and a sixth transistor T6.
  • the gate of the fifth transistor T5 is connected to the intermediate output terminal GOUT, the first pole of the fifth transistor T5 is connected to the second level terminal VGH, and the second pole of the fifth transistor T5 is connected to the third node N3.
  • the gate of the sixth transistor T6 is connected to the third clock terminal CLK, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first level terminal VGL.
  • the second voltage regulator circuit 6 includes a second capacitor C2 and a seventh transistor T7.
  • the gate of the seventh transistor T7 is connected to the lower node connection terminal Next.
  • the first pole of the seventh transistor T7 is adjacent to the final output terminal EOUT.
  • the second pole of the seventh transistor T7 is connected to the first terminal of the second capacitor C2.
  • the second end of the second capacitor C2 is connected to the third node N3.
  • the second pull-up control sub-circuit 7 includes an eighth transistor T8 and a ninth transistor T9.
  • the gate of the eighth transistor T8 is connected to the first clock terminal CK
  • the first pole of the eighth transistor T8 is connected to the first level terminal VGL
  • the second pole of the eighth transistor T8 is connected to the fourth node N4.
  • the gate of the ninth transistor T9 is connected to the first node N1
  • the first pole of the ninth transistor T9 is connected to the fourth node N4
  • the second pole of the ninth transistor T9 is connected to the first clock terminal CK.
  • the third voltage regulator sub-circuit 8 includes a third capacitor C3. A first terminal of the third capacitor C3 is connected to the fourth node N4, and a second terminal is connected to the second level terminal VGH.
  • the third pull-up control sub-circuit 9 includes a tenth transistor T10, a gate of the tenth transistor T10 is connected to the fourth node N4, a first pole of the tenth transistor T10 is connected to the second level terminal VGH, The two poles are connected to the intermediate output terminal GOUT.
  • the second pull-down control sub-circuit 10 includes an eleventh transistor T11, a twelfth transistor T12, and a fourth capacitor C4.
  • the gate of the eleventh transistor T11 is connected to the fourth node N4, the first pole of the eleventh transistor T11 is connected to the first end of the fourth capacitor C4, and the second pole of the eleventh transistor T11 is connected to the twelfth.
  • the first pole of the transistor T12 is connected.
  • the gate of the twelfth transistor T12 and the second terminal of the fourth capacitor C4 are both connected to the third node N3, and the second electrode of the twelfth transistor T12 is connected to the fourth clock terminal CLB.
  • the fourth pull-up control sub-circuit 11 includes a thirteenth transistor T13 and a fourteenth transistor T14.
  • the gate of the thirteenth transistor T13 is connected to the fourth node N4, the first pole of the thirteenth transistor T13 is connected to the second level terminal VGH, and the second pole of the thirteenth transistor T13 is connected to the fourteenth transistor.
  • the first pole of T14 is connected.
  • the gate of the fourteenth transistor T14 is connected to the second clock terminal CB, and the second pole of the fourteenth transistor is connected to the first node N1.
  • each transistor in the shift register of the present disclosure is a P-type transistor.
  • each transistor is a P-type transistor.
  • the first level terminal VGL provides a low-level signal
  • the second level terminal VGH provides a high-level signal.
  • the voltage of the low-level signal is VL
  • the voltage of the high-level signal is VH.
  • FIG. 4 is a working timing diagram of the shift register provided by the present disclosure.
  • the working process of the shift register includes: an input stage t1, an output stage t2, a reset stage t3, a first pull-down stage t4, and a first stage.
  • the two pull-down phases t5, the first pull-down phase t4 and the second pull-down phase t5 are alternately performed after the reset phase t3.
  • the input terminal IN of the shift register receives a low-level signal
  • the first clock terminal CK provides a low-level signal
  • the second clock terminal CB provides a high-level signal
  • the third clock terminal CLK provides a low Signal
  • the fourth clock terminal CLB provides a high-level signal.
  • the first transistor T1 Under the control of the low-level signal provided by the first clock terminal CK, the first transistor T1 is turned on; under the control of the low-level signal provided by the first voltage terminal VGL, the second transistor T2 is turned on, and the input terminal IN and the first The node N1 and the second node N2 are electrically connected. Because the P-type transistor is fully turned on when the gate potential is less than the source potential and the difference is at least the transistor threshold (that is, the P-type transistor will have a threshold loss when transmitting a low-level signal), therefore, the The potential is VL +
  • , VL is the voltage of the low-level signal provided by the input terminal IN, and
  • the second transistor T2 Since the potential of the first level terminal VGL is lower than the potential of the first node N1, the second transistor T2 is fully turned on, and the potential of the second node N2 reaches VL +
  • the fifth transistor T5 is turned off; and the sixth transistor T6 is turned on under the control of a low-level signal provided by the third clock terminal CLK, thereby turning the low voltage of the first level terminal VGL
  • the flat signal is transmitted to the third node N3, and then the pull-down transistor Tp is controlled to be turned on.
  • the output terminal EOUT receives the low-level signal of the first level terminal VGL.
  • the third node N3 receives the low-level signal of the first level terminal VGL through the sixth transistor T6 during the input phase, and after the first display period, the third node N3 is in the input phase
  • the potential at the end of the previous display period is maintained (the potential is lower than the low level of the first level terminal VGL, see the description below for details).
  • the input terminal IN of the shift register receives a high-level signal
  • the first clock terminal CK and the third clock terminal CLK provide a high-level signal
  • the second clock terminal CB and the fourth clock terminal CLB provide a low voltage.
  • Level signal; the next-level node connection terminal Next provides a low-level signal.
  • the first transistor T1 is turned off, and the third transistor T3 transmits the low-level signal of the second clock terminal CB to the intermediate output terminal GOUT. Because the potential of the intermediate output terminal GOUT is reduced relative to the input stage t1, the potential of the second node N2 is further reduced to reach 2VL +
  • the sixth transistor T6 Under the control of the high-level signal of the third clock terminal CLK, the sixth transistor T6 is turned off. Since the intermediate output terminal GOUT reaches a low potential, the fourth transistor T4 and the fifth transistor T5 are both turned on, and the third node N3 and the final output terminal EOUT receive the high-level signal of the second level terminal VGH. At the same time, the seventh transistor T7 is turned on under the control of the low-level signal provided by the lower node connection terminal Next, and the potentials at the two ends of the second capacitor C2 are respectively the same as the potentials at the final output terminal EOUT and the third node N3.
  • the first node N1 maintains the low potential of the previous stage, so that the ninth transistor T9 is turned on, and the high-level signal of the first clock terminal CK is transmitted.
  • the tenth transistor T10 and the eleventh transistor T11 are both turned off to prevent the high-level signal of the second signal terminal VGH from affecting the potential of the intermediate output terminal GOUT and the first The influence of the four clock terminals CLKB on the potential of the third node N3.
  • the input terminal IN of the shift register receives a high-level signal.
  • the first clock terminal CK, the second clock terminal CB, and the fourth clock terminal CLKB all provide a high-level signal, and the third clock terminal CLK provides a low-level signal.
  • Level signal; the low-level node connection terminal provides a low-level signal.
  • the first transistor T1 and the second transistor T2 are both turned off, and the third transistor T3 is turned on.
  • the high-level signal of the second clock terminal CB is transmitted to the intermediate output terminal GOUT.
  • both the fourth transistor T4 and the fifth transistor T5 are turned off.
  • the sixth transistor T6 is turned on under the control of the high-level signal provided by the third clock terminal CLK, so that the third node N3 is electrically connected to the first level terminal VGL to reach a low potential.
  • the pull-down transistor Tp is turned on to electrically connect the final output terminal EOUT to the first level terminal VGL, so that the potential of the final output terminal EOUT is lowered compared to the output stage t2.
  • the seventh transistor T7 is turned on under the control of the low-level signal provided by the connection node of the lower node, so that the potential of the first terminal of the second capacitor C2 is lower than that of the output stage t2.
  • the potential of the third node N3 (that is, the second terminal of the second capacitor C2) will be further reduced to below VL, thereby ensuring that the pull-down transistor Tp is more fully turned on, so that the final output EOUT output has no threshold loss Low-level signals.
  • the input terminal IN of the shift register receives a high-level signal
  • the first clock terminal CK and the third clock terminal CLK both provide a low-level signal
  • the second clock terminal CB and the fourth clock terminal CLB provides high-level signals
  • the next-level node connection Next provides low-level signals.
  • the first clock terminal CK provides a low-level signal
  • the first transistor T1 is turned on, and the high-level signal at the input terminal IN is transmitted to the first node N1; and the second transistor T2 is turned on under the control of the first signal terminal VGL , So that the second node N2 receives the high-level signal of the input terminal IN, and then turns off the third transistor T3.
  • the eighth transistor T8 is turned on under the control of the low-level signal provided by the first clock terminal CK, thereby transmitting the low-level signal of the first level terminal VGL to the fourth node N4.
  • the tenth transistor T10 is turned on to transmit the high-level signal of the second level terminal VGH to the intermediate output terminal GOUT, so that both the fourth transistor T4 and the fifth transistor T5 are turned off .
  • the seventh transistor T7 is kept on under the control of the low-level signal provided by the lower node connection terminal Next, and the second capacitor C2 keeps the third node N3 at a low potential in the reset stage t3, so that the twelfth transistor T12 is turned on. Because the fourth node N4 is in a low potential state, the eleventh transistor T11 is turned on. At this time, the fourth capacitor C4 stores the potential difference between the third node N3 and the high-level signal provided by the fourth clock terminal CLB.
  • the input terminal IN of the shift register receives a high-level signal
  • the first clock terminal CK and the third clock terminal CLK both provide a high-level signal
  • the second clock terminal CB and the fourth clock terminal CLB Both provide low-level signals
  • Next-level node connection terminal Next provides high-level signals.
  • the eighth transistor T8 and the first transistor T1 are both turned off; under the voltage regulation of the first capacitor C1, the first node N1 remains before the first pull-down stage t4 High potential, so that the ninth transistor T9 is also turned off; under the voltage regulation of the third capacitor C3, the fourth node N4 maintains the low potential in the first pull-down stage t4. In addition, under the stabilized voltage of the fourth capacitor C4, the third node N3 first maintains the low potential of the first pull-down stage t4.
  • the eleventh transistor T11 is turned on and the twelfth transistor T12 is turned on.
  • the first terminal of the fourth capacitor C4 receives the low-level signal of the fourth clock terminal CLB. . Since the potential of the first terminal of the fourth capacitor C4 is lower than that of the first pull-down stage, the potential of the second terminal of the fourth capacitor C4 (that is, the third node N3) will also decrease accordingly, reaching The state of the low potential during the pull-down phase t4 is lower, thereby ensuring that the pull-down transistor Tp is fully turned on, and then the final output terminal EOUT outputs a low-level signal without a threshold loss.
  • the thirteenth transistor T13 is turned on under the control of the low potential of the fourth node N4, and the fourteenth transistor T14 is a low-level signal provided by the second clock terminal CB.
  • the first pull-down phase t4 and the second pull-down phase t5 may be alternately performed after the reset phase t3, until the input terminal IN of the shift register receives a low-level signal again and enters the next cycle.
  • FIG. 5 is a flowchart of a method for driving a shift register according to an embodiment of the present disclosure.
  • the shift register uses the above-mentioned shift register. As shown in FIG. 5, the driving method includes steps S1-S3.
  • step S1 in the input stage, an input sub-circuit electrically connects the input end of the shift register with the first node; a first voltage-regulating sub-circuit electrically connects the first node with the second node, and A first pull-up control sub-circuit transmits a second level signal provided by the second clock terminal to an intermediate output terminal; the first pull-down control sub-circuit electrically connects the first level terminal to the third node Connection; the pull-down transistor electrically connects the first level terminal to the final output terminal.
  • step S2 in the output stage, the first pull-up control sub-circuit transmits the first level signal provided by the second clock terminal to the intermediate output terminal; the pull-up sub-circuit transmits the second level terminal And is electrically connected to the final output terminal.
  • step S3 in the reset phase, the first pull-up control sub-circuit transmits a second level signal provided by the second clock terminal to an intermediate output terminal; the first pull-down control sub-circuit transmits the first A level terminal is electrically connected to the third node; the pull-down transistor electrically connects the first level terminal to a final output terminal; and the second voltage regulator circuit connects the voltage between the final output terminal and the third node Stability remains the same as in the output phase.
  • the shift register further includes a second pull-up control sub-circuit, a third regulator sub-circuit, a third pull-up control sub-circuit, and a second pull-down control sub-circuit, in the output stage in step S2, the second pull-up control sub-circuit
  • the pull control sub-circuit transmits the second-level signal provided by the first clock terminal to the fourth node.
  • the driving method further includes steps S4 and S5 performed after the reset phase.
  • step S4 in the first pull-down stage, the second pull-up control sub-circuit electrically connects the first level terminal to the fourth node.
  • step S5 in the second pull-down stage, the third voltage regulator sub-circuit keeps the potential of the fourth node the same as that in the first pull-down stage; the second pull-down control sub-circuit holds the third node and The voltage between the fourth clock terminals remains the same as the previous first pull-down stage.
  • the first pull-down phase and the second pull-down phase are alternately performed until the next cycle.
  • the shift register further includes a fourth pull-up control sub-circuit
  • the fourth pull-up control sub-circuit electrically connects the second level terminal to the first node to ensure that the first node is at a high potential .
  • FIG. 6 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the gate driving circuit includes cascaded n shift registers GOA_1, GOA_2, ..., GOA_n-1, GOA_n.
  • the shift register adopts any of the above-mentioned shift registers.
  • the final output terminals EOUT of the shift registers at each level are respectively connected to the gate lines G1, G2,... Gn one by one. Except for the last-stage shift register GOA_n, the intermediate output terminal GOUT of each of the remaining shift registers GOA_1 to GOA_n-1 is connected to the input terminal IN of the next-stage shift register. In addition, except for the last-stage shift register GOA_n, the lower node connection end Next of each of the remaining shift registers GOA_1 to GOA_n-1 is connected to the first node N1 of the next-stage shift register, thereby not increasing In the case of an extra power signal, the upper and lower signals are used to achieve a low-level output without a threshold loss in the upper shift register.
  • the input terminal IN of the first stage shift register GOA_1 is connected to the start of the frame STV, and the signal of the next node connection terminal Next of the last stage shift register GOA_n is connected to the signal terminal END.
  • the output stage, reset stage, and first pull-down stage of the shift register GOA_n provide low-level signals.
  • the gate driving circuit may further include a first clock signal line CKL, a second clock signal line CBL, a third clock signal line CLKL, and a fourth clock signal line CLBL, all of which are used to provide a clock signal.
  • the first clock terminal CK of the odd-stage shift register and the second clock terminal CB of the even-stage shift register are connected to the first clock signal line CKL, and the second clock terminal CB of the odd-stage shift register and the even-stage shift
  • the first clock terminal CK of the bit register is connected to the second clock signal line CBL, and the third clock terminal CLK of the odd-numbered shift register and the fourth clock terminal CLB of the even-numbered shift register are connected to the third clock signal line CBL.
  • the fourth clock terminal CLB of the odd-numbered stage shift register and the third clock terminal CLK of the even-numbered stage shift register are connected to the fourth clock signal line CLKL.
  • the final output terminal of the shift register outputs a low-level signal only when the second clock terminal CB provides a low-level signal, when one of the first clock signal line CKL and the second clock signal line CBL is provided
  • the final output terminal of the first-stage shift register outputs a high-level signal. For example, if the final output terminal of the first-stage shift register outputs a high-level signal at t2 in FIG. 4, the final output terminal of the second-stage shift register outputs a high-level signal at t4, and the third stage shifts The final output of the bit register outputs a high-level signal during the second t4 phase, and so on.
  • the setting of the interval stage t0 can make the output stages of the shift registers at all levels evenly distributed. It should be noted that, the present disclosure does not limit the duty cycle of the clock signals provided by the clock signal lines CKL, CBL, CLKL, and CLBL, as long as the intervals between the output stages of the shift registers at all levels are the same.
  • the gate driving circuit provided by the embodiment of the present disclosure can use the signals of the upper and lower shift registers to realize the output low-level signal of the shift register without threshold loss, and has a simple structure.
  • An embodiment of the present disclosure provides a display device including the above gate driving circuit.

Abstract

一种移位寄存器及其驱动方法、栅极驱动电路、显示装置。移位寄存器包括：输入子电路（1），用于在输入阶段响应于第一时钟端（CK）提供的第一电平信号，将输入端（IN）与第一节点（N1）电连接；控制子电路，用于根据第一节点（N1）的电平，在输入阶段、输出阶段和复位阶段将第二时钟端（CB）提供的信号传输至中间输出端（GOUT），并且根据该中间输出端（GOUT）的电位和第三时钟端（CLK）提供的信号控制第三节点（N3）的电位；上拉子电路（4），用于在输出阶段响应于中间输出端（GOUT）的电位，将第二电平端（VGH）与最终输出端（EOUT）电连接；第二稳压子电路（6），用于在输出阶段和复位阶段响应于下级节点连接端（Next）提供的第一电平信号，稳定最终输出端（EOUT）与第三节点（N3）之间的电压；下拉晶体管（Tp），其栅极与第三节点（N3）相连，第一极与第一电平端（VGL）相连，第二极与最终输出端（EOUT）相连。该第二稳压子电路（6）在复位阶段将第三节点（N3）的电位降低至低于第一电平端（VGL）提供的第一电平信号的电平。

Description

移位寄存器及其驱动方法、栅极驱动电路、显示装置 技术领域
本申请涉及显示技术领域，具体涉及一种移位寄存器及其驱动方法、栅极驱动电路、显示装置。
背景技术
显示装置在进行显示时，栅极驱动单元的多个移位寄存器依次向相应的栅线提供扫描信号。其中，每个移位寄存器在其工作的输出阶段输出有效信号，在输出阶段之后输出无效信号。期望的是，在输出阶段之后输出的无效信号没有阈值损失。
发明内容
本公开提出了一种移位寄存器及其驱动方法、栅极驱动电路、显示装置。
在一方面，本公开提供一种移位寄存器，包括：输入子电路，与所述移位寄存器的输入端、第一时钟端和第一节点相连，用于在输入阶段响应于所述第一时钟端提供的第一电平信号，将所述输入端与所述第一节点电连接；控制子电路，与所述第一节点、所述移位寄存器的中间输出端、第二时钟端、第三节点、第三时钟端、提供第二电平信号的第二电平端和提供第一电平信号的第一电平端相连，用于根据所述第一节点的电平，在所述输入阶段、输出阶段和复位阶段将所述第二时钟端提供的信号传输至所述中间输出端，并且根据所述中间输出端的电位和所述第三时钟端提供的信号控制所述第三节点的电位；上拉子电路，与所述中间输出端、所述移位寄存器的最终输出端和所述第二电平端相连，用于在所述输出阶段响应于所述中间输出端的电位，将所述第二电平端与所述最终输出端电连接；第一稳压子电路，与下级节点连接端、所述最终输出端和所述第三节点相连，用于 在所述输出阶段和所述复位阶段响应于所述下级节点连接端提供的第一电平信号，稳定所述最终输出端与所述第三节点之间的电压；下拉晶体管，其栅极与所述第三节点相连，第一极与所述第一电平端相连，第二极与所述最终输出端相连。所述第一稳压子电路在所述复位阶段将所述第三节点的电位降低至低于所述第一电平端提供的第一电平信号的电平。
在一些实施例中，所述第一稳压子电路还用于在所述复位阶段之后的第一下拉阶段响应于所述下级节点连接端提供的第一电平信号，稳定所述最终输出端与所述第三节点之间的电压。
在一些实施例中，所述控制子电路包括：第二稳压子电路，与所述第一节点、第二节点和所述中间输出端相连，用于在所述输入阶段将所述第一节点与所述第二节点电连接，并稳定所述第二节点和所述中间输出端之间的电压；第一上拉控制子电路，与所述中间输出端、所述第二节点和所述第二时钟端相连，响应于所述第二节点的电位，用于在所述输入阶段和所述复位阶段将所述第二时钟端提供的第二电平信号传输至所述中间输出端；并在所述输出阶段将所述第二时钟端提供的第一电平信号传输至所述中间输出端；第一下拉控制子电路，与所述中间输出端、所述第三节点、所述第三时钟端、所述第二电平端和所述第一电平端相连，用于在所述输出阶段响应于所述中间输出端的电位，将所述第二电平端与所述第三节点电连接；并在所述输入阶段和所述复位阶段响应于所述第三时钟端提供的第一电平信号，将所述第一电平端与所述第三节点电连接。
在一些实施例中，所述移位寄存器还包括：第二上拉控制子电路，与所述第一时钟端、所述第一节点、所述第一电平端和第四节点相连，用于在所述输出阶段响应于所述第一节点的电位，将所述第一时钟端提供的第二电平信号传输至所述第四节点，并在所述第一下拉阶段响应于所述第一时钟端提供的第一电平信号的控制，将所述第一电平端与所述第四节点电连接；第三上拉控制子电路，与所述第四节点、所述第二电平端和所述中间输出端相连，用于在所述第一下拉阶段和第二下拉阶段响应于所述第四节点电位，将所述第二电平端与所 述中间输出端电连接；第二下拉控制子电路，与所述中间输出端、所述第三节点和第四时钟端相连，响应于所述第四节点和所述中间输出端的电位，用于在所述第四时钟端提供的信号从所述第一下拉阶段的第二电平信号变为所述第二下拉阶段的第一电平信号时，稳定所述第三节点和所述第四时钟端之间的电压。
在一些实施例中，所述输入子电路包括第一晶体管，所述第一晶体管的栅极与所述第一时钟端相连，所述第一晶体管的第一极与所述移位寄存器的输入端相连，所述第一晶体管的第二极与所述第一节点相连。
在一些实施例中，所述第二稳压子电路包括第一电容和第二晶体管，所述第一电容的第一端与所述第二节点相连，所述第一电容的第二端与所述中间输出端相连；所述第二晶体管的栅极与所述第一电平端相连，所述第二晶体管的第一极与所述第二节点相连，所述第二晶体管的第二极与所述第一节点相连。
在一些实施例中，所述第一上拉控制子电路包括第三晶体管，所述第三晶体管的栅极与所述第二节点相连，所述第三晶体管的第一极与所述中间输出端相连，所述第三晶体管的第二极与所述第二时钟端相连。
在一些实施例中，所述上拉子电路包括第四晶体管，所述第四晶体管的栅极与所述中间输出端相连，所述第四晶体管的第一极与所述第二电平端相连，所述第四晶体管的第二极与所述最终输出端相连。
在一些实施例中，所述第一下拉控制子电路包括第五晶体管和第六晶体管。所述第五晶体管的栅极与所述中间输出端相连，所述第五晶体管的第一极与所述第二电平端相连，所述第五晶体管的第二极与所述第三节点相连。所述第六晶体管的栅极与所述第三时钟端相连，所述第六晶体管的第一极与所述第三节点相连，所述第六晶体管的第二极与所述第一电平端相连。
在一些实施例中，所述第一稳压子电路包括第二电容和第七晶体管，所述第七晶体管的栅极与所述下级节点连接端相连，所述第七 晶体管的第一极与所述最终输出端相邻，所述第七晶体管的第二极与所述第二电容的第一端相连，所述第二电容的第二端与所述第三节点相连。
在一些实施例中，所述第二上拉控制子电路包括第八晶体管和第九晶体管，所述第八晶体管的栅极与所述第一时钟端相连，所述第八晶体管的第一极与所述第一电平端相连，所述第八晶体管的第二极与所述第四节点相连；所述第九晶体管的栅极与所述第一节点相连，所述第九晶体管的第一极与所述第四节点相连，所述第九晶体管的第二极与所述第一时钟端相连。
在一些实施例中，所述移位寄存器还包括第三稳压子电路，与所述第二电平端和所述第四节点相连，用于稳定所述第二电平端与所述第四节点之间的电压。
在一些实施例中，所述第三稳压子电路包括第三电容，所述第三电容的第一端与所述第四节点相连，所述第三电容的第二端与所述第二电平端相连。
在一些实施例中，所述第三上拉控制子电路包括第十晶体管，所述第十晶体管的栅极与所述第四节点相连，所述第十晶体管的第一极与所述第二电平端相连，所述第十晶体管的第二极与所述中间输出端相连。
在一些实施例中，所述第二下拉控制子电路包括第十一晶体管、第十二晶体管和第四电容，所述第十一晶体管的栅极与所述第四节点相连，所述第十一晶体管的第一极与所述第四电容的第一端相连，所述第十一晶体管的第二极与所述第十二晶体管的第一极相连；所述第十二晶体管的栅极和所述第四电容的第二端均与所述第三节点相连，所述第十二晶体管的第二极与所述第四时钟端相连。
在一些实施例中，所述移位寄存器还包括第四上拉控制子电路，所述第四上拉控制子电路与所述第四节点、所述第二时钟端、所述第一节点和所述第二电平端相连，用于在所述第二下拉阶段响应于所述第四节点的电位和所述第二时钟端提供的第一电平信号的控制，将所述第二电平端与所述第一节点电连接。
在一些实施例中，所述第四上拉控制子电路包括第十三晶体管和第十四晶体管，所述第十三晶体管的栅极与所述第四节点相连，所述第十三晶体管的第一极与所述第二电平端相连，所述第十三晶体管的第二极与所述第十四晶体管的第一极相连；所述第十四晶体管的栅极与所述第二时钟端相连，所述第十四晶体管的第二极与所述第一节点相连。
在另一方面，本公开提供一种移位寄存器的驱动方法。所述移位寄存器包括：输入子电路，与所述移位寄存器的输入端、第一时钟端和第一节点相连；控制子电路，与所述第一节点、所述移位寄存器的中间输出端、第二时钟端、第三节点、第三时钟端、提供第二电平信号的第二电平端和提供第一电平信号的第一电平端相连；上拉子电路，与所述中间输出端、所述移位寄存器的最终输出端和所述第二电平端相连；第一稳压子电路，与下级节点连接端、所述最终输出端和所述第三节点相连；下拉晶体管，其栅极与所述第三节点相连，第一极与所述第一电平端相连，第二极与所述最终输出端相连。所述驱动方法包括：在输入阶段，向所述第一时钟端提供第一电平信号，向所述输入端提供第一电平信号，向所述第二时钟端提供第二电平信号，向所述第三时钟端提供第一电平信号，所述输入子电路将移位寄存器的输入端与所述第一节点电连接，所述控制子电路将所述第二时钟端提供的第二电平信号传输至中间输出端并且将所述第一电平端与所述第三节点电连接；所述下拉晶体管将所述第一电平端与所述最终输出端电连接；在输出阶段，向所述第一时钟端提供第二电平信号，向所述第二时钟端提供第一电平信号，向所述第三时钟端提供第二电平信号，所述控制子电路将所述第二时钟端提供的第一电平信号传输至中间输出端；所述上拉子电路将所述第二电平端与所述最终输出端电连接；在复位阶段，向所述第一时钟端提供第二电平信号，向所述第二时钟端提供第二电平信号，向所述第三时钟端提供第一电平信号，所述第一上拉控制子电路将所述第二时钟端提供的第二电平信号传输至中间输出端；所述第一下拉控制子电路将所述第一电平端与所述第三节点电连接；所述下拉晶体管将第一电平端与最终输出端电连 接；所述第一稳压子电路将所述第三节点的电位降低至低于所述第一电平端提供的第一电平信号的电平。
在一些实施例中，所述移位寄存器还包括：第二上拉控制子电路，与所述第一时钟端、所述第一节点、所述第一电平端和第四节点相连；第三上拉控制子电路，与所述第四节点、所述第二电平端和所述中间输出端相连；第二下拉控制子电路，与所述中间输出端、所述第三节点和第四时钟端相连。所述驱动方法还包括：在所述输出阶段，所述第二上拉控制子电路将所述第一时钟端提供的第二电平信号传输至所述第四节点；并且在所述复位阶段之后：在第一下拉阶段，向所述第一时钟端提供第一电平信号，向所述第二时钟端提供第二电平信号，向所述第三时钟端提供第一电平信号，所述第二上拉控制子电路将所述第一电平端与所述第四节点电连接；在第二下拉阶段，向所述第一时钟端提供第二电平信号，向所述第二时钟端提供第一电平信号，向所述第三时钟端提供第二电平信号，所述第三稳压子电路将所述第四节点的电位保持与第一下拉阶段相同；所述第二下拉控制子电路将所述第三节点和第四时钟端之间的电压保持与之前的第一下拉阶段相同。其中，所述第一下拉阶段和所述第二下拉阶段交替进行。
在另一方面，本公开提供一种栅极驱动电路，包括级联的N个移位寄存器，每个所述移位寄存器为上述任一移位寄存器。第1至第(N-1)移位寄存器中的每一个的中间输出端均与下一级移位寄存器的输入端相连，并且第1至第(N-1)移位寄存器中的每一个的下级节点连接端均与下一级移位寄存器的第一节点相连。
在另一方面，本公开提供一种显示装置，包括上述栅极驱动电路。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1是本公开实施例提供的移位寄存器的示意框图；
图2是本公开实施例提供的移位寄存器的示意框图；
图3是本公开实施例提供的移位寄存器的电路示意图；
图4是本公开实施例提供的移位寄存器的工作时序图；
图5是本公开实施例提供的一种移位寄存器的驱动方法流程图；
图6是本公开实施例提供的一种栅极驱动电路的示意框图。
具体实施方式
以下结合附图对本公开的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本公开，并不用于限制本公开。
现有的移位寄存器在输出阶段之后输出的无效信号存在一定的阈值损失。例如，对于移位寄存器中的晶体管为P型晶体管，且在输出阶段输出高电平信号为例，在输出阶段之后，下拉晶体管将低电平信号端的信号传输至移位寄存器的输出端，但P型晶体管在传输低电平信号时存在阈值损失，从而导致移位寄存器输出阶段之后输出的低电平会有一定的损失。
因此，如何在输出阶段之后输出无阈值损失的低电平成为亟待解决的技术问题。
图1是本公开实施例提供的移位寄存器的示意框图。如图1所示，所述移位寄存器包括输入子电路1、第一稳压子电路2、第一上拉控制子电路3、上拉子电路4、第一下拉控制子电路5、第二稳压子电路6和下拉晶体管Tp。其中，第一稳压子电路2、第一上拉控制子电路3和第一下拉控制子电路构成控制子电路，其用于根据第一节点N1的电平，在输入阶段、输出阶段和复位阶段将第二时钟端CB提供的信号传输至中间输出端GOUT，并且根据中间输出端GOUT的电位和第三时钟端CLK提供的信号控制第三节点N3的电位。
输入子电路1与所述移位寄存器的输入端IN、第一时钟端CK、第一节点N1相连，用于在输入阶段响应于第一时钟端CK提供的第一电平信号，将移位寄存器的输入端IN与第一节点N1电连接。第 一节点N1为输入子电路1和第一稳压子电路2之间的连接节点。
第一稳压子电路2与第一节点N1、第二节点N2和所述移位寄存器的中间输出端GOUT相连，用于在输入阶段将第一节点N1与第二节点N2电连接，并稳定第二节点N2和中间输出端GOUT之间的电压，以使第一节点N1在输出阶段没有信号输入时，能够保持第二节点N2与中间输出端GOUT之间的电压与输入阶段相同。其中，第二节点N2为第一稳压子电路2与第一上拉控制子电路3之间的连接节点；中间输出端GOUT用于连接下一级移位寄存器的输入端。
第一上拉控制子电路3与中间输出端GOUT、第二节点N2和第二时钟端CB相连，响应于第二节点N2电位，用于在输入阶段和复位阶段将第二时钟端CB提供的第二电平信号传输至中间输出端GOUT；并在输出阶段将第二时钟端CB提供的第一电平信号传输至中间输出端GOUT。
上拉子电路4与中间输出端GOUT、移位寄存器的最终输出端EOUT和提供第二电平信号的第二电平端VGH相连，用于在输出阶段响应于中间输出端GOUT电位，将第二电平端VGH与最终输出端EOUT电连接。其中，最终输出端EOUT用于与栅线相连，以向栅线提供扫描信号。
第一下拉控制子电路5与中间输出端GOUT、第三节点N3、第三时钟端CLK、第二电平端VGH和提供第一电平信号的第一电平端VGL相连，用于在输出阶段响应于中间输出端GOUT电位，将第二电平端VGH与第三节点N3电连接；并在输入阶段和复位阶段响应于第三时钟端CLK提供的第一电平信号，将第一电平端VGL与第三节点N3电连接。其中，第三节点N3为下拉晶体管的栅极、第二稳压子电路以及第二下拉控制子电路之间的连接节点。
第二稳压子电路6与下级节点连接端Next、最终输出端EOUT和第三节点N3相连，用于在输出阶段和复位阶段响应于下级节点连接端Next提供的第一电平信号，稳定最终输出端EOUT和第三节点N3之间的电压，即，在输出阶段对最终输出端EOUT和第三节点N3之间的电压进行存储，且在复位阶段保持存储的电压与输出阶段相 同。其中，下级节点连接端Next用于连接下一级移位寄存器的第一节点N1。
下拉晶体管Tp的栅极与第三节点N3相连，第一极与第一电平端VGL相连，第二极与移位寄存器的最终输出端EOUT相连。下拉晶体管Tp的第一极和第二极在其栅极接收到第一电平信号时导通。
上述各子电路中可以包括晶体管，第一电平信号和第二电平信号可以根据各子电路中的晶体管和下拉晶体管Tp的类型确定，当各个晶体管为N型晶体管时，第一电平信号为高电平信号，第二电平信号为低电平信号；当各个晶体管为P型晶体管时，第一电平信号为低电平信号，第二电平信号为高电平信号，相应地，第一电平端VGL为低电平信号端，第二电平端VGH为高电平信号端。本公开以移位寄存器中的各晶体管为P型晶体管、第一电平信号为低电平信号、第二电平信号为高电平信号、移位寄存器的最终输出端EOUT在输出阶段输出高电平信号为例进行介绍。
现有技术中移位寄存器在输出阶段之后输出有阈值损失的低电平信号的原因在于：在输出阶段之后的复位阶段，下拉晶体管的栅极接收到的低电平信号与下拉晶体管的源极所连接的低电平信号端的电位相同，但P型晶体管是在栅极小于源极电位、且电位差不小于P型晶体管阈值的绝对值时才充分开启，因此，目前移位寄存器的下拉晶体管在复位阶段并不能充分开启，导致低电平信号端的信号传输至移位寄存器的输出端时产生阈值损失。例如，下拉晶体管的阈值电压为-1V，当下拉晶体管栅极电位和源极电位均为-7V时，下拉晶体管并不能将源极的-7V的电位充分传输至漏极，漏极电位最多会达到-6V。同理，N型晶体管在传输高电平信号时也会有阈值损失，那么，对于移位寄存器的各晶体管为N型晶体管、移位寄存器在输出阶段低电平信号的情况，移位寄存器在复位阶段输出的高电平信号也会有阈值损失。
和现有技术相比，本公开中的移位寄存器的工作过程如下：在输入阶段，输入端IN的第一电平信号(例如，低电平信号)通过输入子电路1和第一稳压子电路2传输至第二节点N2；第一上拉控制 子电路3将第二时钟端CB提供的第二电平信号(例如，高电平信号)传输至中间输出端GOUT；第一下拉控制子电路5在第三时钟端CLK的第一电平信号的控制下，将第一电平端VGL的第一电平信号传输至第三节点N3，从而使下拉晶体管Tp开启，最终输出端EOUT接收到第一电平端VGL的低电平信号。在输出阶段，在第一稳压子电路2的稳压作用下，第二节点N2保持低电位，从而使第一上拉控制子电路3将第二时钟端CB的低电平信号传输至中间输出端GOUT，进而在中间输出端GOUT的低电位控制下，第一下拉控制子电路5将第二电平端VGH的第二电平信号(高电平信号)传输至第三节点N3；此时，上拉子电路4将第二电平端VGH的高电平信号传输至最终输出端EOUT。在复位阶段，在第三时钟端CLK提供的低电平信号的控制下，第一下拉控制子电路5将第一电平端VGL的低电平信号传输至第三节点N3，从而使得下拉晶体管Tp开启，最终输出端EOUT接收到第一电平端VGL的低电平信号；此时，由于最终输出端EOUT的电位相较于输出阶段有所降低，因此，在第二稳压子电路6的稳压作用下，第三节点N3在复位阶段开始时的低电位基础上进一步降低，从而保证下拉晶体管Tp可以充分开启，进而使得最终输出端EOUT可以输出无阈值损失的低电平信号。
例如，第一电平信号为-7V的信号，第二电平信号为+7V的信号，下拉晶体管Tp的阈值电压为-1V。这种情况下，对于本公开的移位寄存器而言，在输入阶段，输入端IN提供的-7V的信号通过输入子电路1和第一稳压子电路2向第二节点N2传输；此时，若输入子电路1包括阈值电压为-1V的晶体管，则第二节点N2电位达到-7+|-1|＝-6V。在输出阶段，第二时钟端的-7V的信号通过第一上拉控制子电路3向中间输出端GOUT传输，此时，在第一稳压子电路2的稳压作用下，第二节点N2的电位达到-6-(7+7)＝-20V，因此，第一下拉控制子电路5将第二电平端VGH与第三节点N3导通，第三节点N3达到+7V的电位；另外，在中间输出端GOUT的电位控制下，上拉子电路4将第二电平端VGH与最终输出端EOUT导通，最终输出端EOUT达到+7V的电位，从而使得最终输出端EOUT与第 三节点N3之间的电压为0V。在复位阶段，第一下拉控制子电路5将第一电平端VGL的-7V的信号传输至第三节点N3，从而使得下拉晶体管Tp开启，最终输出端EOUT开始先达到-6V的电位；而由于最终输出端的电位由之前的+7V降低为-6V，因此，在第二稳压子电路6的稳压作用下，第三节点N3的电位会在之前的-7V的基础上进一步降低至-7-(7+6)＝-20V，从而保证下拉晶体管Tp可以充分开启，以将第一信号端VGL的-7V的电压充分传输至最终输出端EOUT。
图2是本公开实施例提供的移位寄存器的示意框图，如图2所示，所述移位寄存器相较于参照图1描述的移位寄存器而言，还包括第二上拉控制子电路7、第三稳压子电路8、第三上拉控制子电路9和第二下拉控制子电路10。
第二上拉控制子电路7与第一时钟端CK、第一节点N1、第一电平端VGL和第四节点N4相连，用于在输出阶段响应于第一节点N1电位，将第一时钟端CK提供的第二电平信号传输至第四节点N4；在第一下拉阶段响应于第一时钟端CK的第一电平信号，将第一电平端VGL与第四节点N4导通。
第三稳压子电路8与第二电平端VGH和第四节点N4相连，用于稳定第二电平端VGH与第四节点N4之间的电压。其中，第四节点N4为第二上拉控制子电路7与第三稳压子电路8之间的连接节点。
第三上拉控制子电路9与第四节点N4、第二电平端VGH和中间输出端GOUT相连，用于在第一下拉阶段和第二下拉阶段响应于第四节点N4电位，将第二电平端VGH与中间输出端GOUT导通。
第二下拉控制子电路10与中间输出端GOUT、第三节点N3和第四时钟端CLB相连，响应于第四节点N4和中间输出端GOUT的电位，用于在第一下拉阶段对所述第三节点N3和第四时钟端CLB之间的电压进行存储；且在第四时钟端CLB提供的信号从第一下拉阶段的第二电平信号变为第二下拉阶段的第一电平信号时，稳定第三节点N3和第四时钟端CLB之间的电压。
下面以第一电平信号为低电位、第二电平信号为高电位为例，来描述图2的移位寄存器的工作过程。在输出阶段，第一节点N1达 到低电位(参见上文描述)，在第一节点N1的低电位的控制下，第二上拉控制子电路7将第一时钟端CK提供的高电平信号传输至第四节点N4；此时，第三上拉控制子电路9并不会将第二电平端VGH与中间输出端GOUT电连接，从而保证中间输出端GOUT在输出阶段的低电位。在复位阶段之后的第一下拉阶段，第二上拉控制子电路7将第一电平端VGL的低电平信号传输至第四节点N4，这时，第三上拉控制子电路9将第二电平端VGH的高电平信号传输至中间输出端GOUT，进而防止最终输出端EOUT通过上拉子电路4与第二电平端VGH电连接；另外，第三节点N3在第二稳压子电路6的稳压作用下保持上一阶段的低电位，而在第三节点N3的低电位和第四节点N4的低电位的共同控制下，第二下拉控制子电路10将第四时钟端CLB与第三节点N3之间的电压稳定为当前状态。在第二下拉阶段，第三节点N3开始先保持第一下拉阶段的低电位，第四节点N4在第三稳压子电路8的稳压作用下保持低电位；在第三节点N3和第四节点N4的低电位控制下，第二下拉控制子电路10将第四时钟端CLB与第三节点N3之间的电位稳定为与第一下拉阶段相同；而由于第四时钟端CLB提供的信号从第一下拉阶段的高电平跳变为第二下拉阶段的低电平信号，因此，第三节点N3的电位也会相应地再降低。其中，第一下拉阶段和第二下拉阶段可以交替进行，从而周期性地将第三节点N3拉低至较低电位，以防止因晶体管漏电而导致第三节点N3电位升高，因此，图2的移位寄存器能够使第三节点N3在复位阶段之后一直处于比第一电平端VGL更低的电位，从而保证下拉晶体管Tp的充分开启，最终输出端EOUT无阈值损失地输出低电平信号。和图1的移位寄存器相比，图2的移位寄存器能够将第三节点N3保持与复位阶段相同或更低的电位，以防止出现因第三节点N3漏电而无法使下拉晶体管Tp充分开启的现象。
同样以上文中第一电平信号为-7V的信号、第二电平信号为+7V的信号、下拉晶体管Tp的阈值电压为-1V为例，在图2的移位寄存器中，在输入阶段，和图1相同的，第二节点N2电位达到-7+|-1|＝-6V。在输出阶段，和图1相同的，第二节点N2的电位达到-20V，第三节 点的电位N3达到+7V，最终输出端EOUT的电位达到+7V。在复位阶段，第三节点N3的电位在-7V的基础上进一步降低至-20V，从而保证下拉晶体管Tp可以充分开启。在第一下拉阶段，第二上拉控制子电路7将第一电平端VGL的-7V的信号向第四节点N4传输，这时，中间输出端GOUT通过第三上拉控制子电路9接收到第二电平端VGH提供的+7V的信号；另外，第三节点N3在第二稳压子电路6的稳压作用下保持上一阶段-20V的电位；而在第三节点N3和第四节点N4的低电位的共同控制下，第二下拉控制子电路10将第四时钟端CLB与第三节点N3之间的电压稳定为当前状态。在第二下拉阶段，第四时钟端CLB提供的信号电压从第一下拉阶段的+7V跳变为第二下拉阶段的-7V，从而使第三节点N3的电位进一步降低，从而达到-20-(7+7)＝-27V。
在一些实施例中，所述移位寄存器还包括第四上拉控制子电路11，第四上拉控制子电路11与第四节点N4、第二时钟端CB、第一节点N1和第二电平端VGH相连，用于在所述第二下拉阶段响应于第四节点N4的电位和第二时钟端CB提供的第一电平信号的控制，将第二电平端VGH与第一节点N1电连接。第四上拉控制子电路11能够保证第一节点N1和第二节点N2在第二下拉阶段处于高电位，从而保证第二时钟端CB与中间输出端GOUT断开，防止中间输出端GOUT受到第二时钟端CB的低电平信号的影响。
图3是本公开实施例提供的移位寄存器的电路示意图，其示出了图2的移位寄存器的一种具体化实施方式。下面结合图3对本公开实施例的移位寄存器的结构进行介绍。
输入子电路1包括第一晶体管T1，第一晶体管T1的栅极与第一时钟端CK相连，第一晶体管T1的第一极与所述移位寄存器的输入端IN相连，第一晶体管T1的第二极与第一节点N1相连。
第一稳压子电路2包括第一电容C1和第二晶体管T2。第一电容C1的的第一端与第二节点N2相连，第二端与中间输出端GOUT相连。第二晶体管T2的栅极与第一电平端VGL相连，第二晶体管T2的第一极与第二节点N2相连，第二晶体管T2的第二极与第一节 点N1相连。
第一上拉控制子电路3包括第三晶体管T3，第三晶体管T3的栅极与第二节点N2相连，第三晶体管T3的第一极与中间输出端GOUT相连，第三晶体管T3的第二极与第二时钟端CB相连。
上拉子电路4包括第四晶体管T4，第四晶体管T4的栅极与中间输出端GOUT相连，第四晶体管T4的第一极与第二电平端VGH相连，第四晶体管T4的第二极与最终输出端EOUT相连。
第一下拉控制子电路5包括第五晶体管T5和第六晶体管T6。其中，第五晶体管T5的栅极与中间输出端GOUT相连，第五晶体管T5的第一极与第二电平端VGH相连，第五晶体管T5的第二极与第三节点N3相连。第六晶体管T6的栅极与第三时钟端CLK相连，第六晶体管T6的第一极与第三节点N3相连，第六晶体管T6的第二极与第一电平端VGL相连。
第二稳压子电路6包括第二电容C2和第七晶体管T7。其中，第七晶体管T7的栅极与下级节点连接端Next相连，第七晶体管T7的第一极与最终输出端EOUT相邻，第七晶体管T7的第二极与第二电容C2的第一端相连，第二电容C2的第二端与第三节点N3相连。
第二上拉控制子电路7包括第八晶体管T8和第九晶体管T9。其中，第八晶体管T8的栅极与第一时钟端CK相连，第八晶体管T8的第一极与第一电平端VGL相连，第八晶体管T8的第二极与第四节点N4相连。第九晶体管T9的栅极与第一节点N1相连，第九晶体管T9的第一极与第四节点N4相连，第九晶体管T9的第二极与第一时钟端CK相连。
第三稳压子电路8包括第三电容C3，第三电容C3的第一端与第四节点N4相连，第二端和第二电平端VGH相连。
第三上拉控制子电路9包括第十晶体管T10，第十晶体管T10的栅极与第四节点N4相连，第十晶体管T10的第一极与第二电平端VGH相连，第十晶体管T10的第二极与中间输出端GOUT相连。
第二下拉控制子电路10包括第十一晶体管T11、第十二晶体管T12和第四电容C4。其中，第十一晶体管T11的栅极与第四节点N4 相连，第十一晶体管T11的第一极与第四电容C4的第一端相连，第十一晶体管T11的第二极与第十二晶体管T12的第一极相连。第十二晶体管T12的栅极和第四电容C4的第二端均与第三节点N3相连，第十二晶体管T12的第二极与第四时钟端CLB相连。
第四上拉控制子电路11包括第十三晶体管T13和第十四晶体管T14。其中，第十三晶体管T13的栅极与第四节点N4相连，所述第十三晶体管T13的第一极与第二电平端VGH相连，第十三晶体管T13的第二极与第十四晶体管T14的第一极相连。第十四晶体管T14的栅极与第二时钟端CB相连，第十四晶体管的第二极与第一节点N1相连。
在本实施例中，“第一极”具体是指晶体管的源极，“第二极”具体是指晶体管的漏极。当然，“第一极”与“第二极”可进行互换。另外，在一些实施例中，本公开的移位寄存器中的各晶体管为P型晶体管。
下面结合图3和图4对本实施例中的移位寄存器的工作过程进行介绍。作为示例，各晶体管均为P型晶体管，第一电平端VGL提供低电平信号，第二电平端VGH提供高电平信号，低电平信号的电压为VL，高电平信号的电压为VH。图4是本公开提供的移位寄存器的工作时序图，如图3所示，该移位寄存器的工作过程包括：输入阶段t1、输出阶段t2、复位阶段t3、第一下拉阶段t4和第二下拉阶段t5，第一下拉阶段t4和第二下拉阶段t5在复位阶段t3之后交替进行。
在输入阶段t1，移位寄存器的输入端IN接收到低电平信号，第一时钟端CK提供低电平信号，第二时钟端CB提供高电平信号，第三时钟端CLK提供低电平信号，第四时钟端CLB提供高电平信号。
在第一时钟端CK提供的低电平信号的控制下，第一晶体管T1开启；在第一电平端VGL提供的低电平信号的控制下，第二晶体管T2开启，输入端IN与第一节点N1和第二节点N2电连接。由于P型晶体管在栅极电位小于源极电位且差值至少为晶体管阈值时，才充分开启(即，P型晶体管在传输低电平信号时会有阈值损失)，因此， 第一节点N1的电位为VL+|Vth|，VL为输入端IN提供的低电平信号的电压，|Vth|为第一晶体管T1阈值电压的绝对值。而由于第一电平端VGL的电位小于第一节点N1的电位，因此，第二晶体管T2充分开启，第二节点N2的电位达到VL+|Vth|，从而使得第三晶体管T3开启，中间输出端GOUT接收到第二时钟端CB的高电平信号。
由于中间输出端GOUT达到高电位，因此，第五晶体管T5关断；而第六晶体管T6在第三时钟端CLK提供的低电平信号的控制下开启，从而将第一电平端VGL的低电平信号传输至第三节点N3，进而控制下拉晶体管Tp开启，最终输出端EOUT接收到第一电平端VGL的低电平信号。
其中，在第一个显示周期，第三节点N3在输入阶段通过第六晶体管T6接收到第一电平端VGL的低电平信号，而在第一个显示周期之后，第三节点N3在输入阶段保持上一显示周期结束时的电位(该电位比第一电平端VGL的低电平更低，具体参见下文描述)。
在输出阶段t2，移位寄存器的输入端IN接收到高电平信号，第一时钟端CK和第三时钟端CLK提供高电平信号，第二时钟端CB和第四时钟端CLB提供低电平信号；下级节点连接端Next提供低电平信号。
此时，第一晶体管T1关断，第三晶体管T3将第二时钟端CB的低电平信号传输至中间输出端GOUT。由于中间输出端GOUT的电位相对于输入阶段t1有所降低，因此在C1的自举作用下，第二节点N2的电位进一步降低，达到2VL+|Vth|-VH，从而使得第三晶体管T3更充分的开启。另外，由于此时第二晶体管T2的栅极电位高于第二节点N2的电位，因此，第二晶体管T2关断，从而防止第一节点N1漏电。
在第三时钟端CLK的高电平信号控制下，第六晶体管T6关断。而由于中间输出端GOUT达到低电位，因此第四晶体管T4和第五晶体管T5均开启，第三节点N3和最终输出端EOUT接收到第二电平端VGH的高电平信号。同时，第七晶体管T7在下级节点连接端Next提供的低电平信号的控制下开启，第二电容C2两端的电位分别与最 终输出端EOUT和第三节点N3的电位相同。
另外，由于第一晶体管T1和第二晶体管T2均关断，则第一节点N1保持上一阶段的低电位，从而使得第九晶体管T9开启，进而将第一时钟端CK的高电平信号传输至第四节点N4。在第四节点N4的高电位的控制下，第十晶体管T10和第十一晶体管T11均关断，以防止第二信号端VGH的高电平信号对中间输出端GOUT电位的影响，以及防止第四时钟端CLKB对第三节点N3电位的影响。
在复位阶段t3，移位寄存器的输入端IN接收到高电平信号，第一时钟端CK、第二时钟端CB和第四时钟端CLKB均提供高电平信号，第三时钟端CLK提供低电平信号；下级节点连接端提供低电平信号。
和输出阶段t2中相同地，第一晶体管T1和第二晶体管T2均关断，第三晶体管T3开启。此时，第二时钟端CB的高电平信号传输至中间输出端GOUT。在中间输出端GOUT高电位的控制下，第四晶体管T4和第五晶体管T5均关断。同时，第六晶体管T6在第三时钟端CLK提供的高电平信号的控制下开启，从而使第三节点N3与第一电平端VGL电连接而达到低电位。
在第三节点N3低电位的控制下，下拉晶体管Tp开启，以将最终输出端EOUT与第一电平端VGL电连接，从而导致最终输出端EOUT的电位相较于输出阶段t2有所降低。同时，第七晶体管T7在下级节点连接端提供的低电平信号的控制下开启，从而使得第二电容C2的第一端的电位相较于输出阶段t2降低，因此，在第二电容C2的自举作用下，第三节点N3(即，第二电容C2第二端)的电位将进一步降低至VL以下，从而保证下拉晶体管Tp更充分地开启，进而使得最终输出端EOUT输出无阈值损失的低电平信号。
在第一下拉阶段t4，移位寄存器的输入端IN接收到高电平信号，第一时钟端CK和第三时钟端CLK均提供低电平信号，第二时钟端CB和第四时钟端CLB均提供高电平信号；下级节点连接端Next提供低电平信号。
由于第一时钟端CK提供低电平信号，因此第一晶体管T1开启， 将输入端IN的高电平信号传输至第一节点N1；且第二晶体管T2在第一信号端VGL的控制下开启，从而使第二节点N2接收到输入端IN的高电平信号，进而将第三晶体管T3关断。与此同时，第八晶体管T8在第一时钟端CK提供的低电平信号的控制下开启，从而将第一电平端VGL的低电平信号传输至第四节点N4。
在第四节点N4的低电位控制下，第十晶体管T10开启，以将第二电平端VGH的高电平信号传输至中间输出端GOUT，从而使第四晶体管T4和第五晶体管T5均关断。另外，第七晶体管T7在下级节点连接端Next提供的低电平信号的控制下保持开启，第二电容C2使第三节点N3保持复位阶段t3的低电位，从而使第十二晶体管T12开启。又由于第四节点N4处于低电位状态，因此，第十一晶体管T11开启，此时，第四电容C4存储第三节点N3与第四时钟端CLB提供的高电平信号之间的电位差。
在第二下拉阶段t5，移位寄存器的输入端IN接收到高电平信号，第一时钟端CK和第三时钟端CLK均提供高电平信号，第二时钟端CB和第四时钟端CLB均提供低电平信号；下级节点连接端Next提供高电平信号。
由于第一时钟端CK提供高电平信号，因此，第八晶体管T8和第一晶体管T1均关断；在第一电容C1的稳压作用下，第一节点N1保持之前第一下拉阶段t4的高电位，从而使第九晶体管T9也关断；在第三电容C3的稳压作用下，第四节点N4保持第一下拉阶段t4的低电位。另外，在第四电容C4的稳压作用下，第三节点N3先保持第一下拉阶段t4的低电位。
由于第三节点N3和第四节点N4处于低电位，因此第十一晶体管T11开启和第十二晶体管T12均开启，第四电容C4的第一端接收到第四时钟端CLB的低电平信号。由于第四电容C4第一端的电位相较于第一下拉阶段有所降低，因此，第四电容C4第二端(即，第三节点N3)的电位也会相应降低，达到比第一下拉阶段t4时的低电位更低的状态，从而保证下拉晶体管Tp的充分开启，进而使最终输出端EOUT输出无阈值损失的低电平信号。
另外，由于在实际应用中，晶体管中难免会产生寄生电容，这样就容易导致当晶体管源极或漏极连接的时钟端发生信号跳变时，其栅极电位也会发生波动，从而影响晶体管的开启程度。而本实施例的移位寄存器在第二下拉阶段t5，第十三晶体管T13在第四节点N4低电位的控制下开启，第十四晶体管T14在第二时钟端CB提供的低电平信号的控制下开启，从而将第二电平端VGH的高电平信号传输至第一节点N1，进而通过第二晶体管T2传输至第二节点N2，从而稳定第二节点N2的电位，以保证第三晶体管T3处于关断状态。
在本实施例中，第一下拉阶段t4和第二下拉阶段t5可以在复位阶段t3之后交替进行，直至移位寄存器的输入端IN再次接收到低电平信号而进入下一周期。通过在第二下拉阶段t5将第三节点N3的电位在第一下拉阶段t4的基础上进一步下拉，可以防止因晶体管的漏电而导致第三节点N3电位升高的情况，保证下拉晶体管Tp的充分开启。
另外，如图4的时序中，输出阶段t2与输入阶段t1之间、第二下拉阶段t5与其之前第一下拉阶段t4之间、以及第二下拉阶段t5与其之后的第一下拉阶段t4之间均存在间隔阶段t0。在每个间隔阶段t0，第一时钟端CK和第二时钟端CB均提供高电平信号；第三时钟端CLK和第四时钟端CLB在每个间隔阶段t0中提供的信号分别与各自在该间隔阶段t0之后的下一阶段中提供的信号相同。该间隔阶段t0的设置作用将在下文的栅极驱动电路中进行说明，这里先不赘述。
图5是本公开实施例提供的一种移位寄存器的驱动方法流程图，该移位寄存器采用上述移位寄存器。如图5所示，所述驱动方法包括步骤S1-S3。
在步骤S1、在输入阶段，输入子电路将移位寄存器的输入端与所述第一节点电连接；第一稳压子电路将所述第一节点与所述第二节点电连接，所述第一上拉控制子电路将所述第二时钟端提供的第二电平信号传输至中间输出端；所述第一下拉控制子电路将所述第一电平端与所述第三节点电连接；所述下拉晶体管将所述第一电平端与所述 最终输出端电连接。
在步骤S2、在输出阶段，所述第一上拉控制子电路将所述第二时钟端提供的第一电平信号传输至中间输出端；所述上拉子电路将所述第二电平端与所述最终输出端电连接。
在步骤S3、在复位阶段，所述第一上拉控制子电路将所述第二时钟端提供的第二电平信号传输至中间输出端；所述第一下拉控制子电路将所述第一电平端与所述第三节点电连接；所述下拉晶体管将第一电平端与最终输出端电连接；所述第二稳压子电路将最终输出端和所述第三节点之间的电压稳定保持与输出阶段相同。
当移位寄存器还包括第二上拉控制子电路、第三稳压子电路、第三上拉控制子电路和第二下拉控制子电路时，在步骤S2中的输出阶段，所述第二上拉控制子电路将所述第一时钟端提供的第二电平信号传输至所述第四节点。所述驱动方法还包括在复位阶段之后进行的步骤S4和S5。
在步骤S4、在第一下拉阶段，所述第二上拉控制子电路将所述第一电平端与所述第四节点电连接。
在步骤S5、在第二下拉阶段，所述第三稳压子电路将所述第四节点的电位保持与第一下拉阶段相同；所述第二下拉控制子电路将所述第三节点和第四时钟端之间的电压保持与之前的第一下拉阶段相同。
所述第一下拉阶段和所述第二下拉阶段交替进行，直至下一周期。
另外，当移位寄存器还包括第四上拉控制子电路时，在第二下拉阶段，第四上拉控制子电路将第二电平端与第一节点电连接，以保证第一节点处于高电位。
上述各步骤的具体工作过程已在上述参照图1至图3描述中进行介绍，此处不再赘述。
图6是本公开实施例提供的一种栅极驱动电路的结构示意图，如图6所示，所述栅极驱动电路包括级联的n个移位寄存器GOA_1、GOA_2……GOA_n-1、GOA_n，所述该移位寄存器采用上述任一移 位寄存器。
其中，各级移位寄存器的最终输出端EOUT分别与各条栅线G1、G2……Gn一一对应相连。除最后一级移位寄存器GOA_n以外，其余移位寄存器GOA_1至GOA_n-1中的每一个的中间输出端GOUT均与下一级移位寄存器的输入端IN相连。并且，除最后一级移位寄存器GOA_n以外，其余移位寄存器GOA_1至GOA_n-1中的每一个的下级节点连接端Next均与下一级移位寄存器的第一节点N1相连，从而在不增加额外电源信号的情况下，利用上下级信号实现上一级移位寄存器的无阈值损失的低电平输出。
另外，第一级移位寄存器GOA_1的输入端IN与帧起始端STV相连，最后一级移位寄存器GOA_n的下级节点连接端Next的信号与信号端END相连，信号端END用于在最后一级移位寄存器GOA_n的输出阶段、复位阶段和第一下拉阶段提供低电平信号。
另外，栅极驱动电路还可以包括第一时钟信号线CKL、第二时钟信号线CBL、第三时钟信号线CLKL和第四时钟信号线CLBL，该四条信号线均用于提供时钟信号。其中，奇数级移位寄存器的第一时钟端CK、偶数级移位寄存器的第二时钟端CB均与第一时钟信号线CKL相连，奇数级移位寄存器的第二时钟端CB、偶数级移位寄存器的第一时钟端CK均与第二时钟信号线CBL相连，奇数级移位寄存器的第三时钟端CLK、偶数级移位寄存器的第四时钟端CLB均与第三时钟信号线CBL相连，奇数级移位寄存器的第四时钟端CLB、偶数级移位寄存器的第三时钟端CLK均与第四时钟信号线CLKL相连。
由于移位寄存器的最终输出端是在其第二时钟端CB提供低电平信号时才输出低电平信号的，因此，当第一时钟信号线CKL和第二时钟信号线CBL中的一者提供高电平信号时，则有一级移位寄存器的最终输出端输出高电平信号。例如，若第一级移位寄存器的最终输出端在图4中t2阶段输出高电平信号时，则第二级移位寄存器的最终输出端在t4阶段输出高电平信号，第三级移位寄存器的最终输出端在第二个t4阶段输出高电平信号，以此类推。而图4中，间隔阶段t0设置能够使各级移位寄存器的输出阶段均匀分布。需要说明 的是，本公开对各时钟信号线CKL、CBL、CLKL和CLBL提供的时钟信号的占空比不作限定，只要使各级移位寄存器的输出阶段之间的间隔相同即可。
本公开实施例提供的栅极驱动电路能够利用上下级移位寄存器的信号实现移位寄存器无阈值损失的输出低电平信号，具有简单的结构。
本公开实施例提供一种显示装置，该显示装置包括上述栅极驱动电路。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (21)

  1. 一种移位寄存器，包括：
    输入子电路，与所述移位寄存器的输入端、第一时钟端和第一节点相连，用于在输入阶段响应于所述第一时钟端提供的第一电平信号，将所述输入端与所述第一节点电连接；
    控制子电路，与所述第一节点、所述移位寄存器的中间输出端、第二时钟端、第三节点、第三时钟端、提供第二电平信号的第二电平端和提供第一电平信号的第一电平端相连，用于根据所述第一节点的电平，在所述输入阶段、输出阶段和复位阶段将所述第二时钟端提供的信号传输至所述中间输出端，并且根据所述中间输出端的电位和所述第三时钟端提供的信号控制所述第三节点的电位；
    上拉子电路，与所述中间输出端、所述移位寄存器的最终输出端和所述第二电平端相连，用于在所述输出阶段响应于所述中间输出端的电位，将所述第二电平端与所述最终输出端电连接；
    第一稳压子电路，与下级节点连接端、所述最终输出端和所述第三节点相连，用于在所述输出阶段和所述复位阶段响应于所述下级节点连接端提供的第一电平信号，稳定所述最终输出端与所述第三节点之间的电压；
    下拉晶体管，其栅极与所述第三节点相连，第一极与所述第一电平端相连，第二极与所述最终输出端相连，
    其中，所述第一稳压子电路在所述复位阶段将所述第三节点的电位降低至低于所述第一电平端提供的第一电平信号的电平。
  2. 根据权利要求1所述的移位寄存器，其中，所述第一稳压子电路还用于在所述复位阶段之后的第一下拉阶段响应于所述下级节点连接端提供的第一电平信号，稳定所述最终输出端与所述第三节点之间的电压。
  3. 根据权利要求1或2所述的移位寄存器，其中，所述控制子 电路包括：
    第二稳压子电路，与所述第一节点、第二节点和所述中间输出端相连，用于在所述输入阶段将所述第一节点与所述第二节点电连接，并稳定所述第二节点和所述中间输出端之间的电压；
    第一上拉控制子电路，与所述中间输出端、所述第二节点和所述第二时钟端相连，响应于所述第二节点的电位，用于在所述输入阶段和所述复位阶段将所述第二时钟端提供的第二电平信号传输至所述中间输出端；并在所述输出阶段将所述第二时钟端提供的第一电平信号传输至所述中间输出端；
    第一下拉控制子电路，与所述中间输出端、所述第三节点、所述第三时钟端、所述第二电平端和所述第一电平端相连，用于在所述输出阶段响应于所述中间输出端的电位，将所述第二电平端与所述第三节点电连接；并在所述输入阶段和所述复位阶段响应于所述第三时钟端提供的第一电平信号，将所述第一电平端与所述第三节点电连接。
  4. 根据权利要求1至3中任一项所述的移位寄存器，还包括：
    第二上拉控制子电路，与所述第一时钟端、所述第一节点、所述第一电平端和第四节点相连，用于在所述输出阶段响应于所述第一节点的电位，将所述第一时钟端提供的第二电平信号传输至所述第四节点；并在所述第一下拉阶段响应于所述第一时钟端提供的第一电平信号的控制，将所述第一电平端与所述第四节点电连接；
    第三上拉控制子电路，与所述第四节点、所述第二电平端和所述中间输出端相连，用于在所述第一下拉阶段和第二下拉阶段响应于所述第四节点电位，将所述第二电平端与所述中间输出端电连接；
    第二下拉控制子电路，与所述中间输出端、所述第三节点和第四时钟端相连，响应于所述第四节点和所述中间输出端的电位，用于在所述第四时钟端提供的信号从所述第一下拉阶段的第二电平信号变为所述第二下拉阶段的第一电平信号时，稳定所述第三节点和所述第四时钟端之间的电压。
  5. 根据权利要求1至4中任一项所述的移位寄存器，其中，所述输入子电路包括第一晶体管，所述第一晶体管的栅极与所述第一时钟端相连，所述第一晶体管的第一极与所述移位寄存器的输入端相连，所述第一晶体管的第二极与所述第一节点相连。
  6. 根据权利要求3至5中任一项所述的移位寄存器，其中，所述第二稳压子电路包括第一电容和第二晶体管，
    所述第一电容的第一端与所述第二节点相连，所述第一电容的第二端与所述中间输出端相连；
    所述第二晶体管的栅极与所述第一电平端相连，所述第二晶体管的第一极与所述第二节点相连，所述第二晶体管的第二极与所述第一节点相连。
  7. 根据权利要求3至5中任一项所述的移位寄存器，其中，所述第一上拉控制子电路包括第三晶体管，所述第三晶体管的栅极与所述第二节点相连，所述第三晶体管的第一极与所述中间输出端相连，所述第三晶体管的第二极与所述第二时钟端相连。
  8. 根据权利要求1至7中任一项所述的移位寄存器，其中，所述上拉子电路包括第四晶体管，所述第四晶体管的栅极与所述中间输出端相连，所述第四晶体管的第一极与所述第二电平端相连，所述第四晶体管的第二极与所述最终输出端相连。
  9. 根据权利要求3至8中任一项所述的移位寄存器，其中，所述第一下拉控制子电路包括第五晶体管和第六晶体管，
    所述第五晶体管的栅极与所述中间输出端相连，所述第五晶体管的第一极与所述第二电平端相连，所述第五晶体管的第二极与所述第三节点相连；
    所述第六晶体管的栅极与所述第三时钟端相连，所述第六晶体 管的第一极与所述第三节点相连，所述第六晶体管的第二极与所述第一电平端相连。
  10. 根据权利要求1至9中任一项所述的移位寄存器，其中，所述第一稳压子电路包括第二电容和第七晶体管，
    所述第七晶体管的栅极与所述下级节点连接端相连，所述第七晶体管的第一极与所述最终输出端相邻，所述第七晶体管的第二极与所述第二电容的第一端相连，所述第二电容的第二端与所述第三节点相连。
  11. 根据权利要求4所述的移位寄存器，其中，所述第二上拉控制子电路包括第八晶体管和第九晶体管，
    所述第八晶体管的栅极与所述第一时钟端相连，所述第八晶体管的第一极与所述第一电平端相连，所述第八晶体管的第二极与所述第四节点相连；
    所述第九晶体管的栅极与所述第一节点相连，所述第九晶体管的第一极与所述第四节点相连，所述第九晶体管的第二极与所述第一时钟端相连。
  12. 根据权利要求4或11所述的移位寄存器，还包括：第三稳压子电路，与所述第二电平端和所述第四节点相连，用于稳定所述第二电平端与所述第四节点之间的电压。
  13. 根据权利要求12所述的移位寄存器，其中，所述第三稳压子电路包括第三电容，所述第三电容的第一端与所述第四节点相连，所述第三电容的第二端与所述第二电平端相连。
  14. 根据权利要求4和11-13中任一项所述的移位寄存器，其中，所述第三上拉控制子电路包括第十晶体管，所述第十晶体管的栅极与所述第四节点相连，所述第十晶体管的第一极与所述第二电平端 相连，所述第十晶体管的第二极与所述中间输出端相连。
  15. 根据权利要求4和11-14中任一项所述的移位寄存器，其中，所述第二下拉控制子电路包括第十一晶体管、第十二晶体管和第四电容，
    所述第十一晶体管的栅极与所述第四节点相连，所述第十一晶体管的第一极与所述第四电容的第一端相连，所述第十一晶体管的第二极与所述第十二晶体管的第一极相连；
    所述第十二晶体管的栅极和所述第四电容的第二端均与所述第三节点相连，所述第十二晶体管的第二极与所述第四时钟端相连。
  16. 根据权利要求4和11-15中任一项所述移位寄存器，还包括第四上拉控制子电路，所述第四上拉控制子电路与所述第四节点、所述第二时钟端、所述第一节点和所述第二电平端相连，用于在所述第二下拉阶段响应于所述第四节点的电位和所述第二时钟端提供的第一电平信号的控制，将所述第二电平端与所述第一节点电连接。
  17. 根据权利要求16所述移位寄存器，其中，所述第四上拉控制子电路包括第十三晶体管和第十四晶体管，
    所述第十三晶体管的栅极与所述第四节点相连，所述第十三晶体管的第一极与所述第二电平端相连，所述第十三晶体管的第二极与所述第十四晶体管的第一极相连；
    所述第十四晶体管的栅极与所述第二时钟端相连，所述第十四晶体管的第二极与所述第一节点相连。
  18. 一种移位寄存器的驱动方法，
    所述移位寄存器包括：
    输入子电路，与所述移位寄存器的输入端、第一时钟端和第一节点相连；
    控制子电路，与所述第一节点、所述移位寄存器的中间输出端、 第二时钟端、第三节点、第三时钟端、提供第二电平信号的第二电平端和提供第一电平信号的第一电平端相连；
    上拉子电路，与所述中间输出端、所述移位寄存器的最终输出端和所述第二电平端相连；
    第一稳压子电路，与下级节点连接端、所述最终输出端和所述第三节点相连；
    下拉晶体管，其栅极与所述第三节点相连，第一极与所述第一电平端相连，第二极与所述最终输出端相连，
    所述驱动方法包括：
    在输入阶段，向所述第一时钟端提供第一电平信号，向所述输入端提供第一电平信号，向所述第二时钟端提供第二电平信号，向所述第三时钟端提供第一电平信号，所述输入子电路将移位寄存器的输入端与所述第一节点电连接，所述控制子电路将所述第二时钟端提供的第二电平信号传输至中间输出端并且将所述第一电平端与所述第三节点电连接；所述下拉晶体管将所述第一电平端与所述最终输出端电连接；
    在输出阶段，向所述第一时钟端提供第二电平信号，向所述第二时钟端提供第一电平信号，向所述第三时钟端提供第二电平信号，所述控制子电路将所述第二时钟端提供的第一电平信号传输至中间输出端；所述上拉子电路将所述第二电平端与所述最终输出端电连接；
    在复位阶段，向所述第一时钟端提供第二电平信号，向所述第二时钟端提供第二电平信号，向所述第三时钟端提供第一电平信号，所述第一上拉控制子电路将所述第二时钟端提供的第二电平信号传输至中间输出端；所述第一下拉控制子电路将所述第一电平端与所述第三节点电连接；所述下拉晶体管将第一电平端与最终输出端电连接；所述第一稳压子电路将所述第三节点的电位降低至低于所述第一电平端提供的第一电平信号的电平。
  19. 根据权利要求18所述的驱动方法，其中，所述移位寄存器 还包括：
    第二上拉控制子电路，与所述第一时钟端、所述第一节点、所述第一电平端和第四节点相连；
    第三上拉控制子电路，与所述第四节点、所述第二电平端和所述中间输出端相连；
    第二下拉控制子电路，与所述中间输出端、所述第三节点和第四时钟端相连；
    第三稳压子电路，与所述第二电平端和所述第四节点相连，
    所述驱动方法还包括：
    在所述输出阶段，所述第二上拉控制子电路将所述第一时钟端提供的第二电平信号传输至所述第四节点；
    并且在所述复位阶段之后：
    在第一下拉阶段，向所述第一时钟端提供第一电平信号，向所述第二时钟端提供第二电平信号，向所述第三时钟端提供第一电平信号，所述第二上拉控制子电路将所述第一电平端与所述第四节点电连接；
    在第二下拉阶段，向所述第一时钟端提供第二电平信号，向所述第二时钟端提供第一电平信号，向所述第三时钟端提供第二电平信号，所述第三稳压子电路将所述第四节点的电位保持与第一下拉阶段相同；所述第二下拉控制子电路将所述第三节点和第四时钟端之间的电压保持与之前的第一下拉阶段相同；
    其中，所述第一下拉阶段和所述第二下拉阶段交替进行。
  20. 一种栅极驱动电路，包括级联的N个移位寄存器，每个所述移位寄存器为权利要求1至17中任意一项所述的移位寄存器；
    第1至第(N-1)移位寄存器中的每一个的中间输出端与下一级移位寄存器的输入端相连，并且第1至第(N-1)移位寄存器中的每一个的下级节点连接端与下一级移位寄存器的第一节点相连。
  21. 一种显示装置，包括权利要求20所述的栅极驱动电路。
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