WO2020026516A1 - 半導体装置、焼結金属シートおよび焼結金属シートの製造方法 - Google Patents

半導体装置、焼結金属シートおよび焼結金属シートの製造方法 Download PDF

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WO2020026516A1
WO2020026516A1 PCT/JP2019/011935 JP2019011935W WO2020026516A1 WO 2020026516 A1 WO2020026516 A1 WO 2020026516A1 JP 2019011935 W JP2019011935 W JP 2019011935W WO 2020026516 A1 WO2020026516 A1 WO 2020026516A1
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sintered metal
low porosity
metal layer
region
semiconductor device
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PCT/JP2019/011935
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English (en)
French (fr)
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鈴木　智久
守谷　浩志
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株式会社日立製作所
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Priority to US17/261,715 priority Critical patent/US11437338B2/en
Publication of WO2020026516A1 publication Critical patent/WO2020026516A1/ja

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    • B22—CASTING; POWDER METALLURGY
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Definitions

  • the present invention relates to a semiconductor device, a sintered metal sheet, and a method for manufacturing a sintered metal sheet that are suitably used for power conversion equipment and the like.
  • a power module using a SiC semiconductor can operate at a high temperature of 200 ° C. or higher, and can not only increase the efficiency of power conversion but also significantly reduce the size and weight.
  • a lead-free solder conventionally used as a chip bonding material cannot be used due to a remelting problem.
  • High-melting-point solders with a lead content of 85% or more, which are currently excluded from the RoHS (Restriction of Hazardous Substances) directive will inevitably be subject to the RoHS directive in the future. Therefore, there is an urgent need to develop a substitute material for lead-free solder.
  • the bonding layer made of a sintered metal material has a porous structure including pores inside as shown in Patent Document 1, for example.
  • a semiconductor element is bonded to a substrate via a sintered metal material as disclosed in Patent Document 2, for example.
  • Patent Document 1 a sintered metal sheet prepared by preliminarily heating and temporarily sintering a metal paste material mixed with metal fine particles and an organic solvent was placed on a substrate, and a semiconductor element was mounted thereon. Thereafter, a method of heating and sintering again to join the semiconductor element to the substrate is shown. Further, in Patent Document 2, a metal paste material in which metal fine particles and an organic solvent are mixed is applied on a substrate, a semiconductor element is mounted thereon, and then the metal paste material is sintered by heating. A method for bonding to a substrate is shown.
  • the pressure during sintering may be increased to lower the porosity of the sintered metal layer.
  • the pressure during sintering is too high, the rigidity of the sintered metal layer becomes too high, which causes another problem that peripheral members such as semiconductor elements are easily damaged.
  • Patent Document 2 discloses that the porosity is low in a portion near the side of the semiconductor element and the porosity is low in a portion near the center by making a difference in the thickness of the metal paste when applying the metal paste.
  • a technique for forming a sintered metal layer having an increased surface roughness In such a sintered metal layer, the outer edge is formed hard, so that the growth of a crack from the outer edge can be suppressed.
  • Patent Document 3 discloses a technique of forming a sintered metal layer having a region with a lower porosity at a peripheral portion or a corner portion of a semiconductor element than at a central portion by using two types of metal pastes. ing.
  • Patent Document 4 discloses a sintered metal layer having a region with low porosity at its outer edge and corners by disposing a metal foam after applying a metal paste and densifying the metal foam by a sintering process. Are disclosed.
  • the porosity of the sintered metal layer is high, that is, since the gap is large, the sintered metal layer There is a problem that cracks are likely to occur from the sides and corners. Further, if the porosity of the sintered metal layer is simply reduced, stress is concentrated on the interface between the sintered metal layer and the semiconductor element, and there is a problem that separation is likely to occur at the interface.
  • Patent Document 4 also mentions a sintered metal layer having a region with a low porosity inside the outer edge portion, but the region with a low porosity is printed after printing a metal paste of a material. It is formed by a method of mounting another member (metal foam) from the upper part of the surface. For this reason, the size of the metal foam to be arranged needs to be large enough to be self-sustaining, due to the workability of the mount. That is, it is difficult to form a low porosity region with a fine pattern.
  • an object of the present invention is to provide a highly reliable semiconductor device, a sintered metal sheet, and a sintered metal capable of suppressing risks such as peeling, crack propagation, and semiconductor element destruction.
  • An object of the present invention is to provide a sheet manufacturing method.
  • the present invention is a semiconductor device in which a semiconductor element is bonded onto a support substrate via a sintered metal layer, and the sintered metal layer has an outer peripheral portion of the semiconductor element when bonded.
  • a low porosity region having a lower porosity than other regions is formed in a region corresponding to the inside.
  • a highly reliable semiconductor device a sintered metal sheet, and a method for manufacturing a sintered metal sheet that can suppress risks such as occurrence of peeling, crack propagation, and semiconductor element destruction.
  • FIG. 2 is a view showing an example of a cross-sectional structure of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 2 is a diagram illustrating an example of a top view of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 4 is a diagram showing a difference in structure between the semiconductor device according to the first embodiment of the present invention and a semiconductor device according to the related art.
  • FIG. 6 is a view showing a difference between the effects of the semiconductor device according to the first embodiment of the present invention and the semiconductor device according to the related art.
  • FIG. 1 is a view showing an example of a cross-sectional structure of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 2 is a diagram illustrating an example of a top view of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 4 is a diagram showing a difference in structure between the semiconductor device according to the first embodiment of the present invention and a semiconductor device according to the related art.
  • FIG. 6 is
  • FIG. 4 schematically shows a state in which a crack generated from an end of the sintered metal layer of the semiconductor device according to the first embodiment of the present invention propagates inside the sintered metal layer and is stopped and stopped in a low porosity region.
  • FIG. FIG. 7 is a view showing an example of a cross-sectional structure of a semiconductor device according to a second embodiment of the present invention.
  • FIG. 6 is a diagram illustrating an example of a top view of a semiconductor device according to a second embodiment of the present invention.
  • FIG. 9 is a view showing an example of a cross-sectional structure of a semiconductor device according to a third embodiment of the present invention.
  • FIG. 11 is a diagram illustrating an example of a top view of a semiconductor device according to a third embodiment of the present invention.
  • FIG. 14 is a view showing an example of a cross-sectional structure of a semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 14 is a diagram showing an example of a top view of a semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 14 is a view showing an example of a cross-sectional structure of a semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 14 is a diagram showing an example of a top view of a semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 4 is a view showing an example of a process of manufacturing a sheet of a sintered metal layer in a manufacturing process of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 4 is a diagram showing an example of a process of forming a low porosity region in a sintered metal layer and manufacturing a sintered metal sheet in a manufacturing process of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 4 is a diagram illustrating an example of a process of manufacturing a semiconductor device using a sintered metal sheet in a process of manufacturing the semiconductor device according to the first embodiment of the present invention. It is the figure which showed the example of the result which computed the temperature distribution inside the sintered metal layer at the time of the heating by energization by thermal analysis simulation.
  • FIG. 1A is a diagram showing an example of a cross-sectional structure of a semiconductor device 100 according to the first embodiment of the present invention
  • FIG. 1B is an example of a top view of the semiconductor device 100 according to the second embodiment of the present invention.
  • a semiconductor device 100 is configured by joining a semiconductor element 1 to a support substrate 10 via a sintered metal layer 2.
  • the top view of the semiconductor device 100 in FIG. 1B shows a top view in a state where the semiconductor element 1 is removed
  • the cross-sectional view in FIG. 1 shows a cross-sectional view including an element 1.
  • FIG. 1A is a diagram showing an example of a cross-sectional structure of a semiconductor device 100 according to the first embodiment of the present invention
  • FIG. 1B is an example of a top view of the semiconductor device 100 according to the second embodiment of the present invention.
  • FIG. 1A and 1B a semiconductor device 100 is configured by joining a semiconductor element 1 to a support substrate 10 via a sintered metal layer 2.
  • the semiconductor element 1 is an IGBT (Insulated Gate Bipolar Transistor) or a diode for current control, and is made of a semiconductor material such as silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).
  • a semiconductor material such as silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).
  • the semiconductor material it is preferable to use a wide band gap semiconductor such as silicon carbide (SiC) or gallium nitride (GaN) with low power loss.
  • the support substrate 10 has a three-layer structure including the conductive member 4, the insulating member 5, and the cooling member 6.
  • each of the conductive member 4 and the cooling member 6 is made of a conductive material having high electric conductivity or heat conductivity such as copper (Cu) or aluminum (Al).
  • the insulating member 5 is made of an insulating material such as aluminum nitride (AlN), silicon nitride (Si3N4), aluminum oxide (Al2O3), a resin sheet, and grease.
  • the cross-sectional structure of the semiconductor device 100 is not limited to this, and may be a structure in which the periphery of the semiconductor element 1 is covered with a sealing material.
  • a sealing material an insulating material including a thermosetting resin such as an epoxy resin and a silica filler, a silicone gel, or the like is used.
  • the support substrate 10 may be configured entirely of the conductive member 4.
  • FIG. 1A shows only a semiconductor device 100 in which one semiconductor element 1 is bonded on a support substrate 10, the semiconductor device 100 has a plurality of semiconductor elements 1 on one support substrate 10. 1 may be joined.
  • the sintered metal layer 2 is made of a sintered metal bonding material obtained by firing a paste material in which fine particles of metal such as Ag, Cu, Au, Ni, and Pt on the order of nm to ⁇ m and an organic solvent are mixed. In this case, it is preferable to use Ag or Cu as the metal fine particles of the paste.
  • the sintered metal joining material thus obtained is a porous body having a large number of pores inside.
  • a low porosity region 3 having a lower porosity than other regions is provided in the sintered metal layer 2.
  • the low porosity region 3 is made of a sintered metal bonding material obtained by sintering a paste material having the same composition as that of the sintered metal layer 2, and is characterized in that the porosity is higher than other regions.
  • the low porosity region 3 is formed along the outer edge of the semiconductor element 1 in the sintered metal layer 2 inside the outer edge of the semiconductor element 1 when joined. It is formed so as to make one round of the part.
  • the low porosity region 3 is formed so as to penetrate the sintered metal layer 2 from the upper surface to the lower surface of the sintered metal layer 2 as shown in FIG. 1A.
  • the low porosity region 3 divides the sintered metal layer 2 in plane into a high porosity region on the outside and a high vacancy region on the inside, and has a planar shape in the form of an elongated cord. It can be called a structure.
  • a low porosity region 3 does not necessarily need to be formed linearly in plan view, but may be formed in a wavy curved shape.
  • the planar shape is preferably a symmetrical pattern in order to avoid biased deformation due to stress.
  • the porosity of the low porosity region 3 is preferably higher by at least 10% than the porosity of the region of the sintered metal layer 2 other than the low porosity region 3.
  • the porosity of the region 3 is preferably less than 10%.
  • the structure in the vertical direction (z-axis direction) of the low porosity region 3 is not limited to a single layer having a constant porosity. It may be composed of layers.
  • FIG. 2A is a diagram illustrating a difference in structure between the semiconductor device 100 according to the first embodiment of the present invention and the semiconductor device 101 according to the related art
  • FIG. 2B is a diagram illustrating a semiconductor according to the first embodiment of the present invention
  • FIG. 11 is a diagram showing a difference in effect between the device 100 and a semiconductor device 101 according to the related art
  • 2A are a cross-sectional structure and a top view of the semiconductor device 100 according to the first embodiment, and are substantially the same as FIG. 1. However, the cross-sectional structure is shown as the structure of the outer edge of the semiconductor device 100.
  • 2A are a cross-sectional structure and a top view of the semiconductor device 101 according to the related art, and the cross-sectional structure is shown as a structure of an outer edge portion of the semiconductor device 101.
  • FIG. 2B shows the results of calculating and comparing the stress applied to the semiconductor element 1 in each of the semiconductor device 100 according to the first embodiment and the conventional semiconductor device 101.
  • the following conditions were set for each of the semiconductor device 100 according to the present embodiment and the semiconductor device 101 according to the related art.
  • the chip size of the semiconductor element 1 was 5 mm ⁇ 5 mm.
  • the low porosity region 3 in the sintered metal layer 2 is provided with a width of 0.2 mm just below the outer edge of the semiconductor element 1 by 1 mm inside. did.
  • the low porosity region 3 is provided at a position immediately below the outer edge of the semiconductor device 101, that is, at the outer edge of the sintered metal layer 2 with a width of 0.2 mm.
  • the sintered metal layer 2 was a sintered copper (Cu) layer having a thickness of 50 ⁇ m in each case.
  • the semiconductor element 1 is made of Si
  • the insulating member 5 is made of AlN
  • the conductive member and the cooling member are made of Cu
  • the stress distribution when a temperature change from 200 ° C. to ⁇ 40 ° C. is applied to the entire semiconductor devices 100 and 101 is finite. Calculated by element analysis.
  • the stress applied to the semiconductor element 1 is reduced to about 1 / 1.3 at the position A in the first embodiment and 1 at the position B in the first embodiment as compared with the related art. /2.1.
  • position A represents the upper and lower center position of the outer peripheral end of semiconductor element 1
  • position B is the outer peripheral end of the interface between semiconductor element 1 and sintered metal layer 2. Indicates the position.
  • the stress applied to the semiconductor element 1 is smaller than that in the related art, the damage to the semiconductor element 1 is reduced, and the risk of the semiconductor element 1 being broken is also reduced. . In addition, the risk of separation between the semiconductor element 1 and the sintered metal layer 2 is reduced.
  • FIG. 3 shows that the crack 8 generated from the end of the sintered metal layer 2 of the semiconductor device 100 according to the first embodiment propagates into the sintered metal layer 2 and is stopped and stopped in the low porosity region 3.
  • FIG. 3 is a diagram schematically showing the state of the operation.
  • the outer edge of the sintered metal layer 2 is a high porosity region, a crack is easily generated from the outer peripheral end.
  • the wall-shaped low porosity region 3 is provided at the inner position, the crack progresses. Is stopped in the low porosity region 3 and stopped.
  • FIG. 4A is a diagram showing an example of a cross-sectional structure of a semiconductor device 100a according to the second embodiment of the present invention
  • FIG. 4B is an example of a top view of the semiconductor device 100a according to the second embodiment of the present invention.
  • the semiconductor device 100a is configured by joining a semiconductor element 1 to a support substrate 10 via a sintered metal layer 2.
  • the top view of the semiconductor device 100a in FIG. 4B shows a top view in a state where the semiconductor element 1 is removed
  • the cross-sectional view in FIG. 4A shows the semiconductor in the Ya-Ya portion in the plan view in FIG. 4B. 1 shows a cross-sectional view including an element 1.
  • FIG. 4A shows a diagram showing an example of a cross-sectional structure of a semiconductor device 100a according to the second embodiment of the present invention
  • FIG. 4B is an example of a top view of the semiconductor device 100a according to the second embodiment of the present invention.
  • FIG. 4A shows a top view in a
  • the difference between the semiconductor device 100a according to the present embodiment and the semiconductor device 100 according to the first embodiment is that a sintered metal layer 2 has a low porosity region 3 provided therein. Except for this, the structures of the two are almost the same. Therefore, the following mainly describes the points different from the first embodiment.
  • the low porosity region 3 is preferably formed so as to have no corners (a circle, an ellipse, or the like) when viewed from above. This is for the purpose of avoiding stress that tends to concentrate on the corners.
  • the low porosity region 3 looks like a column when viewed from the side, the column does not need to be a straight columnar column, and may be a column having a curved surface such as a barrel type or a constricted type.
  • the pillar may be a pillar that is inclined obliquely.
  • the diameter of these columns is preferably at least larger than the diameter of the pores in the sintered metal layer 2 and smaller than the thickness of the sintered metal layer 2, for example, about 5 ⁇ m to 100 ⁇ m.
  • a plurality of columnar low porosity regions 3 are continuously formed, and the semiconductor element 1 is included in the sintered metal layer 2 which is located inside the outer edge of the semiconductor element 1 to be joined. Is formed so as to surround the region immediately below the central portion of the semiconductor element 1 along the outer edge of the semiconductor device 1.
  • the columnar low porosity regions 3 need not be formed in a line as shown in FIG. 4B, but may be formed in a plurality of lines as long as they are formed along the outer edge of the semiconductor element 1.
  • the arrangement may be a staggered arrangement or a random arrangement. However, in order to avoid bias of deformation due to stress, the planar shape of the arrangement is preferably a symmetric pattern.
  • the low porosity region 3 is made of a sintered metal bonding material obtained by sintering a paste material having the same composition as the sintered metal layer 2, and has a higher porosity than other regions.
  • the porosity of the low porosity region 3 is preferably at least 10% or more higher than the porosity of the region of the sintered metal layer 2 other than the low porosity region 3.
  • the porosity of the rate region 3 is preferably less than 10%.
  • the crack that occurs at the outer peripheral end of the sintered metal layer 2 and propagates to the inside easily hits the low porosity region 3, so that the effect of suppressing the crack growth is expected. be able to.
  • the low porosity region 3 is formed of minute columns, it has flexibility against shear deformation. Therefore, peeling at the interface with the semiconductor element 1 and damage to peripheral members including the semiconductor element 1 can be reduced.
  • the low porosity region 3 is formed of minute columns, cracks in the thickness direction are more likely to occur than cracks in the direction along the surface of the sintered metal layer 2. The thermal conductivity and electrical conductivity of the binding metal layer 2 are not impaired. Conversely, as the crack propagates in the thickness direction, the stress in the sintered metal layer 2 is alleviated, so that the effect of suppressing the generation and propagation of the subsequent crack can be expected.
  • FIG. 5A is a diagram showing an example of a cross-sectional structure of a semiconductor device 100b according to the third embodiment of the present invention
  • FIG. 5B is an example of a top view of the semiconductor device 100b according to the third embodiment of the present invention.
  • the semiconductor device 100b is configured by joining a semiconductor element 1 to a support substrate 10 via a sintered metal layer 2.
  • the top view of the semiconductor device 100b in FIG. 5B shows a top view in a state where the semiconductor element 1 is removed
  • the cross-sectional view in FIG. 5A shows the semiconductor in the Yb-Yb portion in the plan view in FIG. 5B
  • 1 shows a cross-sectional view including an element 1.
  • FIG. 5A shows a cross-sectional view including an element 1.
  • the difference between the semiconductor device 100b according to the present embodiment and the semiconductor device 100a according to the second embodiment is that the sintered metal layer 2 is a method of arranging the columnar low porosity region 3 provided in the inside 2. Except for this, the structures of the two are almost the same. Therefore, the following mainly describes the points different from the second embodiment.
  • the columnar low porosity region 3 is provided in the sintered metal layer 2.
  • the columnar low porosity region 3 is formed in the sintered metal layer 2 corresponding to immediately below four corners inside the outer edge of the semiconductor element 1 as shown in FIG. 5B. Provided.
  • the columnar low porosity region 3 is provided near the four corners of the sintered metal layer 2, thereby efficiently suppressing the growth of cracks generated at the end of the sintered metal layer 2. be able to. Further, in the present embodiment, since the number of the columnar low porosity regions 3 formed in the sintered metal layer 2 can be reduced, the steps of the manufacturing process for forming the low porosity regions 3 are simplified. The effect can be expected.
  • the number is not limited to three.
  • the low porosity region 3 may be arranged in any manner as long as it is arranged near each corner of the sintered metal layer 2.
  • the planar shape of the arrangement is preferably a symmetric pattern.
  • FIG. 6A is a diagram showing an example of a cross-sectional structure of a semiconductor device 100c according to the fourth embodiment of the present invention
  • FIG. 6B is an example of a top view of the semiconductor device 100c according to the fourth embodiment of the present invention.
  • the semiconductor device 100c is configured by joining a semiconductor element 1 to a support substrate 10 via a sintered metal layer 2.
  • the top view of the semiconductor device 100c in FIG. 6B shows a top view in a state where the semiconductor element 1 is removed
  • the cross-sectional view in FIG. 6A shows the semiconductor in the Yc-Yc portion in the plan view in FIG. 6B
  • 1 shows a cross-sectional view including an element 1.
  • the difference between the semiconductor device 100c according to the present embodiment and the semiconductor device 100a according to the second embodiment is that the sintered metal layer 2 is a method of arranging the columnar low porosity region 3 provided in the inside 2. Except for this, the structures of the two are almost the same, and therefore, the points that are different from the second embodiment will be mainly described.
  • the columnar low porosity region 3 is provided in the sintered metal layer 2.
  • the low porosity regions 3 are spread at predetermined intervals over the entire region of the sintered metal layer 2 immediately below the inner region from the outer edge of the semiconductor element 1. It is provided in such a manner. Therefore, also in the present embodiment, it is possible to expect an effect of suppressing a crack generated at an end portion of the sintered metal layer 2 from extending to the center along the surface of the sintered metal layer 2.
  • cracks generated in the sintered metal layer 2 are easily induced in the thickness direction, but the cracks in the thickness direction do not impair the thermal conductivity and the electrical conductivity of the sintered metal layer 2. .
  • the stress in the sintered metal layer 2 is alleviated, so that the effect of suppressing the subsequent generation and propagation of the crack can be expected.
  • a large number of columnar low porosity regions 3 having excellent thermal conductivity and electrical conductivity are provided over the entire region between the semiconductor element 1 and the conductive member 4 of the support substrate 10. The effect of improving the heat dissipation and electrical conductivity of the sintered metal layer 2 can be expected.
  • the columnar low porosity regions 3 need not be regularly arranged at regular intervals in the sintered metal layer 2 as shown in FIG. Whatever is done is good. However, in order to avoid bias of deformation due to stress, it is preferable that the entire arrangement be a pattern symmetrical in a plane.
  • FIG. 7A is a diagram showing an example of a cross-sectional structure of a semiconductor device 100d according to the fifth embodiment of the present invention
  • FIG. 7B is an example of a top view of the semiconductor device 100d according to the fifth embodiment of the present invention.
  • the semiconductor device 100d is configured by joining a semiconductor element 1 to a support substrate 10 via a sintered metal layer 2.
  • the top view of the semiconductor device 100d in FIG. 7B shows a top view in a state where the semiconductor element 1 is removed
  • the cross-sectional view in FIG. 7A shows the semiconductor in the Yd-Yd portion in the plan view in FIG. 7B
  • 1 shows a cross-sectional view including an element 1.
  • FIG. 7A shows a cross-sectional view including an element 1.
  • the semiconductor device 100d according to the present embodiment is different from the semiconductor device 100 according to the first embodiment.
  • a semiconductor device 100c according to the fourth embodiment That is, in the present embodiment, in the sintered metal layer 2, the wall-shaped low porosity region 3a and the columnar low porosity region 3b are provided.
  • the wall-shaped low porosity region 3a is formed in the sintered metal layer 2 which is located inside the outer edge of the semiconductor element 1 to be joined, as in the first embodiment. It is formed so as to surround a region just below the center of the semiconductor element 1 along the outer edge. Further, the columnar low porosity region 3b is formed in the sintered metal layer 2 at a position closer to the center than the wall-like low porosity region 3a.
  • FIG. 8A is a diagram showing an example of a process of manufacturing a sheet of the sintered metal layer 2 in the manufacturing process of the semiconductor device 100 according to the first embodiment of the present invention
  • FIG. FIG. 8C shows an example of a process of forming the low porosity region 3 therein and manufacturing the sintered metal sheet 20
  • FIG. 8C shows an example of a process of manufacturing the semiconductor device 100 using the sintered metal sheet 20.
  • FIG. Here, for convenience of explanation, a sintered metal sheet 20 in which a low porosity region 3 is formed in a sintered metal layer 2 is referred to as a sintered metal sheet 20, and a sintered metal sheet before the low porosity region 3 is formed is a sintered metal sheet.
  • a sheet of layer 2 in general, both should be called sintered metal sheets.
  • a paste material 21 prepared by mixing fine metal particles of several tens nm to several hundreds nm and an organic solvent is applied on the plate 11 in a sheet shape by a screen printing method, a dispensing method, or the like. Subsequently, the applied paste material 21 is baked at about 70 ° C. to 400 ° C. and removed from the plate 11 to obtain a sheet of the sintered metal layer 2.
  • a portion of the sheet of the sintered metal layer 2 where the low porosity region 3 is to be formed is locally heated. Heating in this case can be realized by local heating by a heater, local energization, local pressurization, and the like.
  • the heating, energizing, and pressing jigs corresponding to the planar shape of the low porosity region 3 shown in the first to fifth embodiments are used, so that the desired metal is formed in the sintered metal layer 2.
  • the low porosity region 3 can be formed.
  • FIG. 8B a method of heating by local energization is shown. That is, the electrodes 9 are arranged on the upper and lower surfaces of the sintered metal layer 2 at positions corresponding to the planar shape in which the low porosity region 3 is to be formed, and the sintered metal layers 2 located between the upper and lower electrodes 9 are arranged. Is energized to the region 31 in the inside. By this energization, the region 31 of the sintered metal layer 2 sandwiched between the upper and lower electrodes 9 is heated at a temperature higher than the sintering temperature of the sintered metal layer 2. As a result, sintering locally proceeds in the region 31 of the sintered metal layer 2 sandwiched between the upper and lower electrodes 9, and the sintered metal sheet 20 having the low porosity region 3 is manufactured.
  • the electrodes 9 are applied to the upper and lower electrodes 9 one by one for each of the plurality of columnar low porosity regions 3. You may energize while.
  • a plurality of electrodes 9 corresponding to the plurality of low porosity regions 3 are provided above and below the plurality of columnar low porosity regions 3, and the plurality of upper and lower electrodes 9 are energized at once. Is also good.
  • the wall-shaped low porosity region 3 for example, the wall-shaped electrode 9 as shown in FIG. May be formed.
  • the region 31 in the sintered metal layer 2 is heated by energization using the upper and lower electrodes 9 to form the low porosity region 3 has been described. Instead, heat generated by a local heater or heat generated by a local pressurization may be used.
  • the temperature for forming the low porosity region 3 is preferably 200 ° C. or more when the sintered metal layer 2 is sintered silver and 350 ° C. or more when the sintered metal layer 2 is sintered copper.
  • a major feature of the process for manufacturing the sintered metal sheet 20 described above is that the entire sintered metal sheet 20 having the low porosity region 3 can be formed of the same material. That is, since the low porosity region 3 is made of the same material as that of the sintered metal layer 2, problems such as poor joining and peeling due to different materials do not occur. Further, advantages such as simplification of the process of manufacturing the sintered metal sheet 20 can be expected.
  • the sintered metal sheet 20 is disposed on the conductive member 4 of the support substrate 10, and the semiconductor element 1 is further disposed thereon, in a high-temperature atmosphere of about 200 ° C. to 400 ° C. Then, the sintered metal sheet 20 is sintered and bonded to the semiconductor element 1 and the supporting substrate 10. At this time, in order to obtain good sinter bonding, it is preferable to apply a pressure of 0.01 MPa or more simultaneously with the heating. Further, it is preferable to select an appropriate atmosphere, such as in the air, N2, or H2, according to the metal fine particles used at that time.
  • FIGS. 8A to 8C illustrate the manufacturing process of the semiconductor device 100 according to the first embodiment, the description is based on the manufacturing processes of the semiconductor devices 100a to 100d according to the second to fifth embodiments. The same can be applied to the process.
  • FIG. 9 is a diagram showing a result of calculating a temperature distribution inside the sintered metal layer 2 at the time of heating by energization by a thermal analysis simulation.
  • the thermal analysis simulation in this case is based on a two-dimensional axisymmetric model. Therefore, the calculation result corresponds to a temperature distribution when the columnar low porosity region 3 is formed.
  • the thickness of the sheet of the sintered metal layer 2 was set to 50 ⁇ m, and the diameter of the energized region of the electrode 9 was set to 6 ⁇ m, and the temperature distribution inside the sintered metal layer 2 due to heat generation during energization was calculated.
  • FIG. 9 shows the calculated temperature distribution in the form of an isotherm. In this case, the horizontal axis represents the distance from the center of the circular electrode 9 and the vertical axis represents the position of the sintered metal layer 2 in the thickness direction.
  • the region where the temperature is 200 ° C. or higher is a columnar region having a diameter of about 40 ⁇ m, and that a neck is formed at the center in the thickness direction. Therefore, for example, in the case of a material whose sintering starts at 200 ° C. or higher, the low porosity region 3 is formed in such a columnar region.
  • the low porosity region 3 is formed as a fine structure or pattern which has been conventionally difficult. It can be formed in the sintered metal layer 2. Therefore, in the semiconductor device 100 manufactured using the sintered metal layer 2 (sintered metal sheet 20) in which the low porosity region 3 is formed, it is easy to disperse the stress in the sintered metal layer 2, A structure capable of preventing the occurrence and progress of cracks and peeling is realized.
  • the present invention is not limited to the embodiment and the modified examples described above, and includes various modified examples.
  • the above-described embodiments and modified examples have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described above.
  • a part of the configuration of an embodiment or a modified example can be replaced with the configuration of another embodiment or a modified example. Can be added.
  • the configuration included in another embodiment or modification can be added, deleted, or replaced.

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Abstract

半導体素子を支持基板に接合する焼結金属層における剥離の発生、亀裂の進展、半導体素子破壊などのリスクを減少させる。そのため、半導体素子（１）が焼結金属層（２）を介して支持基板（１０）の上に接合されてなる半導体装置（１００）において、焼結金属層（２）には、接合されたときの半導体素子（１）の外縁部よりも内側に当たる領域に、空孔率が他の領域よりも低い低空孔率領域（３）が形成される。この低空孔率領域（３）は、例えば、平面形状が細長紐状で、焼結金属層２を上面側から下面側まで貫く壁状の構造体として形成され、半導体素子（１）の外縁部に沿って、半導体素子（１）の中央部直下の領域を取り囲むように形成される。

Description

半導体装置、焼結金属シートおよび焼結金属シートの製造方法
　本発明は、電力変換機器などに好適に用いられる半導体装置、焼結金属シートおよび焼結金属シートの製造方法に関する。
　近年、電気自動車や鉄道をはじめ幅広い分野で、インバータなど電力変換機器用途のパワーモジュールの市場拡大が続いている。そして、環境保護や省エネに対する意識の高まりを背景として、パワーモジュールには電力変換のさらなる高効率化が求められている。しかしながら、Ｓｉ半導体を用いたパワーモジュールでは、電力変換の効率向上の限界が見えてきており、電力変換のさらなる高効率化を目指して、ＳｉＣ半導体などを用いた次世代パワーモジュールの開発が進められている。
　ＳｉＣ半導体を用いたパワーモジュールでは、２００℃以上の高温動作が可能となり、電力変換の高効率化のみならず、大幅な小型化・軽量化が可能となる。一方、２００℃以上の高温環境下では、従来チップ接合材として使用されてきた鉛フリーはんだは、再溶融の問題から使用できなくなるという問題が生じる。また、現在はＲｏＨＳ（Restriction of Hazardous Substances）指令から除外されている鉛含有率８５％以上の高融点はんだも、将来的にはＲｏＨＳ指令の対象となるのは必至である。そのため、鉛フリーはんだの代替材料の開発が急務となっている。
　鉛フリーはんだの代替材料としては、ｎｍ～μｍオーダの金属粒子を焼結させた焼結金属接合材に期待が集まっており、銀（Ａｇ）や銅（Ｃｕ）を用いた焼結接合技術に関して開発が進められている。焼結金属材による接合層は、例えば特許文献１に示されているように内部に空孔を含んだ多孔質構造となる。また、電力変換用などのパワーモジュールでは、例えば特許文献２に示されているように、焼結金属材を介して半導体素子を基板に接合することが行われている。
　さらに、特許文献１には、金属微粒子と有機溶剤とを混合した金属ペースト材を事前に加熱、仮焼結させて作成した焼結金属シートを基板に設置し、その上に半導体素子を搭載した後、再度加熱、焼結させて、半導体素子を基板に接合する方法が示されている。また、特許文献２には、金属微粒子と有機溶剤とを混合した金属ペースト材を基板上に塗布し、その上に半導体素子を搭載した後、加熱により金属ペースト材を焼結させ、半導体素子を基板に接合する方法が示されている。
　ところで、とくにパワーモジュールなどでは、半導体素子の稼働や環境温度などによる熱サイクルが繰り返されると、両者の熱膨張係数差により半導体素子と焼結金属層には熱ひずみが生じる。これにより、焼結金属層の端部に亀裂（クラック）が生じ、その亀裂が焼結金属層の面内方向に進展する。その結果、焼結金属層が熱伝導や電気伝導の機能を喪失することとなり、パワーモジュールが故障に至るという問題が生じる。
　焼結金属層に亀裂が生じにくいようにするには、焼結時の加圧を高くして焼結金属層の空孔率を低くすればよい。しかしながら、焼結時の加圧を高くし過ぎると焼結金属層の剛性が高くなりすぎ、半導体素子などの周辺部材にダメージが及び易くなるという別の問題が生じる。
　これらの問題に対し、特許文献２には、金属ペースト塗布時に塗布の厚さに差をつけることにより、半導体素子の側部に近い部分で空孔率が低く、中央に近い部分で空孔率が高くなる焼結金属層を形成する技術が開示されている。このような焼結金属層では、その外縁端部が硬く形成されるので、外縁端部からの亀裂の進展を抑制することができる。また、特許文献３には、２種類の金属ペーストを用いることで、半導体素子の周辺部や角部に中央部よりも空孔率の低い領域を有する焼結金属層を形成する技術が開示されている。また、特許文献４には、金属ペーストを塗布後に金属発泡体を配置し、これを焼結プロセスで緻密化させることにより、外縁部や角部に空孔率の低い領域を有する焼結金属層の形成技術が開示されている。
特開２０１０－２４８６１７号公報 特開２０１５－２１６１６０号公報 国際公開第２０１４／１５５６１９号 特開２０１５－１８５５５９号公報
　以上のように、半導体素子を基板に接合する接合部材として焼結金属層を用いた場合には、焼結金属層の空孔率が高いため、つまり隙間が大きいために、焼結金属層の側部や角部から亀裂が生じやすいという問題がある。また、焼結金属層の空孔率を単純に低くするだけでは、焼結金属層と半導体素子との界面には応力が集中し、その界面で剥離が生じやすくなるという問題がある。
　これらの問題解決のために、特許文献２～４に開示された焼結金属層においては、半導体素子の外縁部の直下部分に空孔率の低い領域を設ける構造が提案されている。しかしながら、この場合には、半導体素子の外縁部が受ける応力が増大する。この応力の増大により、半導体素子の外縁部で焼結金属層が剥離し易くなるだけでなく、半導体素子自身の破壊のリスクが増大することが問題となる。
　なお、特許文献４には、外縁部より内側に空孔率の低い領域を有する焼結金属層にも言及されているが、その空孔率の低い領域は、材料の金属ペーストを印刷後に印刷面の上部から別の部材（金属発泡体）をマウントする方法により形成される。そのため、マウントの作業性の問題から、配置される金属発泡体のサイズは、自立可能な程度に大きい必要がある。つまり、空孔率の低い領域を微細なパターンで形成することは難しい。
　以上の従来技術の問題に鑑み、本発明の目的は、剥離の発生、亀裂の進展、半導体素子破壊などのリスクを抑制することが可能な高信頼の半導体装置、焼結金属シートおよび焼結金属シートの製造方法を提供することにある。
　本発明は、半導体素子が焼結金属層を介して支持基板の上に接合されてなる半導体装置であって、前記焼結金属層には、接合されたときの前記半導体素子の外縁部よりも内側に当たる領域に、空孔率が他の領域よりも低い低空孔率領域が形成されていることを特徴とする。
　本発明によれば、剥離の発生、亀裂の進展、半導体素子破壊などのリスクを抑制することが可能な高信頼の半導体装置、焼結金属シートおよび焼結金属シートの製造方法が提供される。
本発明の第１の実施形態に係る半導体装置の断面構造の例を示した図。 本発明の第１の実施形態に係る半導体装置の上面図の例を示した図。 本発明の第１の実施形態に係る半導体装置と従来技術に係る半導体装置との構造の相違を示した図。 本発明の第１の実施形態に係る半導体装置と従来技術に係る半導体装置との効果の相違を示した図。 本発明の第１の実施形態に係る半導体装置の焼結金属層の端部から発生した亀裂が焼結金属層の内部に進展し、低空孔率領域で阻止されて停止する様子を模式的に示した図。 本発明の第２の実施形態に係る半導体装置の断面構造の例を示した図。 本発明の第２の実施形態に係る半導体装置の上面図の例を示した図。 本発明の第３の実施形態に係る半導体装置の断面構造の例を示した図。 本発明の第３の実施形態に係る半導体装置の上面図の例を示した図。 本発明の第４の実施形態に係る半導体装置の断面構造の例を示した図。 本発明の第４の実施形態に係る半導体装置の上面図の例を示した図。 本発明の第５の実施形態に係る半導体装置の断面構造の例を示した図。 本発明の第５の実施形態に係る半導体装置の上面図の例を示した図。 本発明の第１の実施形態に係る半導体装置の製造工程において、焼結金属層のシートを作製する工程の例を示した図。 本発明の第１の実施形態に係る半導体装置の製造工程において、焼結金属層の中に低空孔率領域を形成し、焼結金属シートを作製する工程の例を示した図。 本発明の第１の実施形態に係る半導体装置の製造工程において、焼結金属シートを用いて半導体装置製造する工程の例を示した図。 通電による加熱の際の焼結金属層内部の温度分布を熱解析シミュレーションで計算した結果の例を示した図である。
　以下、本発明の実施形態について、図面を参照して詳細に説明する。なお、各図面において、共通する構成要素には同一の符号を付し、重複した説明を省略する。
≪第１の実施形態≫
　図１Ａは、本発明の第１の実施形態に係る半導体装置１００の断面構造の例を示した図、図１Ｂは、本発明の第２の実施形態に係る半導体装置１００の上面図の例を示した図である。図１Ａ、図１Ｂに示すように、半導体装置１００は、半導体素子１が焼結金属層２を介して支持基板１０に接合されて構成される。ここで、図１Ｂの半導体装置１００の上面図は、半導体素子１が取り外されている状態の上面図を表し、また、図１Ａの断面図は、図１Ｂの平面図のＹ－Ｙ部分の半導体素子１を含む断面図を表している。
　半導体素子１は、電流制御用のＩＧＢＴ（Insulated Gate Bipolar Transistor）やダイオードなどであり、シリコン（Ｓｉ）や炭化シリコン（ＳｉＣ）、窒化ガリウム（ＧａＮ）などの半導体材料により構成されている。この場合、半導体材料としては、電力損失の低い炭化シリコン（ＳｉＣ）、窒化ガリウム（ＧａＮ）などのワイドバンドギャップ半導体を用いることが好ましい。
　支持基板１０は、導電部材４、絶縁部材５および冷却部材６からなる３層の積層構造を有している。ここで、導電部材４および冷却部材６は、いずれも銅（Ｃｕ）やアルミニウム（Ａｌ）などの電気伝導度や熱伝導度の高い導電材料により構成されている。また、絶縁部材５は、窒化アルミニウム（ＡｌＮ）、窒化シリコン（Ｓｉ３Ｎ４）、酸化アルミニウム（Ａｌ２Ｏ３）、樹脂シート、グリースなどの絶縁材料によって構成される。
　なお、半導体装置１００の断面構造は、これに限定されるものではなく、半導体素子１の周囲が封止材で覆われた構造などであってもよい。その場合、封止材としては、エポキシ樹脂などの熱硬化性樹脂とシリカフィラーからなる絶縁材料やシリコーンゲルなどが用いられる。また、支持基板１０は、全体が導電部材４だけで構成されるものであってもよい。また、図１Ａには、半導体装置１００として、支持基板１０上に１つの半導体素子１が接合されたものしか示されていないが、半導体装置１００は、１つの支持基板１０上に複数の半導体素子１が接合されたものであってもよい。
　焼結金属層２は、Ａｇ，Ｃｕ，Ａｕ，Ｎｉ，Ｐｔなどのｎｍ～μｍオーダの金属微粒子と有機溶剤とを混合したペースト材を焼成して得られる焼結金属接合材によって構成される。この場合、ペーストの金属微粒子としては、ＡｇやＣｕを用いることが好ましい。なお、こうして得られる焼結金属接合材は、内部に多数の空孔を有する多孔質体となっている。
　本実施形態では、焼結金属層２の中に他の領域よりも空孔率の低い領域である低空孔率領域３が設けられている。低空孔率領域３は、焼結金属層２と同じ組成のペースト材を焼結した焼結金属接合材からなり、空孔率が他の領域よりも高いことを特徴とする。この低空孔率領域３は、図１Ｂに示すように、接合されたときの半導体素子１の外縁部よりも内側に当たる焼結金属層２の中に、半導体素子１の外縁部に沿ってその外縁部を１周するように形成される。また、低空孔率領域３は、図１Ａに示すように、焼結金属層２の上面部から下面部まで焼結金属層２を貫くように形成される。
　したがって、本実施形態では、低空孔率領域３は、焼結金属層２を平面的に外側の高空孔領域と内側の高空孔領域に２分する、平面形状が細長紐状を呈する壁状の構造体ということができる。このような低空孔率領域３は、平面的には、必ずしも直線状に形成される必要はなく、うねりのある曲線状に形成されたものであってもよい。ただし、その平面形状は、応力による変形の偏りを避けるために、対称的なパターンであることが好ましい。
　なお、低空孔率領域３の空孔率は、低空孔率領域３以外の焼結金属層２における領域の空孔率と比べて少なくとも１０％以上高いことが好まく、さらには、低空孔率領域３の空孔率が１０％未満であることが好ましい。また、低空孔率領域３の上下方向（ｚ軸方向）の構造は、空孔率が一定の１層に限定されるものではなく、例えば、空孔率が続的に変化するような多数の層から構成されものであってもよい。
　図２Ａは、本発明の第１の実施形態に係る半導体装置１００と従来技術に係る半導体装置１０１との構造の相違を示した図、図２Ｂは、本発明の第１の実施形態に係る半導体装置１００と従来技術に係る半導体装置１０１との効果の相違を示した図である。
　なお、図２Ａの左側上段および下段の図は、第１の実施形態に係る半導体装置１００の断面構造および上面図であり、実質的には、図１と同じ図である。ただし、その断面構造は、半導体装置１００の外縁部の構造として示されている。また、図２Ａの右側上段および下段の図は、従来技術に係る半導体装置１０１の断面構造および上面図であり、その断面構造は、半導体装置１０１の外縁部の構造として示されている。
　図２Ｂには、第１の実施形態に係る半導体装置１００および従来の半導体装置１０１のそれぞれにおける半導体素子１が受ける応力を計算して比較した結果が示されている。この応力の計算では、本実施形態に係る半導体装置１００および従来技術に係る半導体装置１０１のそれぞれに対し、次のような条件を設定した。
　図２Ａに示すように、第１の実施形態および従来技術のいずれの場合も、半導体素子１のチップサイズを５ｍｍ×５ｍｍとした。また、第１の実施形態では、焼結金属層２内の低空孔率領域３は、半導体素子１の外縁部よりも１ｍｍ内側の直下位置に、０．２ｍｍの幅で設けられているものとした。これに対し、従来技術では、低空孔率領域３は、半導体装置１０１の外縁部直下の位置、つまり焼結金属層２の外縁部に０．２ｍｍの幅で設けられているものとした。また、焼結金属層２は、いずれの場合も厚さ５０μｍの焼結銅（Ｃｕ）層であるとした。
　さらに、半導体素子１はＳｉ、絶縁部材５はＡｌＮ、導電部材および冷却部材はＣｕであるとし、半導体装置１００，１０１全体に２００℃から－４０℃の温度変化を与えた際の応力分布を有限要素解析によって計算した。
　その計算の結果、半導体素子１が受ける応力は、図２Ｂに示されているように、第１の実施形態では従来技術に比べ位置Ａで約１／１．３に減少し、位置Ｂで１／２．１に減少した。なお、図２Ａに示されているように、位置Ａは、半導体素子１の外周端部の上下中央位置を表し、位置Ｂは、半導体素子１と焼結金属層２との界面の外周端部位置を表している。
　以上に説明したように、本実施形態では、従来技術に比べて半導体素子１が受ける応力が小さくなるので、半導体素子１が受けるダメージが減少し、さらには半導体素子１が破壊するリスクも減少する。また、半導体素子１と焼結金属層２との剥離のリスクも減少する。
　図３は、第１の実施形態に係る半導体装置１００の焼結金属層２の端部から発生した亀裂８が焼結金属層２の内部に進展し、低空孔率領域３で阻止されて停止する様子を模式的に示した図である。本実施形態では、焼結金属層２の外縁部が高空孔率領域となるため、外周端部から亀裂が生じやすくなる。しかしながら、焼結金属層２の外周端部から亀裂が発生じ、内部へ進展して行っても、その内側の位置に壁状の低空孔率領域３が設けられているため、その亀裂の進展は、低空孔率領域３で阻止されて停止することになる。これは、低空孔率領域３では、空孔の密度が低く金属組織が緻密になるため、亀裂が進展しにくくなるためである。したがって、本実施形態では、焼結金属層２の端部で生じる亀裂が中央部へ進展するのを抑制する効果を期待することができる。
　以上のように、本実施形態では、従来技術に比べ、熱変動に由来する応力により半導体素子１と焼結金属層２とが剥離したり、半導体素子１が破壊などのダメージを受けたりするリスクが減少する。また、焼結金属層２の端部から発生する亀裂も、低空孔率領域３が設けられた位置で停止させることができる。よって、本実施形態では、熱変動に強い信頼性の高い半導体素子１が得られる。
≪第２の実施形態≫
　図４Ａは、本発明の第２の実施形態に係る半導体装置１００ａの断面構造の例を示した図、図４Ｂは、本発明の第２の実施形態に係る半導体装置１００ａの上面図の例を示した図である。図４Ａ、図４Ｂに示すように、半導体装置１００ａは、半導体素子１が焼結金属層２を介して支持基板１０に接合されて構成される。ここで、図４Ｂの半導体装置１００ａの上面図は、半導体素子１が取り外されている状態の上面図を表し、また、図４Ａの断面図は、図４Ｂの平面図のＹａ－Ｙａ部分の半導体素子１を含む断面図を表している。
　図４Ａ、図４Ｂと図１Ａ、図１Ｂとを比較すれば容易に分かるように、本実施形態に係る半導体装置１００ａと第１の実施形態に係る半導体装置１００との相違は、焼結金属層２の中に設けられた低空孔率領域３の形状にある。このことを除けば、両者の構造は、ほぼ同じであるので、以下、主に、第１の実施形態と相違する事項について説明する。
　図４Ｂに示すように、本実施形態では、低空孔率領域３は、好ましくは上面から見たときに角部のない形状（円形や楕円形など）となるように形成される。これは、応力が角部に集中しやすいので、これを避けることを目的としたものである。また、低空孔率領域３は、側面から見ると柱状に見えるが、その柱は、真直な円柱状の柱でなくともよく、樽型やくびれ型など曲面を有する柱でもあってもよい。また、その柱は、斜めに傾斜した柱などであってもよい。なお、これらの柱の径は、少なくとも焼結金属層２内の空孔の径よりも大きく、焼結金属層２の厚さより小さい、例えば、５μｍ～１００μｍ程度とするのが好ましい。
　本実施形態では、図４Ｂに示すように、柱状の低空孔率領域３が複数個連なって、接合される半導体素子１の外縁部よりも内側に当たる焼結金属層２の中に、半導体素子１の外縁部に沿って半導体素子１の中央部直下の領域を取り囲むように形成される。この際、柱状の低空孔率領域３は、図４Ｂのように１列に並んで形成される必要はなく、半導体素子１の外縁部に沿って形成されていれば、複数列であったり、千鳥配置であったり、ランダムな配置であってもよい。ただし、応力による変形の偏りを避けるために、その配置の平面形状は、対称的なパターンであることが好ましい。
　また、本実施形態でも、低空孔率領域３は、焼結金属層２と同じ組成のペースト材を焼結した焼結金属接合材からなり、空孔率が他の領域よりも高いことを特徴とする。この場合、低空孔率領域３の空孔率は、低空孔率領域３以外の焼結金属層２の領域における空孔率と比べて少なくとも１０％以上高いことが好まく、さらには、低空孔率領域３の空孔率が１０％未満であることが好ましい。
　以上、本実施形態によれば、焼結金属層２の外周端部で発生し、内部へ進展する亀裂は、低空孔率領域３に突き当たり易くなるので、亀裂の進展を抑制する効果を期待することができる。また、低空孔率領域３が微小な柱からなることで、せん断変形に対して柔軟性を有することとなる。そのため、半導体素子１との界面における剥離や、半導体素子１を含む周辺部材へのダメージを低減させることができる。さらに、低空孔率領域３が微小な柱からなることで、焼結金属層２の面に沿った方向の亀裂よりも厚さ方向の亀裂が生じやすくなるが、厚さ方向の亀裂は、焼結金属層２の熱伝導性や電気伝導性を損なわない。逆に、厚さ方向に亀裂が進展することで、焼結金属層２における応力が緩和されるため、後続する亀裂の発生や進展が抑制されるという効果も期待することができる。
≪第３の実施形態≫
　図５Ａは、本発明の第３の実施形態に係る半導体装置１００ｂの断面構造の例を示した図、図５Ｂは、本発明の第３の実施形態に係る半導体装置１００ｂの上面図の例を示した図である。図５Ａ、図５Ｂに示すように、半導体装置１００ｂは、半導体素子１が焼結金属層２を介して支持基板１０に接合されて構成される。ここで、図５Ｂの半導体装置１００ｂの上面図は、半導体素子１が取り外されている状態の上面図を表し、また、図５Ａの断面図は、図５Ｂの平面図のＹｂ－Ｙｂ部分の半導体素子１を含む断面図を表している。
　　図５Ａ、図５Ｂと図４Ａ、図４Ｂとを比較すれば容易に分かるように、本実施形態に係る半導体装置１００ｂと第２の実施形態に係る半導体装置１００ａとの相違は、焼結金属層２の中に設けられた柱状の低空孔率領域３の配置の仕方にある。このことを除けば、両者の構造は、ほぼ同じであるので、以下、主に、第２の実施形態と相違する事項について説明する。
　本実施形態でも、第２の実施形態と同様に、焼結金属層２の中に柱状の低空孔率領域３が設けられる。ただし、本実施形態では、この柱状の低空孔率領域３は、図５Ｂに示すように、半導体素子１の外縁部より内側の４つの角部近傍直下に相当する焼結金属層２の中に設けられる。
　これは、焼結金属層２が矩形である場合、焼結金属層２の中で発生する亀裂は、応力が集中しがちな４つの角部で発生するケースが多いことを考慮したものである。すなわち、本実施形態では、柱状の低空孔率領域３を焼結金属層２の４つの角部近傍に設けることにより、焼結金属層２の端部で発生する亀裂の進展を効率よく抑制することができる。また、本実施形態では、焼結金属層２の中に形成される柱状の低空孔率領域３の数が少なくて済むので、低空孔率領域３を形成する製造プロセスの工程が簡便になるという効果を期待することができる。
　なお、図５Ｂでは、低空孔率領域３は、焼結金属層２の各角部近傍に３つずつしか設けられていないが、その数は３つに限定されない。また、低空孔率領域３は、焼結金属層２の各角部の近傍に配置されていれば、どのように配置されていてもよい。ただし、応力による変形の偏りを避けるために、その配置の平面形状は、対称的なパターンであることが好ましい。
≪第４の実施形態≫
　図６Ａは、本発明の第４の実施形態に係る半導体装置１００ｃの断面構造の例を示した図、図６Ｂは、本発明の第４の実施形態に係る半導体装置１００ｃの上面図の例を示した図である。図６Ａ、図６Ｂに示すように、半導体装置１００ｃは、半導体素子１が焼結金属層２を介して支持基板１０に接合されて構成される。ここで、図６Ｂの半導体装置１００ｃの上面図は、半導体素子１が取り外されている状態の上面図を表し、また、図６Ａの断面図は、図６Ｂの平面図のＹｃ－Ｙｃ部分の半導体素子１を含む断面図を表している。
　図６Ａ、図６Ｂと図４Ａ、図４Ｂとを比較すれば容易に分かるように、本実施形態に係る半導体装置１００ｃと第２の実施形態に係る半導体装置１００ａとの相違は、焼結金属層２の中に設けられた柱状の低空孔率領域３の配置の仕方にある。このことを除けば、両者の構造は、ほぼ同じであるので、主に、第２の実施形態と相違する事項について説明する。
　本実施形態でも、第２の実施形態と同様に、焼結金属層２の中に柱状の低空孔率領域３が設けられる。本実施形態では、この低空孔率領域３は、図６Ｂに示すように、半導体素子１の外縁部よりも内側領域の直下に当たる焼結金属層２の領域内の全域にわたって所定の間隔で敷き詰められるようにして設けられる。したがって、本実施形態でも、焼結金属層２の端部で生じる亀裂が焼結金属層２の面に沿って、中央部へ進展するのを抑制する効果を期待することができる。
　また、本実施形態では、焼結金属層２において生じる亀裂は、厚さ方向に誘導されやすくなるが、厚さ方向の亀裂は、焼結金属層２の熱伝導性や電気伝導性を損なわない。逆に、厚さ方向に亀裂が進展することで、焼結金属層２における応力が緩和されるため、その後の亀裂の発生や進展が抑制されるという効果も期待することができる。
　また、本実施形態では、半導体素子１と支持基板１０の導電部材４との間の全域にわたって熱伝導性や電気伝導性に優れた柱状の低空孔率領域３が多数設けられることになるので、焼結金属層２の放熱性や電気伝導性が向上する効果を期待することができる。
　なお、柱状の低空孔率領域３は、焼結金属層２の中において、図６Ｂのように一定の間隔で規則的に配置される必要はなく、焼結金属層２内の全域にわたって多数配置されたものであればよい。ただし、応力による変形の偏りを避けるために、その全体の配置は、平面的に対称的なパターンとなることが好ましい。
≪第５の実施形態≫
　図７Ａは、本発明の第５の実施形態に係る半導体装置１００ｄの断面構造の例を示した図、図７Ｂは、本発明の第５の実施形態に係る半導体装置１００ｄの上面図の例を示した図である。図７Ａ、図７Ｂに示すように、半導体装置１００ｄは、半導体素子１が焼結金属層２を介して支持基板１０に接合されて構成される。ここで、図７Ｂの半導体装置１００ｄの上面図は、半導体素子１が取り外されている状態の上面図を表し、また、図７Ａの断面図は、図７Ｂの平面図のＹｄ－Ｙｄ部分の半導体素子１を含む断面図を表している。
　図７Ａ、図７Ｂと、図１Ａ、図１Ｂと、図６Ａ、図６Ｂとを比較すれば容易に分かるように、本実施形態に係る半導体装置１００ｄは、第１の実施形態に係る半導体装置１００と第４の実施形態に係る半導体装置１００ｃとを折衷した構造を有している。すなわち、本実施形態では、焼結金属層２の中には、壁状の低空孔率領域３ａが設けられるとともに、柱状の低空孔率領域３ｂが設けられる。
　この場合、壁状の低空孔率領域３ａは、第１の実施形態の場合と同様に、接合される半導体素子１の外縁部よりも内側に当たる焼結金属層２の中に、半導体素子１の外縁部に沿って半導体素子１の中央部直下の領域を取り囲むように形成される。また、柱状の低空孔率領域３ｂは、焼結金属層２において、壁状の低空孔率領域３ａよりもさらに中央部側に形成される。
　したがって、本実施形態では、焼結金属層２の端部で生じる亀裂が焼結金属層２の面に沿って、中央部へ進展するのを抑制する効果を期待することができる。さらには、焼結金属層２の放熱性や電気伝導性が向上するという効果も期待することができる。
≪第６の実施形態≫
　図８Ａは、本発明の第１の実施形態に係る半導体装置１００の製造工程において、焼結金属層２のシートを作製する工程の例を示した図、図８Ｂは、焼結金属層２の中に低空孔率領域３を形成し、焼結金属シート２０を作製する工程の例を示した図、図８Ｃは、焼結金属シート２０を用いて半導体装置１００製造する工程の例を示した図である。なお、ここでは説明の便宜上、焼結金属層２の中に低空孔率領域３が形成されたもの焼結金属シート２０と呼び、低空孔率領域３が形成される前のものを焼結金属層２のシートと呼んで区別しているが、一般的には、両者ともに焼結金属シートと呼ぶべきものである。
　図８Ａの工程では、まず、数１０ｎｍ～数１００ｎｍの金属微粒子と有機溶剤とを混合して作製したペースト材２１を、スクリーン印刷法やディスペンス法などによりプレート１１上にシート状に塗布する。続いて、この塗布されたペースト材２１を７０℃～４００℃程度で焼成し、プレート１１から取り外すことにより、焼結金属層２のシートを得る。
　次に、図８Ｂの工程では、この焼結金属層２のシートについて、低空孔率領域３を形成しようとする部分を局所的に加熱する。この場合の加熱は、ヒータによる局所的な加熱、局所的な通電、局所的な加圧などにより実現することができる。また、この工程では、第１～第５の実施形態に示した低空孔率領域３の平面形状に合わせた加熱、通電、加圧用治具を用いることで、焼結金属層２の中に所望の低空孔率領域３を形成することができる。
　なお、図８Ｂの例では、局所的な通電により加熱する方法が示されている。すなわち、焼結金属層２の上面および下面の、低空孔率領域３を形成しようとする平面形状に合わせた位置に電極９を配置し、その上下の電極９間に位置する焼結金属層２内の領域３１に通電する。この通電により、上下の電極９で挟まれた焼結金属層２の領域３１を焼結金属層２の焼結温度よりも高い温度で加熱する。その結果、上下の電極９で挟まれた焼結金属層２の領域３１での焼結が局所的に進行し、低空孔率領域３を備えた焼結金属シート２０が作製される。
　なお、上下の電極９間の通電は、例えば複数の柱状の低空孔率領域３を形成するような場合には、複数の柱状の低空孔率領域３それぞれについて１つずつ上下に電極９を当てながら通電してもよい。また、複数の柱状の低空孔率領域３の上下に、その複数の低空孔率領域３それぞれに対応する複数の電極９を設け、その複数の上下の電極９間を一挙に通電するようにしてもよい。さらに、壁状の低空孔率領域３を形成するような場合には、上下の電極９の組を所定のスピードで所定のパスに従って連続的に移動させながら、例えば、図１Ｂのような壁状の低空孔率領域３ａを形成するようにしてもよい。
　また、焼結金属層２の上下に設けられる電極９の平面方向の位置を少しずらせば、焼結金属層２内において上下方向に傾斜した低空孔率領域３を形成することができる。
　以上、ここでは、上下の電極９を用いた通電により焼結金属層２内の領域３１を発熱させ、低空孔率領域３を形成する例を説明したが、その発熱の方法は、通電に限定されず、局所的なヒータによる発熱や局所的な加圧による発熱であってもよい。なお、このとき低空孔率領域３を形成するための温度は、焼結金属層２が焼結銀の場合、２００℃以上、焼結銅の場合、３５０℃以上とすることが好ましい。
　以上に説明した焼結金属シート２０を製造する工程の大きな特徴は、低空孔率領域３を備えた焼結金属シート２０全体を同一の材料で形成できることにある。すなわち、低空孔率領域３が焼結金属層２と全く同一の材料で構成されているため、材料が異なることによる接合不良や剥離などの問題が発生しない。さらには、焼結金属シート２０を製造する工程が簡単化されるなどのメリットも期待することができる。
　次に、図８Ｃに示すように、支持基板１０の導電部材４上に焼結金属シート２０を配置し、さらにその上に半導体素子１を配置し、２００℃～４００℃程度の高温の雰囲気下で焼結金属シート２０を半導体素子１と支持基板１０とに焼結接合させる。このとき、良好な焼結接合を得るためには、加熱と同時に０．０１ＭＰａ以上の加圧を行うことが好ましい。また、その際に使用する金属微粒子に合わせて、大気中、Ｎ２中、Ｈ２中など適切な雰囲気を選択するのがよい。
　以上の工程により半導体装置１００が製造される。なお、図８Ａ～図８Ｃは、第１実施形態に係る半導体装置１００の製造工程を説明するものであるが、その説明は、第２～第５の実施形態に係る半導体装置１００ａ～１００ｄの製造工程にも同様に適用することができる。
　図９は、通電による加熱の際の焼結金属層２内部の温度分布を熱解析シミュレーションで計算した結果を示した図である。この場合の熱解析シミュレーションは、２次元軸対称モデルに基づく。したがって、計算結果は、柱状の低空孔率領域３が形成される場合の温度分布に相当する。
　ここでは、焼結金属層２のシートの厚さを５０μｍ、電極９の通電領域の直径を６μｍとして通電時の発熱による焼結金属層２内部の温度分布を計算した。図９には、計算結果の温度分布が等温線の形で示されている。この場合、横軸は、円形の電極９の中心からの距離を表し、縦軸は、焼結金属層２の厚さ方向の位置を表す。
　図９によれば、２００℃以上の温度となる領域は、直径約４０μｍの柱状領域となること、また、厚さ方向中央部にはくびれが生じていることが分かる。したがって、例えば、焼結が２００℃以上で開始する材料の場合、このような柱状領域に低空孔率領域３が形成されることとなる。
　以上、本実施形態によれば、とくに上下の電極９を用いた通電による低空孔率領域３を形成する方法によれば、低空孔率領域３を、従来困難であった微細な構造やパターンとして焼結金属層２内に作り込むことが可能となる。したがって、低空孔率領域３が形成された焼結金属層２（焼結金属シート２０）を用いて製造された半導体装置１００では、焼結金属層２における応力を分散させることが容易になり、亀裂や剥離の発生、進展を防止可能な構造が実現される。
　なお、本発明は、以上に説明した実施形態および変形例に限定されるものではなく、さらに、様々な変形例が含まれる。例えば、前記した実施形態および変形例は、本発明を分かりやすく説明するために詳細に説明したものであり、必ずしも説明した全ての構成を備えるものに限定されるものではない。また、ある実施形態や変形例の構成の一部を、他の実施形態や変形例の構成に置き換えることが可能であり、また、ある実施形態や変形例の構成に他の実施形態や変形例の構成を加えることも可能である。また、各実施形態や変形例の構成の一部について、他の実施形態や変形例に含まれる構成を追加・削除・置換することも可能である。
　１　　　半導体素子
　２　　　焼結金属層
　３　　　低空孔率領域
　３ａ　　壁状の低空孔率領域
　３ｂ　　柱状の低空孔率領域
　４　　　導電部材
　５　　　絶縁部材
　６　　　冷却部材
　８　　　亀裂
　９　　　電極
　１０　　支持基板
　１１　　プレート
　２０　　焼結金属シート
　２１　　ペースト材
　１００，１００ａ，１１ｂ，１００ｃ，１００ｄ　半導体装置

Claims (11)

  1. 　半導体素子が焼結金属層を介して支持基板の上に接合されてなる半導体装置であって、
    　前記焼結金属層には、接合されたときの前記半導体素子の外縁部よりも内側に当たる領域に、空孔率が他の領域よりも低い低空孔率領域が形成されていること
    　を特徴とする半導体装置。
  2. 　請求項１に記載の半導体装置であって、
    　前記焼結金属層の前記低空孔率領域は、前記焼結金属層の前記他の領域と同じ材料で構成されていること
    　を特徴とする半導体装置。
  3. 　請求項１に記載の半導体装置であって、
    　前記焼結金属層の中には、前記低空孔率領域として、前記焼結金属層を上面側から下面側まで貫き、平面形状が細長紐状を呈する壁状の低空孔率領域が形成されており、
    　前記壁状の低空孔率領域は、前記半導体素子の外縁部に沿って、前記半導体素子の中央部直下の領域を取り囲むように形成されていること
    　を特徴とする半導体装置。
  4. 　請求項１に記載の半導体装置であって、
    　前記焼結金属層の中には、前記低空孔率領域として、前記焼結金属層を上面側から下面側まで貫く柱状の低空孔率領域が形成されており、
    　前記柱状の低空孔率領域は、複数個、前記半導体素子の外縁部に沿って、前記半導体素子の中央部直下の領域を取り囲むように形成されていること
    　を特徴とする半導体装置。
  5. 　請求項１に記載の半導体装置であって、
    　前記焼結金属層の中には、前記低空孔率領域として、前記焼結金属層を上面側から下面側まで貫く柱状の低空孔率領域が形成されており、
    　前記柱状の低空孔率領域は、複数個、前記半導体素子の角部近傍の直下に当たる位置に形成されていること
    　を特徴とする半導体装置。
  6. 　請求項１に記載の半導体装置であって、
    　前記焼結金属層の中には、前記低空孔率領域として、前記焼結金属層を上面側から下面側まで貫く柱状の低空孔率領域が形成されており、
    　前記柱状の低空孔率領域は、複数個、前記半導体素子の外縁部よりも内側部分の直下に当たる位置に形成されていること
    　を特徴とする半導体装置。
  7. 　請求項１に記載の半導体装置であって、
    　前記焼結金属層の中には、前記低空孔率領域として、前記焼結金属層を上面側から下面側まで貫き、平面形状が細長紐状を呈する壁状の低空孔率領域と、前記焼結金属層を上面側から下面側まで貫く柱状の低空孔率領域と、が形成されており、
    　前記壁状の低空孔率領域は、前記半導体素子の外縁部に沿って、前記半導体素子の中央部直下の領域を取り囲むように形成され、
    　前記柱状の低空孔率領域は、複数個、前記壁状の低空孔率領域に囲まれた内側の領域に形成されていること
    　を特徴とする半導体装置。
  8. 　半導体素子と支持基板との間に配置されて、前記半導体素子と前記支持基板とを接合する焼結金属シートであって、
    　前記半導体素子と前記支持基板とを接合したとき、前記半導体素子の外縁部よりも内側に当たる領域に、空孔率が他の領域よりも低い低空孔率領域が形成されていること
    　を特徴とする焼結金属シート。
  9. 　請求項８に記載の焼結金属シートであって、
    　前記低空孔率領域を構成する材料は、前記他の領域を構成する材料と同じであること
    　を特徴とする焼結金属シート。
  10. 　金属微粒子を含むペースト材を焼成して焼結金属シートを作製する工程と、
    　前記焼結金属シート上の所定の位置に、前記焼結金属シートを上面および下面から挟むように電極を配置し、前記電極に挟まれた前記焼結金属シートの領域に通電することにより、空孔率が他の領域よりも低い低空孔率領域を形成する工程と、
    　を有すること
    　を特徴とする焼結金属シートの製造方法。
  11. 　請求項１０に記載の焼結金属シートの製造方法であって、
    　前記低空孔率領域を形成する工程において、前記焼結金属シート上に前記電極を配置するときには、前記焼結金属シートの外縁部よりも内側の位置に配置すること
    　を特徴とする焼結金属シートの製造方法。
PCT/JP2019/011935 2018-07-30 2019-03-20 半導体装置、焼結金属シートおよび焼結金属シートの製造方法 WO2020026516A1 (ja)

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