WO2019184380A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2019184380A1
WO2019184380A1 PCT/CN2018/115177 CN2018115177W WO2019184380A1 WO 2019184380 A1 WO2019184380 A1 WO 2019184380A1 CN 2018115177 W CN2018115177 W CN 2018115177W WO 2019184380 A1 WO2019184380 A1 WO 2019184380A1
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Prior art keywords
opening
array substrate
layer
plane
active layer
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PCT/CN2018/115177
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English (en)
French (fr)
Inventor
郑在纹
王念念
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京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Priority to US16/465,791 priority Critical patent/US11127767B2/en
Publication of WO2019184380A1 publication Critical patent/WO2019184380A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133553—Reflecting elements
    • G02F1/133555—Transflectors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/02—Materials and properties organic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

Definitions

  • the present disclosure relates to the field of display panel technologies, and in particular, to an array substrate, a method for fabricating the same, and a display device.
  • an organic film layer is generally disposed between the metal layers.
  • the organic film layer needs to be annealed, and the impurity gas is easily volatilized during the annealing process, and the upper and lower layers of the organic film layer are generally provided with a passivation layer, and the impurity gas cannot be diffused. This causes it to penetrate downward and eventually diffuse to the active layer, which affects the Ion/Ioff characteristics of the TFT and may even cause TFT failure.
  • the present disclosure discloses an array substrate including a substrate, an organic film layer, and a passivation layer, the organic film layer being located between the substrate and the passivation layer;
  • the passivation layer is provided with a vent hole.
  • the array substrate includes an active layer
  • the vent hole includes a first opening
  • a distance between the orthographic projection of the first opening on a plane of the active layer and the active layer is An orthographic projection of an opening in the plane of the active layer is located in or near the area of the active layer.
  • a common electrode layer is further disposed between the organic film layer and the passivation layer in the display region.
  • the substrate of the display area further comprises a scan line and a data line arranged in a cross, the vent hole further comprising a second opening, the orthographic projection of the second opening on a plane of the scan line is located An orthographic projection of the scan line, and/or the second opening on a plane of the data line, is located on the data line.
  • an orthographic projection of the second opening on a plane of the scan line is located at an intersection of the scan line and the data line.
  • the organic film layer is provided with a third opening, and the third opening corresponds to the first opening and penetrates with the first opening.
  • the material of the active layer is indium gallium zinc oxide IGZO.
  • the vent hole has a diameter greater than or equal to 2 ⁇ m.
  • the present disclosure also discloses a display device comprising the array substrate according to any of the above.
  • the present disclosure also discloses a method for preparing an array substrate, including:
  • a vent hole is formed on the passivation layer.
  • the array substrate comprises a display area and a test area; the substrate of the display area and the test area each comprise an active layer, and the step of forming a venting hole on the passivation layer comprises:
  • the relative position of the orthographic projection of the first opening on the plane of the active layer and the active layer is a first opening at the active layer
  • the orthographic projection on the plane is located in the active layer region or in the surrounding region near the active layer.
  • the substrate of the display area further comprises a scanning line and a data line arranged in a cross, the step of forming a venting hole on the passivation layer, further comprising:
  • an orthographic projection of the second opening on a plane of the scan line is on the scan line, and/or the second opening is in the data
  • the orthographic projection on the plane of the line is located on the data line.
  • an orthographic projection of the second opening on a plane of the scan line is located at an intersection of the scan line and the data line.
  • the method further includes:
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram showing the planar structure of an array substrate of a display area according to an embodiment of the present disclosure
  • FIG. 3 is a schematic plan view showing an array substrate of a test area according to an embodiment of the present disclosure
  • FIG. 4 is a cross-sectional structural view of an array substrate of a display area along AA' according to an embodiment of the present disclosure
  • FIG. 5 is a cross-sectional structural view of an array substrate along a DD' of a test area according to an embodiment of the present disclosure
  • FIG. 6 is a cross-sectional structural view of an array substrate of a display area along BB' according to an embodiment of the present disclosure
  • FIG. 7 is a cross-sectional structural view of an array substrate of a display area along CC' according to an embodiment of the present disclosure
  • FIG. 8 is a flow chart showing the steps of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • the array substrate includes a substrate 11 , an organic film layer 12 , and a passivation layer 13 .
  • the organic film layer 12 is located between the substrate 11 and the passivation layer 13 .
  • a vent hole 14 is provided in the passivation layer 13.
  • the array substrate may include a display area and a test area.
  • a planar structure diagram of the array substrate of the display area is shown.
  • FIG. 3 is a schematic diagram showing the planar structure of the array substrate of the test area.
  • the substrate of the display area and the test area may each include a thin film transistor TFT 21 including an active layer; the substrate of the display area further includes scan lines 22 and data lines 23 arranged in a cross.
  • the surface of the passivation layer 13 facing away from the organic film layer 12 may further be provided with a pixel electrode layer 48.
  • the pixel electrode layer 48 needs to pass through the passivation layer 13 and the organic film layer.
  • the lap hole 49 on the 12 is electrically connected to the source and drain of the thin film transistor 21.
  • the venting holes 14 provided in the passivation layer 13 in this embodiment are different from the lap holes 49 for electrically connecting, but the two can be formed simultaneously. For details, refer to the description of the subsequent embodiments.
  • the EPM test is generally It is performed on the thin film transistor 21 of the test area. Therefore, the thin film transistor 21 of the test area is used to test its EPM parameters during the process to characterize the TFT characteristics of the display area.
  • the organic film layer 12 may be an insulating material disposed between the metal layer and the metal layer, and may function to insulate the metal layers or increase the pitch of the metal layers, thereby reducing the coupling capacitance between the metal layers, and thus may also be called Interlayer dielectric layer (ILD).
  • the material of the organic film layer 12 may be SiO 2 , Si 3 N 4 , aerogel, polymer material, etc., and an impurity gas is easily generated in a process such as a high-temperature annealing process.
  • the impurity of the passivation layer 13 prevents the impurity gas from being diffused outward, the impurity gas in the closed space penetrates downward, which may react with the active layer on the substrate to affect the switching characteristics of the TFT, or even cause The TFT is invalid.
  • the present embodiment provides a vent hole 14 on the passivation layer 13, which may be disposed at any position on the passivation layer 13, for example, may be disposed on the passivation layer 13 of the active layer.
  • the upper or the front projection area may also be provided with a data line on the substrate and/or a front projection area of the scan line on the passivation layer 13, and may also be disposed in the effective display area.
  • the position, size and quantity of the specific venting holes can be calculated and calculated according to the parameters of the organic film layer such as the exhaust gas amount, the annealing temperature, the time, and the film quality, which are not limited in this application.
  • the impurity gas generated in the process of the organic film layer can be discharged in time through the vent hole on the passivation layer, thereby ensuring that the characteristics of the device such as the TFT on the substrate are not affected.
  • the vent hole in the above embodiment may include a first opening 40, and the first opening 40 is orthographically projected and active on the plane of the active layer 44.
  • the relative position of layer 44 satisfies the preset condition.
  • the pre-set condition means that the orthographic projection of the first opening 40 on the plane of the active layer 44 may be located in the area of the active layer 44 or may be located in the surrounding area adjacent to the active layer 44.
  • the array substrate along the AA' direction of the display region includes a glass substrate 41, a gate line or a scan line 22, and a gate insulating layer in this order from bottom to top. 43.
  • the common electrode layer 47 disposed between the organic film layer 12 and the passivation layer 13 has a thickness of about 300-1000 angstroms, and has a conductive function, and also has the function of isolating water molecules and permeating gases, such as a material. It can be ITO or MoNb.
  • an opening may be further disposed on the common electrode layer 47 of the corresponding region of the thin film transistor 21, and the opening may penetrate the first opening 40 on the passivation layer 13; further, in the film The region corresponding to the transistor 21 may not be provided with the common electrode layer 47, so that the impurity gas is discharged in time, and the thin film transistor 21 is more effectively protected.
  • the common electrode layer 47 between the organic film layer 12 and the passivation layer 13 is not essential, and may be specifically determined according to a display mode or the like in practical applications.
  • the array substrate along the DD' direction of the test area includes a glass substrate 41, a gate line or a scan line 22, and a gate insulating layer in this order from bottom to top. 43.
  • the active layer 44, the source/drain electrodes or data lines 23, the source insulating layer 46, the organic film layer 12, and the passivation layer 13, the test region has no common electrode layer 47 and pixel electrode layer 48 as compared with the display region.
  • a third opening 51 may be disposed on the organic film layer 12 of the test area, and the third opening 51 corresponds to the first opening 40 and penetrates with the first opening 40, so that the impurity gas diffuses more fully and timely. .
  • the first openings 40 may be arranged on the passivation layer 13 at equal intervals or may be arranged at non-equal intervals; they may be arranged in the lateral direction of the plane of the passivation layer 13 and/or in the plane of the passivation layer 13. Arranged in a longitudinal direction perpendicular to the lateral direction.
  • the specific position, number, and size of the first opening 40 can be determined according to parameters such as the amount of exhaust gas and the annealing temperature, which is not specifically limited in the present application.
  • the setting manner of the first opening 40 in the display area and the test area should be kept as consistent as possible, thereby improving the consistency of the TFT characteristics of the test area and the display area, and ensuring the test.
  • the reference value of the regional TFT characteristics should be kept as consistent as possible, thereby improving the consistency of the TFT characteristics of the test area and the display area, and ensuring the test.
  • FIG. 6 a cross-sectional structure diagram of the array substrate along the BB' of the display region is shown with reference to FIG. 6, and FIG. 7 shows the array substrate of the display region.
  • the venting hole 14 may further include a second opening 61.
  • the orthographic projection of the second opening 61 on the plane of the scanning line 22 is on the scanning line 22, and/or the second opening 61 is on the plane of the data line 23.
  • the orthographic projection is located on the data line 23.
  • the orthographic projection of the second opening 61 on the plane of the scanning line 22 is distributed on the scanning line 22, or the orthographic projection on the plane of the data line 23 is distributed on the data line 23, and may also be on the scanning line 22.
  • the orthographic projections on the plane of the plane are distributed on the scan line 22 and also on the data line 23 with an orthographic projection on the plane of the data line 23.
  • the second openings 61 may be arranged at equal intervals or may be arranged at non-equal intervals; they may be arranged in the lateral direction of the plane of the passivation layer 13 and/or on the plane of the passivation layer 13
  • the transverse direction is arranged vertically in the longitudinal direction, and can be set according to requirements.
  • the orthographic projection of the second opening 61 on the plane of the scanning line 22 may also be located at the intersection of the scanning line 22 and the data line 23.
  • the material of the active layer 44 in each of the above embodiments may be indium gallium zinc oxide (IGZO), amorphous silicon, low temperature polysilicon or the like.
  • the diameter of the vent hole 14 in each of the above embodiments may be greater than or equal to 2 ⁇ m.
  • the size of the vent hole 14 can be set according to actual conditions, and is not specifically limited in the present application.
  • Another embodiment of the present application further provides a display device, including the array substrate described in any of the above embodiments.
  • Another embodiment of the present application further provides a method for preparing an array substrate.
  • the method may include:
  • Step 801 Providing a substrate on which an organic film layer and a passivation layer are sequentially formed.
  • the layer structure on the substrate can be formed by the following patterning process: film formation, formation of a specific film layer by magnetron sputtering or the like, such as a metal film, a non-metal film, and a pixel electrode; exposure development, using a PR material The PR material is exposed and developed by coating and bonding with a mask to form a specific pattern; etching is divided into Dry Etch and Wet Etch, and the film layer in the exposed region after exposure and development can be Etch, forming a necessary line for conducting and Device.
  • a specific film layer by magnetron sputtering or the like such as a metal film, a non-metal film, and a pixel electrode
  • exposure development using a PR material
  • the PR material is exposed and developed by coating and bonding with a mask to form a specific pattern
  • etching is divided into Dry Etch and Wet Etch, and the film layer in the exposed region after exposure and development can be Etch, forming a necessary line for conducting and Device.
  • Step 802 forming a vent hole on the passivation layer.
  • the process of forming the vent holes can also be formed by a series of patterning processes such as exposure development and etching described above. In practical applications, this step can be formed synchronously with the overlapping holes of the pixel electrode connected to the source and drain electrodes, and only the mask version can be modified accordingly.
  • the above preparation method may further include:
  • Step 803 forming a third opening on the organic film layer of the test area, the third opening corresponding to the first opening 40 and penetrating the first opening.
  • the organic film layer may be exposed and developed with the passivation layer on the organic film layer as a mask to form a third opening. It should be noted that step 803 is not necessary, and the process can be specifically determined according to actual conditions.
  • the array substrate may include a display area and a test area; the substrate of the display area and the test area each include an active layer, and the step 802 may further include:
  • a first opening is formed on the passivation layer, and a relative position of the orthographic projection of the first opening on the plane of the active layer and the active layer satisfies a preset condition.
  • the pre-set condition means that the orthographic projection of the first opening on the plane of the active layer may be located in the active layer region or may be located in the surrounding region near the active layer.
  • the substrate of the display area further includes a scan line and a data line that are arranged in a cross.
  • the step 802 may further include:
  • a second opening is formed in the passivation layer, the orthographic projection of the second opening on the plane of the scan line is on the scan line, and/or the orthographic projection of the second opening on the plane of the data line is on the data line.
  • the orthographic projection of the second opening on the plane of the scanning line is located at an intersection of the scanning line and the data line.
  • the embodiment of the present application provides an array substrate, a preparation method thereof, and a display device.
  • the array substrate includes a substrate, an organic film layer and a passivation layer, and the organic film layer is located between the substrate and the passivation layer.
  • the passivation layer is provided with a vent hole; through the vent hole on the passivation layer, the impurity gas generated in the process of the organic film layer can be discharged in time to ensure that the characteristics of the device such as the TFT on the substrate are not affected.

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Abstract

一种阵列基板及其制备方法、显示装置，阵列基板包括基板（11）、有机膜层（12）和钝化层（13），有机膜层位于基板和钝化层之间，钝化层上设置有透气孔（14）。

Description

阵列基板及其制备方法、显示装置
相关申请的交叉引用
本申请主张在2018年3月27日在中国提交的中国专利申请No.201810260421.6的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示面板技术领域，特别是涉及一种阵列基板及其制备方法、显示装置。
背景技术
在相关显示产品的阵列基板中，为了使金属层之间相互绝缘，或者为了降低金属层之间的耦合电容，一般在金属层之间设置有机膜层。但是，在这种产品的制作过程中需要对有机膜层进行退火处理，在退火工艺过程中容易挥发出杂质气体，而有机膜层的上下一般都设置有钝化层，杂质气体无法扩散出去，导致其向下渗透，最终扩散至有源层，对TFT的Ion/Ioff特性造成影响，甚至会导致TFT失效。
发明内容
本公开公开了一种阵列基板，包括基板、有机膜层和钝化层，所述有机膜层位于所述基板和所述钝化层之间；
其中，所述钝化层上设置有透气孔。
优选地，所述阵列基板包括有源层，所述透气孔包括第一开孔，所述第一开孔在所述有源层所在平面上的正投影与所述有源层的距离为第一开孔在有源层所在平面上的正投影位于有源层区域内或靠近有源层的周围区域。
优选地，在所述显示区域，所述有机膜层和所述钝化层之间还设置有公共电极层。
优选地，所述显示区域的基板还包括交叉排布的扫描线和数据线，所述透气孔还包括第二开孔，所述第二开孔在所述扫描线所在平面上的正投影位 于所述扫描线上，和/或所述第二开孔在所述数据线所在平面上的正投影位于所述数据线上。
优选地，所述第二开孔在所述扫描线所在平面上的正投影位于所述扫描线和所述数据线的交叉区域。
优选地，在所述测试区域，所述有机膜层上设置有第三开孔，所述第三开孔对应于所述第一开孔，且与所述第一开孔贯通。
优选地，所述有源层的材质为铟镓锌氧化物IGZO。
优选地，所述透气孔的直径大于或等于2μm。
为了解决上述问题，本公开还公开了一种显示装置，包括上述任一项所述的阵列基板。
为了解决上述问题，本公开还公开了一种阵列基板的制备方法，包括：
提供基板，在所述基板上依次形成有机膜层和钝化层；
在所述钝化层上形成透气孔。
优选地，所述阵列基板包括显示区域和测试区域；所述显示区域和所述测试区域的基板均包括有源层，在所述钝化层上形成透气孔的步骤，包括：
在所述钝化层上形成第一开孔，所述第一开孔在所述有源层所在平面上的正投影与所述有源层的相对位置为第一开孔在有源层所在平面上的正投影位于有源层区域内或位于靠近有源层的周围区域。
优选地，所述显示区域的基板还包括交叉排布的扫描线和数据线，在所述钝化层上形成透气孔的步骤，还包括：
在所述钝化层上形成第二开孔，所述第二开孔在所述扫描线所在平面上的正投影位于所述扫描线上，和/或所述第二开孔在所述数据线所在平面上的正投影位于所述数据线上。
优选地，所述第二开孔在所述扫描线所在平面上的正投影位于所述扫描线和所述数据线的交叉区域。
优选地，所述方法还包括：
在所述测试区域的有机膜层上形成第三开孔，所述第三开孔对应于所述第一开孔，且与所述第一开孔贯通。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了本公开一实施例提供的一种阵列基板的结构示意图；
图2示出了本公开一实施例提供的显示区域的阵列基板的平面结构示意图；
图3示出了本公开一实施例提供的测试区域的阵列基板的平面结构示意图；
图4示出了本公开一实施例提供的显示区域的阵列基板沿AA’的剖面结构示意图；
图5示出了本公开一实施例提供的测试区域的阵列基板沿DD’的剖面结构示意图；
图6示出了本公开一实施例提供的显示区域的阵列基板沿BB’的剖面结构示意图；
图7示出了本公开一实施例提供的显示区域的阵列基板沿CC’的剖面结构示意图；
图8示出了本公开一实施例提供的一种阵列基板的制备方法的步骤流程图；
附图标记说明：
11-基板；12-有机膜层；13-钝化层；14-透气孔；21-薄膜晶体管；22-扫描线；23-数据线；40-第一开孔；41-玻璃衬底；43-栅极绝缘层；44-有源层；46-源极绝缘层；47-公共电极层；48-像素电极层；49-搭接孔；51-第三开孔；61-第二开孔。
具体实施方式
为使本公开的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本公开作进一步详细的说明。
本申请一实施例提供了一种阵列基板，参照图1，该阵列基板包括基板11、有机膜层12和钝化层13，有机膜层12位于基板11和钝化层13之间；其中，钝化层13上设置有透气孔14。
在实际应用中，上述阵列基板可以包括显示区域和测试区域，参照图2示出了显示区域的阵列基板的平面结构示意图，图3示出了测试区域的阵列基板的平面结构示意图。
显示区域和测试区域的基板均可以包括薄膜晶体管TFT 21，薄膜晶体管21包括有源层；显示区域的基板还包括交叉排布的扫描线22和数据线23。在显示区域，钝化层13背离有机膜层12的表面还可以设置有像素电极层48，在这种结构中，参照图4，像素电极层48需要通过设置在钝化层13以及有机膜层12上的搭接孔49与薄膜晶体管21的源漏极实现电连接。值得注意的是，本实施例中在钝化层13上设置的透气孔14与实现电连接的搭接孔49不同，但二者可以同步形成，具体可以参考后续实施例的描述。
在阵列基板的制作工艺过程中，往往需要监测显示区域的TFT特性，如EPM(Electrical parameter measurement)参数等，而EPM参数是通过Prober Contact测试进行，该测试手段为损伤不可逆操作，所以EPM测试一般在测试区域的薄膜晶体管21上进行。因此，测试区域的薄膜晶体管21用于在工艺过程中通过测试其EPM参数，以表征显示区域的TFT特性。
有机膜层12可以是设置在金属层和金属层之间的绝缘材料，其作用可以使金属层间绝缘，或者增大金属层的间距，从而降低金属层之间的耦合电容，因此也可以叫做层间介质层(ILD)。有机膜层12的材质可以为SiO 2、Si 3N 4、气凝胶、高分子材料等，在工艺制程中，如高温退火过程中容易产生杂质气体。相关技术中，由于钝化层13的阻隔使杂质气体不能向外扩散，导致处于封闭空间的杂质气体向下渗透，可能会与基板上的有源层发生反应而影响TFT的开关特性，甚至导致TFT失效。
为了解决这一问题，本实施例通过在钝化层13上设置透气孔14，该透气孔14可以设置在钝化层13上的任意位置，例如，可以设置在有源层在钝化层13上的正投影区域或者正投影周围区域，还可以设置在基板上的数据线和/或扫描线在钝化层13上的正投影区域，还可以设置在有效显示区域。具 体透气孔的设置位置、大小以及数量可以根据有机膜层的排气量、退火温度、时间、膜质等参数特性模拟后计算获取，本申请对此均不作限定。
本实施例提供的阵列基板，通过钝化层上的透气孔，可以将有机膜层在工艺制程中产生的杂质气体及时排出，确保基板上的器件如TFT特性等不受影响。
为了有针对性地避免杂质气体对有源层的影响，上述实施例中的透气孔可以包括第一开孔40，该第一开孔40在有源层44所在平面上的正投影与有源层44的相对位置满足预设条件。其中，预设条件是指第一开孔40在有源层44所在平面上的正投影可以位于有源层44区域内，也可以位于靠近有源层44的周围区域。
参照图4示出了显示区域的阵列基板沿AA’的剖面结构示意图，显示区域沿AA’方向的阵列基板自下而上依次包括玻璃衬底41、栅线或扫描线22、栅极绝缘层43、有源层44、源漏电极或数据线23、源极绝缘层46、有机膜层12、公共电极层47、钝化层13以及像素电极层48。其中，设置在有机膜层12和钝化层13之间的公共电极层47的厚度大约在300-1000埃之间，具有导电功能，同时还具有隔绝水分子、透过气体的功能，例如材质可以为ITO或者MoNb等。为了进一步提高杂质气体的扩散率，在薄膜晶体管21对应区域的公共电极层47上还可以设置开孔，该开孔可以与钝化层13上的第一开孔40贯通；进一步地，在薄膜晶体管21对应的区域还可以不设置公共电极层47，以使杂质气体及时排出，更有效地保护薄膜晶体管21。需要注意的是，有机膜层12和钝化层13之间的公共电极层47不是必需的，在实际应用中可以根据显示模式等具体确定。
参照图5示出了测试区域的阵列基板沿DD’的剖面结构示意图，测试区域沿DD’方向的阵列基板自下而上依次包括玻璃衬底41、栅线或扫描线22、栅极绝缘层43、有源层44、源漏电极或数据线23、源极绝缘层46、有机膜层12以及钝化层13，与显示区域相比，测试区域没有公共电极层47和像素电极层48。测试区域的有机膜层12上还可以设置有第三开孔51，该第三开孔51对应于第一开孔40且与第一开孔40贯通，从而使杂质气体更充分及时地扩散出去。
第一开孔40在钝化层13上的排列方式可以等间距排列，也可以非等间距排列；可以是在钝化层13所在平面的横向方向上排列和/或在钝化层13所在平面上与所述横向方向垂直的纵向方向上排列。第一开孔40的具体位置、数量以及大小可以根据排气量、退火温度等参数模拟确定，本申请不作具体限定。需要注意的是，第一开孔40在显示区域和测试区域的设置方式，包括设置位置、数量以及大小等，应当尽量保持一致，这样可提高测试区域与显示区域TFT特性的一致性，确保测试区域TFT特性的参考价值。
为了进一步避免杂质气体对显示区域的扫描线22和数据线23金属层的影响，参照图6示出了显示区域的阵列基板沿BB’的剖面结构示意图，图7示出了显示区域的阵列基板沿CC’的剖面结构示意图。上述透气孔14还可以进一步包括第二开孔61，第二开孔61在扫描线22所在平面上的正投影位于扫描线22上，和/或第二开孔61在数据线23所在平面上的正投影位于数据线23上。也就是，第二开孔61在扫描线22所在平面上的正投影分布在扫描线22上，或者在数据线23所在平面上的正投影分布在数据线23上，还可以既在扫描线22所在平面上的正投影分布在扫描线22上也在数据线23所在平面上的正投影分布在数据线23上。同样，第二开孔61的排列方式可以等间距排列，也可以非等间距排列；可以是在钝化层13所在平面的横向方向上排列和/或在钝化层13所在平面上与所述横向方向垂直的纵向方向上排列，具体可以根据需求设置。第二开孔61在扫描线22所在平面上的正投影还可以位于扫描线22和数据线23的交叉区域。
上述各实施例中有源层44的材质可以为铟镓锌氧化物(IGZO)、非晶硅、低温多晶硅等。
上述各实施例中透气孔14的直径可以大于或等于2μm。透气孔14的大小可以根据实际情况设定，本申请不作具体限定。
本申请另一实施例还提供了一种显示装置，包括上述任一实施例所述的阵列基板。
本申请另一实施例还提供了一种阵列基板的制备方法，参照图8，可以包括：
步骤801：提供基板，在基板上依次形成有机膜层和钝化层。
具体地，基板上的层结构都可以通过下述的构图工艺形成：成膜，利用磁控溅射等形成特定膜层，如金属膜、非金属膜以及像素电极等；曝光显影，利用PR材料涂覆并结合掩膜版对PR材料进行曝光和显影，形成特定图形；刻蚀，分为Dry Etch和Wet Etch，可以对曝光显影后暴露区域的膜层进行Etch，形成导通必需的线路及器件。
步骤802：在钝化层上形成透气孔。
具体地，形成透气孔的过程同样可以利用上述的曝光显影以及刻蚀等一系列构图工艺形成。在实际应用，该步骤可以与像素电极连接源漏电极的搭接孔同步形成，只需对掩膜版进行相应修改即可。
为了更充分地扩散杂质气体，上述的制备方法还可以包括：
步骤803：在测试区域的有机膜层上形成第三开孔，第三开孔对应于第一开孔40且与第一开孔贯通。
具体地，第三开孔的形成工艺，可以以有机膜层上的钝化层作为掩膜版，对有机膜层进行曝光和显影，从而形成第三开孔。需要注意的是，步骤803不是必须的，工艺过程可以根据实际情况具体确定。
具体地，阵列基板可以包括显示区域和测试区域；显示区域和测试区域的基板均包括有源层，上述步骤802可以进一步包括：
在钝化层上形成第一开孔，第一开孔在有源层所在平面上的正投影与有源层的相对位置满足预设条件。其中，所述预设条件是指第一开孔在有源层所在平面上的正投影可以位于有源层区域内，也可以位于靠近有源层的周围区域。
显示区域的基板还包括交叉排布的扫描线和数据线，上述步骤802还可以包括：
在钝化层上形成第二开孔，第二开孔在扫描线所在平面上的正投影位于扫描线上，和/或第二开孔在数据线所在平面上的正投影位于数据线上。
其中，第二开孔在扫描线所在平面上的正投影位于扫描线和数据线的交叉区域。
本申请实施例提供了一种阵列基板及其制备方法、显示装置，所述阵列基板包括基板、有机膜层和钝化层，所述有机膜层位于所述基板和所述钝化 层之间，所述钝化层上设置有透气孔；通过钝化层上的透气孔，可以将有机膜层在工艺制程中产生的杂质气体及时排出，确保基板上的器件如TFT特性等不受影响。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
以上对本公开所提供的一种阵列基板及其制备方法、显示装置进行了详细介绍，本文中应用了具体个例对本公开的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本公开的方法及其核心思想；同时，对于本领域的一般技术人员，依据本公开的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本公开的限制。

Claims (15)

  1. 一种阵列基板，包括基板、有机膜层和钝化层，所述有机膜层位于所述基板和所述钝化层之间；
    其中，所述钝化层上设置有透气孔。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板包括有源层，所述透气孔包括第一开孔，所述第一开孔在所述有源层所在平面上的正投影与所述有源层的相对位置为第一开孔在有源层所在平面上的正投影位于有源层区域内或位于靠近有源层的周围区域。
  3. 根据权利要求2所述的阵列基板，其中，所述有机膜层和所述钝化层之间还设置有公共电极层。
  4. 根据权利要求2所述的阵列基板，其中，所述阵列基板包括显示区域和测试区域。
  5. 根据权利要求4所述的阵列基板，其中，所述显示区域的基板还包括交叉排布的扫描线和数据线，所述透气孔还包括第二开孔，所述第二开孔在所述扫描线所在平面上的正投影位于所述扫描线上，和/或所述第二开孔在所述数据线所在平面上的正投影位于所述数据线上。
  6. 根据权利要求5所述的阵列基板，其中，所述第二开孔在所述扫描线所在平面上的正投影位于所述扫描线和所述数据线的交叉区域。
  7. 根据权利要求4所述的阵列基板，其中，在所述测试区域，所述有机膜层上设置有第三开孔，所述第三开孔对应于所述第一开孔，且与所述第一开孔贯通。
  8. 根据权利要求2至7任一项所述的阵列基板，其中，所述有源层的材质为铟镓锌氧化物IGZO。
  9. 根据权利要求1至7任一项所述的阵列基板，其中，所述透气孔的直径大于或等于2μm。
  10. 一种显示装置，包括权利要求1至9任一项所述的阵列基板。
  11. 一种阵列基板的制备方法，包括：
    提供基板，在所述基板上依次形成有机膜层和钝化层；
    在所述钝化层上形成透气孔。
  12. 根据权利要求11所述的制备方法，其中，所述阵列基板包括显示区域和测试区域；所述显示区域和所述测试区域的基板均包括有源层，在所述钝化层上形成透气孔的步骤，包括：
    在所述钝化层上形成第一开孔，所述第一开孔在所述有源层所在平面上的正投影与所述有源层的相对位置为第一开孔在有源层所在平面上的正投影位于有源层区域内或位于靠近有源层的周围区域。
  13. 根据权利要求12所述的制备方法，其中，所述显示区域的基板还包括交叉排布的扫描线和数据线，在所述钝化层上形成透气孔的步骤，还包括：
    在所述钝化层上形成第二开孔，所述第二开孔在所述扫描线所在平面上的正投影位于所述扫描线上，和/或所述第二开孔在所述数据线所在平面上的正投影位于所述数据线上。
  14. 根据权利要求13所述的制备方法，其中，所述第二开孔在所述扫描线所在平面上的正投影位于所述扫描线和所述数据线的交叉区域。
  15. 根据权利要求12所述的制备方法，其中，所述方法还包括：
    在所述测试区域的有机膜层上形成第三开孔，所述第三开孔对应于所述第一开孔，且与所述第一开孔贯通。
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