WO2020024693A1 - 薄膜晶体管、阵列基板、显示面板及显示装置 - Google Patents

薄膜晶体管、阵列基板、显示面板及显示装置 Download PDF

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WO2020024693A1
WO2020024693A1 PCT/CN2019/089485 CN2019089485W WO2020024693A1 WO 2020024693 A1 WO2020024693 A1 WO 2020024693A1 CN 2019089485 W CN2019089485 W CN 2019089485W WO 2020024693 A1 WO2020024693 A1 WO 2020024693A1
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Prior art keywords
thin film
film transistor
layer
signal line
drain
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PCT/CN2019/089485
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English (en)
French (fr)
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龙春平
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京东方科技集团股份有限公司
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Priority to US16/642,820 priority Critical patent/US11264509B2/en
Publication of WO2020024693A1 publication Critical patent/WO2020024693A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a thin film transistor, an array substrate, a display panel, and a display device.
  • a thin film transistor is a common electronic device in a display device. For example, it can be applied to an array substrate to drive each pixel of the display device.
  • the driving capability of a single thin-film crystal still needs to be improved, which is difficult to apply to a high-load area of a display device.
  • a display device for example, a liquid crystal display device
  • a thin film transistor still has a large leakage current during operation.
  • An embodiment of the present disclosure provides a thin film transistor including: a substrate; at least two active layers on the substrate, each active layer including a first end and a second end opposite to each other; The source and drain on the substrate are described. A first end of each of the at least two active layers is electrically connected to the source, and a second end of each of the at least two active layers is electrically connected to the source. The drain, and each of the at least two active layers is aligned along the upper surface of the substrate and spaced from each other.
  • the thin film transistor further includes at least two gates corresponding to the at least two active layers, and an orthographic projection of each active layer on the substrate is located at a corresponding gate Within the orthographic projection on the substrate.
  • the thin film transistor further includes at least two gates corresponding to the at least two active layers, and the at least two gates are electrically connected to each other to form an integrated gate Layer, the orthographic projection of the at least two active layers on the substrate is located within the orthographic projection of the gate layer on the substrate.
  • the thin film transistor further includes a source signal line and a drain signal line, the source signal line is electrically connected to the source, and the drain signal line is connected to the drain Electric connection.
  • the source signal line and the drain signal line extend in an extending direction perpendicular to the source or drain.
  • the source signal line and the drain signal line extend along an extending direction parallel to the source or drain.
  • the thin film transistor further includes a gate signal line, the gate signal line is electrically connected to the at least two gates, and an extension direction of the gate signal line is same as the source
  • the extension directions of the polar signal lines are perpendicular to each other.
  • the thin film transistor further includes a gate insulation layer, an etch barrier layer, and a passivation layer on the substrate, wherein the gate insulation layer covers the at least two gate electrodes, each Active layers are located on a side of the gate insulation layer remote from the substrate, the etch stop layer covers the at least two active layers and the gate insulation layer, and the source and drain electrodes are located on The side of the etch barrier layer away from the gate insulation layer, and the passivation layer covers the source electrode, the drain electrode, and the etch barrier layer.
  • the etch barrier layer includes a via hole, and the source electrode and the drain electrode are electrically connected to the at least two active layers through the via hole in the etch barrier layer, respectively.
  • the distance between the upper surface of each active layer across the first end and the second end is L, and the distance between the upper surface of each active layer and the distance is mutually
  • the vertical width is W, and the ratio of W to L is greater than 1.
  • a material of the active layer includes any one of amorphous silicon, polysilicon, and an oxide semiconductor.
  • Another embodiment of the present disclosure provides an array substrate including the thin film transistor according to any one of the foregoing embodiments.
  • Another embodiment of the present disclosure provides a display panel including the array substrate described in the foregoing embodiment.
  • Yet another embodiment of the present disclosure provides a display device including the display panel according to the foregoing embodiment.
  • FIG. 1 illustrates a cross-sectional view of a thin film transistor provided according to an embodiment of the present disclosure
  • FIG. 2 is a schematic top perspective view of a thin film transistor according to another embodiment of the present disclosure.
  • FIG. 3 is a schematic top perspective view of a thin film transistor according to another embodiment of the present disclosure.
  • FIG. 4 shows a schematic cross-sectional view of the thin film transistor shown in FIG. 2 or FIG. 3 along a line AA ′ therein.
  • a channel is usually used TFT (Thin Film Transistor).
  • FIG. 1 schematically illustrates a cross-sectional view of a thin film transistor provided according to an embodiment of the present disclosure.
  • the process of manufacturing the thin film transistor shown in FIG. 1 may include: sequentially forming a gate 12 and a gate insulating layer 13 on a substrate 11, and sequentially forming a continuous active layer 14 and The barrier layer 15 is etched, then a source electrode 16 and a drain electrode 17 are formed on the etch barrier layer 15, and finally a passivation layer 18 is formed.
  • the source and drain electrodes may be electrically connected to the continuous active layer 14 through a via in the etch barrier layer 15.
  • the channel width between the source electrode 16 and the drain electrode 17 is increased, thereby increasing the channel width-to-length ratio of the thin film transistor manufactured.
  • the inventors of the present application are aware of the following problems: due to the large area of the active layer, process defects, impurities, and the like are more likely to affect the active layer, making the active layer's Yield is reduced; in addition, when a thin film transistor is applied to a liquid crystal display device, the light emitted by the backlight source can be easily irradiated to the active layer through refraction, scattering, diffuse reflection, etc., which degrades the material properties of the active layer and causes the thin film The leakage current of the transistor increases.
  • a thin film transistor includes: a substrate; at least two active layers on the substrate, each active layer including a first end and a second end opposite to each other; Source and drain. A first end of each of the at least two active layers is electrically connected to the source, and a second end of each of the at least two active layers is electrically connected to the source. The drain, and each of the at least two active layers is aligned along the upper surface of the substrate and spaced from each other. 2 and 3 illustrate different examples of the thin film transistor according to the above-described embodiment of the present disclosure, respectively.
  • FIG. 1 illustrate different examples of the thin film transistor according to the above-described embodiment of the present disclosure, respectively.
  • the thin film transistor includes a plurality of sub thin film transistor structures 20, and these sub thin film transistor structures 20 may be considered to be connected in parallel with each other.
  • Each of the sub-thin film transistor structures 20 includes a gate electrode 22, an active layer 24, a source electrode 26, and a drain electrode 27, and the active layers 24 of two adjacent sub-thin film transistor structures 20 are disposed separately.
  • the active layers of these sub-thin-film transistor structures 20 are spaced apart, that is, there is no active layer material between two adjacent sub-thin-film transistor structures 20, so that a continuous large-area active layer region is not generated. In this way, the probability that process defects, impurities, and the like affect the active layer can be reduced, and the yield of the active layer 24 can be improved.
  • the active layer of the thin film transistor is not a continuous layer structure, it can reduce the impact of external light (for example, backlight) on its performance, and can reduce the leakage current of the thin film transistor to a certain extent.
  • FIG. 2 and FIG. 3 only show an exemplary thin-film transistor, which includes eight sub-thin-film transistor structures 20 connected in parallel. It can be understood that the thin-film transistor in the embodiment of the present disclosure includes the parallel thin-film transistors.
  • the number of structures 20 is greater than or equal to two. In practical applications, the number of sub-thin-film transistor structures 20 connected in parallel is set according to actual needs.
  • the thin film transistor further includes at least two gates corresponding to the at least two active layers, and an orthographic projection of each active layer on the substrate is located at a corresponding gate in Within the orthographic projection on the substrate.
  • each of the at least two gates is independent of each other. That is, the gates of each sub-thin-film transistor structure are not electrically connected.
  • the same gate signal can be input to the gates 22 of each sub-thin-film transistor structure 20 at the same time.
  • the at least two gate electrodes are electrically connected to each other to form an integrated gate layer, and an orthographic projection of the at least two active layers on the substrate is located on the gate electrode.
  • the layers are within an orthographic projection on the substrate, and FIG. 4 shows an example of such a thin film transistor.
  • the thin film transistor further includes a source signal line 31 and a drain signal line 32.
  • the source signal line 31 is electrically connected to the source 26 of the thin film transistor, and the drain signal line 32 is connected to the drain of the thin film transistor.
  • the pole 27 is electrically connected.
  • the source signal line 31 is used to input a source signal to the source electrode 26, and the drain signal line 32 is also electrically connected to a high load. When the thin film transistor is on, it is input through the source signal line 31 of the thin film transistor. The source signal is provided to a high load via its drain and drain signal lines 32.
  • the source signal line 31 and the drain signal line 32 may be formed at the same time.
  • the source signal line 31, the drain signal line 32, and the source 26 may be formed at the same time.
  • the same material as the drain electrode 27 is used.
  • the source signal line 31 and the drain signal line 32 extend in a direction perpendicular to the source or drain extension of the thin film transistor.
  • the source 26 and the drain 27 of the thin film transistor are arranged in parallel, and the source signal line 31 and the drain signal line 32 extend in a direction perpendicular to the source or drain. That is, if the source electrode 26 and the drain electrode 27 extend in the horizontal direction, the source signal line 31 and the drain signal line 32 extend in the vertical direction.
  • the source signal line 31 and the drain signal line 32 extend in a direction parallel to the extension of the source or drain.
  • the source 26 and the drain 27 are arranged in parallel, and the source signal line 31 and the drain signal line 32 extend in a direction parallel to the source or the drain. If the source 26 and the drain 27 are horizontal, If the direction extends, the source signal line 31 and the drain signal line 32 also extend in the horizontal direction.
  • the thin film transistor further includes a gate signal line (not shown in FIGS. 2 to 4), and the gate signal line is electrically connected to the at least two gates of the thin film transistor.
  • the extending direction of the gate signal line and the extending direction of the source signal line 31 are perpendicular to each other.
  • a distance between an upper surface of each active layer of the thin film transistor across the first end and the second end is L, and an upper surface of each active layer is different from the
  • the widths at which the distances are perpendicular to each other are W, and the ratio of W to L is greater than 1, as shown in FIG. 2, which schematically illustrates the distance L.
  • W is the dimension of the width of the surface of each active layer perpendicular to the distance L shown. Therefore, for a plurality of sub-thin-film transistor structures 20 that can be regarded as being connected in parallel to each other in the thin-film transistor, the width-to-length ratio of the channel of each sub-thin-film transistor structure is greater than one.
  • the channel width-to-length ratio of the thin film transistor is greater than N, and N is a positive integer greater than 1.
  • a thin film transistor having a large channel width and length can be obtained, and a high load can be driven. Therefore, the thin film transistor provided by the embodiment of the present disclosure can be applied to a high load area of a display device, such as a cell test (panel test) area, a GOA (Gate On Array), and a Demux area.
  • FIG. 4 is a partial cross-sectional view of the thin film transistor obtained along a line AA ′ in FIG. 2 or FIG. 3. As shown in FIG.
  • the thin film transistor 20 further includes a gate insulating layer 23, an etch barrier layer 25, and a passivation layer 28 on the substrate 21; each gate is connected to each other to form an integrated gate layer 22, and the gate insulating layer 23 Covers the gate layer 22, each active layer 24 is located on the side of the gate insulation layer 23 away from the substrate 21, and the etch barrier layer 25 covers each of the active layer 24 and the gate insulation layer 23, and the source and drain are located in the etch The side of the etch stop layer 25 away from the gate insulation layer, and the passivation layer 28 covers the source electrode 26, the drain electrode 27 and the etch stop layer 25.
  • the etch barrier layer 25 includes via holes, and the source and drain electrodes are electrically connected to at least two active layers through the via holes in the etch barrier layer, respectively.
  • manufacturing the thin film transistor shown in FIG. 4 may involve the following process: forming a gate metal thin film on the substrate 21, and patterning the gate metal thin film to form the gate layer 22, for example, using a mask
  • the film plate etches the gate metal thin film by the photolithography process to form the gate layer 22, and then uses PECVD (Plasma Enhanced Chemical Deposition) or other deposition methods to form a gate insulating layer 23 on the gate insulating layer 23
  • PECVD Plasma Enhanced Chemical Deposition
  • An active layer film is formed, and the active layer film is patterned to form a plurality of mutually spaced active layers 24. There is no active layer material between any two adjacent active layers 24, and then an etch barrier layer 25 is formed.
  • the etch barrier layer 25 covers each of the active layer 24 and the gate insulating layer 23. At positions corresponding to the active barrier layer 25 and the active layer 24, a via hole is formed by etching, and the via hole penetrates the etch barrier layer 25. Then, a source-drain metal film is formed on the etch barrier layer 25, and the source-drain metal film is patterned to form a source electrode 26 and a drain electrode 27. When the source-drain metal film is formed on the etch barrier layer 25, the material of the source-drain metal film will also be formed in the vias of the etch barrier layer 25. Therefore, the source electrode 26 and the drain electrode 27 formed by the patterning process will pass through The vias of the etch stop layer 25 are electrically connected to the active layer 24. Finally, a passivation layer 28 is formed, which covers the source electrode 26, the drain electrode 27 and the etch stop layer 25.
  • the gate metal film and the source-drain metal film can be made by the same or similar processes, for example, magnetron sputtering, evaporation, and other processes.
  • the materials of the gate 22, source 26, and drain 27 can be molybdenum, aluminum, and aluminum nickel. Materials such as alloy, chromium, copper, etc., and the material of the gate insulating layer 23 may be silicon nitride, silicon oxide, silicon oxynitride, or the like.
  • a material of the active layer 24 includes any one of amorphous silicon, polysilicon, and an oxide semiconductor.
  • the material of the active layer 24 is amorphous silicon
  • an amorphous silicon film is directly formed on the gate insulating layer 23 by PECVD or other deposition methods, a photoresist is coated on the amorphous silicon film, and a mask is used to align the light. The resist is exposed and developed, and then the amorphous silicon thin film is etched to form a desired pattern.
  • the material of the active layer 24 is polysilicon
  • amorphous silicon can be formed on the gate insulating layer 23 by using PECVD or other deposition methods.
  • the thin film is crystallized to form a polysilicon film by laser annealing or solid-phase crystallization, and then a photoresist is coated on the polysilicon film.
  • the photoresist is exposed and developed by using a mask, and then the polysilicon film is progressively processed.
  • Etch to form a desired pattern when the material of the active layer 24 is an oxide semiconductor, such as IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide), after forming an oxide semiconductor thin film on the gate insulating layer 23, A photoresist is coated on the semiconductor film, and the photoresist is exposed and developed by using a mask. Then, the oxide semiconductor film is etched to form a desired pattern.
  • IGZO Indium Gallium Zinc Oxide, indium gallium zinc oxide
  • a thin film transistor is formed by connecting at least two sub thin film transistor structures in parallel, and the active layers of two adjacent sub thin film transistor structures are disposed separately. While improving the channel width-to-length ratio of the thin film transistor, it can reduce The area of the active region in the small thin film transistor can improve the yield of the active region and reduce the leakage current of the thin film transistor.
  • Another embodiment of the present disclosure provides an array substrate including the thin film transistor according to any one of the above embodiments.
  • the substrates of the respective thin film transistors of the array substrate may be connected to each other to form an integrated substrate substrate for the array substrate.
  • the substrate 21 may be a glass substrate or a PI (Polyimide) substrate.
  • Another embodiment of the present disclosure also provides a display panel including the above-mentioned array substrate.
  • Another embodiment of the present disclosure provides a display device including the above-mentioned display panel.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

提供了一种薄膜晶体管、阵列基板、显示面板及显示装置，涉及显示技术领域。一种薄膜晶体管包括：衬底；位于所述衬底上的至少两个有源层，每个有源层包括彼此相对的第一端和第二端；位于所述衬底上的源极和漏极。所述至少两个有源层中的每个有源层的第一端电连接至所述源极，所述至少两个有源层中的每个有源层的第二端电连接至所述漏极，且所述至少两个有源层中的各个有源层沿所述衬底的上表面排列且彼此隔开。

Description

薄膜晶体管、阵列基板、显示面板及显示装置
相关申请的交叉引用
本申请要求于2018年8月3日向中国专利局提交的专利申请201821252825.2的优先权利益，并且在此通过引用的方式将该在先申请的内容并入本文。
技术领域
本公开涉及显示技术领域，特别是涉及一种薄膜晶体管、阵列基板、显示面板及显示装置。
背景技术
薄膜晶体管是显示装置中一种常用电子器件，例如，其可应用在阵列基板上用于驱动显示装置的各个像素。但是，当前，单个的薄膜晶体的驱动能力仍然有待提升，其难以应用于显示装置的高负载区域。此外，包括薄膜晶体管的显示装置(例如，液晶显示装置)在工作时仍存在漏电流较大的现象。
发明内容
本公开的实施例提供了一种薄膜晶体管，包括：衬底；位于所述衬底上的至少两个有源层，每个有源层包括彼此相对的第一端和第二端；位于所述衬底上的源极和漏极。所述至少两个有源层中的每个有源层的第一端电连接至所述源极，所述至少两个有源层中的每个有源层的第二端电连接至所述漏极，且所述至少两个有源层中的各个有源层沿所述衬底的上表面排列且彼此隔开。
根据本公开的一些实施例，所述薄膜晶体管还包括与所述至少两个有源层对应的至少两个栅极，每个有源层在所述衬底上的正投影位于相应的栅极在所述衬底上的正投影之内。
替代性地，根据本公开的一些实施例，所述薄膜晶体管还包括与所述至少两个有源层对应的至少两个栅极，所述至少两个栅极彼此电连接形成一体的栅极层，所述至少两个有源层在所述衬底上的正投影位于所述栅极层在所述衬底上的正投影之内。
根据本公开的一些实施例，所述薄膜晶体管还包括源极信号线和漏极信号线，所述源极信号线与所述源极电电连接，所述漏极信号线与所述漏极电电连接。
根据本公开的一些实施例，所述源极信号线和所述漏极信号线沿垂直于所述源极或漏极的延伸方向延伸。
替代性地，根据本公开的一些实施例，所述源极信号线和所述漏极信号线沿平行于所述源极或漏极的延伸方向延伸。
根据本公开的一些实施例，所述薄膜晶体管还包括栅极信号线，所述栅极信号线与所述至少两个栅极电连接，且所述栅极信号线的延伸方向与所述源极信号线的延伸方向相互垂直。
根据本公开的一些实施例，所述薄膜晶体管还包括位于所述衬底上的栅绝缘层、刻蚀阻挡层和钝化层，其中所述栅绝缘层覆盖所述至少两个栅极，每个有源层位于所述栅绝缘层远离所述衬底的一侧，所述刻蚀阻挡层覆盖所述至少两个有源层和所述栅绝缘层，所述源极和漏极位于所述刻蚀阻挡层远离所述栅绝缘层的一侧，所述钝化层覆盖所述源极、所述漏极和所述刻蚀阻挡层。
根据本公开的一些实施例，所述刻蚀阻挡层包括过孔，所述源极和所述漏极分别通过所述刻蚀阻挡层中的过孔与所述至少两个有源层电连接。
根据本公开的一些实施例，每个有源层的上表面的跨所述第一端和所述第二端之间的距离为L，每个有源层的上表面的与所述距离相互垂直的宽度为W，W与L的比值大于1。
根据本公开的一些实施例，所述有源层的材料包括非晶硅、多晶硅、氧化物半导体中的任意一种。
本公开的另一实施例提供了一种阵列基板，包括如前述的任一实施例所述的薄膜晶体管。
本公开的又一实施例提供了一种显示面板，包括前述实施例所述的阵列基板。
本公开的再一实施例提供了一种显示装置，包括如前述实施例所述的显示面板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他 的附图。
图1示出了根据本公开的一个实施例提供的薄膜晶体管的剖面图；
图2示出了根据本公开的另一实施例提供的薄膜晶体管的俯视透视示意图；
图3示出了根据本公开的另一实施例提供的薄膜晶体管的俯视透视示意图；
图4示出了如图2或图3所示的薄膜晶体管沿着其中的线AA'的截面示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在显示装置的一些高负载区域，如cell test(面板测试)区域、GOA(Gate on Array，阵列基板行驱动)区域、Demux(多路复用)区域，为了能够驱动高负载，通常使用沟道的宽长比较大的TFT(Thin Film Transistor，薄膜晶体管)。
图1示意性地示出了根据本公开的一个实施例提供的薄膜晶体管的剖面图。如图1所示，制作图1所示的薄膜晶体管的过程可包括：在衬底11上依次形成栅极12和栅绝缘层13，在栅绝缘层13上依次形成连续的有源层14和刻蚀阻挡层15，接着在刻蚀阻挡层15上形成源极16和漏极17，最后形成钝化层18。源极和漏极可通过刻蚀阻挡层15中的过孔与连续的有源层14电连接。通过在连续的有源层14上形成源极16和漏极17，使得源极16和漏极17之间的沟道宽度增大，从而增大所制作的薄膜晶体管的沟道宽长比。
对于本公开的上述实施例提供的薄膜晶体管，本申请的发明人意识到以下问题：由于有源层的面积较大，工艺缺陷、杂质等较易对有源层产生影响，使得有源层的良率降低；另外，当薄膜晶体管应用于液晶显示装置时，背光源发出的光线经过折射、散射、漫反射等会较容易地照射到有源层，使得有源层的材料性能退化，导致薄膜晶体管的漏电流增大。
本公开的另一实施例提供了与图1所示的薄膜晶体管结构不同的另一薄膜晶体管。根据该实施例，薄膜晶体管包括：衬底；位于所述衬底上的至少两个有源层，每个有源层包括彼此相对的第一端和第二端；位于所述衬底上的源极和漏极。所述至少两个有源层中的每个有源层的第一端电连接至所述源极，所述至少两个有源层中的每个有源层的第二端电连接至所述漏极，且所述至少两个有源层中的各个有源层沿所述衬底的上表面排列且彼此隔开。图2和图3分别示出了根据本公开的上述实施例的薄膜晶体管的不同示例。图4示出了图2或图3的薄膜晶体管的示例沿着图2或图3中的线AA'而得到的截面图。如图2至图4所示，根据本公开的一些实施例，薄膜晶体管包括多个子薄膜晶体管结构20，这些子薄膜晶体管结构20可以被认为是彼此并联连接。每个子薄膜晶体管结构20包括栅极22、有源层24、源极26和漏极27，且相邻两个子薄膜晶体管结构20的有源层24分隔设置。
对于图2-图4所示的薄膜晶体管，在衬底21上形成多个彼此并联的子薄膜晶体管结构，因此，所形成的薄膜晶体管的整体的沟道的宽长比能够得以提升，因而可适用于驱动高负载。此外，这些子薄膜晶体管结构20的有源层彼间隔，即相邻两个子薄膜晶体管结构20之间没有有源层材料，从而不会产生连续的大面积的有源层区域。这样，可降低工艺缺陷、杂质等对有源层造成影响的机率，从而可提高有源层24的良率。同时，由于薄膜晶体管的有源层不是一个连续的层结构，可减少外部光线(例如，背光)的照射对其性能的影响，在一定程度上可以降低薄膜晶体管的漏电流。
图2和图3中仅仅示出了一种示例性的薄膜晶体管，其包括8个并联的子薄膜晶体管结构20，可以理解的是，本公开实施例中的薄膜晶体管包括的并联的子薄膜晶体管结构20的数量大于或等于2，在实际应用，根据实际的需求，设定并联的子薄膜晶体管结构20的数量。
根据本公开的一些实施例，薄膜晶体管还包括与所述至少两个有源层对应的至少两个栅极，每个有源层在所述衬底上的正投影位于相应的栅极在所述衬底上的正投影之内。在该实施例中，所述至少两个栅极中的每个栅极是彼此独立的。即，每个子薄膜晶体管结构的栅极不是电连接的，在需要通过薄膜晶体管驱动高负载时，可同时向各个子薄膜晶体管结构20的栅极22输入相同的栅极信号。替代性地，在 另一实施例中，所述至少两个栅极彼此电连接形成一体的栅极层，所述至少两个有源层在所述衬底上的正投影位于所述栅极层在所述衬底上的正投影之内，图4示出了这样的薄膜晶体管的示例。对于该示例，在薄膜晶体管的实际制作过程中，在形成栅金属薄膜后，不需要对栅金属薄膜进行图案化处理，可简化制作工艺复杂度。如图2和图3所示，薄膜晶体管还包括源极信号线31和漏极信号线32，源极信号线31与薄膜晶体管的源极26电连接，漏极信号线32与薄膜晶体管的漏极27电连接。
该源极信号线31用于向源极26输入源极信号，该漏极信号线32还与高负载电连接，在薄膜晶体管处于导通的情况下，通过薄膜晶体管的源极信号线31输入的源极信号经由其漏极和漏极信号线32提供给高负载。
根据本公开的一些实施例，在制作形成源极26和漏极27时，可同时形成源极信号线31和漏极信号线32，源极信号线31、漏极信号线32、源极26和漏极27采用的材料相同。
如图2所示，源极信号线31和漏极信号线32沿垂直于薄膜晶体管的源极或漏极的延伸方向延伸。在图2的示例中，薄膜晶体管的源极26和漏极27平行设置，源极信号线31和漏极信号线32沿垂直于源极或漏极的方向延伸。也就是说，若源极26和漏极27沿水平方向延伸，则源极信号线31和漏极信号线32沿竖直方向延伸。
如图3所述，根据本公开的另外的实施例，源极信号线31和漏极信号线32沿平行于源极或漏极的延伸方向延伸。在图3的示例中，源极26和漏极27平行设置，源极信号线31和漏极信号线32沿平行于源极或漏极的方向延伸，若源极26和漏极27沿水平方向延伸，则源极信号线31和漏极信号线32也沿水平方向延伸。
根据本公开的实施例，薄膜晶体管还包括栅极信号线(未在图2至图4中示出)，栅极信号线与薄膜晶体管的所述至少两个栅极电连接。在一个示例中，栅极信号线的延伸方向与源极信号线31的延伸方向相互垂直。
根据本公开的实施例，薄膜晶体管的每个有源层的上表面的跨所述第一端和所述第二端之间的距离为L，每个有源层的上表面的与所述距离相互垂直的宽度为W，W与L的比值大于1，如图2所示，图2 中示意性地示出了距离L。W即为每个有源层的表面与所示的距离L垂直的宽度的尺寸。因此，对于薄膜晶体管中可视为彼此并联连接的多个子薄膜晶体管结构20，每个子薄膜晶体管结构的沟道的宽长比均大于1。当薄膜晶体管包括N个子薄膜晶体管结构20时，薄膜晶体管的沟道宽长比大于N，N为大于1的正整数。由此，可获得具有较大的沟道宽长的薄膜晶体管，从而可以驱动高负载。因此，本公开实施例提供的的薄膜晶体管可应用于显示装置高负载区域，如cell test(面板测试)区域、GOA(Gate onArray，阵列基板行驱动)区域、Demux(多路复用)区域。图4是沿着图2或图3中的AA'线而得到的薄膜晶体管的局部剖面图。如图4所示，薄膜晶体管20还包括位于衬底21上的栅绝缘层23、刻蚀阻挡层25和钝化层28；各个栅极彼此连接形成一体的栅极层22，栅绝缘层23覆盖栅极层22，各个有源层24位于栅绝缘层23远离衬底21的一侧，刻蚀阻挡层25覆盖各个有源层24和栅绝缘层23，源极和漏极位于所述刻蚀阻挡层25远离栅绝缘层的一侧，钝化层28覆盖源极26、漏极27和刻蚀阻挡层25。在图4的示例中，刻蚀阻挡层25包括过孔，源极和漏极分别通过刻蚀阻挡层中的过孔与至少两个有源层电连接。
根据本公开的实施例，制作图4所示的薄膜晶体管可涉及以下过程：在衬底21上形成一层栅金属薄膜，对栅金属薄膜进行图案化处理形成栅极层22，例如，采用掩膜板通过光刻工艺腐蚀栅金属薄膜形成栅极层22，接着采用PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积法)或其它沉积方法形成栅绝缘层23，在栅绝缘层23上形成有源层薄膜，对有源层薄膜进行图案化处理形成多个相互间隔的有源层24，任意相邻两个有源层24之间没有有源层材料，然后形成刻蚀阻挡层25，该刻蚀阻挡层25覆盖各个有源层24和栅绝缘层23，在刻蚀阻挡层25与有源层24对应的位置处，刻蚀形成过孔，该过孔贯穿刻蚀阻挡层25，然后在刻蚀阻挡层25上形成源漏金属薄膜，对源漏金属薄膜进行图案化处理形成源极26和漏极27。在刻蚀阻挡层25上形成源漏金属薄膜时，源漏金属薄膜的材料也会形成在刻蚀阻挡层25的过孔内，因此，图案化处理形成的源极26和漏极27会通过刻蚀阻挡层25的过孔与有源层24电连接，最后，形成钝化层28，该钝化层28覆盖源极26、漏极27和刻蚀阻挡层25。
栅金属薄膜和源漏金属薄膜可采用相同或类似的工艺方法制作，例如，磁控溅射、蒸发等工艺，栅极22、源极26和漏极27的材料可采用钼、铝、铝镍合金、铬、铜等材料，栅绝缘层23的材料可采用氮化硅、氧化硅、氮氧化硅等材料。
根据本公开的实施例，有源层24的材料包括非晶硅、多晶硅、氧化物半导体中的任意一种。当有源层24的材料为非晶硅时，直接用PECVD或其他沉积方法在栅绝缘层23上形成非晶硅薄膜，在非晶硅薄膜上涂覆光刻胶，采用掩膜板对光刻胶进行曝光显影，然后对非晶硅薄膜进行性刻蚀以形成所需图案；当有源层24的材料为多晶硅时，可利用PECVD或其他沉积方法在栅绝缘层23上形成非晶硅薄膜，通过激光退火或者固相结晶方法，使得非晶硅薄膜结晶形成多晶硅薄膜，然后在多晶硅薄膜上涂覆光刻胶，采用掩膜板对光刻胶进行曝光显影，然后对多晶硅薄膜进行性刻蚀以形成所需图案；当有源层24的材料为氧化物半导体时，如IGZO(Indium GalliumZinc Oxide，铟镓锌氧化物)，在栅绝缘层23上形成氧化物半导体薄膜后，在氧化物半导体薄膜上涂覆光刻胶，采用掩膜板对光刻胶进行曝光显影，然后对氧化物半导体薄膜进行性刻蚀以形成所需图案。
对于本公开的实施例，通过将至少两个子薄膜晶体管结构并联形成薄膜晶体管，且相邻两个子薄膜晶体管结构的有源层分隔设置，在提高薄膜晶体管的沟道宽长比的同时，可减小薄膜晶体管中有源区的面积，从而可提高有源区的良率，降低薄膜晶体管的漏电流。
本公开的另外的实施例提供了一种阵列基板，包括上述的任一实施例所述的薄膜晶体管。在该实施例中，阵列基板的各个薄膜晶体管的衬底可以彼此连接形成一个用于阵列基板的整体衬底基板。衬底21可以是玻璃基板或PI(Polyimide，聚酰亚胺)基板。
本公开的另外的实施例还提供了一种显示面板，包括上述的阵列基板。
本公开的另外的实施例提供了一种显示装置，包括上述的显示面板。
尽管已描述了本公开的部分实施例，但本领域内的技术人员一旦得知了本公开过的技术构思，则可对这些实施例做出另外的变更和修改。所以，所附权利要求意欲解释为包括本公开所描述的实施例以及 落入本申请的权利要求的范围的所有变更和修改的实施例。
最后，还需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者终端设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者终端设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者终端设备中还存在另外的相同要素。
以上所述，仅为本公开的部分实施例，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (14)

  1. 一种薄膜晶体管，包括：
    衬底；
    位于所述衬底上的至少两个有源层，每个有源层包括彼此相对的第一端和第二端；
    位于所述衬底上的源极和漏极，
    其中，所述至少两个有源层中的每个有源层的第一端电连接至所述源极，所述至少两个有源层中的每个有源层的第二端电连接至所述漏极，且所述至少两个有源层中的各个有源层沿所述衬底的上表面排列且彼此隔开。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述薄膜晶体管还包括与所述至少两个有源层对应的至少两个栅极，每个有源层在所述衬底上的正投影位于相应的栅极在所述衬底上的正投影之内。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述薄膜晶体管还包括与所述至少两个有源层对应的至少两个栅极，所述至少两个栅极彼此电连接形成一体的栅极层，所述至少两个有源层在所述衬底上的正投影位于所述栅极层在所述衬底上的正投影之内。
  4. 根据权利要求1所述的薄膜晶体管，其中所述薄膜晶体管还包括源极信号线和漏极信号线，所述源极信号线与所述源极电电连接，所述漏极信号线与所述漏极电电连接。
  5. 根据权利要求4所述的薄膜晶体管，其中所述源极信号线和所述漏极信号线沿垂直于所述源极或漏极的延伸方向延伸。
  6. 根据权利要求4所述的薄膜晶体管，其中所述源极信号线和所述漏极信号线沿平行于所述源极或漏极的延伸方向延伸。
  7. 根据权利要求2或3所述的薄膜晶体管，其中所述薄膜晶体管还包括栅极信号线，
    所述栅极信号线与所述至少两个栅极电连接，且所述栅极信号线的延伸方向与所述源极信号线的延伸方向相互垂直。
  8. 根据权利要求2或3所述的薄膜晶体管，其中所述薄膜晶体管还包括位于所述衬底上的栅绝缘层、刻蚀阻挡层和钝化层，其中所述栅绝缘层覆盖所述至少两个栅极，每个有源层位于所述栅绝缘层远离 所述衬底的一侧，所述刻蚀阻挡层覆盖所述至少两个有源层和所述栅绝缘层，所述源极和漏极位于所述刻蚀阻挡层远离所述栅绝缘层的一侧，所述钝化层覆盖所述源极、所述漏极和所述刻蚀阻挡层。
  9. 根据权利要求8所述的薄膜晶体管，其中所述刻蚀阻挡层包括过孔，所述源极和所述漏极分别通过所述刻蚀阻挡层中的过孔与所述至少两个有源层电连接。
  10. 根据权利要求1所述的薄膜晶体管，其中每个有源层的上表面的跨所述第一端和所述第二端之间的距离为L，每个有源层的上表面的与所述距离相互垂直的宽度为W，W与L的比值大于1。
  11. 根据权利要求1所述的薄膜晶体管，其中所述有源层的材料包括非晶硅、多晶硅、氧化物半导体中的任意一种。
  12. 一种阵列基板，包括如权利要求1-11任一项所述的薄膜晶体管。
  13. 一种显示面板，包括如权利要求12所述的阵列基板。
  14. 一种显示装置，包括如权利要求13所述的显示面板。
PCT/CN2019/089485 2018-08-03 2019-05-31 薄膜晶体管、阵列基板、显示面板及显示装置 WO2020024693A1 (zh)

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