CN104218095A - 一种薄膜晶体管及其制备方法、阵列基板和显示装置 - Google Patents

一种薄膜晶体管及其制备方法、阵列基板和显示装置 Download PDF

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CN104218095A
CN104218095A CN201410441698.0A CN201410441698A CN104218095A CN 104218095 A CN104218095 A CN 104218095A CN 201410441698 A CN201410441698 A CN 201410441698A CN 104218095 A CN104218095 A CN 104218095A
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etching barrier
drain electrode
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barrier layer
film transistor
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CN104218095B (zh
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蔡振飞
陈正伟
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Hefei Xinsheng Optoelectronics Technology Co Ltd
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Abstract

本发明公开了一种薄膜晶体管，包括：有源层、刻蚀阻挡层、源电极和漏电极，其中：刻蚀阻挡层设置于有源层的上方，且刻蚀阻挡层中形成有多个过孔；源电极和漏电极设置于刻蚀阻挡层的上方，且所述源电极和漏电极利用刻蚀阻挡层中的多个过孔，通过所述有源层连接。本发明同时还公开了一种薄膜晶体管的制备方法、阵列基板和显示装置。本发明采用了多沟道设计，利用并联的多个子开关解决有源层缺失导致的DGS问题，从而保证了像素的正常工作，进而提高了产品的良率和使用寿命。

Description

一种薄膜晶体管及其制备方法、阵列基板和显示装置
技术领域
本发明涉及显示领域，尤其是一种薄膜晶体管(Thin Film Transistor，TFT)及其制备方法、阵列基板和显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)显示器由于可以做得更轻更薄，可视角度更大，无辐射，并且能够显著节省电能，从而在当前的平板显示装置市场占据了主导地位，被认为是最可能的下一代新型平面显示器。有源矩阵OLED为每一个像素配备了用于控制该像素的薄膜晶体管作为开关，所述薄膜晶体管通常包括栅极、源极和漏极以及栅绝缘层和有源层。
氧化物(Oxide)，如铟镓锌氧化物(IGZO)、铟锡锌氧化物(ITZO)等和非晶硅均可作为薄膜晶体管的有源层材料，与非晶硅薄膜晶体管相比，氧化物薄膜晶体管的载流子浓度是非晶硅薄膜晶体管的十倍左右，载流子迁移率是非晶硅薄膜晶体管的20-30倍，因此，氧化物薄膜晶体管可以大大地提高薄膜晶体管对于像素电极的充放电速率，提高像素的响应速度，进而实现更快的刷新率。氧化物薄膜晶体管能够满足需要快速响应和较大电流的应用场合，如高频、高分辨率、大尺寸的显示器以及有机发光显示器等，因此，氧化物薄膜晶体管成为用于新一代LCD、OLED显示装置的半导体组件。
在目前氧化物薄膜晶体管的制作工艺中，由于氧化物的特殊性质，需要在制作完氧化物层后增加一层刻蚀阻挡层来阻挡源漏极金属刻蚀对于氧化物层的损伤，但在氧化物层的成膜和光刻过程中，通常会因为灰尘等原因造成氧化物层图案的缺失，如图1a所示，在接下来进行的刻蚀阻挡层刻蚀过程中，就有可能直接将氧化物层图案下方的栅极绝缘层也一起刻蚀掉，从而直接裸露出栅线，如图1b和图1c所示，裸露出的栅线与源漏极金属直接接触，形成短路(DGS)，如图1d所示，进而严重地影响了产品的良率。
现有技术中，在找到短路发生的位置后，如图2中的黑色圆圈所示，通常采用对于TFT开关的源极信号输入端进行切割的方式来维修，如图2中的黑色短线所示，但在切割源极信号输入端后，相应的像素由于失去了源极驱动将会变为暗点，即坏点。如果一个显示面板上存在多处短路位置，经过维修后将会产生多个坏点，存在多个坏点的显示面板无法正常使用，只能按照报废处理，这就大大地影响了显示面板的使用寿命。
发明内容
为了解决上述现有技术中存在的问题，本发明提出一种薄膜晶体管及其制备方法、阵列基板和显示装置。
根据本发明的一方面，提出一种薄膜晶体管，包括：有源层、刻蚀阻挡层、源电极和漏电极，其中：
所述刻蚀阻挡层设置于所述有源层的上方，且所述刻蚀阻挡层中形成有多个过孔；
所述源电极和漏电极设置于所述刻蚀阻挡层的上方，且所述源电极和漏电极利用所述刻蚀阻挡层中的多个过孔，通过所述有源层连接。
其中，所述刻蚀阻挡层中过孔的数量大于等于4。
其中，所述多个过孔规律或非规律形成在所述刻蚀阻挡层中，其中一部分过孔与源电极连接，其余过孔与漏电极连接。
其中，所述刻蚀阻挡层中过孔的数量为偶数，分为两行平行排列，所述源电极通过其中一行过孔与所述有源层连接，所述漏电极通过另一行过孔与所述有源层连接。其中，所述有源层由金属氧化物半导体材料制得。
其中，还包括钝化层，所述钝化层设置于所述源电极和漏电极的上方。
根据本发明的另一方面，还提出一种阵列基板，包括如上所述的薄膜晶体管。
根据本发明的另一方面，还提出一种显示装置，包括如上所述的阵列基板。
根据本发明的再一方面，还提出一种薄膜晶体管的制备方法，该制备方法包括以下步骤：
在有源层上形成刻蚀阻挡材料层，进行图形化，得到刻蚀阻挡层，其中，所述刻蚀阻挡层中形成有多个过孔；
在所述刻蚀阻挡层上形成电极材料层，并进行图形化，得到源电极和漏电极，所述源电极和漏电极利用所述刻蚀阻挡层中的多个过孔，通过所述有源层连接。
其中，所述刻蚀阻挡层中过孔的数量大于等于4。其中，所述多个过孔规律或非规律形成在所述刻蚀阻挡层中，其中一部分过孔与源电极连接，其余过孔与漏电极连接。
其中，所述刻蚀阻挡层中过孔的数量为偶数，分为两行平行排列，所述源电极通过其中一行过孔与所述有源层连接，所述漏电极通过另一行过孔与所述有源层连接。
其中，所述有源层为金属氧化物半导体材料。
其中，在形成所述源电极和漏电极后，还包括在所述源电极和漏电极上形成钝化层的步骤。
本发明采用了多沟道设计，在不改变有源层宽度的前提下，增加了子开关的数量，每个子开关都是一个独立的控制单元，并且所有的子开关组成一个对于一个像素点进行控制的、以并联方式连接的子开关阵列。当有源层缺失导致的DGS问题发生在任意一个子开关处时，利用激光将相应子开关的源极信号输入端切断，这样就只需破坏一个子开关，而另外与之并联的子开关可以正常工作，从而保证了该像素的正常工作，进而提高了产品的良率和使用寿命。
附图说明
图1是DGS现象的产生原理示意图；
图2是现有技术中的薄膜晶体管的整体示意图；
图3是根据本发明一实施例的薄膜晶体管的结构示意图；
图4是根据本发明一实施例的薄膜晶体管的整体示意图；
图5是根据本发明另一实施例的薄膜晶体管的整体示意图；
图6是根据本发明一实施例的薄膜晶体管的制备工艺流程图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明进一步详细说明。
根据本发明的一方面，提出一种薄膜晶体管，如图3所示，该薄膜晶体管包括：基板1、栅极2、栅极绝缘层3、有源层4、刻蚀阻挡层5、源电极和漏电极，其中：
所述栅极2、栅极绝缘层3和有源层4依次设置于所述基板1的上方；
所述刻蚀阻挡层5设置于所述有源层4的上方，用于保护处于源漏电极之间的沟道区域中的有源层4部分不受显影液和刻蚀液的侵蚀影响，所述刻蚀阻挡层5中形成有多个过孔；
其中，所述过孔的数量大于等于4。
所述源电极和漏电极设置于所述刻蚀阻挡层5的上方，且所述源电极和漏电极利用所述刻蚀阻挡层5中的多个过孔，通过所述有源层4连接。
这样，在通电的情况下，所述源电极和漏电极通过所述刻蚀阻挡层中的多个过孔形成了多个沟道。在本发明一实施例中，所述刻蚀阻挡层中过孔的数量为偶数，分为两行平行排列，所述源电极通过其中一行过孔与所述有源层4连接，所述漏电极通过另一行过孔与所述有源层4连接，在该实施例中，源电极和漏电极分别通过列方向上相对排列的两个过孔32形成多个沟道，且所述沟道的方向与源漏极信号线的方向相平行，如图4所示，图4中，源电极连接数据信号线31，漏电极通过过孔33连接像素电极34。这样，每一对源电极和漏电极均可看作为一个可独立控制的子开关，所有的子开关组成一个对于一个像素点进行控制的、以并联方式连接的子开关阵列。当所述子开关阵列中的某一子开关的源电极或漏电极对应的位置出现DGS问题时，可仅切断该子开关对应的信号输入端，而其它与之并联的子开关可以继续工作，这样就防止出现现有技术中因DGS问题导致的整个像素点的驱动失效，进而变为坏点的情况，进而提高产品的良率。
其中，所述过孔的数量和排列方式可根据实际情况灵活设置，比如，在制作工艺允许的情况下，所述过孔可在大于等于4的基础上灵活设置；多个过孔可平行排列也可交错排列，可排列为两行也可排列为多行，可规律排列也可非规律排列；与源电极连接的过孔的数量和与漏电极连接的过孔的数量可以相同也可以不相同，需要说明的是，与源电极连接的过孔和与漏电极连接的过孔之间的对应关系可通过有源层位置的对应设置来确定。图5是根据本发明另一实施例的薄膜晶体管的整体示意图，图5中，六个过孔交错排列，上面的三个过孔连接源电极和有源层，下面的三个过孔连接漏电极和有源层，与源电极连接的过孔和与漏电极连接的过孔之间的对应关系通过独立设置的多个斜向有源层来确定。
除了上述说明之外，本发明对于过孔的具体数量、排列方式以及与源漏电极连接的方式不作其他特殊限制，只要能够根据应用的需要实现源电极\漏电极与有源层的连接即可。
另外需要说明的是，所述源电极与数据信号线之间的连接方式、以及所述漏电极与像素电极之间的连接方式可根据实际应用的需要来灵活设置，比如，在考虑过孔位置的情况下，每个过孔对应的源电极可与数据信号线直接连接，也可通过从数据信号线引出的信号线与数据信号线连接；每个过孔对应的漏电极亦可如此灵活设置。本发明对于源电极与数据信号线之间的连接方式，以及漏电极与像素电极之间的连接方式不作具体的限制，所有能够实现源电极与数据信号线之间以及漏电极与像素电极之间有效连接的方式均落入本发明的保护范围内。
可选地，所述基板1的制作材料包括玻璃、硅片、石英、塑料以及硅片等材料，优选为玻璃。
其中，所述栅极2由导电材料制成，比如金属、半导体材料，优选为金属材料。
其中，所述栅极绝缘层3的制作材料优选为绝缘材料，包括二氧化硅、氮化硅、氮氧化硅等，或者以上材料的组合。
其中，所述有源层4由金属氧化物半导体材料制作，优选为载流子迁移率较高的氧化物半导体材料，比如氮氧化锌(ZnON)、铟镓锌氧化物(IGZO)、氧化铟锌(IZO)、铟锡锌氧化物(ITZO)等氧化物半导体材料。
其中，所述刻蚀阻挡层由能够对显影液和刻蚀液起阻挡作用的材料制成，比如硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)和硅的氮氧化物(SiON)中的其中一种或多种。硅的氧化物(SiOx)等材料对显影液和源、漏刻蚀液不敏感，并且具有良好的介电特性以及对水汽、氧气的阻挡特性，因此采用上述材料制作刻蚀阻挡层时，能够阻挡显影液和源、漏极刻蚀液对有源层4造成的不利影响，并且能够满足金属氧化物薄膜晶体管的特性要求。
其中，所述源电极和漏电极由导电材料制成，优选地，所述导电材料为金属材料，比如铝、锌、锡、镆、钨、钛等常用金属，或者金属合金材料。
本发明对于源电极和漏电极的具体区分不作特殊要求，因为具体哪个位置的电极是源电极还是漏电极需要根据其与像素电极的连接关系来决定，本申请中定义与像素电极连接的是漏电极。
在本发明一实施例中，所述薄膜晶体管还包括钝化层7，所述钝化层7设置于所述源电极和漏电极的上方。
根据上述任一实施例的薄膜晶体管，由于采用了多个沟道的设计，在不改变有源层宽度的前提下，增加了子开关的数量，每个子开关都是一个独立的控制单元，且所有的子开关组成一个对于一个像素点进行控制的、以并联方式连接的子开关阵列。当有源层缺失导致的DGS问题发生在任意一个子开关处时，利用激光将相应子开关的源极信号输入端切断，这样就只需破坏一个子开关，而另外与之并联的子开关可以正常工作，从而保证了该像素的正常工作，进而提高了产品的良率和使用寿命。
根据本发明的另一方面，还提出一种阵列基板，所述阵列基板包括上述任一实施例所述的薄膜晶体管。
根据本发明的另一方面，还提出一种显示装置，所述显示装置包括如上所述的阵列基板。
根据本发明的再一方面，还提出一种薄膜晶体管的制备方法，所述制备方法包括以下步骤：步骤1，在基板1上依次形成栅极材料层和栅极绝缘材料层，并进行图形化，得到栅极2和栅极绝缘层3，如图6a所示；
可选地，所述基板1的制作材料包括玻璃、硅片、石英、塑料以及硅片等材料，优选为玻璃。
其中，所述栅极2由导电材料制成，比如金属、半导体材料，优选为金属材料。
可选地，所述栅极绝缘层3可通过CVD方法来沉积，其制作材料优选为绝缘材料，包括二氧化硅、氮化硅、氮氧化硅等，或者以上材料的组合。
步骤2，在所述栅极绝缘层3上形成半导体层，并进行图形化，得到有源层4，如图6b所示；
其中，所述有源层4为金属氧化物半导体材料，优选为载流子迁移率较高的氧化物半导体材料，比如氮氧化锌(ZnON)、铟镓锌氧化物(IGZO)、氧化铟锌(IZO)、铟锡锌氧化物(ITZO)等氧化物半导体材料。
其中，所述半导体层可采用溅射技术或等离子体化学气相沉积(PECVD)技术形成，本发明对于所述半导体层的形成方式不作特殊限定。
可选地，通过灰阶掩膜曝光、刻蚀等常见的构图工艺来对半导体层进行图形化，形成有源层4。
步骤3，在所述有源层4上形成刻蚀阻挡材料层，进行图形化，得到刻蚀阻挡层5，其中，所述刻蚀阻挡层5中形成有多个过孔，如图6c所示，所述刻蚀阻挡层5用于保护处于源漏电极之间的沟道区域中的有源层4部分不受显影液和刻蚀液的侵蚀影响；
其中，利用等离子体化学气相沉积等常见半导体形成工艺来得到刻蚀阻挡材料层。
其中，利用曝光、显影、刻蚀等常见的构图工艺来进行图形化。
图形化之后，所述刻蚀阻挡层5中形成有多个过孔，其中，所述过孔的数量大于等于4。
其中，所述刻蚀阻挡材料层由能够对显影液和刻蚀液起阻挡作用的材料制成，比如硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)和硅的氮氧化物(SiON)中的其中一种或多种。硅的氧化物(SiOx)等材料对显影液和源、漏刻蚀液不敏感，并且具有良好的介电特性以及对水汽、氧气的阻挡特性，因此采用上述材料制作刻蚀阻挡层时，能够阻挡显影液和源、漏极刻蚀液对有源层4造成的不利影响，并且能够满足金属氧化物薄膜晶体管的特性要求。
步骤4，在所述刻蚀阻挡层5上形成电极材料层，并进行图形化，得到源电极和漏电极6，如图6d所示，所述源电极和漏电极6利用所述刻蚀阻挡层5中的多个过孔，通过所述有源层4连接。
其中，所述电极材料层由导电材料制成，优选地，所述导电材料为金属材料，比如铝、锌、锡、镆、钨、钛等常用金属，或者金属合金材料。
可选地，可通过曝光、显影、刻蚀等构图工艺来形成所述源电极和漏电极6。
本发明对于源电极和漏电极的具体区分不作特殊要求，因为具体哪个位置的电极是源电极还是漏电极需要根据与像素电极的连接关系来决定，本申请中定义与像素电极连接的是漏电极。
这样，在通电的情况下，所述源电极和漏电极通过所述刻蚀阻挡层中的多个过孔形成了多个沟道。在本发明一实施例中，所述刻蚀阻挡层中过孔的数量为偶数，分为两行平行排列，所述源电极通过其中一行过孔与所述有源层4连接，所述漏电极通过另一行过孔与所述有源层4连接，在该实施例中，源电极和漏电极分别通过列方向上相对排列的两个过孔32形成多个沟道，且所述沟道的方向与源漏极信号线的方向相平行，如图4所示，图4中，源电极连接数据信号线31，漏电极通过过孔33连接像素电极34。这样，每一对源电极和漏电极均可看作为一个可独立控制的子开关，所有的子开关组成一个对于一个像素点进行控制的、以并联方式连接的子开关阵列。当所述子开关阵列中的某一子开关的源电极或漏电极对应的位置出现DGS问题时，可仅切断该子开关对应的信号输入端，而其它与之并联的子开关可以继续工作，这样就防止出现现有技术中因DGS问题导致的整个像素点的驱动失效，进而变为坏点的情况，进而提高产品的良率。
其中，所述过孔的数量和排列方式可根据实际情况灵活设置，比如，在制作工艺允许的情况下，所述过孔可在大于等于4的基础上灵活设置；多个过孔可平行排列也可交错排列，可排列为两行也可排列为多行，可规律排列也可非规律排列；与源电极连接的过孔的数量和与漏电极连接的过孔的数量可以相同也可以不相同，需要说明的是，与源电极连接的过孔和与漏电极连接的过孔之间的对应关系可通过有源层位置的对应设置来确定。
除了上述说明之外，本发明对于过孔的具体数量、排列方式以及与源漏电极连接的方式不作其他特殊限制，只要能够根据应用的需要实现源电极\漏电极与有源层的连接即可。
另外需要说明的是，所述源电极与数据信号线之间的连接方式、以及所述漏电极与像素电极之间的连接方式可根据实际应用的需要来灵活设置，比如，在考虑过孔位置的情况下，每个过孔对应的源电极可与数据信号线直接连接，也可通过从数据信号线引出的信号线与数据信号线连接；每个过孔对应的漏电极亦可如此灵活设置。本发明对于源电极与数据信号线之间的连接方式，以及漏电极与像素电极之间的连接方式不作具体的限制，所有能够实现源电极与数据信号线之间以及漏电极与像素电极之间有效连接的方式均落入本发明的保护范围内。
在本发明一实施例中，所述方法还包括：
步骤5，在所述源电极和漏电极6上形成钝化层7，如图6e所示。
根据上述任一实施例制得的薄膜晶体管，由于采用了多个沟道的设计，在不改变有源层宽度的前提下，增加了子开关的数量，每个子开关都是一个独立的控制单元，且所有的子开关组成一个对于一个像素点进行控制的、以并联方式连接的子开关阵列。当有源层缺失导致的DGS问题发生在任意一个子开关处时，利用激光将相应子开关的源极信号输入端切断，这样就只需破坏一个子开关，而另外与之并联的子开关可以正常工作，从而保证了该像素的正常工作，进而提高了产品的良率和使用寿命。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (14)

1.一种薄膜晶体管，其特征在于，包括：有源层、刻蚀阻挡层、源电极和漏电极，其中：
所述刻蚀阻挡层设置于所述有源层的上方，且所述刻蚀阻挡层中形成有多个过孔；
所述源电极和漏电极设置于所述刻蚀阻挡层的上方，且所述源电极和漏电极利用所述刻蚀阻挡层中的多个过孔，通过所述有源层连接。
2.根据权利要求1所述的薄膜晶体管，其特征在于，所述刻蚀阻挡层中过孔的数量大于等于4。
3.根据权利要求1所述的薄膜晶体管，其特征在于，所述多个过孔规律或非规律形成在所述刻蚀阻挡层中，其中一部分过孔与源电极连接，其余过孔与漏电极连接。
4.根据权利要求1所述的薄膜晶体管，其特征在于，所述刻蚀阻挡层中过孔的数量为偶数，分为两行平行排列，所述源电极通过其中一行过孔与所述有源层连接，所述漏电极通过另一行过孔与所述有源层连接。
5.根据权利要求1所述的薄膜晶体管，其特征在于，所述有源层由金属氧化物半导体材料制得。
6.根据权利要求1所述的薄膜晶体管，其特征在于，还包括钝化层，所述钝化层设置于所述源电极和漏电极的上方。
7.一种阵列基板，其特征在于，包括如权利要求1-6任一项所述的薄膜晶体管。
8.一种显示装置，其特征在于，包括如权利要求7所述的阵列基板。
9.一种薄膜晶体管的制备方法，其特征在于，该制备方法包括以下步骤：
在有源层上形成刻蚀阻挡材料层，进行图形化，得到刻蚀阻挡层，其中，所述刻蚀阻挡层中形成有多个过孔；
在所述刻蚀阻挡层上形成电极材料层，并进行图形化，得到源电极和漏电极，所述源电极和漏电极利用所述刻蚀阻挡层中的多个过孔，通过所述有源层连接。
10.根据权利要求9所述的制备方法，其特征在于，所述刻蚀阻挡层中过孔的数量大于等于4。
11.根据权利要求9所述的制备方法，其特征在于，所述多个过孔规律或非规律形成在所述刻蚀阻挡层中，其中一部分过孔与源电极连接，其余过孔与漏电极连接。
12.根据权利要求9所述的制备方法，其特征在于，所述刻蚀阻挡层中过孔的数量为偶数，分为两行平行排列，所述源电极通过其中一行过孔与所述有源层连接，所述漏电极通过另一行过孔与所述有源层连接。
13.根据权利要求9所述的制备方法，其特征在于，所述有源层为金属氧化物半导体材料。
14.根据权利要求9所述的制备方法，其特征在于，在形成所述源电极和漏电极后，还包括在所述源电极和漏电极上形成钝化层的步骤。
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