WO2019174309A1 - 移位寄存器及其驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2019174309A1
WO2019174309A1 PCT/CN2018/118637 CN2018118637W WO2019174309A1 WO 2019174309 A1 WO2019174309 A1 WO 2019174309A1 CN 2018118637 W CN2018118637 W CN 2018118637W WO 2019174309 A1 WO2019174309 A1 WO 2019174309A1
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Prior art keywords
pull
node
transistor
potential
circuit
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PCT/CN2018/118637
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English (en)
French (fr)
Inventor
胡琪
敬辉
赵旦红
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US16/488,737 priority Critical patent/US11348501B2/en
Publication of WO2019174309A1 publication Critical patent/WO2019174309A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to a shift register and a driving method thereof, a gate driving circuit, and a display device.
  • the shift register in the related art generally includes a reset circuit for resetting the potential of the pull-up node in the shift register during the reset phase.
  • the reset circuit includes a transistor whose gate is connected to the reset signal input terminal.
  • the pre-charging circuit is respectively connected to the pre-charging signal input end and the pull-up node, and is configured to pre-charge the potential of the pull-up node in response to the pre-charging signal provided by the pre-charging signal input end;
  • a pull-down control circuit is respectively connected to the pull-up node, the pull-down node, and the reset signal end, for pulling down the potential of the pull-down node to a second potential in response to the potential of the pull-up node, and in response to the reset signal a reset signal provided at the input terminal pulls up the potential of the pull-down node to a first potential;
  • a pull-up circuit is respectively connected to the pull-up node and a signal output terminal for pulling up a potential of the signal output end in response to a potential of the pull-up node when outputting;
  • a pull-down circuit connected to the pull-down node and the signal output end, respectively, for pulling down a potential of the signal output end in response to the first potential of the pull-down node;
  • a reset circuit coupled to the pull-up node and the pull-down node, respectively, for disconnecting in response to the second potential of the pull-down node, and responsive to the first potential of the pull-down node,
  • the pull-up node performs a reset.
  • a control electrode of the first transistor is coupled to the precharge signal input terminal to receive the precharge signal, and a first pole of the first transistor is coupled to the precharge signal input terminal, the first transistor The second pole is connected to the pull-up node.
  • the shift register further includes:
  • a voltage stabilizing circuit connected to the first pole of the first transistor and the second clock signal input end for responding to the second clock signal of a high potential provided by the second clock signal input end
  • the first pole of the first transistor provides a high potential.
  • the voltage stabilizing circuit includes: a second transistor and a third transistor, a first pole of the first transistor being coupled to the precharge signal input terminal through the second transistor;
  • a control electrode of the second transistor is coupled to the first clock signal input terminal, a first pole of the second transistor is coupled to the precharge signal input terminal, and a second pole of the second transistor is coupled to the first a first pole connection of the transistor;
  • a control electrode of the third transistor is connected to a second clock signal input end, a first pole of the third transistor is connected to a first pole of the first transistor, and a second pole of the third transistor is The second clock signal input terminal is connected;
  • the second clock signal provided by the second clock signal input terminal is opposite to the phase of the first clock signal provided by the first clock signal input terminal.
  • the pull-down control circuit includes: a fourth transistor and a fifth transistor;
  • a control electrode of the fourth transistor is connected to the pull-up node, a first pole of the fourth transistor is connected to the first power terminal, and a second pole of the fourth transistor is connected to the pull-down node;
  • the control electrode of the fifth transistor is connected to the reset signal input terminal, the first pole of the fifth transistor is connected to the pull-down node, and the second pole of the fifth transistor is connected to the second power supply terminal.
  • the reset circuit includes: a sixth transistor
  • the control electrode of the sixth transistor is connected to the pull-down node, the first pole of the sixth transistor is connected to the pull-up node, and the second pole of the sixth transistor is connected to the first power terminal.
  • the pull-up circuit includes: a seventh transistor and a capacitor
  • a control electrode of the seventh transistor is connected to the pull-up node, a first pole of the seventh transistor is connected to a second clock signal input end, and a second pole of the seventh transistor is connected to the signal output end ;
  • the first end of the capacitor is connected to the pull-up node, and the second end of the capacitor is connected to the signal output end.
  • the pull-down circuit includes: an eighth transistor;
  • the control electrode of the eighth transistor is connected to the pull-down node, the first pole of the eighth transistor is connected to the signal output end, and the second pole of the eighth transistor is connected to the third power supply end.
  • the reset circuit is coupled to the first power terminal for providing the first power supply voltage provided by the first power supply terminal to the pull-up node in response to the first potential of the pull-down node, to The pull-up node performs resetting;
  • the pull-down control circuit is connected to the second power terminal for providing a second power voltage provided by the second power terminal to the pull-down node in response to the reset signal, to pull up the potential of the pull-down node Describe the first potential;
  • the pull-down circuit is connected to the third power terminal for supplying a third power voltage provided by the third power terminal to the signal output end in response to the potential of the pull-down node to pull down a potential of the signal output terminal;
  • the pull-up circuit is connected to the second clock signal input end for responsive to the potential of the pull-up node when outputting, and the second clock signal input by the second clock signal input terminal is used to pull up the signal output end Potential.
  • the first supply voltage and the third supply voltage are low level voltages and the second supply voltage is a high level voltage.
  • the present disclosure also provides a gate driving circuit comprising: a plurality of cascaded shift registers, wherein the shift register adopts any one of the shift registers described above;
  • each stage shift register is connected to the signal output end of the shift register of the previous stage;
  • the reset signal input of each stage shift register is coupled to the signal output of the next stage shift register.
  • the present disclosure also provides a display device comprising: a gate drive circuit as described above.
  • the present disclosure also provides a driving method of a shift register for driving the shift register described above, including the following steps:
  • the precharge path precharges a potential of the pullup node in response to a precharge signal provided by the precharge signal input terminal, and the pulldown control circuit responds to the potential of the pullup node to the pulldown node The potential is pulled down to the second potential;
  • the pull-up circuit pulls up the potential of the signal output end in response to the potential of the pull-up node
  • the pull-down control circuit pulls up the potential of the pull-down node to a first potential in response to a reset signal provided by the reset signal input terminal, and the reset circuit is responsive to the first potential pair of the pull-down node
  • the potential of the pull-up node is reset, and the pull-down circuit pulls down the potential of the signal output in response to the first potential of the pull-down node.
  • the driving method of the shift register further includes: the voltage stabilizing circuit providing a high level to a first pole of the first transistor.
  • the driving method of the shift register further includes the steps of:
  • the pull-down control circuit supplies a low level voltage to the pull-down node in response to a potential of the pull-up node to pull down a potential of the pull-down node to a second potential;
  • the pull-down control circuit supplies a high level voltage to the pull-down node in response to the reset signal to pull up a potential of the pull-down node to a first potential
  • the reset circuit is responsive to the pull-down a first potential of the node provides a low level voltage to the pull up node to reset the pull up node
  • the pull down circuit provides a low level voltage to the first potential in response to the pull down node
  • the signal output terminal pulls the potential of the signal output terminal.
  • 1 is a schematic diagram showing the circuit structure of a shift register in the related art
  • FIG. 2 is a schematic structural diagram of a circuit of a shift register according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a circuit of a shift register according to an embodiment of the present disclosure
  • FIG. 4 is a timing chart showing the operation of the shift register shown in FIG. 3;
  • FIG. 5 is a schematic structural diagram of a circuit of a shift register according to an embodiment of the present disclosure
  • FIG. 6 is a flowchart of a method for driving a shift register according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of a circuit of a gate driving circuit according to an embodiment of the present disclosure.
  • the transistor in the present disclosure may be a thin film transistor or a field effect transistor or other switching device having the same characteristics.
  • a transistor typically includes three poles: a gate, a source, and a drain.
  • the source and drain of the transistor are structurally symmetrical, and are interchangeable as desired.
  • the control electrode refers to the gate of the transistor, one of the first and second poles being the source and the other being the drain.
  • the transistor can be divided into an N-type transistor and a P-type transistor; when the transistor is an N-type transistor, the on-voltage is a high-level voltage, the off-voltage is a low-level voltage; when the transistor is a P-type In the case of a transistor, the on-voltage is a low-level voltage, and the off-voltage is a high-level voltage.
  • the transistor when the transistor is an N-type transistor, the on-voltage is a high-level voltage, the off-voltage is a low-level voltage; when the transistor is a P-type In the case of a transistor, the on-voltage is a low-level voltage, and the off-voltage is a high-level voltage.
  • each transistor is an N-type transistor will be exemplified.
  • the oxide TFT is usually depleted, and when the gate is in a floating state, the oxide TFT is easily turned on, and the output is leaky.
  • the output of the signal output of the register has an effect.
  • the shift register includes: a precharge path 1, a reset circuit 2, a pull-up circuit 3, and a pull-down circuit 4; wherein, a precharge path 1.
  • the reset circuit 2 and the pull-up circuit 3 are connected to the pull-up node PU.
  • the reset circuit 2 in the related art includes: a transistor T0 whose gate is connected to the reset signal input terminal RESET.
  • the precharge path 1 precharges the potential of the pull-up node PU under the control of the precharge signal provided by the precharge signal input terminal INPUT; at the same time, the gate of the transistor T0 is in a floating state.
  • the transistor T0 is easily turned on and outputs a leakage current, thereby affecting the precharge process.
  • the embodiment of the present disclosure provides a shift register, a driving method thereof, a gate driving circuit, and a display device.
  • FIG. 2 is a schematic diagram of a circuit structure of a shift register according to an embodiment of the present disclosure.
  • the shift register may include a precharge circuit 1, a reset circuit 2, a pull-up circuit 3, a pull-down circuit 4, and The control circuit 5 is pulled down.
  • the pre-charging circuit 1 is respectively connected to the pre-charge signal input terminal INPUT and the pull-up node PU for pre-charging the potential of the pull-up node PU in response to the pre-charge signal provided by the pre-charge signal input terminal INPUT.
  • the pull-down control circuit 5 is respectively connected to the pull-up node PU, the pull-down node PD and the reset signal terminal RESET for pulling down the potential of the pull-down node PD to the second potential in response to the potential of the pull-up node PU, and inputting in response to the reset signal
  • the reset signal provided by the terminal RESET pulls up the potential of the pull-down node PD to the first potential.
  • the pull-up circuit 3 is connected to the pull-up node PU and the signal output terminal OUTPUT, respectively, for pulling up the potential of the signal output terminal OUTPUT in response to the potential of the pull-up node PU at the time of output.
  • the pull-down circuit 4 is respectively connected to the pull-down node PD and the signal output terminal OUTPUT for pulling down the potential of the signal output terminal OUTPUT in response to the first potential of the pull-down node PD;
  • the reset circuit 2 is connected to the pull-up node PU and the pull-down node PD, respectively, for disconnecting in response to the second potential of the pull-down node PD, and resetting the pull-up node PU in response to the first potential of the pull-down node PD.
  • the shift register operation process provided by some embodiments of the present disclosure may include three phases: a precharge phase, an output phase, and a reset phase.
  • a precharge phase a precharge phase
  • an output phase a precharge phase
  • a reset phase a phase that is further configured as follows: for example, the reset circuit 2 is connected to the first power supply terminal VGL1 for responding to the pull-down node.
  • the first potential of the PD supplies the first power supply voltage provided by the first power supply terminal to the pull-up node PU to reset the pull-up node PU;
  • the pull-down control circuit 5 is connected to the second power supply terminal VGH2 for responding to the reset signal
  • the second power supply voltage provided by the power supply terminal is supplied to the pull-down node PD to pull up the potential of the pull-down node PD to the first potential;
  • the pull-down circuit 4 is connected to the third power supply terminal VGL3 for responding to the potential of the pull-down node PD to the third power supply.
  • the third supply voltage provided by the terminal is supplied to the signal output terminal OUTPUT to pull down the potential of the signal output terminal OUTPUT; the pull-up circuit is connected to the second clock signal input terminal CK2 for responding to the first of the pull-up node PU at the output The potential is pulled up to the potential of the signal output terminal OUTPUT.
  • the precharge path 1 precharges the potential of the pull-up node PU in response to the precharge signal provided by the precharge signal input terminal INPUT. For example, the precharge path 1 precharges the pull up node PU to a high potential in response to the precharge signal.
  • the pull-down control circuit 5 pulls down the pull-down node PD to the second potential in response to the potential of the pull-up node PU.
  • the second potential is low.
  • the pull-down control circuit 5 is connected to a first power supply terminal that supplies a low-level first power supply voltage VGL1, and the pull-down control circuit 5 writes a low-level first power supply voltage VGL1 to the pull-down in response to the high potential of the pull-up node PU
  • the node PD is configured to pull down the potential of the pull-down node PD to a low potential.
  • the pull-down node PD is always in a low state. Since the reset circuit 2 is controlled by the potential of the pull-down node PD, when the pull-down node PD is in the low state, the reset circuit 2 does not operate and does not output a leakage current, and thus does not precharge the pull-up node PU. The process has an impact, thus ensuring a pre-filling effect.
  • the pull-up circuit 3 pulls up the potential of the signal output terminal OUTPUT in response to the potential of the pull-up node PU.
  • the pull-up circuit 3 is connected to a clock signal input terminal CK2 that provides a second clock signal, and the clock signal provided by the clock signal input terminal CK2 is in a high state during the output phase, and the pull-up circuit 3 is responsive to the pull-up.
  • the high potential of the node PU writes a clock signal in a high state to the signal output terminal to effect pulling up the potential of the signal output terminal, for example, pulling up to a high potential.
  • the pull-down control circuit 5 pulls up the pull-down node PD to the first potential in response to the reset signal provided by the reset signal input terminal RESET.
  • the first potential can be high.
  • the pull-down control circuit 5 is connected to a second power supply terminal that supplies a second high power supply voltage VGH2, and the pull-down control circuit 5 writes a high-level second power supply voltage VGH2 to the pull-down node PD in response to the high-potential reset signal.
  • pull up the potential of the pull-down node PD for example, pull up to a high potential.
  • the reset circuit 2 resets the pull-up node PU in response to the first potential of the pull-down node PD.
  • the first potential is high.
  • the reset circuit 2 is connected to a first power supply terminal that supplies a low-level first power supply voltage VGL1, and the reset circuit 2 writes a low-level first power supply voltage VGL1 to the pull-up node PU in response to a high potential of the pull-down node PD, In order to achieve the pull-down of the potential of the pull-up node PU, for example, pull down to a low potential, thereby achieving reset.
  • the pull-down circuit 4 pulls down the potential of the signal output in response to the first potential of the pull-down node PD.
  • the pull-down circuit 4 is connected to a third power supply terminal that supplies a low-level third power supply voltage VGL3, and the pull-down circuit 4 writes a low-level third power supply voltage VGL3 to the signal output terminal OUTPUT in response to the high potential of the pull-down node PD To achieve the pull-down of the potential of the signal output terminal OUTPUT to a low potential.
  • the first power terminal can be the same as the third power terminal.
  • the technical solution of some embodiments of the present disclosure operates by setting a pull-down control circuit and using a pull-down node to control the reset circuit.
  • the pull-down control circuit pulls down the pull-down node potential so that the pull-down node is at a low level, so that the reset circuit does not operate or output a leakage current, thereby preventing the reset circuit from pre-charging the pull-up node.
  • the process has an impact.
  • FIG. 3 is a schematic diagram of a circuit structure of a shift register according to some embodiments of the present disclosure.
  • the shift register is a specific scheme based on the shift register shown in FIG. 2.
  • the precharge path 1 may include a first transistor T1; the control electrode of the first transistor T1 is connected to the precharge signal input terminal INPUT to receive a precharge signal, and the first pole of the first transistor T1 is connected to the precharge signal input terminal INPUT.
  • the second pole of the first transistor T1 is connected to the pull-up node PU.
  • the pull-down control circuit 5 may include a fourth transistor T4 and a fifth transistor T5; the control electrode of the fourth transistor T4 is connected to the pull-up node PU, and the first pole of the fourth transistor T4 is connected to the first power terminal.
  • the second pole of the fourth transistor T4 is connected to the pull-down node PD; the gate of the fifth transistor T5 is connected to the reset signal input terminal RESET to receive a reset signal, and the first pole of the fifth transistor T5 is The pull-down node PD is connected, and the second pole of the fifth transistor T5 is connected to the second power terminal to receive the second power voltage VGH2.
  • the reset circuit 2 may include a sixth transistor T6; the control electrode of the sixth transistor T6 is connected to the pull-down node PD, the first pole of the sixth transistor T6 is connected to the pull-up node PU, and the sixth transistor T6 is The diode is connected to the first power terminal to receive the first power voltage VGL1.
  • the pull-up circuit 3 may include a seventh transistor T7 and a capacitor C; the control electrode of the seventh transistor T7 is connected to the pull-up node PU, and the first pole of the seventh transistor T7 and the second clock signal input terminal CK2 Connected to receive the first clock signal, the second pole of the seventh transistor T7 is connected to the signal output terminal OUTPUT; the first end of the capacitor C is connected to the pull-up node PU, and the second end of the capacitor C is connected to the signal output terminal OUTPUT.
  • the pull-down circuit 4 may include an eighth transistor T8; the control electrode of the eighth transistor T8 is connected to the pull-down node PD, the first pole of the eighth transistor T8 is connected to the signal output terminal OUTPUT, and the eighth transistor T8 is connected The diode is connected to the third power terminal to receive the third power voltage VGL3.
  • the operation of the shift register shown in Fig. 3 will be described in detail below with reference to the accompanying drawings.
  • the first power terminal and the third power terminal provide low level voltages VGL1 and VGL3, and the second power terminal provides a high level voltage VGH2.
  • FIG. 4 is a timing chart of the operation of the shift register shown in FIG. 3. As shown in FIG. 4, the operation of the shift register includes three phases: a precharge phase t1, an output phase t2, and a reset phase t3.
  • the second clock signal provided by the second clock signal input terminal CK2 is in a low state, and the precharge signal provided by the precharge signal input terminal INPUT is in a high state, and the reset signal input terminal RESET provides The reset signal is in a low state.
  • the pre-charge signal is in a high state
  • the first transistor T1 is turned on, and the pre-charge signal in a high-level state charges the pull-up node PU through the first transistor T1, so that the pull-up node PU is in a high state.
  • the seventh transistor T7 is turned on, and the second clock signal in the low level state is written to the signal output terminal OUTPUT through the seventh transistor T7, that is, the signal output terminal OUTPUT outputs a low level.
  • the fourth transistor T4 is turned on, and the low-level first power supply voltage VGL1 is written to the pull-down node PD through the fourth transistor T4, so that the pull-down node PD is at a low level.
  • the sixth transistor T6 and the eighth transistor T8 are both in an off state in response to the low potential of the pull-down node PD. Therefore, the sixth transistor T6 does not output a leakage current, that is, does not affect the precharge process of the pull-up node PU.
  • the second clock signal provided by the second clock signal input terminal CK2 is in a high state
  • the precharge signal provided by the precharge signal input terminal INPUT is in a low state
  • the reset signal input terminal RESET provides a reset. The signal is in a low state.
  • the pre-charge signal is in a low state
  • the first transistor T1 is turned off, and the pull-up node PU is in a floating state, that is, the first end of the capacitor C is in a floating state, and the seventh transistor T7 is kept on, at a high level.
  • the second clock signal of the state is written to the signal output terminal OUTPUT through the seventh transistor T7, that is, the signal output terminal OUTPUT outputs a high level.
  • the voltage at the second end of the capacitor C jumps, under the self-lifting action of the capacitor C, the voltage at the first end of the capacitor C is pulled up to a higher potential, that is, the potential of the pull-up node PU is pulled up to Higher potential.
  • the fourth transistor T4 maintains the on state in response to the floating state of the pull-up node PU, so that the pull-down node PD maintains the low state.
  • the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 maintain an off state.
  • the second clock signal provided by the second clock signal input terminal CK2 is in a low state
  • the precharge signal provided by the precharge signal input terminal INPUT is in a low state
  • the reset signal input terminal RESET provides a reset. The signal is in a high state.
  • the fifth transistor T5 Since the reset signal is in a high state, the fifth transistor T5 is turned on, and the second power supply voltage VGH2 of the high level is written to the pull-down node PD through the fifth transistor T5, so that the pull-down node PD is in a high state.
  • the sixth transistor T6 and the eighth transistor T8 are both turned on in response to the high potential of the pull-down node PD.
  • the sixth transistor T6 Since the sixth transistor T6 is turned on, the first power supply voltage VGL1 of the low level is written to the pull-up node PU through the sixth transistor T6, and the pull-up node PU is reset to the low state, and the fourth transistor T4 and the The seven transistors T7 are all turned off.
  • the eighth transistor T8 Since the eighth transistor T8 is turned on, the third power supply voltage VGL3 of the low level is written to the signal output terminal OUTPUT through the eighth transistor T8, that is, the signal output terminal OUTPUT outputs a low level.
  • the technical solution of some embodiments of the present disclosure controls the reset circuit to operate by setting a pull-down control circuit, and using a pull-down node; when in the pre-charge phase, the fourth transistor in the pull-down control circuit is turned on, and the low-level voltage passes through The four transistors are written to the pull-down node so that the pull-down node is in a low state, thereby ensuring that the sixth transistor in the reset circuit is always in an off state, and the sixth transistor does not output a leakage current, thereby preventing the pull-up node from being pre- The charging process has an impact.
  • FIG. 5 is a schematic structural diagram of a circuit of a shift register according to an embodiment of the present disclosure.
  • the shift register shown in FIG. 5 may further include a voltage stabilizing circuit 6, a voltage stabilizing circuit 6 and a first
  • the first pole of the transistor T1 and the second clock signal input are respectively connected to provide a high potential to the first pole of the first transistor in response to the high potential second clock signal provided by the second clock signal input terminal.
  • the second pole of the first transistor T1 is connected to the pull-up node PU, so that it has the same higher potential as the pull-up node PU, and the voltage stabilizing circuit 6 responds to the high potential of the second clock signal input terminal.
  • a second clock signal providing a second clock signal of a high level to the first pole of the first transistor T1 (ie, node A), such that the voltage difference between the first pole and the second pole of the first transistor T1 is reduced, Therefore, leakage current can be prevented from being generated at the first transistor T1, thereby maintaining the stability of the PU voltage of the pull-up node.
  • the voltage stabilizing circuit 6 can include a second transistor T2 and a third transistor T3.
  • the first pole of the first transistor T1 is coupled to the precharge signal input terminal INPUT through the second transistor T2.
  • the control electrode of the second transistor T2 is connected to the first clock signal input terminal CK1, the first electrode of the second transistor T2 is connected to the precharge signal input terminal INPUT, and the second electrode of the second transistor T2 is coupled to the first electrode of the first transistor T1.
  • a control electrode of the third transistor T3 is connected to the second clock signal input terminal CK2, a first pole of the third transistor T3 is connected to the first pole of the first transistor T1, and a second pole and a second pole of the third transistor T3
  • the clock signal input terminal CK2 is connected.
  • the second clock signal provided by the second clock signal input terminal CK2 is opposite to the phase of the first clock signal supplied from the first clock signal input terminal CK1, as shown in FIG.
  • the second transistor T2 is turned on, and the precharge signal can be written to the pull-up node PU through the second transistor T2 and the first transistor T1.
  • the third transistor T3 is in the off state.
  • the second transistor T2 In the output phase, since the first clock signal is in a low state, the second transistor T2 is turned off. At the same time, since the second clock signal is in the high level state, the third transistor T3 is in the on state, and the second clock signal in the high level state is written to the first of the first transistor T1 through the third transistor T3. Therefore, the voltage difference between the first pole and the second pole of the first transistor T1 can be reduced.
  • the second transistor T2 is turned on; and since the precharge signal is in a low state, the first transistor T1 is turned off, and the precharge signal is not written at this time. Enter the pull-up node PU.
  • the voltage stabilizing circuit can provide a high level signal to the first pole of the first transistor during the output phase to reduce the first pole and the second pole of the first transistor.
  • the voltage difference can avoid leakage current at the first transistor, which is beneficial to maintain the stability of the pull-up node voltage.
  • At least one embodiment of the present disclosure provides a shift register, by setting a pull-down control circuit, and using a pull-down control circuit to control a pull-down node to be at a low level during a precharge phase, so that the reset circuit does not work or output.
  • the leakage current prevents the reset circuit from affecting the pre-charging process of the pull-up node.
  • FIG. 6 is a flowchart of a method for driving a shift register according to some embodiments of the present disclosure, as shown in FIG. 6 , wherein the shift register adopts the shift register provided in any of the above embodiments, and the shift register is driven.
  • the method may include steps S101 to S103.
  • Step S101 In the precharge phase, the precharge path precharges the potential of the pull-up node in response to the pre-charge signal provided by the pre-charge signal input terminal, and the pull-down control circuit pulls down the potential of the pull-down node in response to the potential of the pull-up node. The second potential.
  • Step S102 In the output stage, the pull-up circuit pulls up the potential of the signal output end in response to the potential of the pull-up node.
  • the output stage may further include: the voltage stabilization circuit provides a high level signal to the first pole of the first transistor to avoid leakage at the first transistor. Current.
  • Step S103 in the reset phase, the pull-down control circuit pulls up the potential of the pull-down node to the first potential in response to the reset signal provided by the reset signal input terminal, and the reset circuit resets the potential of the pull-up node in response to the first potential of the pull-down node;
  • the pull-down circuit pulls down the potential of the signal output in response to the first potential of the pull-down node.
  • the pull-down control circuit supplies a low level voltage to the pull-down node in response to a potential of the pull-up node to pull down a potential of the pull-down node to a second potential (eg, The second potential can be low);
  • the pull-down control circuit supplies a high level voltage to the pull-down node in response to the reset signal to pull up a potential of the pull-down node to a first potential (eg, the first potential may be high)
  • the reset circuit provides a low level voltage to the pull up node to reset the pull up node in response to a first potential of the pull down node, and the pull down circuit is responsive to the pull down node A potential supplies a low level voltage to the signal output, the potential of the signal output being pulled down.
  • Some embodiments of the present disclosure provide a driving method of a shift register by setting a pull-down control circuit and controlling a pull-down node to be at a low level by using a pull-down control circuit during a precharge phase, so that the reset circuit does not work.
  • the leakage current is not output, so that the reset circuit can be prevented from affecting the pre-charging process of the pull-up node.
  • FIG. 7 is a schematic structural diagram of a circuit of a gate driving circuit according to some embodiments of the present disclosure.
  • the gate driving circuit may include a plurality of cascaded shift registers SR_1/SR_2.../SR_N. -1/SR_N.
  • the shift registers SR_1 . . . SR_N may each adopt the shift register provided in any of the above embodiments.
  • the precharge signal input terminal INPUT of each stage shift register is connected to the signal output end of the shift register of the previous stage;
  • the reset signal input terminal RESET of each stage shift register is connected to the signal output terminal of the next stage shift register.
  • the first clock signal input terminal CK1 of the odd-numbered shift register is connected to the first clock signal line CKL1, and the second clock signal input terminal CK2 and the second clock signal line of the odd-numbered shift register are located.
  • the phase of the clock signal in the first clock signal line CKL1 and the second clock signal line CKL2 is opposite.
  • Some embodiments of the present disclosure provide a display device that can include a gate drive circuit, wherein the gate drive circuit employs the gate drive circuit provided in the above embodiments.

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Abstract

一种移位寄存器及其驱动方法、栅极驱动电路和显示装置，该移位寄存器可以包括：预充电路（1），分别连接至预充信号输入端和上拉节点，用于响应所述预充信号输入端所提供的预充信号，对所述上拉节点的电位进行预充；下拉控制电路（5），分别连接至所述上拉节点、下拉节点、复位信号短，用于响应于所述上拉节点的电位，将所述下拉节点的电位下拉为第二电位，以及响应于复位信号输入端所提供的复位信号将所述下拉节点的电位上拉为第一电位；上拉电路（3），分别连接至所述上拉节点、信号输出端，用于在输出时响应于所述上拉节点的电位将所述信号输出端的电位上拉；下拉电路（4），分别连接至所述下拉节点和所述信号输出端，用于响应于所述下拉节点的所述第一电位，将所述信号输出端的电位下拉；复位电路（2），分别连接至所述上拉节点和所述下拉节点，用于响应于所述下拉节点的所述第二电位而断开，以及响应于所述下拉节点的所述第一电位，对所述上拉节点进行复位。

Description

移位寄存器及其驱动方法、栅极驱动电路和显示装置
相关申请的交叉引用
本公开要求于2018年3月15日提交的中国专利申请No.201810214570.9的优先权，所公开的内容以引用的方式合并于此。
技术领域
本公开涉及一种移位寄存器及其驱动方法、栅极驱动电路和显示装置。
背景技术
相关技术中的移位寄存器内一般包括有复位电路，复位电路用于在复位阶段时对移位寄存器内的上拉节点的电位进行复位处理。其中，复位电路包括一个晶体管，该晶体管的栅极与复位信号输入端连接。
发明内容
本公开的一些实施例提供一种移位寄存器，包括：
预充电路，分别连接至预充信号输入端和上拉节点，用于响应所述预充信号输入端所提供的预充信号，对所述上拉节点的电位进行预充；
下拉控制电路，分别连接至所述上拉节点、下拉节点、复位信号端，用于响应于所述上拉节点的电位，将所述下拉节点的电位下拉为第二电位，以及响应于复位信号输入端所提供的复位信号将所述下拉节点的电位上拉为第一电位；
上拉电路，分别连接至所述上拉节点、信号输出端，用于在输出时响应于所述上拉节点的电位将所述信号输出端的电位上拉；
下拉电路，分别连接至所述下拉节点和所述信号输出端，用于响应于所述下拉节点的所述第一电位，将所述信号输出端的电位下拉；
复位电路，分别连接至所述上拉节点和所述下拉节点，用于响应于所述下拉节点的所述第二电位而断开，以及响应于所述下拉节点的所述第一电位，对所述上拉节点进行复位。
在一些实施例中，所述预充电路包括：第一晶体管；
所述第一晶体管的控制极与所述预充信号输入端连接以接收所述预充信号，所述第一晶体管的第一极与所述预充信号输入端连接，所述第一晶体管的第二极与所述上拉节点连接。
在一些实施例中，所述移位寄存器还包括：
稳压电路，与所述第一晶体管的第一极和所述第二时钟信号输入端连接，用于响应所述第二时钟信号输入端提供的高电位的所述第二时钟信号向所述第一晶体管的第一极提供高电位。
在一些实施例中，所述稳压电路包括：第二晶体管和第三晶体管，所述第一晶体管的第一极通过所述第二晶体管与所述预充信号输入端连接；
所述第二晶体管的控制极与第一时钟信号输入端连接，所述第二晶体管的第一极与所述预充信号输入端连接，所述第二晶体管的第二极与所述第一晶体管的第一极连接；
所述第三晶体管的控制极与第二时钟信号输入端连接，所述第三晶体管的第一极与所述第一晶体管的第一极连接，所述第三晶体管的第二极与所述第二时钟信号输入端连接；
所述第二时钟信号输入端所提供的第二时钟信号与所述第一时钟信号输入端所提供的第一时钟信号的相位相反。
在一些实施例中，所述下拉控制电路包括：第四晶体管和第五晶体管；
所述第四晶体管的控制极与所述上拉节点连接，所述第四晶体管的第一极与第一电源端连接，所述第四晶体管的第二极与所述下拉节点连接；
所述第五晶体管的控制极与所述复位信号输入端连接，所述第五晶体管的第一极与所述下拉节点连接，所述第五晶体管的第二极与第二电源端连接。
在一些实施例中，所述复位电路包括：第六晶体管；
所述第六晶体管的控制极与所述下拉节点连接，所述第六晶体管的第一极与所述上拉节点连接，所述第六晶体管的第二极与所述第一电源端连接。
在一些实施例中，所述上拉电路包括：第七晶体管和电容；
所述第七晶体管的控制极与所述上拉节点连接，所述第七晶体管的第一极与第二时钟信号输入端连接，所述第七晶体管的第二极与所述信号输出端连接；
所述电容的第一端与所述上拉节点连接，所述电容的第二端与所述信号输出端连接。
在一些实施例中，所述下拉电路包括：第八晶体管；
所述第八晶体管的控制极与所述下拉节点连接，所述第八晶体管的第一极与所述信号输出端连接，所述第八晶体管的第二极与第三电源端连接。
在一些实施例中，所述复位电路连接第一电源端，用于响应所述下拉节点的第一电位将所述第一电源端提供的第一电源电压提供至所述上拉节点，以对所述上拉节点进行复位；
所述下拉控制电路连接第二电源端，用于响应所述复位信号将所述第二电源端提供的第二电源电压提供至所述下拉节点，以将所述下拉节点的电位上拉为所述第一电位；
所述下拉电路连接第三电源端，用于响应所述下拉节点的电位将所述第三电源端提供的第三电源电压提供至所述信号输出端，以对所述信号输出端的电位下拉；
所述上拉电路连接第二时钟信号输入端，用于在输出时响应于所述上拉节点的电位，利用所述第二时钟信号输入端输入的第二时钟信号上拉所述信号输出端的电位。
在一些实施例中，所述第一电源电压和所述第三电源电压为低电平电压，所述第二电源电压为高电平电压。
本公开还提供一种栅极驱动电路，包括：若干个级联的移位寄存器，所述移位寄存器采用上述的任一所述移位寄存器；
除第一级移位寄存器外，每一级移位寄存器的预充信号输入端与上一级移位寄存器的信号输出端连接；
除最后一级移位寄存器外，每一级移位寄存器的复位信号输入端与下一级移位寄存器的信号输出端连接。
本公开还提供一种显示装置，包括：如上述所述的栅极驱动电路。
本公开还提供一种移位寄存器的驱动方法，用于驱动上述的所述移位寄存器，包括以下步骤：
在预充阶段，所述预充电路响应于预充信号输入端所提供的预充信号对上拉节点的电位进行预充，下拉控制电路响应于所述上拉节点的电位将所述下拉节点的电位下拉至第二电位；
在输出阶段，所述上拉电路响应于所述上拉节点的电位将信号输出端的电位进行上拉；
在复位阶段，所述下拉控制电路响应于复位信号输入端所提供的复位信号将所述下拉节点的电位上拉至第一电位，复位电路响应于所述下拉节点的所述第一电位对所述上拉节点的电位进行复位，所述下拉电路响应于所述下拉节点的所述第一电位对所述信号输出端的电位进行下拉。
在一些实施例中，所述移位寄存器的驱动方法还包括：所述稳压电路向所述第一晶体管的第一极提供高电平。
在一些实施例中，所述移位寄存器的驱动方法还包括步骤：
在预充阶段中，所述下拉控制电路响应于所述上拉节点的电位将低电平电压提供至所述下拉节点，以将所述下拉节点的电位下拉至第二电位；
在复位阶段中，所述下拉控制电路响应于所述复位信号将高电平电压提供至所述下拉节点以将所述下拉节点的电位上拉为第一电位，所述复位电路响应所述下拉节点的第一电位将低电平电压提供至所述上拉节点以对所述上拉节点进行复位，以及所述下拉电路响应于所述下拉节点的第一电位将低电平电压提供至所述信号输出端，以下拉所述信号输出端的电位。
附图说明
图1为相关技术中的移位寄存器的电路结构示意图；
图2为本公开的一个实施例提供的一种移位寄存器的电路结构示意图；
图3为本公开的一个实施例提供的一种移位寄存器的电路结构示意图；
图4为图3所示移位寄存器的工作时序图；
图5为本公开的一个实施例提供的一种移位寄存器的电路结构示意图；
图6为本公开的一个实施例提供的一种移位寄存器的驱动方法的流程图；
图7为本公开的一个实施例提供的一种栅极驱动电路的电路结构示意图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的一种移位寄存器及其驱动方法、栅极驱动电路和显示装置进行详细描述。本公开中的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件。晶体管一般包括三个极：栅极、源极和漏极，晶体管中的源极和漏极在结构上是对称的，根据需要两者是可以互换的。在本公开中，控制极是指晶体管的栅极，第一极和第二极中的一者为源极，另一者为漏极。
此外，按照晶体管特性，可将晶体管分为N型晶体管和P型晶体管；当晶体管为N型晶体管时，其导通电压为高电平电压，截止电压为低电平电压；当晶体管为P型晶体管时，其导通电压为低电平电压，截止电压为高电平电压；本公开实施例中将以各晶体管均为N型晶体管为例进行示例性说明。
在实际应用中发现，当移位寄存器工作于预充阶段时，复位电路中的晶体管的栅极处于悬空状态。
由于相关技术中的显示面板制作过程中常用氧化物薄膜晶体管 (Thin Film Transistor，TFT)，氧化物TFT通常为耗尽型，在其栅极处于悬空状态时，氧化物TFT容易导通，输出漏电流；即，复位电路中的晶体管会在预充阶段时导通，外部的杂质信号容易写入，即复位电路输出漏电流，从而影响上拉节点的电位的预充过程，进而会对移位寄存器的信号输出端的输出造成影响。
图1为相关技术中的移位寄存器的电路结构示意图，如图1所示，该移位寄存器包括：预充电路1、复位电路2、上拉电路3和下拉电路4；其中，预充电路1、复位电路2和上拉电路3连接于上拉节点PU。相关技术中的复位电路2包括：一个晶体管T0，晶体管T0的栅极与复位信号输入端RESET连接。在预充阶段时，预充电路1在预充信号输入端INPUT所提供的预充信号的控制下对上拉节点PU的电位进行预充电处理；与此同时，晶体管T0的栅极处于floating状态，晶体管T0容易导通并输出漏电流，从而预充过程造成影响。
因此，如何避免在预充阶段时复位电路输出漏电流对预充过程造成影响，是本领域技术人员亟待解决的技术问题。
为解决相关技术中复位电路在预充阶段时输出漏电流而影响预充过程的问题，本公开实施例提供了一种移位寄存器及其驱动方法、栅极驱动电路和显示装置。
图2为本公开一实施例提供的一种移位寄存器的电路结构示意图，如图2所示，该移位寄存器可以包括预充电路1、复位电路2、上拉电路3、下拉电路4和下拉控制电路5。
预充电路1与预充信号输入端INPUT和上拉节点PU分别连接，其用于响应预充信号输入端INPUT所提供的预充信号，对上拉节点PU的电位进行预充。
下拉控制电路5与上拉节点PU、下拉节点PD和复位信号端RESET分别连接，其用于响应于上拉节点PU的电位将下拉节点PD的电位下拉为第二电位，以及响应于复位信号输入端RESET所提供的复位信号将下拉节点PD的电位上拉为第一电位。
上拉电路3与上拉节点PU、信号输出端OUTPUT分别连接，其用于在输出时响应于上拉节点PU的电位，将信号输出端OUTPUT的电位 上拉。
下拉电路4与下拉节点PD和信号输出端OUTPUT分别连接，其用于响应于下拉节点PD的第一电位，将信号输出端OUTPUT的电位下拉；
复位电路2与上拉节点PU和下拉节点PD分别连接，其用于响应于下拉节点PD的第二电位而断开，以及响应于下拉节点PD的第一电位，对上拉节点PU进行复位。
本公开的一些实施例提供的移位寄存器工作过程可以包括三个阶段：预充阶段、输出阶段和复位阶段。下面将继续参照图2所示的移位寄存器的电路结构进行描述，并且该实施例中的移位寄存器还进一步地配置如下：例如，复位电路2连接第一电源端VGL1，用于响应下拉节点PD的第一电位将第一电源端提供的第一电源电压提供至上拉节点PU，以对上拉节点PU进行复位；下拉控制电路5连接第二电源端VGH2，用于响应复位信号将第二电源端提供的第二电源电压提供至下拉节点PD，以将下拉节点PD的电位上拉为第一电位；下拉电路4连接第三电源端VGL3，用于响应下拉节点PD的电位将第三电源端提供的第三电源电压提供至信号输出端OUTPUT，以对信号输出端OUTPUT的电位下拉；上拉电路连接第二时钟信号输入端CK2，用于在输出时响应于上拉节点PU的第一电位，对信号输出端OUTPUT的电位上拉。
在预充阶段时，预充电路1响应预充信号输入端INPUT所提供的预充信号，对上拉节点PU的电位进行预充。例如，预充电路1响应预充信号对上拉节点PU进行预充至高电位。
与此同时，下拉控制电路5响应于上拉节点PU的电位将下拉节点PD下拉为第二电位。例如，该第二电位为低电位。下拉控制电路5与一提供低电平的第一电源电压VGL1的第一电源端连接，下拉控制电路5响应于上拉节点PU的高电位将低电平的第一电源电压VGL1写入至下拉节点PD，以实现将下拉节点PD的电位下拉至低电位。
在预充阶段过程中，由于下拉节点PD的电位被下拉至低电位，因此下拉节点PD始终处于低电平状态。由于复位电路2受控于下拉 节点PD的电位，因此当下拉节点PD处于低电平状态时，复位电路2不会进行工作也不会输出漏电流，因而不会对上拉节点PU的预充电过程造成影响，从而保证了预充效果。
在输出阶段时，上拉电路3响应于上拉节点PU的电位将信号输出端OUTPUT的电位进行上拉。例如，上拉电路3与一提供第二时钟信号的时钟信号输入端CK2连接，且该时钟信号输入端CK2提供的时钟信号在输出阶段时处于高电平状态，上拉电路3响应于上拉节点PU的高电位将处于高电平状态的时钟信号写入至信号输出端，以实现将信号输出端的电位上拉，例如上拉至高电位。
在复位阶段时，下拉控制电路5响应复位信号输入端RESET所提供的复位信号将下拉节点PD上拉为第一电位。例如，该第一电位可以为高电位。下拉控制电路5与一提供高电平的第二电源电压VGH2的第二电源端连接，下拉控制电路5响应高电位的复位信号将高电平的第二电源电压VGH2写入至下拉节点PD，以实现将下拉节点PD的电位上拉，例如上拉至高电位。
此外，复位电路2响应于下拉节点PD的第一电位，对上拉节点PU进行复位。例如，该第一电位为高电位。复位电路2与一提供低电平的第一电源电压VGL1的第一电源端连接，复位电路2响应于下拉节点PD的高电位将低电平的第一电源电压VGL1写入至上拉节点PU，以实现将上拉节点PU的电位下拉，例如，下拉至低电位，从而实现复位。
与此同时，下拉电路4响应于下拉节点PD的第一电位对信号输出端的电位进行下拉。下拉电路4与一提供低电平的第三电源电压VGL3的第三电源端连接，下拉电路4响应于下拉节点PD的高电位将低电平的第三电源电压VGL3写入至信号输出端OUTPUT，以实现将信号输出端OUTPUT的电位下拉至低电位。需要说明的是，第一电源端可以与第三电源端相同。
本公开的一些实施例的技术方案通过设置下拉控制电路，并利用下拉节点来控制复位电路进行工作。当在预充阶段时，下拉控制电路将下拉节点电位下拉以使得下拉节点处于低电平，使得复位电路不 会进行工作也不会输出漏电流，从而能避免复位电路对上拉节点的预充电过程造成影响。
图3为本公开的一些实施例提供的一种移位寄存器的电路结构示意图，如图3所示，该移位寄存器为基于图2所示移位寄存器的一种具体方案。其中，预充电路1可以包括第一晶体管T1；第一晶体管T1的控制极与预充信号输入端INPUT连接以接收预充信号，第一晶体管T1的第一极与预充信号输入端INPUT连接，第一晶体管T1的第二极与上拉节点PU连接。
在一些实施例中，下拉控制电路5可以包括第四晶体管T4和第五晶体管T5；第四晶体管T4的控制极与上拉节点PU连接，第四晶体管T4的第一极与第一电源端连接以接收第一电源电压VGL1，第四晶体管T4的第二极与下拉节点PD连接；第五晶体管T5的控制极与复位信号输入端RESET连接以接收复位信号，第五晶体管T5的第一极与下拉节点PD连接，第五晶体管T5的第二极与第二电源端连接以接收第二电源电压VGH2。
在一些实施例中，复位电路2可以包括第六晶体管T6；第六晶体管T6的控制极与下拉节点PD连接，第六晶体管T6的第一极与上拉节点PU连接，第六晶体管T6的第二极与第一电源端连接以接收第一电源电压VGL1。
在一些实施例中，上拉电路3可以包括第七晶体管T7和电容C；第七晶体管T7的控制极与上拉节点PU连接，第七晶体管T7的第一极与第二时钟信号输入端CK2连接以接收第一时钟信号，第七晶体管T7的第二极与信号输出端OUTPUT连接；电容C的第一端与上拉节点PU连接，电容C的第二端与信号输出端OUTPUT连接。
在一些实施例中，下拉电路4可以包括第八晶体管T8；第八晶体管T8的控制极与下拉节点PD连接，第八晶体管T8的第一极与信号输出端OUTPUT连接，第八晶体管T8的第二极与第三电源端连接以接收第三电源电压VGL3。
下面将结合附图来对图3所示移位寄存器的工作过程进行详细描述。其中，第一电源端和第三电源端提供低电平电压VGL1和VGL3， 第二电源端提供高电平电压VGH2。
图4为图3所示移位寄存器的工作时序图，如图4所示，该移位寄存器的工作过程包括三个阶段：预充阶段t1、输出阶段t2和复位阶段t3。
在预充阶段t1时，第二时钟信号输入端CK2提供的第二时钟信号处于低电平状态，预充信号输入端INPUT提供的预充信号处于高电平状态，复位信号输入端RESET提供的复位信号处于低电平状态。
由于预充信号处于高电平状态，则第一晶体管T1导通，处于高电平状态的预充信号通过第一晶体管T1对上拉节点PU进行充电，使得上拉节点PU处于高电平状态，此时第七晶体管T7导通，处于低电平状态的第二时钟信号通过第七晶体管T7写入至信号输出端OUTPUT，即信号输出端OUTPUT输出低电平。
与此同时，由于上拉节点PU处于高电平状态，因此第四晶体管T4导通，低电平的第一电源电压VGL1通过第四晶体管T4写入至下拉节点PD，使得下拉节点PD处于低电平状态，此时第六晶体管T6和第八晶体管T8响应于下拉节点PD的低电位均处于截止状态。因此，第六晶体管T6不会输出漏电流，即不会影响上拉节点PU的预充电过程。
在输出阶段t2时，第二时钟信号输入端CK2提供的第二时钟信号处于高电平状态，预充信号输入端INPUT提供的预充信号处于低电平状态，复位信号输入端RESET提供的复位信号处于低电平状态。
由于预充信号处于低电平状态，则第一晶体管T1截止，上拉节点PU处于悬空状态，即电容C的第一端处于悬空状态，此时第七晶体管T7维持导通，处于高电平状态的第二时钟信号通过第七晶体管T7写入至信号输出端OUTPUT，即信号输出端OUTPUT输出高电平。在此过程中，由于电容C的第二端的电压发生跳变，在电容C自举作用下，电容C第一端的电压会上拉至更高电位，即上拉节点PU的电位上拉至更高电位。
与此同时，由于上拉节点PU处于悬空状态，第四晶体管T4响应上拉节点PU的悬空状态而维持导通状态，从而下拉节点PD维持低 电平状态。第五晶体管T5、第六晶体管T6和第八晶体管T8维持截止状态。
在复位阶段t3时，第二时钟信号输入端CK2提供的第二时钟信号处于低电平状态，预充信号输入端INPUT提供的预充信号处于低电平状态，复位信号输入端RESET提供的复位信号处于高电平状态。
由于复位信号处于高电平状态，则第五晶体管T5导通，高电平的第二电源电压VGH2通过第五晶体管T5写入至下拉节点PD，使得下拉节点PD处于高电平状态，此时第六晶体管T6和第八晶体管T8响应于下拉节点PD的高电位均导通。
由于第六晶体管T6导通，则低电平的第一电源电压VGL1通过第六晶体管T6写入至上拉节点PU，将上拉节点PU复位至低电平状态，此时第四晶体管T4和第七晶体管T7均截止。
由于第八晶体管T8导通，则低电平的第三电源电压VGL3通过第八晶体管T8写入至信号输出端OUTPUT，即信号输出端OUTPUT输出低电平。
本公开的一些实施例的技术方案通过设置下拉控制电路，并利用下拉节点来控制复位电路进行工作；当在预充阶段时，下拉控制电路中的第四晶体管导通，低电平电压通过第四晶体管写入至下拉节点，以使得下拉节点处于低电平状态，从而保证复位电路中的第六晶体管始终处于截止状态，第六晶体管不会输出漏电流，进而不会对上拉节点的预充电过程造成影响。
图5为本公开一实施例提供的一种移位寄存器的电路结构示意图，如图5所示，图5所示的移位寄存器中还可以包括稳压电路6，稳压电路6与第一晶体管T1的第一极和所述第二时钟信号输入端分别连接，用于响应第二时钟信号输入端提供的高电位的第二时钟信号向第一晶体管的第一极提供高电位。例如，在输出阶段时，第一晶体管T1的第二极与上拉节点PU连接，因而其具有与上拉节点PU相同的更高电位，稳压电路6响应第二时钟信号输入端的高电位的第二时钟信号，向第一晶体管T1的第一极(即节点A)提供高电平的第二时钟信号，使得减小第一晶体管T1的第一极与第二极之间的电压差， 从而能避免第一晶体管T1处产生漏电流，进而能维持上拉节点PU电压的稳定。
在一些实施例中，稳压电路6可以包括第二晶体管T2和第三晶体管T3，第一晶体管T1的第一极通过第二晶体管T2与预充信号输入端INPUT连接。第二晶体管T2的控制极与第一时钟信号输入端CK1连接，第二晶体管T2的第一极与预充信号输入端INPUT连接，第二晶体管T2的第二极与第一晶体管T1的第一极连接；第三晶体管T3的控制极与第二时钟信号输入端CK2连接，第三晶体管T3的第一极与第一晶体管T1的第一极连接，第三晶体管T3的第二极与第二时钟信号输入端CK2连接。第二时钟信号输入端CK2所提供的第二时钟信号与第一时钟信号输入端CK1所提供的第一时钟信号的相位相反，如图4所示。
图5所示移位寄存器的工作时序可参照图4中所示，具体工作过程可参见上述实施例中的内容，此处不再赘述。此处仅对稳压电路6工作过程进行描述。
在预充阶段时，由于第一时钟信号处于高电平状态，因此第二晶体管T2导通，预充信号可通过第二晶体管T2、第一晶体管T1写入至上拉节点PU。与此同时，由于第二时钟信号处于低电平状态，因此第三晶体管T3处于截止状态。
在输出阶段时，由于第一时钟信号处于低电平状态，因此第二晶体管T2截止。与此同时，由于第二时钟信号处于高电平状态，因此第三晶体管T3处于导通状态，处于高电平状态的第二时钟信号通过第三晶体管T3写入至第一晶体管T1的第一极，从而能减小第一晶体管T1的第一极与第二极之间的电压差。
在复位阶段时，由于第一时钟信号处于高电平状态，因此第二晶体管T2导通；又由于预充信号处于低电平状态，因此第一晶体管T1截止，此时预充信号不会写入至上拉节点PU。
在本实施例中，通过设置稳压电路，稳压电路可在输出阶段时向第一晶体管的第一极提供高电平信号，以减小第一晶体管的第一极与第二极之间的电压差，从而能避免第一晶体管处产生漏电流，进而 有利于维持上拉节点电压的稳定。
本公开至少一实施例提供了一种移位寄存器，通过设置下拉控制电路，并在预充阶段时利用下拉控制电路控制下拉节点处于低电平，以使得复位电路不会进行工作也不会输出漏电流，从而能避免复位电路对上拉节点的预充电过程造成影响。
图6为本公开一些实施例提供的一种移位寄存器的驱动方法的流程图，如图6所示，其中移位寄存器采用上述任一实施例中提供的移位寄存器，移位寄存器的驱动方法可以包括步骤S101至步骤S103。
步骤S101、在预充阶段，预充电路响应预充信号输入端所提供的预充信号对上拉节点的电位进行预充，下拉控制电路响应于上拉节点的电位将下拉节点的电位下拉至第二电位。
步骤S102、在输出阶段，上拉电路响应于上拉节点的电位将信号输出端的电位进行上拉。
需要说明的是，当移位寄存器中包括有稳压电路时，在输出阶段时还可以包括：稳压电路向第一晶体管的第一极提供高电平信号，以避免第一晶体管处产生漏电流。
步骤S103、在复位阶段，下拉控制电路响应复位信号输入端所提供的复位信号将下拉节点的电位上拉至第一电位，复位电路响应于下拉节点的第一电位对上拉节点电位进行复位；下拉电路响应于下拉节点的第一电位对信号输出端的电位进行下拉。
进一步地，在预充阶段，所述下拉控制电路响应于所述上拉节点的电位将低电平电压提供至所述下拉节点，以将所述下拉节点的电位下拉至第二电位(例如该第二电位可以为低电位)；
在复位阶段，所述下拉控制电路响应于所述复位信号将高电平电压提供至所述下拉节点以将所述下拉节点的电位上拉为第一电位(例如该第一电位可以为高电位)，所述复位电路响应所述下拉节点的第一电位将低电平电压提供至所述上拉节点以对所述上拉节点进行复位，以及所述下拉电路响应于所述下拉节点的第一电位将低电平电压提供至所述信号输出端，以下拉所述信号输出端的电位。
对于上述步骤S101～步骤S103的具体描述，可参见上述任一实 施例中的内容，此处不再赘述。
本公开的一些实施例提供了一种移位寄存器的驱动方法，通过设置下拉控制电路，并在预充阶段时利用下拉控制电路控制下拉节点处于低电平，以使得复位电路不会进行工作也不会输出漏电流，从而能避免复位电路对上拉节点的预充电过程造成影响。
图7为本公开的一些实施例提供的一种栅极驱动电路的电路结构示意图，如图7所示，该栅极驱动电路可以包括若干个级联的移位寄存器SR_1/SR_2……/SR_N-1/SR_N。其中，移位寄存器SR_1……SR_N均可采用上述任一实施例中任一提供的移位寄存器。
在该栅极驱动电路中，除第一级移位寄存器SR_1外，每一级移位寄存器的预充信号输入端INPUT与上一级移位寄存器的信号输出端连接；除最后一级移位寄存器SR_N外，每一级移位寄存器的复位信号输入端RESET与下一级移位寄存器的信号输出端连接。
在实际应用中，位于奇数级的移位寄存器的第一时钟信号输入端CK1与第一时钟信号线CKL1连接，位于奇数级的移位寄存器的第二时钟信号输入端CK2与第二时钟信号线CKL2连接；位于偶数级的移位寄存器的第一时钟信号输入端CK1与第二时钟信号线CKL2连接，位于偶数级的移位寄存器的第二时钟信号输入端CK2与第一时钟信号线CKL1连接。第一时钟信号线CKL1与第二时钟信号线CKL2中时钟信号的相位相反。
本公开的一些实施例提供了一种显示装置，该显示装置可以包括栅极驱动电路，其中栅极驱动电路采用上述实施例中提供的栅极驱动电路。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (15)

  1. 一种移位寄存器，包括：
    预充电路，分别连接至预充信号输入端和上拉节点，用于响应所述预充信号输入端所提供的预充信号，对所述上拉节点的电位进行预充；
    下拉控制电路，分别连接至所述上拉节点、下拉节点、复位信号端，用于响应于所述上拉节点的电位，将所述下拉节点的电位下拉为第二电位，以及响应于复位信号输入端所提供的复位信号将所述下拉节点的电位上拉为第一电位；
    上拉电路，分别连接至所述上拉节点、信号输出端，用于在输出时响应于所述上拉节点的电位将所述信号输出端的电位上拉；
    下拉电路，分别连接至所述下拉节点和所述信号输出端，用于响应于所述下拉节点的所述第一电位，将所述信号输出端的电位下拉；
    复位电路，分别连接至所述上拉节点和所述下拉节点，用于响应于所述下拉节点的所述第二电位而断开，以及响应于所述下拉节点的所述第一电位，对所述上拉节点进行复位。
  2. 根据权利要求1所述的移位寄存器，其中，所述预充电路包括：第一晶体管；
    所述第一晶体管的控制极与所述预充信号输入端连接，所述第一晶体管的第一极与所述预充信号输入端连接，所述第一晶体管的第二极与所述上拉节点连接。
  3. 根据权利要求2所述的移位寄存器，还包括：
    稳压电路，与所述第一晶体管的第一极和所述第二时钟信号输入端连接，用于响应所述第二时钟信号输入端提供的高电位向所述第一晶体管的第一极提供高电位。
  4. 根据权利要求3所述的移位寄存器，其中，所述稳压电路包括：第二晶体管和第三晶体管，所述第一晶体管的第一极通过所述第二晶体管与所述预充信号输入端连接；
    所述第二晶体管的控制极与第一时钟信号输入端连接，所述第二晶体管的第一极与所述预充信号输入端连接，所述第二晶体管的第二极与所述第一晶体管的第一极连接；
    所述第三晶体管的控制极与第二时钟信号输入端连接，所述第三晶体管的第一极与所述第一晶体管的第一极连接，所述第三晶体管的第二极与所述第二时钟信号输入端连接；
    所述第二时钟信号输入端所提供的第二时钟信号与所述第一时钟信号输入端所提供的第一时钟信号的相位相反。
  5. 根据权利要求2或4所述的移位寄存器，其中，所述下拉控制电路包括：第四晶体管和第五晶体管；
    所述第四晶体管的控制极与所述上拉节点连接，所述第四晶体管的第一极与第一电源端连接，所述第四晶体管的第二极与所述下拉节点连接；
    所述第五晶体管的控制极与所述复位信号输入端连接，所述第五晶体管的第一极与所述下拉节点连接，所述第五晶体管的第二极与第二电源端连接。
  6. 根据权利要求5所述的移位寄存器，其中，所述复位电路包括：第六晶体管；
    所述第六晶体管的控制极与所述下拉节点连接，所述第六晶体管的第一极与所述上拉节点连接，所述第六晶体管的第二极与所述第一电源端连接。
  7. 根据权利要求2或6所述的移位寄存器，其中，所述上拉电路包括：第七晶体管和电容；
    所述第七晶体管的控制极与所述上拉节点连接，所述第七晶体 管的第一极与第二时钟信号输入端连接，所述第七晶体管的第二极与所述信号输出端连接；
    所述电容的第一端与所述上拉节点连接，所述电容的第二端与所述信号输出端连接。
  8. 根据权利要求2或7所述的移位寄存器，其中，所述下拉电路包括：第八晶体管；
    所述第八晶体管的控制极与所述下拉节点连接，所述第八晶体管的第一极与所述信号输出端连接，所述第八晶体管的第二极与第三电源端连接。
  9. 根据权利要求1所述的移位寄存器，其中，
    所述复位电路连接第一电源端，用于响应所述下拉节点的第一电位将所述第一电源端提供的第一电源电压提供至所述上拉节点，以对所述上拉节点进行复位；
    所述下拉控制电路连接第二电源端，用于响应所述复位信号将所述第二电源端提供的第二电源电压提供至所述下拉节点，以将所述下拉节点的电位上拉为所述第一电位；
    所述下拉电路连接第三电源端，用于响应所述下拉节点的电位将所述第三电源端提供的第三电源电压提供至所述信号输出端，以对所述信号输出端的电位下拉；
    所述上拉电路连接第二时钟信号输入端，用于在输出时响应于所述上拉节点的电位，利用所述第二时钟信号输入端输入的第二时钟信号上拉所述信号输出端的电位。
  10. 根据权利要求9所述的移位寄存器，其中，所述第一电源电压和所述第三电源电压为低电平电压，所述第二电源电压为高电平电压。
  11. 一种栅极驱动电路，包括：若干个级联的移位寄存器，所述移位寄存器采用上述权利要求1-10中任一所述移位寄存器；
    除第一级移位寄存器外，每一级移位寄存器的预充信号输入端与上一级移位寄存器的信号输出端连接；
    除最后一级移位寄存器外，每一级移位寄存器的复位信号输入端与下一级移位寄存器的信号输出端连接。
  12. 一种显示装置，包括：如上述权利要求11所述的栅极驱动电路。
  13. 一种移位寄存器的驱动方法，用于驱动上述权利要求1-10中任一所述移位寄存器，包括以下步骤：
    在预充阶段，所述预充电路响应于预充信号输入端所提供的预充信号对上拉节点的电位进行预充，下拉控制电路响应于所述上拉节点的电位将所述下拉节点的电位下拉至第二电位；
    在输出阶段，所述上拉电路响应于所述上拉节点的电位将信号输出端的电位进行上拉；
    在复位阶段，所述下拉控制电路响应于复位信号输入端所提供的复位信号将所述下拉节点的电位上拉至第一电位，复位电路响应于所述下拉节点的所述第一电位对所述上拉节点的电位进行复位，所述下拉电路响应于所述下拉节点的所述第一电位对所述信号输出端的电位进行下拉。
  14. 根据权利要求13所述的移位寄存器的驱动方法，其中，还包括：
    所述稳压电路向所述第一晶体管的第一极提供高电平。
  15. 根据权利要求13所述的移位寄存器的驱动方法，进一步包括步骤：
    在预充阶段中，所述下拉控制电路响应于所述上拉节点的电位 将低电平电压提供至所述下拉节点，以将所述下拉节点的电位下拉至第二电位；
    在复位阶段中，所述下拉控制电路响应于所述复位信号将高电平电压提供至所述下拉节点以将所述下拉节点的电位上拉为第一电位，所述复位电路响应所述下拉节点的第一电位将低电平电压提供至所述上拉节点以对所述上拉节点进行复位，以及所述下拉电路响应于所述下拉节点的第一电位将低电平电压提供至所述信号输出端，以下拉所述信号输出端的电位。
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