WO2019152226A1 - Chaînes de transistors en couches minces flash non-ou verticales tridimensionnelles - Google Patents

Chaînes de transistors en couches minces flash non-ou verticales tridimensionnelles Download PDF

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Publication number
WO2019152226A1
WO2019152226A1 PCT/US2019/014319 US2019014319W WO2019152226A1 WO 2019152226 A1 WO2019152226 A1 WO 2019152226A1 US 2019014319 W US2019014319 W US 2019014319W WO 2019152226 A1 WO2019152226 A1 WO 2019152226A1
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Prior art keywords
vertical
memory structure
local
bit line
string
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PCT/US2019/014319
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English (en)
Inventor
Eli Harari
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Sunrise Memory Corporation
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Priority claimed from US16/107,732 external-priority patent/US10249370B2/en
Application filed by Sunrise Memory Corporation filed Critical Sunrise Memory Corporation
Priority to JP2020541723A priority Critical patent/JP7141462B2/ja
Priority to KR1020227033231A priority patent/KR102626137B1/ko
Priority to CN201980024463.2A priority patent/CN111937147B/zh
Priority to KR1020207025160A priority patent/KR102448489B1/ko
Publication of WO2019152226A1 publication Critical patent/WO2019152226A1/fr
Priority to JP2022143443A priority patent/JP7573578B2/ja

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

Definitions

  • Figure 3b shows a basic circuit representation in a Z-Y plane of vertical NOR string 305 formed in an active column; vertical NOR string 305 represents a three-dimensional arrangement of non-volatile storage TFTs, including a dedicated pre-charge TFT 370 for setting a voltage (“V ss ”) on shared local source line 355, which has a parasitic capacitance C, according to one embodiment of the present invention.
  • V ss voltage
  • Figure 4b is a cross section in the Z-X plane showing active columns 430R, 430L,
  • Figure 6c is a cross section in the X-Y plane showing, in accordance with one embodiment of the current invention, dedicated word line stacks 623p, each having word lines each surrounding (“wrapping around”) a TFT of a vertical NOR string, and local vertical pillar bit line 654 (extending along the Z-direction) and local vertical pillar source line 655 (extending along the Z-direction), which are accessed by global horizontal bit line 614 and global horizontal source line 615, respectively; in Figure 6c, adjacent word line stacks 623p are isolated from each other by air gap 610 or another dielectric isolation.
  • Figure 6f illustrates one implementation of global word lines for connecting the local word lines on one plane (i.e., at one stair-case step) in conjunction with the bit line segmentation scheme of the present invention.
  • Figure 6g illustrates one implementation of a vertical NOR string memory array that avoids doubling of the silicon area taken up by word line stair-case steps when the number of layers of storage transistors are doubled in the vertical direction, according to one embodiment of the present invention.
  • conceptualized memory structure 100 may have M vertical NOR strings along each row in the X- and Y-directions, with M being a number that is not necessarily 2 n , for any integer n.
  • M may be a number that is not necessarily 2 n , for any integer n.
  • two vertical NOR strings may share a vertical local source line and a vertical local bit line, but their respective storage elements are controlled by two separate word line stacks. This effectively doubles the storage density of the vertical NOR string.
  • Figure 3a shows a basic circuit representation in a Z-Y plane of vertical NOR string 300 formed in an active column; vertical NOR string 300 represents a three-dimensional arrangement of non-volatile storage TFTs, with each TFT sharing local source line 355 and local bit line 354, according to one embodiment of the current invention.
  • the term“active region,”“active column” or“active strip” refers to a region, column or strip of one or more semiconductor materials on which an active device (e.g., a transistor or a diode) may be formed.
  • vertical NOR string 300 runs along the Z-direction, with TFTs 316 and 317 connected in parallel between vertical local source line 355 and vertical local drain or bit line 354.
  • Body region 356 of the active column may be connected at terminal 331 to substrate bias voltage V bt>.
  • Substrate bias voltage V bb may be used, for example during an erase operation.
  • the V bb supply voltage can be applied to an entire multi-gate vertical NOR string array, or be applied selectively to one or more rows of vertical NOR strings via a decoding mechanism. Lines connecting the V bb supply voltage to body region 356 run preferably along the direction of the word lines.
  • Figure 4a is a cross section in a Z-Y plane showing side-by-side active columns 431 and 432, each of which may form a vertical NOR string that has a basic circuit representation illustrated in either Figure 3a or Figure 3b, according to one embodiment of the present invention.
  • active columns 431 and 432 each include vertical N+ doped local source region 455 and vertical N+ doped local drain or bit line region 454, separated by lightly P- doped or undoped channel region 456.
  • P- doped channel region 456, N+ doped local source region 455 and N+ doped local drain or bit line region 454 may be biased to body bias voltage V bt> , source supply voltage V ss , and bit line voltage V bi , respectively.
  • body bias voltage V bb is optional, such as when the active strip is sufficiently thin (e.g., 10 nanometers or less).
  • the active region is readily fully depleted under appropriate voltage on the control gate, such that voltage V bb may not provide a solid supply voltage to the channel regions of the TFTs along the vertical NOR string.
  • Isolation region 436 which electrically insulates active columns 431 and 432, may be either a dielectric insulator or an air-gap.
  • a vertical stack of word lines 423 p respectively labeled WL0-WL31 (and optionally WLCHG), provides control gates to the TFTs in the vertical NOR strings formed in active columns 431 and 432.
  • word line WL31 in word line stack 423 -R serves as control gates for both transistor 416L on active column 430L and transistor 416R on active column 431R.
  • Adjacent word line stacks e.g., word lines stacks 423 -L and 423 -R
  • a distance 495 which is the width of a trench formed by etching through successive word line layers, as described below.
  • Active columns 430R and 430L, and their respective charge-trapping layers 432 and 434, are subsequently formed inside the trench etched through the word line layers.
  • Charge-trapping layer 434 is provided interposed between word line stack 423 -R and vertical active columns 431R and 430L.
  • active columns 430R and 430L are shown in Figure 4b as two separate active columns separated by an air-gap or dielectric insulation 433, the adjacent vertical N+ local source lines may be implemented by a single shared vertical local source line.
  • the vertical N+ local drain or bit lines may be implemented by a single shared vertical local bit line.
  • Such a configuration provides“vertical NOR string pair”.
  • active columns 430L and 430R may be seen as two branches (hence the “pair”) in one active column.
  • the vertical NOR string pair provides double-density storage through charge-trapping layers 432 and 434 interposed between active columns 430R and 430L and word lines stacks 423 -L and 423 -R on opposite sides.
  • active columns 430R and 430L may be merged into one active string by eliminating the air gap or dielectric insulation 433, yet still achieve the pair of NOR TFT strings implemented at the two opposite faces of the single active column.
  • vertical NOR string pairs 491 and 492 are served by global source line 413-1 (GSLi) and global source line 413-2 (GSL2), respectively (source line select access transistors can be similarly provided and are not shown in Figure 4c).
  • vertical NOR string pair 491 includes vertical NOR strings 45 la and 45 lb that share local source line 455, local bit line 454, and optional body connection 456.
  • vertical NOR string pair 491 represent the vertical NOR strings formed on active columns 430R and 430L of Figure 4b.
  • Word line stacks 423/?-L and 423/2- R (where, in this example, 31 3p >0) provide control gates for vertical NOR string 45 la and vertical NOR string 45 lb, respectively.
  • the hard- wired global source lines 413-1, 413-2 of figure 4c are eliminated, to be substituted for by a parasitic capacitance (e.g., the parasitic capacitance represented by capacitor 460 of Figure 4c or capacitor 360 of Figure 3c) between shared N+ local source line 455— which is common to both vertical NOR strings 45 la and 45 lb— and its numerous associated word lines 423/?-L and 423p-R.
  • a parasitic capacitance e.g., the parasitic capacitance represented by capacitor 460 of Figure 4c or capacitor 360 of Figure 3c
  • each of the 32 word lines contribute their parasitic capacitance to provide total parasitic capacitance C, such that it is sufficiently large to temporarily hold the voltage supplied by pre-charge TFT 470 to provide a virtual source voltage V ss during the relatively short duration of read or programming operations.
  • the virtual source voltage temporarily held on the parasitic capacitor (C) is provided to local source line 455 from global bit line GBLi through access transistor 411 and pre-charge transistor
  • Figure 5a is a cross section in the Z-Y plane showing connections of vertical NOR string of active column 531 to global bit line 514-1 (GBLi), global source line 507 (GSLi), and common body bias source 506 (V t>b ), according to one embodiment of the present invention.
  • bit- line access select transistor 511 connects GBLi with local bit line 554, and buried contact 556 optionally connects a P- body region on the active strip to body bias source 506 (V bt> ) in the substrate.
  • Bit- line access select transistor 511 is formed in Figure 5a above active column 531.
  • P- doped channel regions 656L and 656R form a pair of active strings between local source pillar 655 and local drain pillar 654 and extend along the Z-direction, isolated from each other by isolation region 640.
  • Charge trapping layer 634 is formed between word lines 623p-L (WL31-0) and 623p-R (WL31-1) and the outside of channel regions 656L and 656R respectively.
  • word lines 623 -L and 623 -R are contoured to enhance tunneling efficiency into the TFTs 684 and 685 during programming, while reducing reverse-tunneling efficiency during erasing.
  • curvature 675 of channel region 656R amplifies the electric field at the interface between the active channel polysilicon and the tunneling dielectric during programming, while reducing the electric field at the interface between the word line and the blocking dielectric during erasing. This feature is particularly helpful when storing more than one bit per TFT transistor in a multi-level cell (MLC) configuration. Using this technique, 2, 3, or 4 bits or more may be stored in each TFT.
  • MLC multi-level cell
  • word line 623 -R is shared by TFTs 684 and 683 of two vertical NOR strings on opposite sides of word line 623 -R. Accordingly, to allow TFTs 684 and 683 to be read or programmed independently, global bit line 614-1 (GBLi) contacts local drain or bit line region 657-1 (“odd addresses”), while global bit line 614-2 (GBL 2 ) contacts local drain or bit line region 657-2 (“even addresses”). To achieve this effect, contacts along global bit lines 614-1 and 614-2 are staggered, with each global bit line contacting every other one of the vertical NOR string pair along the X-direction row.
  • each vertical active strip may have 32, 48 or more TFTs connected in series.
  • each active column forming the vertical NOR strings of the present invention the vertical column may have one or two sets of 32, 48 or more TFTs connected in parallel.
  • the word lines in some embodiments typically wrap around the active strip.
  • separate designated left and right word lines are employed for each active strip, thereby to achieve a doubling (i.e.
  • Formation of transistors in a vertical NOR string is facilitated by the N+ doped vertical pillars extending to the entire depth of the void, providing shared local source line 655 (LSL) and shared local bit line (drain) 654 (LBL) for all the TFTs along the vertical NOR string, with undoped or lightly doped channel region 656 adjacent to both.
  • Charge storage element 634 is positioned between channel 656 and word line stack 623p, thus forming a stack of 2, 4, 8, ... 32, 64 or more TFTs (e.g., device 685 (Tio)) along the vertical active strip.
  • the word line stacks run in the Y-direction, with individual horizontal strips 623p (WL31-0), 623p (WL31-1) being separated from each other by air gap or dielectric isolation 610.
  • Global bit lines 614 (GBL) and global source lines 615 (GSL) run horizontally in rows along the X-direction, perpendicular to the word lines.
  • Each global bit line 614 accesses local bit line pillars 654 (LBL) along the row of vertical strips through access select transistors (511 in Figure 5a, not shown here) that can be positioned either below the memory array or above it.
  • each global source line 615 accesses the local source line pillars along the row.
  • Figure 6d shows a more compact vertical NOR string with wrap-around word lines, according to one embodiment of the present invention.
  • vertical NOR strings are staggered as to be closer together, so that word line stack 623p (WL31-0) can be shared by more vertical NOR strings.
  • the staggered configuration is enabled by using the parasitic capacitor (i.e., parasitic capacitors 660) of local source line pillar 655 (LSL).
  • LSL local source line pillar 655
  • Figures 3d, 3e, 3f and 3g show embodiments of the present invention that achieve fast read access and utilize the silicon substrate underneath the array to form support circuitry, such as sense amplifiers, decoders, registers, and voltage sources.
  • vertical NOR string 380 represents a three-dimensional arrangement of non-volatile storage TFTs, with each TFT sharing local source line 375 and local bit line 374, according to one embodiment of the present invention.
  • Local bit line 374 and local source line 375 are spaced apart by body region 356, which provides channel regions for the TFTs in vertical NOR string 380.
  • neighboring active columns are grouped, with the local bit lines of each group of active columns being connected to an associated bit line segment (e.g., bit line segments MSBLi and MSBL 2 ) provided beneath the memory array.
  • Bit line segment MSBLi provides a low-resistivity connector 373, which may be implemented by, for example, a narrow strip of N+ doped polysilicon, a silicide or a refractory metal.
  • the group of neighboring local vertical bit lines 374-1, 374-2, ... 374-n connected by horizontal bit line segment MSBLi may be provided lengthwise along the X-direction, orthogonally to word lines WLo to WL31.
  • Bit line segments MSBLi, MSBL2, ... are formed on dielectric insulator 392 and may be relatively short, such as encompassing from 1 (i.e., no segmentation) to 16, 64, 256, 512 or more vertical local bit lines.
  • Each bit line segment can be connected through a segment-select transistor (e.g., segment- select transistors 586-1, ..., 586-n, which may be implemented as thin-film transistors) to longer horizontal conductors forming regional bit line segments SGBLi,
  • Horizontal regional bit line segment SGBLi may be formed on an insulating layer 393 above substrate 310, to allow logic elements such as sense amplifiers to be formed in the substrate immediately underneath the regional bit line segment.
  • the regional segment is sufficiently long to allow sense amplifiers, decoders, registers, voltage sources and other circuitry formed in the substrate to physically fit underneath the regional bit line segment.
  • each word line services both active columns on both sides of the word line.
  • two adjacent local bit lines on opposite sides of the word line are associated respectively with bit line segments MSBLi(L) and MSBLi(R) and their respective segment sense amplifiers and decoders, which are closely spaced apart from and run parallel to each other. This spacing is also the spacing along the Y-direction between adjacent vertical active columns in the memory array. It may not be possible to provide a dedicated sense amplifier and other supporting circuits for each of the bit line segments laid out along the Y-direction. In such an arrangement, each sense amplifier may serve 1, 2, 4, 8 or more adjacent bit line segments through a segment- select decoder in the substrate. In the X-direction, a 1 -terabit 3-dimensional vertical NOR flash memory chip may have hundreds of regional bit line segments, rather than a long global bit line, thereby significantly reducing the bit-line RC delay.
  • the vertical local source lines connected by a horizontal source line segment are also closely associated with the vertical local bit lines connected by the corresponding horizontal bit line segment.
  • the number of vertical local bit-lines associated with a bit line segment need not be the same as the number of vertical local source lines associated with a source line segment.
  • Figure 3f shows a variation of the circuit architecture of the embodiment in Figure 3e, in which neither global source line (e.g., global source line 313) nor source line-select transistor (e.g., source-select transistor SLSi) is provided.
  • the local vertical source lines associated with each source line segment are pre-charged to source voltage V ss through a pre-charge transistor (e.g., pre-charge transistor 370) whose word line WCHG is turned on with a voltage pulse sufficient to transfer voltage V bi supplied from the circuitry in substrate 310 through the associated local vertical bit lines associated with the source line segment.
  • a pre-charge transistor e.g., pre-charge transistor 370
  • bit line segment SEGi and SEGi there is provided an array of charging columns, with each row extending along the X-direction having two charging columns and a predetermined number (e.g. 2048) of such rows laid out in along the Y-direction.
  • This array of charging columns is provided between the two discontinuities or openings in the bit lines (labeled in Figure 3i as“BLO”.)
  • a source line connector extending along the X-direction connects the right charging column to the local source lines in source line segment MSSLi (i.e., every other active column along the upper dash line) in bit line segment SEGi.
  • the height of the stack which is also the length of charging column 381, can exceed 5 microns, which is a rather long distance for vertical local source line 375(LSL) or local bit line 374 (LBL) of charging column 381 ( Figure 3h).
  • the electrical resistance (R; in ohms) of the corresponding N+ doped polysilicon pillars 455 and 454 may become excessive, introducing an RC delay that adversely impacts the read path primarily.
  • the pillar’ s resistance R can be reduced by an order of magnitude or more by providing a low-resistivity metallic material in the core of the pillar.
  • Figure 4a- 1 shows metallic core 420 (M)
  • Figure 7d-l shows metallic core 720 (M).
  • Figure 6e illustrates providing the body bias voltage through conductors 690- 1 and 690-2(“body bias conductors”).
  • the body bias voltage is shared between body regions in adjacent rows of active columns, using the layout of the embodiment shown in Figure 6b.
  • word line 592 i.e., word line 623p-L
  • the block size of an erase operation is limited to the active columns on the left and the active columns on the right of each body bias conductor (e.g., conductor 690-1). Larger erase blocks can be configured for example by having a cluster of body bias conductors tied together to match the number of word lines addressing a bit line segment.
  • a decoder in the substrate provides the appropriate body bias voltage (e.g., the erase voltage) to one or more selected erase blocks.
  • dielectric layer 592 is formed over the active columns. Thereafter, via holes are anisotropically etched from the top of dielectric layer 592 to the top of body region 556.
  • a layer of P + -doped polysilicon is then deposited over dielectric layer 592, filling the via holes to form conductive pillars (e.g., conductive pillars 591).
  • This layer of P + -doped polysilicon is then patterned and etched to form conductors (e.g., conductor 590) to connect through vias 593 to voltage source 594, which provides body bias voltage V bb .
  • Body bias voltage V bb can be a positive high voltage applied during erase or a low negative substrate bias voltage applied during read to raise the TFT threshold voltage or reduce its sub-threshold leakage.
  • Figure 6e is a top view showing P + -doped polysilicon features 690-1 and 690-2 formed.
  • conductor 590 is provided above body region 556. In other embodiments, however, conductor 590 may be provided underneath body region 556 to contact body region 556 from below. In fact, it may be advantageous to provide a body bias voltage from both above body region 556 and from below. In case of providing a body bias voltage from below, a conductor similar to conductor 590 may be provided or directly from the substrate through a via in the interlayer dielectric, similar to that shown in Figure 5 a.
  • bit line voltage (V bi ) will discharge its bit line voltage (V bi ) to its local source line (and its associated source line segment, if applicable), which has previously been pre-charged to virtual ground potential (V ss ).
  • V ss virtual ground potential
  • the rate of discharge of bit line voltage V bi is sensed by the sense amplifier for the bit line segment.
  • Other storage transistors on the selected plane i.e., 25 th plane, in this example
  • that are associated with other bit line segments along the Y-direction sharing the same word line or other storage transistors associated with other bit line segments along the X-direction that are addressed by different word lines, can be read concurrently, since each bit line segment has its dedicated sense amplifier.
  • bit line segments are MSBLi(L) for the left-side storage transistors and MSBLi(R) for the right-side storage transistor.
  • all word lines on all planes except the selected plane are set at ground potential, while the word line addressing the selected storage transistor (i.e., on the 25 th plane) is raised to a suitable programming voltage using, for example, incremental voltage steps (e.g., starting at ⁇ 8 volts and applying voltage pulses of increasing magnitude in incremental steps) until the desired programmed voltage is verified by a read operation to have been reached.
  • the voltage on the bit line segment is held at ground potential, as is the associated source line segment.
  • storage transistors associated with other bit line segments along the Y-direction i.e., sharing the same word line as the selected storage transistor
  • storage transistors associated with other bit line segments along the X- direction i.e., associated with different word lines
  • An erase operation may be accomplished by holding all word lines for storage transistors associated with the bit line segments, the source line segments, or blocks to be erased at 0V, while raising the body bias voltage (V bt> ) to -12V for virgin storage transistors (i.e., storage transistors that have never been programmed or erased), and up to 20V or higher for high cycle-count storage transistors. All sense amplifiers associated with a bit line segment may be isolated from their bit lines or bit line segments, as the floating N+ vertical local source lines and N+ vertical local bit lines within the erase block follow the positive voltage applied to their p- body regions.
  • the bit line segmentation in embodiments of the present invention serves to significantly reduce the RC delays in conventional global bit lines of conventional 3D NAND and 3D NOR memory arrays.
  • Another major contributor to long read latency are the long and highly capacitive local word line conductors that typically run almost half or the entire width of the chip, orthogonal to the global bit lines.
  • the 3D vertical NOR Flash memory arrays of US 2017/0092371 Al like conventional 3D NAND Flash memory arrays, require a minimum of one layer of local word line conductors for each memory plane. In a 64-plane NAND or NOR memory array, these word line conductors are constructed in tall stair-case steps.
  • word lines supply high voltage during programming, their decoders require high voltage transistors circuitry that can occupy significant silicon real estate for each such stair-case step.
  • word lines are typically made to be very long, which translates into high RC delays and poor read latency (e.g., in the range of a few microseconds).
  • the global bit lines too are long and have slow rise or fall times, which essentially hides the long word line latency.
  • bit- line response time can be very short (e.g., in the range of 100 nanoseconds)
  • long word line RC delays become the limiting factor to fast read access.
  • word line delays may be further reduced by partitioning the memory array into more blocks with shorter word lines, each formed with its repeat stair-case steps. Partitioning the memory arrays by doubling the number of stair-case steps and their word line decoders reduce the RC delays by 4-fold.
  • each step in the stair-case is performed using the global word lines.
  • the global word lines connect the word lines at each plane of the memory array to their respective decoders, voltage sources and other support circuitry in substrate 605.
  • bit line segmentation to the architecture, for example, of Figures 3d, 3e, 3f and 3g, each step in the stair-case
  • the embodiment illustrated in Figure 6f may be considered costly in silicon real estate: if there are 128 word lines in each bit line segment and 64 steps in the stair-case, 128 global word lines would be required for every step of a 64-step stair-case (or 8192 global word lines in total).
  • the number of global word lines required can be reduced by a factor of 2, 4, 8, 16 or more by having each global word line contact more than one local word line within each bit- line segment.
  • global word line GSLi may contact not only word line WLi, WL129, ... but also word lines WL33, WLev ...
  • the global word lines are implemented at the top of the memory array above the stair-case steps, the global word lines can be implemented using low resistivity copper interconnects. Capacitance between adjacent global word lines within a step can be reduced by substitution air gaps as the dielectric between them, as known to a person of ordinary skill in the art.
  • the global word line RC delays can be reduced further by connecting global word line decoders and voltage sources in the silicon substrate underneath the stair-case steps to access the global word lines every half, quarter or eighth of their length through breaks along the length of the global word lines.
  • Figure 6g shows an implementation of a vertical NOR string memory array that avoids such step-doubling, according to one embodiment of the present invention.
  • a Z-Y cross section of a memory array is shown with the total number of planes in the memory array being provided as two or more successively formed stacks (e.g., STKi and STK 2 ), one on top of another.
  • Each stack is provided its own set of stair-case steps completed before the next stack is formed.
  • 3-dimensional NAND memory arrays of the prior art two stacks of memory cells, each of 32 planes, are formed.
  • FIG. 6f shows forming stacks STKi and stack STK 2 each having just 32 stair-case wide steps (Steps A, Steps B), each step being a word line (running along the Y-direction) connected by one of global word line GWLi, GWL 2 , ..., GWL 32 (running along the X-direction).
  • Stacks STK1 and STK2 are isolated from each other by isolation layer 617, thus reduced in half the total width of providing 64 stair-case steps.
  • local bit line e.g., BL 654
  • local source line e.g.
  • SL 655) in stack STK 2 are connected to their corresponding local bit line and local source line in stack STKi by etching openings through isolation layer 617 to expose the top of the N+ doped vertical columns, thereby connecting the vertical active columns of the top 32 planes to their counterparts in the lower 32 planes above substrate 605.
  • P- doped channel regions e.g., channel region 656, corresponding to channel region 556 of Figure 5b
  • P+ doped plugs 691 which is formed in isolation layer 617 prior to forming STK 2 .
  • the silicon substrate area associated with the global word lines can be reduced by positioning the global word line decoders and voltage sources either below the stair-case steps or on top of the memory arrays rather than outside of the arrays in the substrate. Such placement may be provided in conjunction with memory arrays of Figures 3f and 3g. In those embodiments, the top surface of the memory array is clear of any source line or bit line interconnects.
  • word line decoders and voltage sources are implemented using thin-film transistors that must be able to support the relatively high voltages (e.g., in the range of 12V-20V) required on the global word lines during programming.
  • Such thin-film transistors may be achieved through shallow (Excimer) laser anneal to partially recrystallize deposited polysilicon or through other seeding techniques developed for solar panels or LED displays or other applications.
  • the top surface of the memory array can also be exploited to run wider or taller global word line interconnects with greater spacing in-between to reduce their RC delays without unduly increasing the memory chip area.
  • Non-provisional Patent Application III which is incorporated by reference above and which is now published as US 2017/0092371A1 (“the’237 publication”), discloses quasi volatile NOR strings (see the‘237 publication, at paragraphs [0128]-[0131]) that are suitable for replacing DRAM in certain storage applications that do not require extremely high cycle endurance.
  • the read access time of quasi-volatile NOR strings approaches the read access time of DRAM, which, at under 100 nanoseconds, is approximately 500 times faster than conventional 3D NAND flash memory.
  • the segmented bit- lines at the bottom of the array with their dedicated sense amplifiers, decoders in the substrate beneath the bit line segment (e.g., shown in Figures 3d, 3e, 3f, and 3g) closely emulate the horizontal strings of Non-Provisional Patent Application III and are equally capable of achieving near-DRAM read latency.
  • the process steps for building these quasi- volatile vertical NOR strings are similar to the steps described at paragraph [0129] of’ 237 publication.
  • the quasi volatile storage transistors Because of the relatively short retention time (e.g., in the range of one hour to a few days) of the quasi volatile storage transistors, they need to be frequently read-refreshed; in that context, having the ability to read or reprogram a large number of storage transistors concurrently (i.e.
  • reading and reprogramming storage transistors associated with many bit line segments in parallel is critical for minimizing interruption of normal reads when chip densities approach 1 -terabit.
  • the read output signals from the two transistors TL (683), TR (682) in two adjacent bit-line segments MSBLi(L), MSBLi(R) sharing the two sides of the same word line WL31-1 are fed into a differential sense amplifier in the silicon substrate.
  • the differential sense amplifier is shared between the two adjacent bit line segments along the Y-direction.
  • Figures 7a, 7b, 7c and 7d are cross sections of intermediate structures formed in a fabrication process for a multi-gate NOR string array, in accordance with one embodiment of the present invention.
  • Figure 7a shows a cross section in the Z-Y plane of semiconductor structure 700, after low resistivity layers 723 p have been formed above substrate 701, in accordance with one embodiment of the present invention.
  • p is an integer between 0 and 31, representing each of 32 word lines.
  • semiconductor structure 700 includes low resistivity layers 723-0 to 723-31.
  • Semiconductor substrate 701 represents, for example, a P- doped bulk silicon wafer on and in which support circuits for memory structure 700 may be formed prior to forming the vertical NOR strings. Such support circuits may include both analog and digital logic circuits.
  • Some examples of such support circuits may include shift registers, latches, sense amplifiers, reference cells, power supply lines, bias and reference voltage generators, inverters, NAND, NOR, Exclusive-OR and other logic gates, input/output drivers, address decoders, including bit-line and word line decoders, other memory elements, sequencers and state machines.
  • the building blocks of conventional N-Wells, P-Wells, triple wells (not shown), N + diffusion regions (e.g., region 707-0) and P + diffusion regions (e.g., region 706), isolation regions, low and high voltage transistors, capacitors, resistors, diodes and interconnects are provided, as known to a person skilled in the art.
  • insulating layers 708 are provided, which may be deposited or grown thick silicon dioxide, for example.
  • one or more metallic interconnect layers may be formed, including global source line 713-0, which may be provided as horizontal long narrow strips running along a predetermined direction. Global source line 713-0 is connected through etched openings 714 to circuitry 707 in substrate 701. To facilitate discussion in this detailed description, the global source lines are presumed to run along the X-direction.
  • the metallic interconnect lines may be formed by applying photo-lithographical patterning and etching steps on one or more deposited metal layers. (Alternatively, these metallic interconnect lines can be formed using a conventional damascene process, such as a conventional copper or tungsten damascene process). Thick dielectric layer 709 is then deposited, followed by planarization using conventional chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • Conductor layers 723-0 to 723-31 are then successively formed, each conductor layer being insulated from the layer underneath it and the layer above it by an intervening insulating layers 726.
  • FIG 7a although thirty two conductor layers are indicated, any number of such layers may be provided. In practice, the number of conductor layers that can be provided may depend on the process technology, such as the availability of a well- controlled anisotropic etching process that allows cutting through the multiple conductor layers and dielectric isolation layers 726 there -between.
  • conductor layers 723 p may be formed by first depositing 1-2 nm thick layer of titanium nitride (TiN), followed by depositing a 10 - 50 nm thick layer of tungsten (W) or a similar refractory metal, or a silicide such as silicides of nickel, cobalt or tungsten among others, or a salicide, followed by a thin layer of etch-stop material such as aluminum oxide (AI2O3).
  • Each conductor layer is etched in a block 700 after deposition, or is deposited as a block through a conventional damascene process.
  • each successive conductor layer 723 p extends in the Y- direction a distance 727 short of (i.e.
  • Dielectric isolation layers 726 may be, for example, a silicon dioxide of a thickness between 15 and 50 nanometers.
  • the number of conductor layers in the stack of block 700 corresponds to at least the number of memory TFTs in a vertical NOR string, plus any additional conductor layers that may be used as control gates of non-memory TFTs such as pre-charge TFTs (e.g., pre-charge TFT 575 of Figure 5a), or as control gates of bit-line access select TFTs (e.g., 585 bit- line access select TFT 511 of Figure 5 a).
  • pre-charge TFTs e.g., pre-charge TFT 575 of Figure 5a
  • bit-line access select TFTs e.g., 585 bit- line access select TFT 511 of Figure 5 a.
  • Dielectric isolation layer 710 and hard mask layer 715 are then deposited.
  • Hard mask 715 is patterned to allow etching of conductor layers 723 p to form long strips of yet to be formed word lines.
  • the word lines extend in length along the Y-direction.
  • One example of a masking pattern is shown in Figure 6 for word lines 623p-R, 623p-L, which includes features such as the extensions in adjacent word lines towards each other at separation 676 and the recesses in each word line to create the desired curvatures 675.
  • Deep trenches are created by anisotropically etching through successive conductor layers 723 p and their respective intervening dielectric insulator layers 726, until dielectric layer 709 at the bottom of conductor layers 723 p is reached.
  • Figure 7b illustrates, in a cross section in the Z-X plane of semiconductor structure 700, etching through successive conductor layers 723 p and corresponding dielectric layers 726 to form trenches (e.g., deep trench 795), which reach down to dielectric layer 709, according to one embodiment of the present invention.
  • conductor layers 723p are anisotropically etched to form conductor stacks 723p-R and 723p-L, which are separated from each other by deep trench 795. This anisotropic etch is a high aspect-ratio etch.
  • etch chemistry may have to be alternated between conductor material etch and dielectric etch, as the materials of the different layers are etched through, as in known to a person skilled in the art.
  • the anisotropy of the multi-step etch is important, as undercutting of any of the layers should be avoided, so that a resulting word line at the bottom of a stack would have approximately the same conductor width and trench spacing as the corresponding width and spacing of a word line near or at the top of the stack.
  • the greater the number of conductor layers in the stack the more challenging it becomes to maintain a tight pattern tolerance through the numerous successive etches.
  • these stacks are supported by active vertical strips of polysilicon, allowing the sacrificial layers to be etched away, preferably through selective chemical or isotropic etch.
  • the cavities thus created are then filled through conformal deposition of the conductor material, resulting in conductor layers 723p separated by intervening insulating layers 726.
  • charge-trapping layers 734 and polysilicon layers 730 are then deposited in succession conformally on the vertical sidewalls of the etched conductor word line stacks.
  • a cross section in the Z-X plane of the resulting structure is shown in Figure 7c.
  • charge-trapping layers 734 are formed, for example, by first depositing blocking dielectric 732a, between 5 to 15 nanometers thick and consisting of a dielectric film of a high dielectric constant (e.g., aluminum oxide, hafnium oxide, or some combination silicon dioxide and silicon nitride). Thereafter, charge-trapping material 732b is deposited to a thickness of 4 to 10 nanometers.
  • blocking dielectric 732a between 5 to 15 nanometers thick and consisting of a dielectric film of a high dielectric constant (e.g., aluminum oxide, hafnium oxide, or some combination silicon dioxide and silicon nitride).
  • charge-trapping material 732b is deposited to a thickness of 4 to 10 nanometers.
  • contact openings are made at the bottom of trench 795, using a masking step and by anisotropically etching through charge trapping layers 734 and dielectric layer 709 at the bottom of trench 795, stopping at bottom global source line landing pad 713 for the source supply voltage V ss (see, Figure 7b), or at global bit line voltage V bi (not shown), or at P+ region 706 for contact to a back bias supply voltage V bb (see, Figure 7c).
  • this etch step is preceded by a deposition of an ultra-thin film of polysilicon (e.g.
  • polysilicon thin film 730 is deposited to a thickness ranging between 5 and 10 nanometers.
  • polysilicon thin film 730 is shown on the opposite sidewalls of trench 795, labeled respectively 730R and 730L.
  • Polysilicon thin film 730 is undoped or preferably doped P- with boron, at a doping concentration typically in the range of lxlO 16 per cm 3 to lxlO 17 per cm 3 , which allows a TFT to be formed therein to have an enhancement native threshold voltage.
  • Trench 795 is sufficiently wide to accommodate charge-trapping layers 734 and polysilicon thin film 730 on its opposing sidewalls.
  • a photolithographic step then exposes openings 776 and 777, which is followed by a high aspect-ratio selective etching to excavate the fast-etching dielectric material in exposed areas 776 and 777 all the way down to the bottom of trench 795.
  • a hard mask may be required in this etching step to avoid excessive pattern degradation during etch.
  • the excavated voids are then filled with an in-situ N+ doped polysilicon.
  • the N+ dopants diffuse into the very thin lightly doped active polysilicon pillars 730L and 730R within the exposed voids to make them N+ doped.
  • the lightly doped polysilicon inside the voids can be etched away through a brief isotropic plasma etch or selective wet etch. CMP or top surface etching then removes the N+ polysilicon from the top surface, leaving tall N+ polysilicon pylons in areas 754 (N+) and 755(N+). These N+ pylons form the shared vertical local source line and the shared vertical local bit line for the TFTs in the resulting vertical NOR strings.
  • Fig.7d- 1 shows materially enhancing electrical conductivity of the tall vertical source/drain pylons by only partially filling the exposed voids 776 of vertical pylons 754 and 755, for example, by first depositing ultra-thin layers of N+ doped polysilicon 754(N+) and 755(N+), each of thickness between 5 and 15 nanometers (which is insufficient to fill the voids), followed by depositing (e.g., using Atomic Layer Deposition (ALD)) a metallic conductive material (e.g., titanium nitride, tungsten nitride or tungsten) to fill remaining void 720(M) at the core of the source/drain pylons.
  • ALD Atomic Layer Deposition
  • the thin P- doped polysilicon that is in region 757— outside the channel region 756— can first be more heavily doped P+ (e.g., 10 19 per cm 3 or higher), compared to the P- doping in channel region 756, which may be 2xl0 18 per cm 3 or lower. Adding the P+ poly in the source pylon that contacts the P- poly in the channel can enhance erase efficiency when the local source line is raised to a high positive voltage during an erase operation. Next, a dielectric isolation layer is deposited and patterned using photolithographic masking and etching steps.
  • P+ e.g. 10 19 per cm 3 or higher
  • All global bit lines, as well as all metal layers 723p of the word line stacks ( Figure 7a) are connected by etched vias to word line and bit- line decoding and sensing circuits in the substrate, as is known to a person skilled in the art.
  • Switch and sensing circuits, decoders and reference voltage sources can be provided to global bit lines and global word lines, either individually or shared by several ones of the bit lines and word lines.
  • bit line access select transistors (511 in Figure 5a) and their associated control gate word lines are formed as isolated vertical N+P-N+ transistors, as known to a person skilled in the art, to selectively connect odd and even global bit lines (e.g., bit lines 614-1 and 614-2 in Figure 6a) to vertical NOR strings at alternate odd and even addresses (e.g., local bit lines 657-1 and 657-2, respectively, in Figure 6a).
  • all TFTs in an active column should preferably be in enhancement mode - i.e., each TFT should have a positive gate-to-source threshold voltage— so as to suppress leakage currents during a read operation between the shared local source line and the shared local bit line (e.g., local bit line 455 and local source line 454 shown in Figure 4c).
  • Enhancement mode TFTs are achieved by doping the channel regions (e.g., P- channel region 756 of Figure 7c) with boron in a concentration typically between lxlO 16 and lxl0 17 per cm 3 , targeting for a native TFT threshold voltage of around IV.
  • all unselected word lines in the vertical NOR string pair of an active column may be held at 0V.
  • the read operation may raise the voltage on the shared local N+ source line (e.g., local source line 455 of Figure 4c) to around 1.5V, while raising the voltage on the shared local N+ drain line (e.g., local bit line 454) to around 2V and holding all unselected local word lines at 0V.
  • Such a configuration is equivalent to setting the word line to -1.5V with respect to the source, thereby suppressing leakage current due to TFTs that are in slightly depleted threshold voltage, which occurs, for example, if the TFTs are slightly over erased.
  • a soft programming operation may be required to shift any TFT in the vertical NOR string that is over-erased (i.e., now having a depletion mode threshold voltage) back to an enhancement mode threshold voltage.
  • an optional connection 556 is shown by which P- channel is connected to back bias voltage 506 (V bt>, ) (also shown as body connection 456 in Figure 4c).
  • a negative voltage may be used for V t>b to modulate the threshold voltage of the TFTs in each active column to reduce subthreshold leakage currents between the shared N+ source and the shared N+ drain/local bit line.
  • a positive V bb voltage can be used during an erase operation to tunnel-erase TFTs whose control gates are held at 0V.
  • each vertical NOR string may be directly connected through a global bit-line (e.g., GBL1 of Figure 4c) to a dedicated sensing circuit. In the latter case, one or more vertical NOR strings sharing the same word line plane may be sensed in parallel.
  • GBL1 of Figure 4c global bit-line
  • Each addressed vertical NOR string has its local source line set at V ss ⁇ 0V, either through its hard-wired global source line (e.g., GSL1 in Figure 4c) as shown schematically in Figure 8a, or as a virtual V ss ⁇ 0V through a pre-charge transistor (e.g., pre charge transistor 470 in Figure 4c or transistor 317 in Figure 3c) which momentarily transfers V bi ⁇ 0V to parasitic capacitance C (e.g., capacitor 460 or capacitor 360) of floating local source line 455 or 355) during the pre-charge, as shown schematically in Figure 8b.
  • a pre-charge transistor e.g., pre charge transistor 470 in Figure 4c or transistor 317 in Figure 3c
  • the local bit line (e.g., local bit line 454 of Figure 4c) is set at V bi ⁇ 2V through the bit line access select transistor (e.g., bit line access select transistor 411 of Figure 4c or access select transistor 511 in Figure 5a).
  • V bi ⁇ 2V is also the voltage at the sense amplifiers for the addressed vertical NOR strings.
  • the addressed word line is raised in small incremental voltage steps from 0V to typically about 6V, while all the un-selected word lines at both the odd address TFTs and the even address TFTs of the vertical NOR string pair remain at 0V.
  • the addressed TFT has been programmed in one example to a threshold voltage of 2.5V, therefore the voltage V bi at local bit line LBL begins to discharge through the selected TFT towards the OV of the local source line (V ss ) as soon as its WLs exceeds 2.5V, thus providing a voltage drop (shown by the dashed arrow in Figure 8a) that is detected at the sense amplifier serving the selected global bit line.
  • pre-charge transistor word line WLCHG momentarily is turned on to pre-charge floating local source line LSL to 0V at the start of the read sequence.
  • selected word line WLs goes through its incremental voltage steps, and as soon as it exceeds the programmed 2.5V, the selected TFT momentarily dips the voltage on its local bit line from its V t>i ⁇ 2V.
  • This voltage dip (shown by the dashed arrow in Figure 8b) is detected by the sense amplifier of the global bit line connected to the selected local bit line.
  • the embodiments relying on parasitic capacitance C to temporarily hold virtual voltage V ss, the higher the vertical stack the bigger is capacitance C and therefore the longer is the hold time and the greater is the read signal presented to the selected sense amplifier.
  • To further increase C it is possible to add in one embodiment one or more dummy conductors in the vertical string whose primary purpose is to increase capacitance C.
  • the addressed TFT may have been programmed to one of several voltages (e.g., IV (erased state), 2.5V, 4V or 5.5V).
  • the addressed word line WLs is raised in incremental voltage steps until conduction in the TFT is detected at the sense amplifier.
  • a single word line voltage can be applied (e.g., ⁇ 6 volts), and the rate of discharge of the local bit line LBL (V t>i ) can be compared with the rates of discharge from several programmable reference voltages representative of the voltage states of the stored multi-bit. This approach can be extended for a continuum of states, effectively providing analog storage.
  • the programmable reference voltages maybe stored in dedicated reference vertical NOR strings located within the multi-gate vertical NOR string array, so that the characteristics during read, program, and background leakage are closely tracked.
  • a vertical NOR string pair only the TFTs on one of the two vertical NOR strings can be read in each read cycle; the TFTs on the other vertical NOR string are placed in the“off’ state (i.e., all word lines at 0V).
  • the“off’ state i.e., all word lines at 0V.
  • 64 TFTs and one or more pre charge TFTs may be provided on each vertical NOR string of a vertical NOR string pair.
  • Each word line at its intersection with the local vertical N+ source line pillar forms a capacitor (see, e.g., capacitor 660 of Figure 6a).
  • a typical value for such a capacitor may be, for example, 1 x 10 18 farads.
  • the overall distributed capacitance C totals approximately 1 x 10 16 farads, which is sufficient for a local source line to preserve a pre-charged source voltage (V ss ) during a read cycle, which is completed in typically less than a microsecond immediately following the pre-charge operation.
  • the charging time through bit-line access select transistors 411 and pre-charge TFT 470 is in the order of a few nanoseconds, thus the charging time does not add noticeably to the read latency. Reading from a TFT in a vertical NOR string is fast, as the read operation involves conduction in only one of the TFTs in the vertical NOR string, unlike the read operation on a NAND string, in which many TFTs connected in series are required to be conducting.
  • RC time delay associated with resistance R t>i and capacitance CM of a global bit line e.g., GBL 614-1 in Figure 6a
  • response time of a sense amplifier to a voltage drop V t>i on the local bit line e.g., LBL-l
  • the RC time delay associated with a global bit line serving, for example, 16,000 vertical NOR strings is of the order of a few tens of nanoseconds.
  • the read latency for reading a TFT of a prior art vertical NAND string is determined by the current through 32 or more series-connected TFTs and select transistors discharging capacitance C t>i of the global bit line.
  • the read current discharging CM is provided through just the one addressed transistor (e.g., transistor 416L of Figure 4a) in series with bit line access select transistor 411, resulting in a much faster discharge of the local bit line voltage (V t>i ). As a result, a much lower latency is achieved.
  • a word line stack includes 32 or more word lines provided in 32 planes.
  • each plane may include 8000 word lines controlling 16,000 TFTs, each of which may be read in parallel through 16,000 global bit lines, provided that each bit line is connected to a dedicated sense amplifier.
  • the 16000 TFTs are read over several successive read cycles. Reading in parallel a massive number of discharging TFTs can cause a voltage bounce in the ground supply (V ss ) of the chip, which may result in read errors.
  • V ss ground supply
  • an embodiment that uses the pre-charged parasitic capacitor C in the local source line i.e., providing a virtual source voltage (V ss ) for vertical NOR string
  • V ss virtual source voltage
  • Programming of an addressed TFT may be achieved by tunneling— either direct tunneling or Fowler-Nordheim tunneling, - of electrons from the channel region of the TFT (e.g., channel region 430L shown in Figure 4b) to the charge-trapping layer (e.g., charge trapping layer 434) when a high programming voltage is applied between the selected word line (e.g., word line 423 -R) and the active channel region (e.g., active channel region 456 in Figure 4a).
  • the selected word line e.g., word line 423 -R
  • active channel region e.g., active channel region 456 in Figure 4a
  • Programming by tunneling may require, for example, a 20V, lOO-microsecond pulse.
  • the programming is implemented through a succession of shorter duration stepped voltage pulses, starting at around 14V and going as high as approximately 20V. Stepped voltage pulsing reduces electrical stress across the TFT and avoids overshooting the intended programmed threshold voltage.
  • the addressed transistor After each programming high-voltage pulse the addressed transistor is read to check if it has reached its target threshold voltage. If the target threshold voltage has not been reached, the next programming pulse applied to the selected word line is incremented typically by a few hundred millivolts.
  • This program- verify sequence is repeatedly applied to the one addressed word line (i.e., a control gate) with 0V applied to the local bit line (e.g., local bit line 454 of Figure 4a) of the active column (e.g., column 430L of Figure 4b).
  • TFT 4l6L’s channel region is inverted and is held at 0V, so that electrons tunnel into the charge storage layer of TFT 416L.
  • the addressed TFT When the read sensing indicates that the addressed TFT has reached its target threshold voltage, the addressed TFT must be inhibited from further programming, while other TFTs sharing the same word line may continue programming to their higher target threshold voltages. For example, when programming TFT 416L in vertical NOR string 45 lb, programming of all other TFTs in vertical NOR strings 45 lb and 45 la must be inhibited by keeping all their word lines at 0V. To inhibit further programming or TFT 416L once it has reached its target threshold voltage, a half-select voltage (i.e., approximately 10V) is applied to local bit line 454.
  • a half-select voltage i.e., approximately 10V
  • TFT 416R and TFT 416L share the same word line, they belong to different vertical NOR string pairs 452 and 451. It is possible to program both TFT 416L and TFT 416R in the same programming pulsed voltage sequence, as their respective bit line voltages are supplied through GBL1 and GBL2 and are independently controlled. For example, TFT 416L can continue to be programmed while TFT 416R can be inhibited from further programming at any time.
  • Each of the incrementally higher voltage programming pulses is followed by a read cycle to determine if TFTs 416L and 416R have reached their respective target threshold voltage. If so, the drain, source and body voltages are raised to 10V (alternatively, these voltages are floated to close to 10V) to inhibit further programming, while word line WL31 continues to program other addressed TFTs on the same plane that have not yet attained their target threshold voltages. This sequence terminates when all addressed TFTs have been read- verified to be correctly programmed.
  • programming of one of the multiple threshold voltage states can be accelerated by setting each addressed global bit line to one of several predetermined voltages (e.g., 0V, 1.5V, 3.0V, or 4.5V, representing the four distinct states of the 2-bit data to be stored), and then applying the stepped programming pulses (up to around 20V) to word line WL31.
  • the addressed TFT receives a predetermined one of the effective tunneling voltages (i.e., 20, 18.5, 17, and 15.5 volts, respectively), resulting in one of predetermined threshold voltages being programmed into a TFT in a single programming sequence. Fine programming pulses may be subsequently provided at the individual TFT level.
  • all local source lines in a multi-gate vertical NOR string array can have 0V (for program) or 10V (for inhibit) momentarily placed (e.g., through global bit line GBL1 and bit line access string select transistor 411 and pre-charge transistor 470) on all vertical NOR strings in advance of applying the high voltage pulsing sequence.
  • This procedure may be carried out by addressing the word line planes plane-by-plane.
  • the programming pulsing sequence may be applied to many or all word lines on the addressed word line plane, while holding all word lines on the other word line planes at 0V, so as to program in parallel a large number of TFTs on the addressed plane, followed by individual read-verify, and where necessary, resetting the local source line of a properly programmed TFT into program-inhibit voltage.
  • This approach provides a significant advantage, as programming time is relatively long (i.e., around 100 microsecond), while pre-charging all local source line capacitors or read-verifying all TFTs sharing the addressed word line plane is more than 1 ,000 times faster. Therefore, it pays to parallel program as many TFTs as possible in each word line plane.
  • This accelerated programming feature provides even greater advantage in MLC programming which is considerably slower than single bit programming.
  • the erase operation is performed by reverse tunneling of the trapped charge, which can be rather slow, sometimes requiring tens of milliseconds of 20V or higher pulsing. Therefore, the erase operation may be implemented at the vertical NOR string array level (“block erase”), often performed in the background.
  • a typical vertical NOR string array may have 64 word line planes, with each word line plane controlling, for example, 16,384 x 16,384 TFTs, for a total of approximately seventeen billion TFTs.
  • a one-terabit chip may therefore include approximately 30 such vertical NOR string arrays, if two bits of data are stored on each TFT.
  • block erase may be carried out by applying around 20V to the P- channel shared by all TFTs in a vertical NOR string (e.g., body connection 456 in Figure 4c and contact 556 in Figure 5a), while holding all word lines in the block at 0V.
  • the duration of the erase pulse should be such that most TFTs in the block are erased to a slight enhancement mode threshold voltage, i.e., between zero and one volt. Some TFTs will overshoot and be erased into depletion mode (i.e., a slightly negative threshold voltage).
  • a soft programming may be required to return the over-erased TFTs back into a slight enhancement mode threshold voltage after the termination of the erase pulses, as part of the erase command.
  • Vertical NOR strings that may include one of more depletion mode TFTs that cannot be programmed into enhancement mode may have to be retired, to be replaced by spare strings.
  • the local source lines and the local bit lines (e.g., local source line 455 and local bit line 454 in Figure 4c) on all vertical NOR string pairs in the vertical NOR string array are raised to around 20V, while holding all word lines on all word line planes at 0V for the duration of the erase pulse.
  • This scheme requires that the global source line and the global bit line select decoders employ high voltage transistors that can withstand the 20V at their junctions.
  • all TFTs sharing an addressed word line plane can be erased together by applying -20V pulses to all word lines on the addressed plane, while holding word lines on all other planes at 0V. All other voltages in the vertical NOR string pairs are held at 0V. This will erase only the X-Y slice of all TFTs touched by the one addressed plane of word lines.
  • Some charge-trapping materials e.g., oxide-nitride-oxide or“ONO”) suitable for use in the vertical NOR string have long data retention time, typically in the order of many years, but relatively low endurance (i.e., performance degrades after some number of write-erase cycles, typically of the order of ten thousand cycles or less).
  • charge-trapping materials that store charge for much reduced retention times, but with much increased endurances (e.g., retention times in order of minutes or hours, endurance in the order of tens of millions of write-erase cycles).
  • Blocking layer 732a can be silicon dioxide, aluminum oxide, hafnium oxide, silicon nitride, a high dielectric constant dielectric, or any combination thereof. Blocking layer 732a blocks electrons in charge-trapping layer 732b from escaping to the control gate word line. Trapped electrons will eventually leak out back into active region 730R, either as a result of the breakdown of the ultra-thin tunnel dielectric layer, or by reverse direct tunneling. However, such loss of trapped electrons is relatively slow.
  • the vertical NOR strings of the present invention have a relatively fast read access (i.e. low latency), they may be used in some applications that currently require the use of dynamic random access memories (DRAMs).
  • DRAMs dynamic random access memories
  • the vertical NOR strings of the present invention have significant advantages over DRAMs, having a much lower cost-per-bit, as DRAMs cannot be built in three dimensional stacks, and having a much lower power dissipation, as the refresh cycles need only be ran approximately once every few minutes or every few hours, as compared to every few milliseconds required to refresh DRAMs.
  • the three-dimensional semi-volatile storage TFTs of the present invention are achieved by selecting an appropriate material, such as those discussed above, for the charge-trapping material and by appropriately adapting the program/read/program-inhibit/erase conditions and incorporating the periodic data refreshes.
  • the vertical NOR strings may be programmed using a channel hot-electron injection approach, similar to that which is used in two-dimensional NROM/Mirror Bit transistors, known to a person skilled in the art.
  • programming conditions for channel hot- electron injection may be: 8V on control gate 423 p, 0V on local source line 455 and 5V on local drain line 454.
  • Charge representing one bit is stored in the charge storage layer at one end of channel region 456 next to the junction with local bit line 454.
  • charge representing a second bit is
  • NROM TFT embodiment can be achieved by employing the conventional NROM erase mechanism of band to band tunneling-induced hot-hole injection to neutralize the charge of the trapped electrons: apply -5V on the word line, 0V to local source line 455 and 5V to local bit line 454.
  • the NROM TFT can be erased by applying a high positive substrate voltage V bb to body region 456 with the word line at 0V. Because of the high programming current attendant to channel hot electron injection programming, all embodiments of vertical NROM TFT strings must employ hard-wired local source line and local bit line, such as in the embodiments of Figures 3 a and 6c.

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Abstract

La présente invention concerne une structure de mémoire, comprenant des colonnes actives de polysilicium formées sur un substrat semi-conducteur, chaque colonne active comprenant une ou plusieurs chaînes non-ou verticales, chaque chaîne non-ou présentant des transistors de stockage en couches minces partageant une ligne de source locale et une ligne de bit locale, la ligne de bit locale étant connectée par un segment d'une ligne de bit globale segmentée à un amplificateur de détection situé dans le substrat semi-conducteur.
PCT/US2019/014319 2018-02-02 2019-01-18 Chaînes de transistors en couches minces flash non-ou verticales tridimensionnelles WO2019152226A1 (fr)

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JP2020541723A JP7141462B2 (ja) 2018-02-02 2019-01-18 ３次元垂直ｎｏｒフラッシュ薄膜トランジスタストリング
KR1020227033231A KR102626137B1 (ko) 2018-02-02 2019-01-18 3-차원 수직 nor 플래시 박막 트랜지스터 스트링들
CN201980024463.2A CN111937147B (zh) 2018-02-02 2019-01-18 三维垂直nor闪速薄膜晶体管串
KR1020207025160A KR102448489B1 (ko) 2018-02-02 2019-01-18 3-차원 수직 nor 플래시 박막 트랜지스터 스트링들
JP2022143443A JP7573578B2 (ja) 2018-02-02 2022-09-09 ３次元垂直ｎｏｒフラッシュ薄膜トランジスタストリング

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US16/107,732 US10249370B2 (en) 2015-09-30 2018-08-21 Three-dimensional vertical NOR flash thing-film transistor strings
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113540114A (zh) * 2020-06-30 2021-10-22 台湾积体电路制造股份有限公司 存储器单元、存储器件及其形成方法
CN113540116A (zh) * 2020-06-30 2021-10-22 台湾积体电路制造股份有限公司 存储器单元、存储器器件及其形成方法
KR20210148856A (ko) * 2020-05-28 2021-12-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 강유전체 메모리 디바이스 및 그 형성 방법
KR20210148868A (ko) * 2020-05-29 2021-12-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 메모리 어레이 채널 영역
KR20210148862A (ko) * 2020-05-28 2021-12-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 3차원 메모리 디바이스 및 방법
US20210408047A1 (en) * 2020-06-29 2021-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional memory device and manufacturing method thereof
KR20220000341A (ko) * 2020-06-25 2022-01-03 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 메모리 어레이 접촉 구조
KR20220000807A (ko) * 2020-06-26 2022-01-04 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 메모리 어레이 구조물의 에어 갭
KR20220001432A (ko) * 2020-06-29 2022-01-05 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 메모리 어레이를 포함한 3d 반도체 패키지
EP3940778A1 (fr) * 2020-07-14 2022-01-19 Taiwan Semiconductor Manufacturing Company, Ltd. Dispositif de mémoire et son procédé de fabrication
US11251199B2 (en) 2019-12-09 2022-02-15 Sandisk Technologies Llc Three-dimensional NOR array including active region pillars and method of making the same
TWI807984B (zh) * 2022-06-21 2023-07-01 大陸商長鑫存儲技術有限公司 半導體結構及其製造方法、記憶體晶片、電子設備
US11695073B2 (en) 2020-05-29 2023-07-04 Taiwan Semiconductor Manufacturing Co., Ltd. Memory array gate structures
US11710790B2 (en) 2020-05-29 2023-07-25 Taiwan Semiconductor Manufacturing Company, Ltd. Memory array channel regions
US11716855B2 (en) 2020-05-28 2023-08-01 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional memory device and method
US11716856B2 (en) 2021-03-05 2023-08-01 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional memory device and method
DE102021100089B4 (de) 2020-07-30 2023-10-12 Taiwan Semiconductor Manufacturing Co., Ltd. Dreidimensionale speichervorrichtung und verfahren
US11903214B2 (en) 2020-07-16 2024-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional ferroelectric random access memory devices and methods of forming
US11985825B2 (en) 2020-06-25 2024-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. 3D memory array contact structures
US12022659B2 (en) 2020-07-30 2024-06-25 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional memory device and method
US12040006B2 (en) 2020-06-26 2024-07-16 Taiwan Semiconductor Manufacturing Co., Ltd. Memory array including dummy regions
US12051750B2 (en) 2020-05-29 2024-07-30 Taiwan Semiconductor Manufacturing Co., Ltd. Memory array gate structures
DE102020135119B4 (de) 2020-05-28 2024-08-08 Taiwan Semiconductor Manufacturing Co. Ltd. Ferroelektrische speichervorrichtung und verfahren zu deren herstellung

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11968833B2 (en) * 2021-01-15 2024-04-23 Macronix International Co., Ltd. Memory device with vertically separated channels
US11587931B2 (en) 2021-03-03 2023-02-21 Micron Technology, Inc. Multiplexor for a semiconductor device
CN112909012B (zh) * 2021-03-08 2023-09-22 中国科学院微电子研究所 Nor型存储器件及其制造方法及包括存储器件的电子设备
CN114927527B (zh) * 2022-07-20 2022-11-04 合肥晶合集成电路股份有限公司 闪存器件、存储单元及其制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6873004B1 (en) * 2002-02-04 2005-03-29 Nexflash Technologies, Inc. Virtual ground single transistor memory cell, memory array incorporating same, and method of operation thereof
US9190293B2 (en) * 2013-12-18 2015-11-17 Applied Materials, Inc. Even tungsten etch for high aspect ratio trenches
US9412752B1 (en) * 2015-09-22 2016-08-09 Macronix International Co., Ltd. Reference line and bit line structure for 3D memory
US20170148517A1 (en) * 2015-11-25 2017-05-25 Eli Harari Three-dimensional vertical nor flash thin film transistor strings
US9748172B2 (en) * 2015-02-25 2017-08-29 Sandisk Technologies Llc Floating staircase word lines and process in a 3D non-volatile memory having vertical bit lines

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080051014A (ko) * 2006-12-04 2008-06-10 삼성전자주식회사 수직구조를 갖는 앤드형 및 노아형 플래시 메모리 어레이와그 각각의 제조방법 및 동작방법
US7898857B2 (en) 2008-03-20 2011-03-01 Micron Technology, Inc. Memory structure having volatile and non-volatile memory portions
JP5354944B2 (ja) 2008-03-27 2013-11-27 株式会社東芝 半導体装置および電界効果トランジスタ
US8148763B2 (en) 2008-11-25 2012-04-03 Samsung Electronics Co., Ltd. Three-dimensional semiconductor devices
US8630114B2 (en) 2011-01-19 2014-01-14 Macronix International Co., Ltd. Memory architecture of 3D NOR array
KR20130095499A (ko) * 2012-02-20 2013-08-28 에스케이하이닉스 주식회사 비휘발성 메모리 장치, 그 동작 방법 및 그 제조 방법
US10014317B2 (en) * 2014-09-23 2018-07-03 Haibing Peng Three-dimensional non-volatile NOR-type flash memory
US9449701B1 (en) * 2015-06-30 2016-09-20 Sandisk Technologies Llc Non-volatile storage systems and methods
US10121553B2 (en) * 2015-09-30 2018-11-06 Sunrise Memory Corporation Capacitive-coupled non-volatile thin-film transistor NOR strings in three-dimensional arrays
EP3381036B1 (fr) 2015-11-25 2021-07-21 Sunrise Memory Corporation Chaînes de transistors à couches minces flash non-ou verticales tridimensionnelles

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6873004B1 (en) * 2002-02-04 2005-03-29 Nexflash Technologies, Inc. Virtual ground single transistor memory cell, memory array incorporating same, and method of operation thereof
US9190293B2 (en) * 2013-12-18 2015-11-17 Applied Materials, Inc. Even tungsten etch for high aspect ratio trenches
US9748172B2 (en) * 2015-02-25 2017-08-29 Sandisk Technologies Llc Floating staircase word lines and process in a 3D non-volatile memory having vertical bit lines
US9412752B1 (en) * 2015-09-22 2016-08-09 Macronix International Co., Ltd. Reference line and bit line structure for 3D memory
US20170148517A1 (en) * 2015-11-25 2017-05-25 Eli Harari Three-dimensional vertical nor flash thin film transistor strings

Cited By (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11251199B2 (en) 2019-12-09 2022-02-15 Sandisk Technologies Llc Three-dimensional NOR array including active region pillars and method of making the same
KR102568611B1 (ko) 2020-05-28 2023-08-18 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 강유전체 메모리 디바이스 및 그 형성 방법
KR20210148856A (ko) * 2020-05-28 2021-12-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 강유전체 메모리 디바이스 및 그 형성 방법
KR20210148862A (ko) * 2020-05-28 2021-12-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 3차원 메모리 디바이스 및 방법
US11716855B2 (en) 2020-05-28 2023-08-01 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional memory device and method
KR102602494B1 (ko) 2020-05-28 2023-11-14 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 3차원 메모리 디바이스 및 방법
DE102020135119B4 (de) 2020-05-28 2024-08-08 Taiwan Semiconductor Manufacturing Co. Ltd. Ferroelektrische speichervorrichtung und verfahren zu deren herstellung
KR20210148868A (ko) * 2020-05-29 2021-12-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 메모리 어레이 채널 영역
US11710790B2 (en) 2020-05-29 2023-07-25 Taiwan Semiconductor Manufacturing Company, Ltd. Memory array channel regions
US11695073B2 (en) 2020-05-29 2023-07-04 Taiwan Semiconductor Manufacturing Co., Ltd. Memory array gate structures
KR102667247B1 (ko) 2020-05-29 2024-05-20 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 메모리 어레이 채널 영역
US12051750B2 (en) 2020-05-29 2024-07-30 Taiwan Semiconductor Manufacturing Co., Ltd. Memory array gate structures
US20220384348A1 (en) * 2020-06-25 2022-12-01 Taiwan Semiconductor Manufacturing Co., Ltd. Memory Array Contact Structures
US11653500B2 (en) * 2020-06-25 2023-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Memory array contact structures
US11985825B2 (en) 2020-06-25 2024-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. 3D memory array contact structures
KR20220000341A (ko) * 2020-06-25 2022-01-03 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 메모리 어레이 접촉 구조
KR102558611B1 (ko) * 2020-06-25 2023-07-21 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 메모리 어레이 접촉 구조
KR20220000807A (ko) * 2020-06-26 2022-01-04 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 메모리 어레이 구조물의 에어 갭
US12040006B2 (en) 2020-06-26 2024-07-16 Taiwan Semiconductor Manufacturing Co., Ltd. Memory array including dummy regions
US12087621B2 (en) 2020-06-26 2024-09-10 Taiwan Semiconductor Manufacturing Co., Ltd. Air gaps in memory array structures
KR102638126B1 (ko) 2020-06-26 2024-02-16 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 메모리 어레이 구조물의 에어 갭
KR20220001432A (ko) * 2020-06-29 2022-01-05 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 메모리 어레이를 포함한 3d 반도체 패키지
US20220384485A1 (en) * 2020-06-29 2022-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional memory device and manufacturing method thereof
US11581337B2 (en) * 2020-06-29 2023-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional memory device and manufacturing method thereof
US20210408047A1 (en) * 2020-06-29 2021-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional memory device and manufacturing method thereof
US12063787B2 (en) * 2020-06-29 2024-08-13 Taiwan Semiconductor Manufacturing Company, Ltd Three-dimensional memory device and manufacturing method thereof
US11950428B2 (en) * 2020-06-29 2024-04-02 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional memory device and manufacturing method thereof
KR102595711B1 (ko) 2020-06-29 2023-10-27 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 메모리 어레이를 포함한 3d 반도체 패키지
KR20220002058A (ko) * 2020-06-30 2022-01-06 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 메모리 어레이 소스/드레인 전극 구조
CN113540116B (zh) * 2020-06-30 2024-08-02 台湾积体电路制造股份有限公司 存储器单元、存储器器件及其形成方法
KR102607654B1 (ko) * 2020-06-30 2023-11-29 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 메모리 어레이 소스/드레인 전극 구조
KR102602495B1 (ko) * 2020-06-30 2023-11-14 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 메모리 어레이 격리 구조물들
US11729987B2 (en) 2020-06-30 2023-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Memory array source/drain electrode structures
CN113540116A (zh) * 2020-06-30 2021-10-22 台湾积体电路制造股份有限公司 存储器单元、存储器器件及其形成方法
KR20220002060A (ko) * 2020-06-30 2022-01-06 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 메모리 어레이 격리 구조물들
CN113540114A (zh) * 2020-06-30 2021-10-22 台湾积体电路制造股份有限公司 存储器单元、存储器件及其形成方法
US11640974B2 (en) 2020-06-30 2023-05-02 Taiwan Semiconductor Manufacturing Co., Ltd. Memory array isolation structures
EP3940778A1 (fr) * 2020-07-14 2022-01-19 Taiwan Semiconductor Manufacturing Company, Ltd. Dispositif de mémoire et son procédé de fabrication
US11903214B2 (en) 2020-07-16 2024-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional ferroelectric random access memory devices and methods of forming
DE102021100089B4 (de) 2020-07-30 2023-10-12 Taiwan Semiconductor Manufacturing Co., Ltd. Dreidimensionale speichervorrichtung und verfahren
US12022659B2 (en) 2020-07-30 2024-06-25 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional memory device and method
US11716856B2 (en) 2021-03-05 2023-08-01 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional memory device and method
TWI807984B (zh) * 2022-06-21 2023-07-01 大陸商長鑫存儲技術有限公司 半導體結構及其製造方法、記憶體晶片、電子設備

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