WO2019145814A1 - 記憶装置、半導体装置、および電子機器 - Google Patents
記憶装置、半導体装置、および電子機器 Download PDFInfo
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- WO2019145814A1 WO2019145814A1 PCT/IB2019/050255 IB2019050255W WO2019145814A1 WO 2019145814 A1 WO2019145814 A1 WO 2019145814A1 IB 2019050255 W IB2019050255 W IB 2019050255W WO 2019145814 A1 WO2019145814 A1 WO 2019145814A1
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- transistor
- insulator
- oxide
- conductor
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- 229910052754 neon Inorganic materials 0.000 description 1
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 1
- 229910000480 nickel oxide Inorganic materials 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 229910000484 niobium oxide Inorganic materials 0.000 description 1
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 229910052756 noble gas Inorganic materials 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 229910052706 scandium Inorganic materials 0.000 description 1
- SIXSYDAISGFNSX-UHFFFAOYSA-N scandium atom Chemical compound [Sc] SIXSYDAISGFNSX-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004611 spectroscopical analysis Methods 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
- 230000037303 wrinkles Effects 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H10B12/36—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being a FinFET
Abstract
Description
本実施の形態では、本発明の一形態に係わる記憶装置の構成例について説明する。本発明の一形態に係わる記憶装置は、半導体特性を利用することで機能しうる記憶装置であり、メモリとも呼ばれている(以下、メモリという)。また、本発明の一形態に係わる記憶装置は、半導体基板に構成した周辺回路の上方に、酸化物半導体トランジスタ(以下、OSトランジスタという)を用いたメモリセルを積層して設けた構造を有する。
図1は、本発明の一形態に係わるメモリ100の構成例を示す斜視概略図である。
図2は、メモリ100の構成例を示すブロック図である。
図3(A)は、メモリセルアレイ210の構成例を示す上面図である。図3(A)を用いて、メモリセルアレイ210の詳細を説明する。
図3(B)は、メモリセル211の構成例を示す回路図である。
なお、メモリセル211の構成は、上記に限られない。メモリセル211の別の構成例を、図4(A)に示すメモリセル212を用いて説明する。
また、メモリセル212を、3トランジスタ1容量素子のゲインセル型のメモリセルとしてもよい。メモリセル212を、3トランジスタ1容量素子のゲインセル型のメモリセルとした場合の構成例を、図4(C)に示すメモリセル214を用いて説明する。
上述のように、層201は、メモリセルアレイ220の下方に導電層50を有し、メモリセルアレイ230の下方に導電層60を有する。そして、メモリセルアレイ220が有するk×n個のメモリセル211において、導電層50の電位はトランジスタM11のバックゲートに印加され、メモリセルアレイ230が有する(m−k)×n個のメモリセル211において、導電層60の電位はトランジスタM11のバックゲートに印加される。
本実施の形態では、上記実施の形態で説明した周辺回路110に適用可能なSiトランジスタ、およびメモリセル211に適用可能なOSトランジスタの構成例について説明する。なお、本実施の形態では、前記SiトランジスタおよびOSトランジスタを合わせて、半導体装置と呼ぶ。
図9に示す半導体装置は、トランジスタ300、トランジスタ500、トランジスタ501、および容量素子600を有している。図10(A)はトランジスタ500のチャネル長方向の断面図であり、図10(B)はトランジスタ500のチャネル幅方向の断面図であり、図10(C)はトランジスタ300のチャネル幅方向の断面図である。
なお、本実施の形態に示す半導体装置のトランジスタ500は、上記の構造に限られるものではない。以下、トランジスタ500に用いることができる構造例について説明する。
図11(A)乃至図11(C)を用いてトランジスタ510Aの構造例を説明する。図11(A)はトランジスタ510Aの上面図である。図11(B)は、図11(A)に一点鎖線L1−L2で示す部位の断面図である。図11(C)は、図11(A)に一点鎖線W1−W2で示す部位の断面図である。なお、図11(A)の上面図では、図の明瞭化のために一部の要素を省いて図示している。
図12(A)乃至図12(C)を用いてトランジスタ510Bの構造例を説明する。図12(A)はトランジスタ510Bの上面図である。図12(B)は、図12(A)に一点鎖線L1−L2で示す部位の断面図である。図12(C)は、図12(A)に一点鎖線W1−W2で示す部位の断面図である。なお、図12(A)の上面図では、図の明瞭化のために一部の要素を省いて図示している。
図13(A)乃至図13(C)を用いてトランジスタ510Cの構造例を説明する。図13(A)はトランジスタ510Cの上面図である。図13(B)は、図13(A)に一点鎖線L1−L2で示す部位の断面図である。図13(C)は、図13(A)に一点鎖線W1−W2で示す部位の断面図である。なお、図13(A)の上面図では、図の明瞭化のために一部の要素を省いて図示している。
図14(A)乃至図14(C)を用いてトランジスタ510Dの構造例を説明する。図14(A)はトランジスタ510Dの上面図である。図14(B)は、図14(A)に一点鎖線L1−L2で示す部位の断面図である。図14(C)は、図14(A)に一点鎖線W1−W2で示す部位の断面図である。なお、図14(A)の上面図では、図の明瞭化のために一部の要素を省いて図示している。
図15(A)乃至図15(C)を用いてトランジスタ510Eの構造例を説明する。図15(A)はトランジスタ510Eの上面図である。図15(B)は、図15(A)に一点鎖線L1−L2で示す部位の断面図である。図15(C)は、図15(A)に一点鎖線W1−W2で示す部位の断面図である。なお、図15(A)の上面図では、図の明瞭化のために一部の要素を省いて図示している。
本実施の形態では、上記実施の形態で説明したOSトランジスタに用いることができる金属酸化物の構成について説明する。
本明細書等において、CAAC(c−axis aligned crystal)、及びCAC(Cloud−Aligned Composite)と記載する場合がある。なお、CAACは結晶構造の一例を表し、CACは機能、または材料の構成の一例を表す。
酸化物半導体は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、例えば、CAAC−OS(c−axis aligned crystalline oxide semiconductor)、多結晶酸化物半導体、nc−OS(nanocrystalline oxide semiconductor)、擬似非晶質酸化物半導体(a−like OS:amorphous−like oxide semiconductor)および非晶質酸化物半導体などがある。
続いて、上記酸化物半導体をトランジスタに用いる場合について説明する。
ここで、酸化物半導体中における各不純物の影響について説明する。
本実施の形態では、上記実施の形態で説明した記憶装置を搭載した電子機器の一例について説明する。
Claims (15)
- 第1乃至第N(Nは2以上の整数)の電極と、
第1および第2の回路と、を有し、
前記第1の回路と、前記第2の回路は、複数の配線を介して電気的に接続され、
前記第2の回路は、第1乃至第Nの領域を有し、
前記第1乃至第Nの領域は、それぞれ、第1トランジスタを有し、
前記第1乃至第Nの領域において、第K(Kは1以上N以下の整数)の前記領域は、第Kの前記電極を介して、前記第1の回路と重なる領域を有し、
前記第Kの電極は、前記第Kの領域が有する前記第1トランジスタのバックゲートとして機能する、半導体装置。 - 請求項1において、
第1乃至第M(Mは2以上の整数)の電位のいずれかが、前記第1乃至第Nの電極のそれぞれに印加され、
前記第1乃至第Mの電位は、互いに異なる、半導体装置。 - 請求項1または請求項2において、
前記第1トランジスタは、チャネル形成領域に金属酸化物を有する、半導体装置。 - 請求項1乃至請求項3のいずれか一項において、
前記第1トランジスタは、シリコンおよび窒素を含む層と重なり、
前記層の抵抗率は1×1010以上1×1015Ωcm以下である、半導体装置。 - 請求項1乃至請求項4のいずれか一項において、
前記第1の回路は、第2トランジスタを有し、
前記第2トランジスタは、チャネル形成領域にシリコンを有する、半導体装置。 - 第1乃至第N(Nは2以上の整数)の電極と、
制御回路と、
セルアレイと、を有し、
前記制御回路は、前記セルアレイを制御する機能を有し、
前記セルアレイは、第1乃至第Nの領域を有し、
前記第1乃至第Nの領域は、それぞれ、複数のメモリセルを有し、
前記複数のメモリセルは、それぞれ、第1トランジスタおよび容量素子を有し、
前記第1乃至第Nの領域において、第K(Kは1以上N以下の整数)の前記領域は、第Kの前記電極を介して、前記第1の回路と重なる領域を有し、
前記第Kの電極は、前記第Kの領域において、前記メモリセルが有する前記第1トランジスタのバックゲートとして機能する、記憶装置。 - 請求項6において、
第1乃至第M(Mは2以上の整数)の電位のいずれかが、前記第1乃至第Nの電極のそれぞれに印加され、
前記第1乃至第Mの電位は、互いに異なる、記憶装置。 - 請求項6または請求項7において、
前記第1トランジスタは、チャネル形成領域に金属酸化物を有する、記憶装置。 - 請求項6乃至請求項8のいずれか一項において、
前記第1トランジスタは、シリコンおよび窒素を含む層と重なり、
前記層の抵抗率は1×1010以上1×1015Ωcm以下である、記憶装置。 - 請求項6乃至請求項9のいずれか一項において、
前記第1の回路は、第2トランジスタを有し、
前記第2トランジスタは、チャネル形成領域にシリコンを有する、記憶装置。 - 第1および第2の電極と、
制御回路と、
セルアレイと、を有し、
前記制御回路は、前記セルアレイを制御する機能を有し、
前記セルアレイは、第1および第2の領域を有し、
前記第1および第2の領域は、それぞれ、複数のメモリセルを有し、
前記複数のメモリセルは、それぞれ、第1トランジスタおよび容量素子を有し、
前記第1の領域は、前記第1の電極を介して、前記制御回路と重なる領域を有し、
前記第2の領域は、前記第2の電極を介して、前記制御回路と重なる領域を有し、
前記第1の電極は、前記第1の領域において、前記メモリセルが有する前記第1トランジスタのバックゲートとして機能し、
前記第2の電極は、前記第2の領域において、前記メモリセルが有する前記第1トランジスタのバックゲートとして機能する、記憶装置。 - 請求項11において、
前記第1の電極に印加される電位と、前記第2の電極に印加される電位は、異なる、記憶装置。 - 請求項11または請求項12において、
前記第1トランジスタは、チャネル形成領域に金属酸化物を有する、記憶装置。 - 請求項11乃至請求項13のいずれか一項において、
前記第1トランジスタは、シリコンおよび窒素を含む層と重なり、
前記層の抵抗率は1×1010以上1×1015Ωcm以下である、記憶装置。 - 請求項11乃至請求項14のいずれか一項において、
前記制御回路は、第2トランジスタを有し、
前記第2トランジスタは、チャネル形成領域にシリコンを有する、記憶装置。
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