WO2019127636A1 - 一种阵列基板及其制备方法 - Google Patents

一种阵列基板及其制备方法 Download PDF

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WO2019127636A1
WO2019127636A1 PCT/CN2018/071381 CN2018071381W WO2019127636A1 WO 2019127636 A1 WO2019127636 A1 WO 2019127636A1 CN 2018071381 W CN2018071381 W CN 2018071381W WO 2019127636 A1 WO2019127636 A1 WO 2019127636A1
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layer
etching
passivation layer
flat
passivation
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PCT/CN2018/071381
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English (en)
French (fr)
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袁文豪
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/749,473 priority Critical patent/US10797083B2/en
Publication of WO2019127636A1 publication Critical patent/WO2019127636A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes

Definitions

  • the present invention relates to the field of screen display technologies, and in particular, to an array substrate and a method for fabricating the same.
  • a typical array substrate fabrication process is: first, a metal layer 11' is deposited on a substrate substrate 1', and then a passivation layer 12' is formed on the substrate substrate 1' and the metal layer 11'.
  • a flat layer 13' is formed on the passivation layer 12', and the flat layer 13' and the passivation layer 12' are etched to form contact holes 15'.
  • the passivation layer 12' is usually made of a material such as SiNx. Since the etching speeds of the flat layer 13' and the passivation layer 12' are different, generally, the etching speed of the flat layer 13' is slower than that of the passivation layer 12'.
  • the flat layer 13' formed by the PFA process remains on the base substrate 1' after etching, so that the edge of the flattened layer 13' after etching is more protruded than the edge of the passivation layer 12', the contact hole 15'
  • the walls of the holes are discontinuous and eventually form an undercut 10'.
  • the technical problem to be solved by the present invention is to provide an array substrate and a preparation method thereof to prevent the deposited pixel electrode layer from being broken.
  • an array substrate including:
  • a contact hole formed by etching a flat layer on the metal layer and the passivation layer, the metal layer being at least partially exposed to the contact hole, the contact hole being at the passivation layer
  • the wall of the hole is in the same plane as the wall of the hole at the flat layer or forms an obtuse angle
  • a continuous pixel electrode layer is formed at the flat layer and the contact hole, and the pixel electrode layer is in contact with the metal layer.
  • the contact hole forms a step at the hole wall at the passivation layer, including a first hole wall parallel to the base substrate, and inclined from the first hole wall toward the metal layer and An adjacent second hole wall, the first hole wall and the contact hole forming an obtuse angle at a hole wall at the flat layer.
  • the passivation layer is made of any one of SiNx, SiOx, and SiOxNy.
  • the invention also provides a method for preparing an array substrate, comprising:
  • planarization layer and the passivation layer on the metal layer are etched in two steps to form a contact hole, the metal layer being at least partially exposed to the contact hole, the contact hole being at the passivation layer
  • the wall of the hole is in the same plane as the wall of the hole at the flat layer or forms an obtuse angle
  • a continuous pixel electrode layer is formed at the flat layer and the contact hole, and the pixel electrode layer is in contact with the metal layer.
  • the etching rate selection ratio of the flat layer and the passivation layer in the first etching is smaller than the flat layer in the second etching step The etching rate selection ratio of the passivation layer.
  • the etch rate selection ratio of the flat layer and the passivation layer in the first etching step is [0.8, 1], and the etching rate of the flat layer and the passivation layer in the second etching step is selected.
  • the value range is [1.8, 2].
  • the ratio of the thickness of the etched flat layer to the thickness of the etched passivation layer is 1.2 to 1.5 by the two-step etching.
  • the two-step etching on the flat layer and the passivation layer on the metal layer further includes: adjusting the etching time of the first step or the second step according to the flat layer material or the passivation layer film quality.
  • the etching time of the first step is increased; if the flat layer is made of a material with a faster etching rate, the etching time of the second step is reduced.
  • the etching time of the first step is reduced; if the flat layer is made of a material with a slower etching rate, the etching time of the second step is increased.
  • the beneficial effects of the embodiments of the present invention are that the two-step etching of the flat layer and the passivation layer on the metal layer forms an obtuse angle between the hole wall of the contact hole at the passivation layer and the hole wall at the flat layer.
  • FIG. 1 is a schematic structural view of a conventional array substrate.
  • FIG. 2 is another schematic structural view of a conventional array substrate.
  • FIG. 3 is a schematic structural view of an array substrate according to an embodiment of the present invention.
  • FIG 4 is another schematic structural view of an array substrate according to an embodiment of the present invention.
  • FIG. 5 is still another schematic structural view of an array substrate according to an embodiment of the present invention.
  • FIG. 6 is still another schematic structural view of an array substrate according to an embodiment of the present invention.
  • FIG. 7 is a schematic view showing still another structure of an array substrate according to an embodiment of the present invention.
  • FIG. 8 is a schematic flow chart of a method for fabricating an array substrate according to Embodiment 2 of the present invention.
  • an embodiment of the present invention provides an array substrate, including:
  • the metal layer 11 is at least partially exposed to the contact hole 15 by a contact hole 15 formed by etching the flat layer 13 on the metal layer 11 and the passivation layer 12, the contact hole 15 being
  • the hole wall 120 at the passivation layer 12 is in the same plane as the hole wall 130 at the flat layer 13 or forms an obtuse angle ⁇ ;
  • a continuous pixel electrode layer 14 is formed at the flat layer 13 and the contact hole 15, and the pixel electrode layer 14 is connected to the metal layer 11.
  • a step etching method is adopted: the first step etches more passivation layer 12 and less The flat layer 13; the second step etches the remaining passivation layer 12 and more of the planar layer 13, whereby the hole wall 130 of the formed contact hole 15 at the flat layer 13 does not protrude at the passivation layer 12
  • the hole wall 120, the front end of the hole wall 130 at the flat layer 13 does not hang to cause undercut, but is in the same plane as the hole wall 120 at the passivation layer 12 or forms an obtuse angle ⁇ .
  • the pixel electrode layer 14 is then deposited on the flat layer 13 and along the walls of the holes continuous along the contact holes 15, without the undercuts that occur in the prior art, so that no cracking occurs.
  • the flat layer 13 in the present embodiment is formed of an organic material by a PFA process, and may be, for example, an organic insulating film.
  • FIG. 3 is a schematic view showing the structure in which the hole wall 120 of the contact hole 15 at the passivation layer 12 and the hole wall 130 at the flat layer 13 are in the same plane, that is, the hole wall 120 of the contact hole 15 at the passivation layer 12 and The angle ⁇ formed by the hole wall 130 at the flat layer 13 is 180°
  • FIG. 4 is a schematic view showing the structure of the pixel electrode layer 14 deposited on the flat layer 13 and the contact hole 15 correspondingly, due to the hole wall at the flat layer 13. In the same plane as the hole wall 120 at the passivation layer 12, the front end of the 130 at the flat layer 13 is not suspended to cause undercut, so that the pixel electrode layer 14 is deposited without cracking.
  • FIG. 5 is a schematic view showing the structure in which the hole wall 120 of the contact hole 15 at the passivation layer 12 forms an obtuse angle with the hole wall 130 at the flat layer 13.
  • the angle formed by the hole wall 120 of the contact hole 15 at the passivation layer 12 and the hole wall 130 at the flat layer 13 is in the range of (90°, 180°).
  • 6 is a schematic view showing the structure of depositing the pixel electrode layer 14 on the flat layer 13 and the contact hole 15 correspondingly. Since the hole wall at the flat layer 13 forms an obtuse angle with the hole wall 120 at the passivation layer 12, the flat layer 13 The front end of the 130 is not suspended to cause undercut, so that the pixel electrode layer 14 is deposited without breaking.
  • the present embodiment further provides a structure of the hole wall at the passivation layer 12, that is, the contact hole 15 forms a step at the hole wall of the passivation layer 12, including parallel to the base substrate 1. a first hole wall 120, and a second hole wall 121 inclined from the first hole wall 120 toward the metal layer 11 and being in contact therewith, the first hole wall 120 and the contact hole 15 forming a hole wall 130 at the flat layer 13 Obtuse angle ⁇ .
  • the above-described structure for forming a step at the passivation layer 12 can ensure a sufficient process window.
  • the passivation layer 12 is made of any one of SiNx, SiOx, and SiOxNy.
  • a second embodiment of the present invention provides a method for preparing an array substrate, including:
  • planarization layer and the passivation layer on the metal layer are etched in two steps to form a contact hole, the metal layer being at least partially exposed to the contact hole, the contact hole being at the passivation layer
  • the wall of the hole is in the same plane as the wall of the hole at the flat layer or forms an obtuse angle
  • a continuous pixel electrode layer is formed at the flat layer and the contact hole, and the pixel electrode layer is connected to the metal layer.
  • the present embodiment performs etching on the flat layer and the passivation layer on the metal layer in two steps, wherein the etching rate selection ratio of the flat layer and the passivation layer in the first step is smaller than that in the second step.
  • the etching rate selection ratio of the passivation layer that is, the first step etches more passivation layer and less flat layer
  • the second step etches the remaining passivation layer and more flat layers, thereby making
  • the hole wall 130 of the formed contact hole at the flat layer 13 does not protrude from the hole wall 120 at the passivation layer 12, and the front end of the hole wall 130 at the flat layer 13 does not hang to cause undercut, but is passivated
  • the cell walls 120 at layer 12 are in the same plane or form an obtuse angle ⁇ (as shown in Figure 3).
  • the embodiment of the present invention adopts a two-step etching, and the etching rate selection ratio of the flat layer and the passivation layer in the first step is smaller than the etching rate selection ratio of the flat layer and the passivation layer in the second step, and the bluntness is ensured.
  • the etching rate selection ratio of the flat layer and the passivation layer in the first step is smaller than the etching rate selection ratio of the flat layer and the passivation layer in the second step, and the bluntness is ensured.
  • the passivation layer 12 is made of any one of SiNx, SiOx, and SiOxNy.
  • the embodiment of the present invention does not limit the metal layer 11, and may form a source or a drain by patterning, and is connected to the pixel electrode at the contact hole 15.
  • the etching rate refers to the thickness of the film layer etched per unit time, for example, the etching rate of the flat layer is 800 A/min, which means that the thickness of the etched flat layer per minute is 800 angstroms;
  • the passivation rate of the passivation layer was 1000 A/min, indicating that the thickness of the etched passivation layer per minute was 1000 angstroms.
  • the etch rate selection ratio of the flat layer and the passivation layer is the ratio of the etch rate of the flat layer to the etch rate of the passivation layer.
  • the matching of the film quality of the different passivation layers and the material of the flat layer can be coped with the fine adjustment of the etching time.
  • the film quality affects the etching rate. For example, when the SiNx film becomes dense, the etching rate is slowed down. As mentioned above, in the first etching, the SiNx etching rate is relatively fast. Increase the etching time of the first step to etch more SiNx to ensure the etching effect. For example, if the flat layer is replaced with a material, the etching rate is increased. Similarly, as described above, in the second etching step, the etching rate of the flat layer is relatively fast, so that the etching of the second step can be appropriately reduced.
  • the etching time of the first step is reduced; if the flat layer is made of a material having a slower etching rate, the etching time of the second step is increased.
  • the beneficial effects of the embodiments of the present invention are: the hole wall of the contact hole at the passivation layer and the hole at the flat layer by performing two-step etching on the flat layer and the passivation layer on the metal layer.
  • the wall forms an obtuse angle, which solves the problem that the pixel electrode layer is broken due to the undercut in the prior art; and on the basis of ensuring that the passivation layer at the contact hole is etched, a relatively small flat layer is etched away to avoid
  • the RGB color resistance is contaminated by the contact of the liquid crystal; in addition, the matching of the film quality of the different passivation layers and the flat layer material can be dealt with by fine-tuning the two-step etching time.

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Abstract

一种阵列基板及其制备方法，其中，阵列基板包括：衬底基板（1）；形成在衬底基板（1）上的金属层（11）；形成在衬底基板（1）和金属层（11）上的钝化层（12）；形成在钝化层（12）上的平坦层（13）；通过对金属层（11）上的平坦层（12）和钝化层（13）进行刻蚀形成的接触孔（15），金属层（11）至少部分地暴露于接触孔（15），接触孔（15）在钝化层（12）处的孔壁（120）与在平坦层（13）处的孔壁（130）处于同一平面或者形成一钝角（θ）；形成在平坦层（13）以及接触孔（15）处的连续的像素电极层（14），像素电极层（14）与金属层（11）相连接。通过对金属层（11）上的平坦层（13）和钝化层（12）进行两步刻蚀，使接触孔（15）在钝化层（12）处的孔壁（120）与在平坦层（13）处的孔壁（130）处于同一平面或者形成一钝角（θ），解决了因出现底切导致像素电极层（14）断裂的问题。

Description

一种阵列基板及其制备方法
本申请要求于2017年12月28日提交中国专利局、申请号为201711461754.7、发明名称为“一种阵列基板及其制备方法”的中国专利申请的优先权，上述专利的全部内容通过引用结合在本申请中。
技术领域
本发明涉及屏幕显示技术领域，尤其涉及一种阵列基板及其制备方法。
背景技术
随着LCD面板阵列基板(Array)段的制程中，越来越多应用COA(彩膜层集成到阵列基板，Color filter on Array)、POA(光阻间隔物集成到阵列基板，Photo spacer on Array)等新技术，需要引入PFA(polymer film on array)工艺来制备平坦层，优化膜层表面平坦度。
请参照图1所示，通常的阵列基板制作过程是：首先在衬底基板1′上沉积形成金属层11′，然后在衬底基板1′和金属层11′上形成钝化层12′，再在钝化层12′上形成平坦层13′，对平坦层13′和钝化层12′进行刻蚀形成接触孔15′。钝化层12′通常由SiNx等材料制成，由于平坦层13′和钝化层12′的刻蚀速度不相同，一般来说平坦层13′的刻蚀速度较钝化层12′慢，而且通过PFA工艺形成的平坦层13′在刻蚀后会保留在衬底基板1′上，使得刻蚀后平坦层13′的边缘比钝化层12′的边缘更突出，接触孔15′的孔壁不连续，最终形成底切(undercut)10′。
接下来沉积像素电极层14′时，请在参照图2所示，由于平坦层13′的边缘与钝化层12′的边缘之间形成有底切10′，导致该处的像素电极层14′容易发生断裂。
发明内容
本发明所要解决的技术问题在于，提供一种阵列基板及其制备方法，以避免沉积的像素电极层发生断裂。
为了解决上述技术问题，本发明提供一种阵列基板，包括：
衬底基板；
形成在所述衬底基板上的金属层；
形成在所述衬底基板和所述金属层上的钝化层；
形成在所述钝化层上的平坦层；
通过对所述金属层上的平坦层和所述钝化层进行刻蚀形成的接触孔，所述金属层至少部分地暴露于所述接触孔，所述接触孔在所述钝化层处的孔壁与在所述平坦层处的孔壁处于同一平面或者形成一钝角；
形成在所述平坦层以及所述接触孔处的连续的像素电极层，所述像素电极层与所述金属层相接触。
其中，所述接触孔在所述钝化层处的孔壁形成一台阶，包括平行于所述衬底基板的第一孔壁，以及自所述第一孔壁朝向所述金属层倾斜并与其相接的第二孔壁，所述第一孔壁与所述接触孔在所述平坦层处的孔壁形成一钝角。
其中，所述钝化层材质为SiNx、SiOx、SiOxNy中的任一种。
本发明还提供一种阵列基板的制备方法，包括：
提供一衬底基板；
在所述衬底基板上依次形成金属层、钝化层和平坦层；
对所述金属层上的平坦层和钝化层分两步进行刻蚀形成接触孔，使所述金属层至少部分地暴露于所述接触孔，所述接触孔在所述钝化层处的孔壁与在所述平坦层处的孔壁处于同一平面或者形成一钝角；
在所述平坦层及所述接触孔处形成连续的像素电极层，所述像素电极层与所述金属层相接触。
其中，对所述金属层上的平坦层和钝化层进行的两步刻蚀中，第一步刻蚀中平坦层和钝化层的刻蚀速率选择比小于第二步刻蚀中平坦层和钝化层的刻蚀速率选择比。
其中，第一步刻蚀中平坦层与钝化层的刻蚀速率选择比的取值范围为[0.8,1]，第二步刻蚀中平坦层与钝化层的刻蚀速率选择比的取值范围为[1.8,2]。
其中，通过所述两步刻蚀，刻蚀掉的平坦层厚度与刻蚀掉的钝化层厚度 之比为1.2～1.5。
其中，对所述金属层上的平坦层和钝化层进行的两步刻蚀中，进一步包括：根据平坦层材质或钝化层膜质相应调整第一步或第二步的刻蚀时间。
其中，如果所述钝化层选用更致密的膜质，则增加第一步的刻蚀时间；如果平坦层选用刻蚀速率更快的材质，则减少第二步的刻蚀时间。
其中，如果所述钝化层选用更疏松的膜质，则减少第一步的刻蚀时间；如果平坦层选用刻蚀速率更慢的材质，则增加第二步的刻蚀时间。
本发明实施例的有益效果在于：通过对金属层上的平坦层和钝化层进行两步刻蚀，使接触孔在钝化层处的孔壁与在平坦层处的孔壁形成一钝角，解决现有技术中因出现底切导致像素电极层断裂的问题；并且在保证接触孔处的钝化层刻蚀干净的基础上，刻蚀掉相对较少的平坦层，避免RGB色阻与液晶接触造成污染；此外，还可以通过对两步刻蚀时间的微调来应对不同钝化层膜质和平坦层材质的搭配。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有阵列基板的结构示意图。
图2是现有阵列基板的另一结构示意图。
图3是本发明实施例一一种阵列基板的结构示意图。
图4是本发明实施例一一种阵列基板的另一结构示意图。
图5是本发明实施例一一种阵列基板的又一结构示意图。
图6是本发明实施例一一种阵列基板的又一结构示意图。
图7是本发明实施例一一种阵列基板的再一结构示意图。
图8是本发明实施例二一种阵列基板的制备方法的流程示意图。
具体实施方式
以下各实施例的说明是参考附图，用以示例本发明可以用以实施的特定实施例。
请同时参照图3至图7所示，本发明实施例一提供一种阵列基板，包括：
衬底基板1；
形成在所述衬底基板1上的金属层11；
形成在所述衬底基板1和所述金属层11上的钝化层12；
形成在所述钝化层12上的平坦层13；
通过对所述金属层11上的平坦层13和所述钝化层12进行刻蚀形成的接触孔15，所述金属层11至少部分地暴露于所述接触孔15，所述接触孔15在所述钝化层12处的孔壁120与在所述平坦层13处的孔壁130处于同一平面或者形成一钝角θ；
形成在所述平坦层13以及所述接触孔15处的连续的像素电极层14，所述像素电极层14与所述金属层11相连接。
具体地，本实施例在对金属层11上的平坦层13和钝化层12进行刻蚀时，采取分步刻蚀的方式：第一步刻蚀较多的钝化层12和较少的平坦层13；第二步刻蚀剩余的钝化层12和较多的平坦层13，由此使得形成的接触孔15在平坦层13处的孔壁130不会突出于在钝化层12处的孔壁120，平坦层13处的孔壁130前端不会悬空而造成底切，而是与钝化层12处的孔壁120处于同一平面或者形成一个钝角θ。之后在平坦层13上以及沿着接触孔15连续的孔壁沉积像素电极层14，没有现有技术中出现的底切，因而不会发生断裂。可以理解的是，本实施例中平坦层13由有机材料通过PFA工艺形成，例如可以是一种有机绝缘膜。
图3所示为接触孔15在钝化层12处的孔壁120与在平坦层13处的孔壁130处于同一平面的结构示意图，即接触孔15在钝化层12处的孔壁120与在平坦层13处的孔壁130形成的夹角θ为180°，图4为相应地在平坦层13上以及接触孔15沉积形成像素电极层14的结构示意图，由于平坦层13处的孔壁与钝化层12处的孔壁120处于同一平面，平坦层13处的130前端不会悬空而造成底切，因此沉积像素电极层14时不会发生断裂。
图5所示为接触孔15在钝化层12处的孔壁120与在平坦层13处的孔壁130形成一钝角的结构示意图。与图3所示的结构结合起来可知，接触孔15在钝化层12处的孔壁120与在平坦层13处的孔壁130形成的夹角的取值 范围是(90°,180°]。图6为相应地在平坦层13上以及接触孔15沉积形成像素电极层14的结构示意图，由于平坦层13处的孔壁与钝化层12处的孔壁120形成一钝角，平坦层13处的130前端不会悬空而造成底切，因此沉积像素电极层14时不会发生断裂。
再请参照图7所示，本实施例还提供另一种钝化层12处孔壁的结构，即接触孔15在钝化层处12的孔壁形成一台阶，包括平行于衬底基板1的第一孔壁120，以及自第一孔壁120朝向金属层11倾斜并与其相接的第二孔壁121，第一孔壁120与接触孔15在平坦层13处的孔壁130形成一钝角θ。考虑到形成钝化层12和平坦层13的材质均匀性，以及面板内各点位刻蚀状况可能存有差异，上述在钝化层12处形成台阶的结构，能够保证有足够的制程窗口。
本实施例中，钝化层12材质为SiNx、SiOx、SiOxNy中的任一种。
请再参照图8所示，相应于本发明实施例一，本发明实施例二提供一种阵列基板的制备方法，包括：
提供一衬底基板；
在所述衬底基板上依次形成金属层、钝化层和平坦层；
对所述金属层上的平坦层和钝化层分两步进行刻蚀形成接触孔，使所述金属层至少部分地暴露于所述接触孔，所述接触孔在所述钝化层处的孔壁与在所述平坦层处的孔壁处于同一平面或者形成一钝角；
在所述平坦层及所述接触孔处形成连续的像素电极层，所述像素电极层与所述金属层相连接。
具体地，本实施例对金属层上的平坦层和钝化层进行刻蚀分成两步进行，其中第一步中平坦层和钝化层的刻蚀速率选择比小于第二步中平坦层和钝化层的刻蚀速率选择比，即：第一步刻蚀较多的钝化层和较少的平坦层，第二步刻蚀剩余的钝化层和较多的平坦层，由此使得形成的接触孔在平坦层13处的孔壁130不会突出于在钝化层12处的孔壁120，平坦层13处的孔壁130前端不会悬空而造成底切，而是与钝化层12处的孔壁120处于同一平面或者形成一个钝角θ(如图3所示)。之后在平坦层13上以及沿着接触孔15连续的孔壁沉积像素电极层14时，由于没有现有技术中出现的底切，因而 不会发生断裂。
需要说明的是，如果为避免出现前述底切而采用一步刻蚀，则需加快平坦层的刻蚀，减慢钝化层的刻蚀；这样为保证钝化层刻蚀干净，必然要增加时间，影响了产能；另一方面，加快平坦层的刻蚀，即增大平坦层的刻蚀速率，必然将降低平坦层最终的剩余量，当平坦层剩余量不足时，容易出现RGB色阻与液晶接触造成污染的情况，影响产品品质。因此，本发明实施例采用两步刻蚀，并且第一步中平坦层和钝化层的刻蚀速率选择比小于第二步中平坦层和钝化层的刻蚀速率选择比，在保证钝化层刻蚀干净的基础上，解决了平坦层剩余量和底切之间的矛盾。
本实施例中，钝化层12材质为SiNx、SiOx、SiOxNy中的任一种。此外，本发明实施例不对金属层11做限制，其可以通过图案化后形成源极或漏极，在接触孔15处与像素电极连接。
进一步地，第一步刻蚀中，平坦层与钝化层的刻蚀速率选择比的取值范围为[0.8,1]，以平坦层为有机绝缘膜、钝化层为SiNx为例，即有机绝缘膜:SiNx＝0.8～1，刻蚀大部分SiNx，少部分有机绝缘膜；第二步刻蚀中，平坦层与钝化层的刻蚀速率选择比的取值范围为[1.8,2]，即有机绝缘膜:SiNx＝1.8～2，刻蚀剩余的SiNx并刻蚀大部分有机绝缘膜，保证由此形成的接触孔15在平坦层13处的孔壁130不会突出于在钝化层12处的孔壁120，平坦层13处的孔壁130前端不会因悬空而造成底切。可以理解地，本实施例中，刻蚀速率是指单位时间内刻蚀的膜层厚度，例如，平坦层的刻蚀速率是800A/min，表示每分钟刻蚀平坦层的厚度为800埃；钝化层的刻蚀速率是1000A/min，表示每分钟刻蚀钝化层的厚度为1000埃。平坦层与钝化层的刻蚀速率选择比即平坦层的刻蚀速率与钝化层的刻蚀速率的比例。通过控制每一步的刻蚀时间，按照上述刻蚀速率选择比，使刻蚀掉的平坦层厚度与刻蚀掉的钝化层厚度之比控制在1.2～1.5。
再进一步地，本实施例可以通过刻蚀时间的微调来应对不同钝化层膜质和平坦层材质的搭配。膜质会影响刻蚀速率，比如当SiNx膜质变得致密，会使得其刻蚀速率变慢，如前所述，在第一步刻蚀中，SiNx刻蚀速率相对较快，为此可以适当增加第一步的刻蚀时间来刻蚀较多的SiNx，保证刻蚀 效果。又比如平坦层更换了材质，导致其刻蚀速率变快，同样如前所述，在第二步刻蚀中，平坦层刻蚀速率相对较快，为此可以适当减少第二步的刻蚀时间来避免刻蚀过多的平坦层，保证刻蚀效果。同样地，如果钝化层选用更疏松的膜质，则减少第一步的刻蚀时间；如果平坦层选用刻蚀速率更慢的材质，则增加第二步的刻蚀时间。
通过上述说明可知，本发明实施例的有益效果在于：通过对金属层上的平坦层和钝化层进行两步刻蚀，使接触孔在钝化层处的孔壁与在平坦层处的孔壁形成一钝角，解决现有技术中因出现底切导致像素电极层断裂的问题；并且在保证接触孔处的钝化层刻蚀干净的基础上，刻蚀掉相对较少的平坦层，避免RGB色阻与液晶接触造成污染；此外，还可以通过对两步刻蚀时间的微调来应对不同钝化层膜质和平坦层材质的搭配。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (10)

  1. 一种阵列基板，其中，包括：
    衬底基板；
    形成在所述衬底基板上的金属层；
    形成在所述衬底基板和所述金属层上的钝化层；
    形成在所述钝化层上的平坦层；
    通过对所述金属层上的平坦层和所述钝化层进行刻蚀形成的接触孔，使所述金属层至少部分地暴露于所述接触孔，所述接触孔在所述钝化层处的孔壁与在所述平坦层处的孔壁处于同一平面或者形成一钝角；
    形成在所述平坦层以及所述接触孔处的连续的像素电极层，所述像素电极层与所述金属层相连接。
  2. 根据权利要求1所述的阵列基板，其中，所述接触孔在所述钝化层处的孔壁形成一台阶，包括平行于所述衬底基板的第一孔壁，以及自所述第一孔壁朝向所述金属层倾斜并与其相接的第二孔壁，所述第一孔壁与所述接触孔在所述平坦层处的孔壁形成一钝角。
  3. 根据权利要求1所述的阵列基板，其中，所述钝化层材质为SiNx、SiOx、SiOxNy中的任一种。
  4. 一种阵列基板的制备方法，其中，包括：
    提供一衬底基板；
    在所述衬底基板上依次形成金属层、钝化层和平坦层；
    对所述金属层上的平坦层和钝化层分两步进行刻蚀形成接触孔，使所述金属层至少部分地暴露于所述接触孔，所述接触孔在所述钝化层处的孔壁与在所述平坦层处的孔壁处于同一平面或者形成一钝角；
    在所述平坦层及所述接触孔处形成连续的像素电极层，所述像素电极层与所述金属层相连接。
  5. 根据权利要求4所述的制备方法，其中，对所述金属层上的平坦层和钝化层进行的两步刻蚀中，第一步刻蚀中平坦层和钝化层的刻蚀速率选择比小于第二步刻蚀中平坦层和钝化层的刻蚀速率选择比。
  6. 根据权利要求5所述的制备方法，其中，第一步刻蚀中平坦层与钝化 层的刻蚀速率选择比的取值范围为[0.8,1]，第二步刻蚀中平坦层与钝化层的刻蚀速率选择比的取值范围为[1.8,2]。
  7. 根据权利要求5所述的制备方法，其中，通过所述两步刻蚀，刻蚀掉的平坦层厚度与刻蚀掉的钝化层厚度之比为1.2～1.5。
  8. 根据权利要求5所述的制备方法，其中，对所述金属层上的平坦层和钝化层进行的两步刻蚀中，进一步包括：根据平坦层材质或钝化层膜质相应调整第一步或第二步的刻蚀时间。
  9. 根据权利要求8所述的制备方法，其中，如果所述钝化层选用更致密的膜质，则增加第一步的刻蚀时间；如果平坦层选用刻蚀速率更快的材质，则减少第二步的刻蚀时间。
  10. 根据权利要求8所述的制备方法，其中，如果所述钝化层选用更疏松的膜质，则减少第一步的刻蚀时间；如果平坦层选用刻蚀速率更慢的材质，则增加第二步的刻蚀时间。
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