WO2019114357A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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WO2019114357A1
WO2019114357A1 PCT/CN2018/106546 CN2018106546W WO2019114357A1 WO 2019114357 A1 WO2019114357 A1 WO 2019114357A1 CN 2018106546 W CN2018106546 W CN 2018106546W WO 2019114357 A1 WO2019114357 A1 WO 2019114357A1
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layer
substrate
forming
array substrate
molybdenum oxide
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PCT/CN2018/106546
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English (en)
French (fr)
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王守坤
邵喜斌
宋勇志
郭会斌
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US16/758,488 priority Critical patent/US20200343329A1/en
Publication of WO2019114357A1 publication Critical patent/WO2019114357A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning

Definitions

  • the present disclosure relates to the field of display, and in particular to an array substrate, a method of fabricating an array substrate, and a display device including the array substrate.
  • the display panel is one of the important components for obtaining information in an electronic device.
  • the performance of the array substrate determines the performance of the display panel, and its performance directly affects the performance and user experience of the terminal device.
  • Metal traces are typically formed in a substrate in the art. However, the reflectivity of the metal trace is extremely high, and the adhesion between the metal and the substrate is limited, which causes a series of problems. These problems greatly limit the performance of display panels and display devices.
  • an array substrate including:
  • the metal wiring layer including a first molybdenum oxide substrate layer and a first metal layer on a surface of the first molybdenum oxide substrate layer away from the substrate substrate .
  • the first molybdenum oxide substrate layer is a substrate layer directly formed by physical vapor deposition.
  • the array substrate further includes a thin film transistor disposed on the base substrate, the metal wiring layer including a gate of the thin film transistor.
  • a source drain of the thin film transistor includes a second molybdenum oxide layer and a second metal layer.
  • the array substrate further includes a trace pattern
  • the metal wiring layer includes the trace pattern
  • the thickness of the first molybdenum oxide substrate layer is not lower than
  • the first metal layer is made of copper or aluminum.
  • the base substrate is a glass substrate.
  • a method of fabricating an array substrate including:
  • the method of fabricating the array substrate further includes forming a thin film transistor on the base substrate.
  • forming a thin film transistor on the base substrate includes:
  • Forming an active layer forming an active layer film on the gate insulating layer, and forming a pattern including the active layer by a patterning process;
  • a source drain is formed, a source/drain material layer is formed on the active layer, and a pattern including a source drain is formed by a patterning process.
  • forming a source drain includes: forming a second molybdenum oxide substrate layer on the active layer, and forming a second metal layer on the second molybdenum oxide underlayer, by patterning The process forms a pattern comprising the source and drain.
  • the method of fabricating the array substrate further includes forming a trace pattern on which a trace pattern is formed by a patterning process.
  • the first molybdenum oxide substrate layer is directly formed by physical vapor deposition, and the deposition parameters are: argon gas flow rate of 10 to 3000 sccm, gas pressure of 0.1-2 Pa, power of 0.5-80 kw, deposition rate.
  • the thickness of the first molybdenum oxide substrate layer is not lower than
  • a display device including the above array substrate.
  • FIG. 1 is a schematic structural view of an array substrate in an exemplary embodiment of the present disclosure
  • Figure 2 shows a comparison of reflectance of various materials in the art
  • FIG. 3 is a schematic structural view of a thin film transistor in which a gate electrode is formed of a metal wiring layer in an exemplary embodiment of the present disclosure
  • FIG. 4 is a schematic structural view of a thin film transistor in which a source and a drain are formed of a metal wiring layer in an exemplary embodiment of the present disclosure
  • FIG. 5 is a schematic structural view of a thin film transistor in which a gate electrode and a source and a drain are formed of two metal wiring layers in an exemplary embodiment of the present disclosure
  • FIG. 6 shows a manufacturing flow chart of an array substrate in an exemplary embodiment of the present disclosure
  • FIG. 7 is a flowchart showing the manufacture of an array substrate in an exemplary embodiment of the present disclosure.
  • FIG. 8 is a flowchart showing the manufacture of an array substrate in an exemplary embodiment of the present disclosure.
  • FIG. 9 is a flowchart showing the manufacture of an array substrate in an exemplary embodiment of the present disclosure.
  • FIG. 10 is a block diagram showing the structure of a display device in an exemplary embodiment of the present disclosure.
  • the present exemplary embodiment first provides an array substrate.
  • the array substrate 100 includes a base substrate 101 and a metal wiring layer 102 .
  • the metal wiring layer 102 is located on the substrate substrate 101 and includes The first molybdenum oxide substrate layer 103 and the first metal layer 104 are located on a surface of the first molybdenum oxide substrate layer 103 away from the base substrate 102.
  • the base substrate 101 is a base substrate commonly used in the art, such as a glass substrate, a quartz substrate, or the like, and is optionally a glass substrate.
  • the metal wiring layer 102 includes a first molybdenum oxide substrate layer 103 and a first metal layer 104.
  • the first metal layer 104 may be made of a highly conductive material such as copper or aluminum, or may be commonly used in the art. Other metal materials or metal alloy materials having high electrical conductivity.
  • Figure 2 shows the reflectance of each material.
  • the reflectivity of Cu or MoNb/Cu is very high, the reflectivity of pure copper is about 95%, and when molybdenum oxide is used as the substrate layer, incident.
  • the light at the contact interface between the Cu metal wiring and the molybdenum oxide is in the same phase as the reflected light, and the light waves are destructively interfered in the space, thereby greatly reducing the reflectance of the Cu metal wiring and reducing the reflectance of the Cu metal wiring. About 93%.
  • a molybdenum oxide substrate layer in the array substrate of the present disclosure to adhere the metal layer on the base substrate enhances the adhesion of the metal layer to the substrate as compared to directly adhering the metal layer to the substrate.
  • the reflectivity of the metal layer is lowered, and the diffusion of metal elements in the metal layer into the base substrate is avoided, further improving the performance of the array substrate.
  • the thickness of the first molybdenum oxide substrate layer is not lower than
  • the array substrate 100 further includes a thin film transistor disposed on the base substrate 101, the metal wiring layer 102 including the gate electrode 105 of the thin film transistor, and FIG. 3 illustrates the metal wiring layer 102.
  • FIG. 3 illustrates the metal wiring layer 102.
  • FIG. 4 is a schematic structural diagram of a thin film transistor in which a drain of a thin film transistor is formed by another metal wiring layer 102 ′.
  • the thin film transistor may further include The molybdenum dioxide substrate layer 103' and the second metal layer 104' form a source drain (S/D) of the thin film transistor by patterning the second molybdenum oxide substrate layer 103' and the second metal layer 104'.
  • S/D source drain
  • FIG. 5 illustrates a structure of a thin film transistor in which a gate electrode 105 and a source and drain (S/D) are respectively formed by the metal wiring layer 102 and another metal wiring layer 102'.
  • the gate electrode 105 and the source and drain (S/D) of the thin film transistor in the present disclosure can be obtained by a patterning process by two metal wiring layers to further reduce the reflectance of the metal wiring. To improve the performance of the display device.
  • the metal wiring layer 102 may include a trace pattern on the array substrate 100, and any trace pattern formed on the base substrate 101 may be formed by patterning the metal wiring layer 102, and the trace pattern may be a gate line pattern, a data line pattern or a signal line pattern, and the like.
  • the exemplary embodiment provides a method for manufacturing an array substrate, as shown in FIG. 6 , specifically:
  • the first molybdenum oxide substrate layer 103 is formed by depositing directly on the base substrate 101 by a PVD (physical vapor deposition) device, specifically using a molybdenum oxide metal block as a target, and bombarding the target with an inert gas ion to make the target in the target Oxygen and molybdenum are bombarded and deposited on the substrate to form a molybdenum oxide film layer.
  • PVD physical vapor deposition
  • the deposition parameters of the molybdenum oxide substrate layer 103 in the present disclosure are: gas pressure 0.1 to 2 Pa, Ar gas flow rate 10 to 3000 sccm, power 0.5 to 80 kw, deposition rate
  • the gas pressure is 0.5 to 1 Pa
  • the Ar gas flow rate is 1350 sccm
  • the power is 11 to 13 kw
  • the deposition rate is
  • the thickness of the first molybdenum oxide substrate layer is not lower than
  • a first metal layer 104 is formed on the first molybdenum oxide substrate layer 103, and the first molybdenum oxide substrate layer 103 and the first metal layer 104 form a metal wiring layer 102.
  • the first metal layer 104 is formed thereon.
  • the first metal layer 104 may be made of a high conductivity material such as copper or aluminum, or other metals having high conductivity commonly used in the art may be used. Material or metal alloy material.
  • the method of forming the first metal layer 104 may be a process such as PVD, CVD, PECVD, etc., optionally adopting a PVD method, and may be sequentially deposited in the same device as the first molybdenum oxide substrate layer 103, thereby reducing the process flow and improving the manufacturing efficiency. .
  • a thin film transistor is formed thereon, and the gate electrode 105 of the thin film transistor is formed by patterning the metal wiring layer 102, and further, may be Another metal wiring layer is patterned to form the source and drain (S/D) of the thin film transistor.
  • S/D source and drain
  • the array substrate 100 includes a display area AA and a non-display area around the display area AA.
  • the metal compound in the region D is removed by a patterning process.
  • the wire layer 102 is formed such that the metal wiring layer 102 in the display area AA is formed as the gate electrode 105 of the thin film transistor, and the metal wiring layer 102 in the non-display area is formed as a wiring layer around the array substrate, the patterning process It may be a photolithography process, or other processes commonly used in the art, optionally forming a pattern including the gate electrode 105 by a photolithography process, specifically by forming a first mask layer on the metal layer 104.
  • the metal wiring layer 102 not shielded by the first mask layer is etched to form the gate electrode 105 and the trace.
  • the concentration of the etching solution can be adjusted, the etching time and the etching rate can be controlled to prevent residual or over-etching, which affects the performance of the array substrate.
  • a gate insulating layer 106 is deposited on the gate electrode 105, the trace of the non-display area, and the exposed base substrate 101.
  • the material of the gate insulating layer 106 may be SiOx, SiNx, or the like, and may be other insulating materials commonly used in the art, which is not specifically limited in the present disclosure.
  • an active layer film is deposited on the gate insulating layer 106.
  • the material of the active layer film is a material commonly used in the art, and details are not described herein.
  • the active layer film is patterned by a patterning process to form an active layer 107.
  • the patterning process is similar to the patterning process for forming the gate electrode 105.
  • the specific process is: forming a second mask layer on the gate insulating layer 106, exposing and developing the second mask layer to form a corresponding layer of the active layer 107.
  • the pattern exposes the non-active layer region, and the non-active layer region is etched by the etching solution to form the active layer 107.
  • the concentration of the etching solution can be adjusted, the etching time and the etching rate can be controlled to prevent residue. Or over etched.
  • S6 Forming the source and drain electrodes 109, forming a source/drain material layer 108 on the active layer 107, and forming a pattern including the source and drain electrodes 109 by a patterning process.
  • a source/drain material layer 108 is deposited on the active layer 107.
  • the source and drain material layer 108 may be a metal material or a metal alloy material commonly used in the art, such as a highly conductive material such as Cu, Al, Au, Ag, or the like.
  • the metal wiring layer in the disclosure optionally forms a source/drain material layer using the metal wiring layer in the present disclosure, that is, the source/drain material layer 108 includes a second molybdenum oxide substrate layer and a second metal layer, wherein the second The molybdenum oxide substrate layer can further reduce the reflectivity of metal traces such as Cu and Al, thereby improving the performance of the array substrate 100 and the display device.
  • the patterning process for forming the source and drain electrodes 109 is similar to the patterning process for forming the gate electrode 105. Specifically, a third mask layer is formed on the source/drain material layer 108, and the third mask layer is exposed, developed, and formed with the source and drain electrodes. The corresponding pattern of 109 exposes the channel region, and then the source and drain material layers are etched by an etching solution to form the source and drain electrodes 109 and the channel.
  • the performance of the array substrate 100 can be affected by adjusting the concentration of the etching solution, controlling the etching time and the etching rate to prevent residual or over-etching.
  • a planarization insulating layer 110 is formed on the source and drain electrodes 109 and the gate insulating layer 106, and then a fourth mask layer is formed on the planarization insulating layer 110 and etched to form a pixel via hole. Then, the transparent via material is filled into the pixel via hole, and the pixel electrode 111 is formed by forming a fourth mask layer on the transparent conductive material layer, and the transparent conductive material may be a transparent metal or a transparent metal oxide. Transparent metal oxides such as FTO, ZTO, ITO, etc.
  • a transparent conductive layer may be deposited on the substrate 101 located in the display area AA before the metal wiring layer 102 is formed (as in FIG. 8) or after the gate electrode 105 is formed (as in FIG. 9).
  • the common electrode 112 of the pixel region is formed by forming a mask layer on the transparent conductive layer and etching the transparent conductive layer.
  • the method of fabricating the array substrate 100 further includes forming a trace pattern: forming a trace pattern on the metal wiring layer by a patterning process, and the trace pattern may be a gate line pattern, a data line pattern, or Signal line pattern, etc.
  • the display device 1000 includes a display panel 1001.
  • the display panel 1001 is a display panel in the present disclosure, and the display device 1000 may be a product or component having a display function such as an electronic paper, an OLED display, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, or the like.

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Abstract

一种阵列基板(100)，所述阵列基板(100)包括：衬底基板(101)；金属配线层(102)，位于所述衬底基板(101)上；所述金属配线层(102)包括第一氧化钼衬底层(103)以及位于所述第一氧化钼衬底层(103)上的第一金属层(104)。

Description

阵列基板及其制造方法、显示装置
交叉引用
本申请要求于2017年12月15日提交的申请号为201711351791.2的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示领域，特别涉及一种阵列基板、阵列基板的制造方法、包含阵列基板的显示装置。
背景技术
随着科学技术的进步，越来越多的电子设备进入了人们的生活中，比如智能手机、平板电脑、液晶电视等终端设备，丰富和方便了人们的日常生活。
显示面板是电子设备中获取信息的重要部件之一，同时阵列基板的性能决定了显示面板的性能，其性能的好坏直接影响终端设备的性能及用户体验。本领域通常在衬底基板形成金属走线。但是金属走线的反射率极高，并且金属和基板之间的粘附力有限，会产生一系列的问题。这些问题极大的限制了显示面板及显示装置的性能。
鉴于此，为了降低金属配线的反射率，并提高金属配线和衬底基板的粘附力，进一步提高显示面板及显示装置的性能，本领域亟需研发一种高性能的阵列基板、显示面板及显示装置。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
根据本公开的第一方面，提供一种阵列基板，其中，包括：
衬底基板；以及
金属配线层，位于所述衬底基板上；所述金属配线层包括第一氧化钼衬底层以及位于所述第一氧化钼衬底层远离所述衬底基板的表面上的第一金属层。
在本公开的示例性实施例中，所述第一氧化钼衬底层为采用物理气相沉积法直接成膜的衬底层。
在本公开的示例性实施例中，所述阵列基板还包括设置在所述衬底基板上的薄膜晶体管，所述金属配线层包括所述薄膜晶体管的栅极。
在本公开的示例性实施例中，所述薄膜晶体管的源漏极包括第二氧化钼层和第二金属层。
在本公开的示例性实施例中，所述阵列基板还包括走线图案，所述金属配线层包括所述走线图案。
在本公开的示例性实施例中，所述第一氧化钼衬底层的厚度不低于
Figure PCTCN2018106546-appb-000001
在本公开的示例性实施例中，所述第一金属层的材质为铜或铝。
在本公开的示例性实施例中，所述衬底基板为玻璃基板。
根据本公开的第二方面，提供一种阵列基板的制造方法，其中，包括：
在衬底基板上形成第一氧化钼衬底层；
在所述第一氧化钼衬底层远离所述衬底基板的表面上形成第一金属层，所述第一氧化钼衬底层和所述第一金属层形成金属配线层
在本公开的示例性实施例中，所述阵列基板的制造方法还包括：在所述衬底基板上形成薄膜晶体管。
在本公开的示例性实施例中，在所述衬底基板上形成薄膜晶体管，包括：
形成包括所述薄膜晶体管栅极的图案，对所述金属配线层通过构图工艺形成包括所述薄膜晶体管栅极的图案；
形成栅绝缘层，在所述栅极上形成栅绝缘层；
形成有源层，在所述栅绝缘层上形成有源层薄膜，通过构图工艺形成包含有源层的图案；
形成源漏极，在所述有源层上形成源漏极材料层，通过构图工艺形 成包含源漏极的图案。
在本公开的示例性实施例中，形成源漏极，包括：在所述有源层上形成第二氧化钼衬底层，在所述第二氧化钼成底层上形成第二金属层，通过构图工艺形成包含源漏极的图案。
在本公开的示例性实施例中，所述阵列基板的制造方法还包括，形成走线图案：在所述金属配线层上通过构图工艺形成走线图案。
在本公开的示例性实施例中，所述第一氧化钼衬底层采用物理气相沉积法直接成膜，沉积参数为：氩气流量10～3000sccm，气压0.1-2Pa，功率0.5-80kw，沉积速率
Figure PCTCN2018106546-appb-000002
在本公开的示例性实施例中，所述第一氧化钼衬底层的厚度不低于
Figure PCTCN2018106546-appb-000003
根据本公开的第三方面，提供一种显示装置，其中，包括上述的阵列基板。
本公开应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出本公开示例性实施例中阵列基板的结构示意图；
图2示出本领域中各材料反射率的对比图；
图3示出本公开示例性实施例中由金属配线层形成栅极的薄膜晶体管的结构示意图；
图4示出本公开示例性实施例中由金属配线层形成源漏极的薄膜晶体管的结构示意图；
图5示出本公开示例性实施例中由两个金属配线层形成栅极和源漏极的薄膜晶体管的结构示意图；
图6示出本公开示例性实施例中阵列基板的制造流程图；
图7示出本公开示例性实施例中阵列基板的制造流程图；
图8示出本公开示例性实施例中阵列基板的制造流程图；
图9示出本公开示例性实施例中阵列基板的制造流程图；
图10示出本公开示例性实施例中显示装置的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
本说明书中使用用语“一个”、“一”、“该”和“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。
本示例实施方式首先提供了一种阵列基板，如图1所示，阵列基板100包括衬底基板101和金属配线层102，所述金属配线层102位于所述衬底基板101上，包括第一氧化钼衬底层103和第一金属层104，第一金属层104位于第一氧化钼衬底层103远离所述衬底基板102的表面上。
衬底基板101为本领域常用的衬底基板，例如玻璃基板、石英基板 等，可选地地为玻璃基板。金属配线层102包含第一氧化钼衬底层103和第一金属层104，为了提高阵列基板的电性能，第一金属层104可以采用铜、铝等高导电性材料，也可以采用本领域常用的其它具有高导电率的金属材料或金属合金材料。
图2示出了各材料的反射率，从图2中可以看出，Cu或MoNb/Cu的反射率很高，纯铜的反射率约为95％，当采用氧化钼作为衬底层时，入射到Cu金属配线与氧化钼的接触界面的光线和反射的光线相位相同，光波在空间相遇发生相消干涉，因此大大降低了Cu金属配线的反射率，使Cu金属配线的反射率降低约93％。
本公开的阵列基板中采用氧化钼衬底层将金属层附着在衬底基板上，相比于直接将金属层粘附在衬底基板上，一方面增强了金属层与衬底基板的粘附力，另一方面，降低了金属层的反射率、避免了金属层中金属元素扩散到衬底基板中，进一步提高了阵列基板的性能。
在本公开的示例实施方式中，为了提高金属层形成的金属走线和衬底基板的粘附力，并最大程度的降低金属层的反射率，第一氧化钼衬底层的厚度不低于
Figure PCTCN2018106546-appb-000004
在本公开的示例实施方式中，阵列基板100还包括设置在衬底基板101上的薄膜晶体管，金属配线层102包括该薄膜晶体管的栅极105，图3示出了由金属配线层102形成薄膜晶体管栅极105的薄膜晶体管结构示意图。
在本公开的另一示例实施方式中，图4示出了由另一金属配线层102’形成薄膜晶体管源漏极的薄膜晶体管的结构示意图，如图4所示，薄膜晶体管还可以包括第二氧化钼衬底层103’和第二金属层104’，通过对第二氧化钼衬底层103’和第二金属层104’构图工艺形成薄膜晶体管的源漏极(S/D)。
在本公开的另一示例实施方式中，图5示出了由金属配线层102和另一金属配线层102’分别形成栅极105和源漏极(S/D)的薄膜晶体管的结构示意图，如图5所示，本公开中的薄膜晶体管的栅极105和源漏极(S/D)可以由两个金属配线层通过构图工艺获得，以进一步减小金属配线的反射率，提高显示装置的性能。
同时，金属配线层102可以包括阵列基板100上的走线图案，任意的形成在衬底基板101上的走线图案均可以通过对金属配线层102进行构图工艺形成，走线图案可以是栅线图案、数据线图案或信号线图案等。
本示例实施方式提供了一种阵列基板的制造方法，如图6所示，具体为：
S1：在衬底基板101上形成第一氧化钼衬底层103；
第一氧化钼衬底层103通过PVD(物理气相沉积)设备直接在衬底基板101上沉积形成，具体以氧化钼金属块为靶材，采用惰性气体离子对靶材进行轰击，使得靶材中的氧和钼被轰出并沉积在基板上形成氧化钼膜层。为了保证氧化钼膜层的均一性，本公开中的氧化钼衬底层103的沉积参数为：气压0.1～2Pa，Ar气流量10～3000sccm，功率0.5～80kw，沉积速率
Figure PCTCN2018106546-appb-000005
可选地，气压为0.5～1Pa，Ar气流量为1350sccm，功率为11～13kw，沉积速率为
Figure PCTCN2018106546-appb-000006
并且第一氧化钼衬底层的厚度不低于
Figure PCTCN2018106546-appb-000007
S2：在第一氧化钼衬底层103上形成第一金属层104，第一氧化钼衬底层103和第一金属层104形成金属配线层102。
形成第一氧化钼衬底层103后，在其上形成第一金属层104，第一金属层104可以采用铜、铝等高导电率材料，也可以采用本领域常用的其它具有高导电率的金属材料或金属合金材料。形成第一金属层104的方法可以是PVD、CVD、PECVD等工艺，可选采用PVD法，可以与第一氧化钼衬底层103在同一设备中依次沉积形成，减少了工艺流程，提高了制造效率。
在本公开的示例实施方式中，形成金属配线层102后，在其上形成薄膜晶体管，通过对所述金属配线层102进行构图工艺形成薄膜晶体管的栅极105，进一步的，也可以对另一金属配线层进行构图工艺形成薄膜晶体管的源漏极(S/D)，具体流程如图7所示：
S3：形成包括薄膜晶体管栅极105的图案，对金属配线层102通过构图工艺形成包括所述薄膜晶体管栅极105的图案；
阵列基板100包括显示区AA以及位于显示区AA周围的非显示区，在衬底基板101上形成第一氧化钼衬底层103和第一金属层104后，采 用构图工艺去除区域D中的金属配线层102，以使显示区AA中的金属配线层102形成为薄膜晶体管的栅极105，同时非显示区中的金属配线层102形成为阵列基板周围的走线层，所述构图工艺可以是光刻工艺，也可以是本领域常用的其它工艺，可选地采用光刻工艺形成包括栅极105的图案，具体的可以是通过在金属层104上形成第一掩膜层，对所述第一掩膜层曝光、显影以形成与栅极105及非显示区走线所在区域对应的图案，暴露非栅极区及非走线区的金属配线层102，然后采用刻蚀液对未被第一掩膜层遮蔽的金属配线层102进行刻蚀，以形成栅极105及走线。在刻蚀过程中，可以通过调整刻蚀液的浓度，管控刻蚀时间及刻蚀速率，防止出现残留或过刻蚀，影响阵列基板的性能。
S4：形成栅绝缘层106，在栅极105上形成栅绝缘层106；
形成薄膜晶体管的栅极105后，在栅极105、非显示区的走线和暴露的衬底基板101上沉积栅绝缘层106。栅绝缘层106的材料可以是SiOx、SiNx等，也可以是本领域常用的其它绝缘材料，本公开对此不做具体限定。
S5：形成有源层107，在栅绝缘层106上形成有源层薄膜，通过构图工艺形成包含有源层107的图案；
首先在栅绝缘层106上沉积有源层薄膜，有源层薄膜的材料为本领域常用的材料，在此不再赘述；然后通过构图工艺对有源层薄膜进行图案化形成包含有源层107的图案，该构图工艺与形成栅极105的构图工艺相似，具体工艺为：在栅绝缘层106上形成第二掩膜层，对第二掩膜层曝光、显影形成与有源层107对应的图案，暴露非有源层区域，并采用刻蚀液对非有源层区域进行刻蚀形成有源层107，可以通过调整刻蚀液的浓度，管控刻蚀时间及刻蚀速率，防止出现残留或过刻蚀。
S6：形成源漏极109，在有源层107上形成源漏极材料层108，通过构图工艺形成包含源漏极109的图案。
在有源层107上沉积源漏极材料层108，源漏极材料层108可以是本领域常用的金属材料或金属合金材料，如Cu、Al、Au、Ag等高导电材料，也可以是本公开中的金属配线层，可选地采用本公开中的金属配线层形成源漏极材料层，即源漏极材料层108包含第二氧化钼衬底层和 第二金属层，其中第二氧化钼衬底层可以进一步降低Cu、Al等金属走线的反射率，进而提高阵列基板100和显示装置的性能。
形成源漏极109的构图工艺与形成栅极105的构图工艺相似，具体可以是在源漏极材料层108上形成第三掩膜层，对第三掩膜层曝光、显影形成与源漏极109对应的图案，暴露沟道区，然后采用刻蚀液对源漏极材料层进行刻蚀形成源漏极109及沟道。可以通过调整刻蚀液的浓度，管控刻蚀时间及刻蚀速率，防止出现残留或过刻蚀，影响阵列基板100的性能。
进一步的，刻蚀形成薄膜晶体管后，在源漏极109及栅绝缘层106上形成平坦化绝缘层110，接着在平坦化绝缘层110上形成第四掩膜层并刻蚀形成像素过孔，然后向像素过孔中填充透明导电材料，通过在透明导电材料层上形成第四掩膜层并刻蚀形成像素电极111，所述透明导电材料可以是透明金属或透明金属氧化物，可选采用透明金属氧化物，如FTO、ZTO、ITO等。
在本示例实施方式中，可以在形成金属配线层102之前(如图8)或形成栅极105之后(如图9)，在位于显示区AA中的衬底基板101上沉积一透明导电层，通过在透明导电层上形成掩膜层并刻蚀透明导电层形成像素区的公共电极112。
在本公开的示例性实施例中，阵列基板100的制造方法还包括形成走线图案：在金属配线层上通过构图工艺形成走线图案，走线图案可以是栅线图案、数据线图案或信号线图案等。
本示例性实施例中还提供了一种显示装置，如图10所示，显示装置1000包括显示面板1001。显示面板1001为本公开中的显示面板，所述显示装置1000可以是电子纸、OLED显示器、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等具有显示功能的产品或部件。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限。

Claims (16)

  1. 一种阵列基板，包括：
    衬底基板；以及
    金属配线层，位于所述衬底基板上；
    其中，所述金属配线层包括第一氧化钼衬底层以及位于所述第一氧化钼衬底层远离所述衬底基板的表面上的第一金属层。
  2. 根据权利要求1所述的阵列基板，其中，所述第一氧化钼衬底层为采用物理气相沉积法直接成膜的衬底层。
  3. 根据权利要求1或2所述的阵列基板，其中，所述阵列基板还包括设置在所述衬底基板上的薄膜晶体管，所述金属配线层包括所述薄膜晶体管的栅极。
  4. 根据权利要求3所述的阵列基板，其中，所述薄膜晶体管的源漏极包括第二氧化钼衬底层和第二金属层。
  5. 根据权利要求1至4中任一项所述的阵列基板，其中，所述阵列基板还包括走线图案，所述金属配线层包括所述走线图案。
  6. 根据权利要求1至5中任一项所述的阵列基板，其中，所述第一氧化钼衬底层的厚度不低于
    Figure PCTCN2018106546-appb-100001
  7. 根据权利要求1-6任一项所述的阵列基板，其中，所述第一金属层的材质为铜或铝。
  8. 根据权利要求1-7任一项所述的阵列基板，其中，所述衬底基板为玻璃基板。
  9. 一种阵列基板的制造方法，包括：
    在衬底基板上形成第一氧化钼衬底层；
    在所述第一氧化钼衬底层远离所述衬底基板的表面上形成第一金属层；
    其中，所述第一氧化钼衬底层和所述第一金属层形成金属配线层。
  10. 根据权利要求9所述的阵列基板的制造方法，其中，所述阵列基板的制造方法还包括：在所述衬底基板上形成薄膜晶体管。
  11. 根据权利要求10所述的阵列基板的制造方法，其中，在所述衬底基板上形成薄膜晶体管，包括：
    形成包括所述薄膜晶体管栅极的图案：对金属配线层通过构图工艺形成包括所述薄膜晶体管栅极的图案；
    形成栅绝缘层：在所述栅极上形成栅绝缘层；
    形成有源层：在所述栅绝缘层上形成有源层薄膜，通过构图工艺形成包含有源层的图案；
    形成源漏极：在所述有源层上形成源漏极材料层，通过构图工艺形成包含源漏极的图案。
  12. 根据权利要求11所述的阵列基板的制造方法，其中，形成源漏极，包括：在所述有源层上形成第二氧化钼衬底层；在所述第二氧化钼成底层上形成第二金属层；通过构图工艺形成包含源漏极的图案。
  13. 根据权力要求9-12任一项所述的所述的阵列基板的制造方法，其中，所述阵列基板的制造方法还包括，形成走线图案：在所述金属配线层上通过构图工艺形成走线图案。
  14. 根据权利要求9-13任一项所述的阵列基板的制造方法，其中，所述第一氧化钼衬底层采用物理气相沉积法直接成膜，沉积参数为：氩气流量10～3000sccm，气压0.1-2Pa，功率0.5-80kw，沉积速率
    Figure PCTCN2018106546-appb-100002
  15. 根据权利要求14所述的阵列基板的制造方法，其中，所述第一氧化钼衬底层的厚度不低于
    Figure PCTCN2018106546-appb-100003
  16. 一种显示装置，其中，包括如权利要求1-8任一项所述的阵列基板。
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CN110767660B (zh) * 2018-07-24 2022-09-16 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板
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CN111081766A (zh) * 2019-12-13 2020-04-28 Tcl华星光电技术有限公司 显示面板及其制备方法
CN114762118A (zh) * 2020-10-29 2022-07-15 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板和显示装置
CN114921750B (zh) * 2022-05-07 2024-03-22 枣庄睿诺电子科技有限公司 一种高附着力光电薄膜及其制备方法和应用

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