CN108155196A - 一种阵列基板及其制备方法 - Google Patents

一种阵列基板及其制备方法 Download PDF

Info

Publication number
CN108155196A
CN108155196A CN201711461754.7A CN201711461754A CN108155196A CN 108155196 A CN108155196 A CN 108155196A CN 201711461754 A CN201711461754 A CN 201711461754A CN 108155196 A CN108155196 A CN 108155196A
Authority
CN
China
Prior art keywords
layer
flatness
passivation layer
contact hole
hole wall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201711461754.7A
Other languages
English (en)
Other versions
CN108155196B (zh
Inventor
袁文豪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to CN201711461754.7A priority Critical patent/CN108155196B/zh
Priority to US15/749,473 priority patent/US10797083B2/en
Priority to PCT/CN2018/071381 priority patent/WO2019127636A1/zh
Publication of CN108155196A publication Critical patent/CN108155196A/zh
Application granted granted Critical
Publication of CN108155196B publication Critical patent/CN108155196B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本发明提供一种阵列基板及其制备方法，其中，阵列基板包括：衬底基板；形成在衬底基板上的金属层；形成在衬底基板和金属层上的钝化层；形成在钝化层上的平坦层；通过对金属层上的平坦层和钝化层进行刻蚀形成的接触孔，金属层至少部分地暴露于接触孔，接触孔在钝化层处的孔壁与在平坦层处的孔壁处于同一平面或者形成一钝角；形成在平坦层以及接触孔处的连续的像素电极层，所述像素电极层与金属层相连接。本发明通过对金属层上的平坦层和钝化层进行两步刻蚀，使接触孔在钝化层处的孔壁与在平坦层处的孔壁处于同一平面或者形成一钝角，解决了现有技术中因出现底切导致像素电极层断裂的问题。

Description

一种阵列基板及其制备方法
技术领域
本发明涉及屏幕显示技术领域，尤其涉及一种阵列基板及其制备方法。
背景技术
随着LCD面板阵列基板（Array）段的制程中，越来越多应用COA（彩膜层集成到阵列基板，Color filter on Array）、POA（光阻间隔物集成到阵列基板，Photo spacer onArray）等新技术，需要引入PFA（polymer film on array）工艺来制备平坦层，优化膜层表面平坦度。
请参照图1所示，通常的阵列基板制作过程是：首先在衬底基板1´上沉积形成金属层11´，然后在衬底基板1´和金属层11´上形成钝化层12´，再在钝化层12´上形成平坦层13´，对平坦层13´和钝化层12´进行刻蚀形成接触孔15´。钝化层12´通常由SiNx等材料制成，由于平坦层13´和钝化层12´的刻蚀速度不相同，一般来说平坦层13´的刻蚀速度较钝化层12´慢，而且通过PFA工艺形成的平坦层13´在刻蚀后会保留在衬底基板1´上，使得刻蚀后平坦层13´的边缘比钝化层12´的边缘更突出，接触孔15´的孔壁不连续，最终形成底切（undercut）10´。
接下来沉积像素电极层14´时，请在参照图2所示，由于平坦层13´的边缘与钝化层12´的边缘之间形成有底切10´，导致该处的像素电极层14´容易发生断裂。
发明内容
本发明所要解决的技术问题在于，提供一种阵列基板及其制备方法，以避免沉积的像素电极层发生断裂。
为了解决上述技术问题，本发明提供一种阵列基板，包括：
衬底基板；
形成在所述衬底基板上的金属层；
形成在所述衬底基板和所述金属层上的钝化层；
形成在所述钝化层上的平坦层；
通过对所述金属层上的平坦层和所述钝化层进行刻蚀形成的接触孔，所述金属层至少部分地暴露于所述接触孔，所述接触孔在所述钝化层处的孔壁与在所述平坦层处的孔壁处于同一平面或者形成一钝角；
形成在所述平坦层以及所述接触孔处的连续的像素电极层，所述像素电极层与所述金属层相接触。
其中，所述接触孔在所述钝化层处的孔壁形成一台阶，包括平行于所述衬底基板的第一孔壁，以及自所述第一孔壁朝向所述金属层倾斜并与其相接的第二孔壁，所述第一孔壁与所述接触孔在所述平坦层处的孔壁形成一钝角。
其中，所述钝化层材质为SiNx、SiOx、SiOxNy中的任一种。
本发明还提供一种阵列基板的制备方法，包括：
提供一衬底基板；
在所述衬底基板上依次形成金属层、钝化层和平坦层；
对所述金属层上的平坦层和钝化层分两步进行刻蚀形成接触孔，使所述金属层至少部分地暴露于所述接触孔，所述接触孔在所述钝化层处的孔壁与在所述平坦层处的孔壁处于同一平面或者形成一钝角；
在所述平坦层及所述接触孔处形成连续的像素电极层，所述像素电极层与所述金属层相接触。
其中，对所述金属层上的平坦层和钝化层进行的两步刻蚀中，第一步刻蚀中平坦层和钝化层的刻蚀速率选择比小于第二步刻蚀中平坦层和钝化层的刻蚀速率选择比。
其中，第一步刻蚀中平坦层与钝化层的刻蚀速率选择比的取值范围为[0.8, 1]，第二步刻蚀中平坦层与钝化层的刻蚀速率选择比的取值范围为[1.8, 2]。
其中，通过所述两步刻蚀，刻蚀掉的平坦层厚度与刻蚀掉的钝化层厚度之比为1.2~1.5。
其中，对所述金属层上的平坦层和钝化层进行的两步刻蚀中，进一步包括：根据平坦层材质或钝化层膜质相应调整第一步或第二步的刻蚀时间。
其中，如果所述钝化层选用更致密的膜质，则增加第一步的刻蚀时间；如果平坦层选用刻蚀速率更快的材质，则减少第二步的刻蚀时间。
其中，如果所述钝化层选用更疏松的膜质，则减少第一步的刻蚀时间；如果平坦层选用刻蚀速率更慢的材质，则增加第二步的刻蚀时间。
本发明实施例的有益效果在于：通过对金属层上的平坦层和钝化层进行两步刻蚀，使接触孔在钝化层处的孔壁与在平坦层处的孔壁形成一钝角，解决现有技术中因出现底切导致像素电极层断裂的问题；并且在保证接触孔处的钝化层刻蚀干净的基础上，刻蚀掉相对较少的平坦层，避免RGB色阻与液晶接触造成污染；此外，还可以通过对两步刻蚀时间的微调来应对不同钝化层膜质和平坦层材质的搭配。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有阵列基板的结构示意图。
图2是现有阵列基板的另一结构示意图。
图3是本发明实施例一一种阵列基板的结构示意图。
图4是本发明实施例一一种阵列基板的另一结构示意图。
图5是本发明实施例一一种阵列基板的又一结构示意图。
图6是本发明实施例一一种阵列基板的又一结构示意图。
图7是本发明实施例一一种阵列基板的再一结构示意图。
图8是本发明实施例二一种阵列基板的制备方法的流程示意图。
具体实施方式
以下各实施例的说明是参考附图，用以示例本发明可以用以实施的特定实施例。
请同时参照图3至图7所示，本发明实施例一提供一种阵列基板，包括：
衬底基板1；
形成在所述衬底基板1上的金属层11；
形成在所述衬底基板1和所述金属层11上的钝化层12；
形成在所述钝化层12上的平坦层13；
通过对所述金属层11上的平坦层13和所述钝化层12进行刻蚀形成的接触孔15，所述金属层11至少部分地暴露于所述接触孔15，所述接触孔15在所述钝化层12处的孔壁120与在所述平坦层13处的孔壁130处于同一平面或者形成一钝角θ；
形成在所述平坦层13以及所述接触孔15处的连续的像素电极层14，所述像素电极层14与所述金属层11相连接。
具体地，本实施例在对金属层11上的平坦层13和钝化层12进行刻蚀时，采取分步刻蚀的方式：第一步刻蚀较多的钝化层12和较少的平坦层13；第二步刻蚀剩余的钝化层12和较多的平坦层13，由此使得形成的接触孔15在平坦层13处的孔壁130不会突出于在钝化层12处的孔壁120，平坦层13处的孔壁130前端不会悬空而造成底切，而是与钝化层12处的孔壁120处于同一平面或者形成一个钝角θ。之后在平坦层13上以及沿着接触孔15连续的孔壁沉积像素电极层14，没有现有技术中出现的底切，因而不会发生断裂。可以理解的是，本实施例中平坦层13由有机材料通过PFA工艺形成，例如可以是一种有机绝缘膜。
图3所示为接触孔15在钝化层12处的孔壁120与在平坦层13处的孔壁130处于同一平面的结构示意图，即接触孔15在钝化层12处的孔壁120与在平坦层13处的孔壁130形成的夹角θ为180˚，图4为相应地在平坦层13上以及接触孔15沉积形成像素电极层14的结构示意图，由于平坦层13处的孔壁与钝化层12处的孔壁120处于同一平面，平坦层13处的130前端不会悬空而造成底切，因此沉积像素电极层14时不会发生断裂。
图5所示为接触孔15在钝化层12处的孔壁120与在平坦层13处的孔壁130形成一钝角的结构示意图。与图3所示的结构结合起来可知，接触孔15在钝化层12处的孔壁120与在平坦层13处的孔壁130形成的夹角的取值范围是（90˚, 180˚]。图6为相应地在平坦层13上以及接触孔15沉积形成像素电极层14的结构示意图，由于平坦层13处的孔壁与钝化层12处的孔壁120形成一钝角，平坦层13处的130前端不会悬空而造成底切，因此沉积像素电极层14时不会发生断裂。
再请参照图7所示，本实施例还提供另一种钝化层12处孔壁的结构，即接触孔15在钝化层处12的孔壁形成一台阶，包括平行于衬底基板1的第一孔壁120，以及自第一孔壁120朝向金属层11倾斜并与其相接的第二孔壁121，第一孔壁120与接触孔15在平坦层13处的孔壁130形成一钝角θ。考虑到形成钝化层12和平坦层13的材质均匀性，以及面板内各点位刻蚀状况可能存有差异，上述在钝化层12处形成台阶的结构，能够保证有足够的制程窗口。
本实施例中，钝化层12材质为SiNx、SiOx、SiOxNy中的任一种。
请再参照图8所示，相应于本发明实施例一，本发明实施例二提供一种阵列基板的制备方法，包括：
提供一衬底基板；
在所述衬底基板上依次形成金属层、钝化层和平坦层；
对所述金属层上的平坦层和钝化层分两步进行刻蚀形成接触孔，使所述金属层至少部分地暴露于所述接触孔，所述接触孔在所述钝化层处的孔壁与在所述平坦层处的孔壁处于同一平面或者形成一钝角；
在所述平坦层及所述接触孔处形成连续的像素电极层，所述像素电极层与所述金属层相连接。
具体地，本实施例对金属层上的平坦层和钝化层进行刻蚀分成两步进行，其中第一步中平坦层和钝化层的刻蚀速率选择比小于第二步中平坦层和钝化层的刻蚀速率选择比，即：第一步刻蚀较多的钝化层和较少的平坦层，第二步刻蚀剩余的钝化层和较多的平坦层，由此使得形成的接触孔在平坦层13处的孔壁130不会突出于在钝化层12处的孔壁120，平坦层13处的孔壁130前端不会悬空而造成底切，而是与钝化层12处的孔壁120处于同一平面或者形成一个钝角θ（如图3所示）。之后在平坦层13上以及沿着接触孔15连续的孔壁沉积像素电极层14时，由于没有现有技术中出现的底切，因而不会发生断裂。
需要说明的是，如果为避免出现前述底切而采用一步刻蚀，则需加快平坦层的刻蚀，减慢钝化层的刻蚀；这样为保证钝化层刻蚀干净，必然要增加时间，影响了产能；另一方面，加快平坦层的刻蚀，即增大平坦层的刻蚀速率，必然将降低平坦层最终的剩余量，当平坦层剩余量不足时，容易出现RGB色阻与液晶接触造成污染的情况，影响产品品质。因此，本发明实施例采用两步刻蚀，并且第一步中平坦层和钝化层的刻蚀速率选择比小于第二步中平坦层和钝化层的刻蚀速率选择比，在保证钝化层刻蚀干净的基础上，解决了平坦层剩余量和底切之间的矛盾。
本实施例中，钝化层12材质为SiNx、SiOx、SiOxNy中的任一种。此外，本发明实施例不对金属层11做限制，其可以通过图案化后形成源极或漏极，在接触孔15处与像素电极连接。
进一步地，第一步刻蚀中，平坦层与钝化层的刻蚀速率选择比的取值范围为[0.8,1]，以平坦层为有机绝缘膜、钝化层为SiNx为例，即有机绝缘膜:SiNx=0.8~1，刻蚀大部分SiNx，少部分有机绝缘膜；第二步刻蚀中，平坦层与钝化层的刻蚀速率选择比的取值范围为[1.8, 2]，即有机绝缘膜:SiNx=1.8~2，刻蚀剩余的SiNx并刻蚀大部分有机绝缘膜，保证由此形成的接触孔15在平坦层13处的孔壁130不会突出于在钝化层12处的孔壁120，平坦层13处的孔壁130前端不会因悬空而造成底切。可以理解地，本实施例中，刻蚀速率是指单位时间内刻蚀的膜层厚度，例如，平坦层的刻蚀速率是800A/min，表示每分钟刻蚀平坦层的厚度为800埃；钝化层的刻蚀速率是1000A/min，表示每分钟刻蚀钝化层的厚度为1000埃。平坦层与钝化层的刻蚀速率选择比即平坦层的刻蚀速率与钝化层的刻蚀速率的比例。通过控制每一步的刻蚀时间，按照上述刻蚀速率选择比，使刻蚀掉的平坦层厚度与刻蚀掉的钝化层厚度之比控制在1.2~1.5。
再进一步地，本实施例可以通过刻蚀时间的微调来应对不同钝化层膜质和平坦层材质的搭配。膜质会影响刻蚀速率，比如当SiNx膜质变得致密，会使得其刻蚀速率变慢，如前所述，在第一步刻蚀中，SiNx刻蚀速率相对较快，为此可以适当增加第一步的刻蚀时间来刻蚀较多的SiNx，保证刻蚀效果。又比如平坦层更换了材质，导致其刻蚀速率变快，同样如前所述，在第二步刻蚀中，平坦层刻蚀速率相对较快，为此可以适当减少第二步的刻蚀时间来避免刻蚀过多的平坦层，保证刻蚀效果。同样地，如果钝化层选用更疏松的膜质，则减少第一步的刻蚀时间；如果平坦层选用刻蚀速率更慢的材质，则增加第二步的刻蚀时间。
通过上述说明可知，本发明实施例的有益效果在于：通过对金属层上的平坦层和钝化层进行两步刻蚀，使接触孔在钝化层处的孔壁与在平坦层处的孔壁形成一钝角，解决现有技术中因出现底切导致像素电极层断裂的问题；并且在保证接触孔处的钝化层刻蚀干净的基础上，刻蚀掉相对较少的平坦层，避免RGB色阻与液晶接触造成污染；此外，还可以通过对两步刻蚀时间的微调来应对不同钝化层膜质和平坦层材质的搭配。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (10)

1.一种阵列基板，其特征在于，包括：
衬底基板；
形成在所述衬底基板上的金属层；
形成在所述衬底基板和所述金属层上的钝化层；
形成在所述钝化层上的平坦层；
通过对所述金属层上的平坦层和所述钝化层进行刻蚀形成的接触孔，使所述金属层至少部分地暴露于所述接触孔，所述接触孔在所述钝化层处的孔壁与在所述平坦层处的孔壁处于同一平面或者形成一钝角；
形成在所述平坦层以及所述接触孔处的连续的像素电极层，所述像素电极层与所述金属层相连接。
2.根据权利要求1所述的阵列基板，其特征在于，所述接触孔在所述钝化层处的孔壁形成一台阶，包括平行于所述衬底基板的第一孔壁，以及自所述第一孔壁朝向所述金属层倾斜并与其相接的第二孔壁，所述第一孔壁与所述接触孔在所述平坦层处的孔壁形成一钝角。
3.根据权利要求1所述的阵列基板，其特征在于，所述钝化层材质为SiNx、SiOx、SiOxNy中的任一种。
4.一种阵列基板的制备方法，其特征在于，包括：
提供一衬底基板；
在所述衬底基板上依次形成金属层、钝化层和平坦层；
对所述金属层上的平坦层和钝化层分两步进行刻蚀形成接触孔，使所述金属层至少部分地暴露于所述接触孔，所述接触孔在所述钝化层处的孔壁与在所述平坦层处的孔壁处于同一平面或者形成一钝角；
在所述平坦层及所述接触孔处形成连续的像素电极层，所述像素电极层与所述金属层相连接。
5.根据权利要求4所述的制备方法，其特征在于，对所述金属层上的平坦层和钝化层进行的两步刻蚀中，第一步刻蚀中平坦层和钝化层的刻蚀速率选择比小于第二步刻蚀中平坦层和钝化层的刻蚀速率选择比。
6.根据权利要求5所述的制备方法，其特征在于，第一步刻蚀中平坦层与钝化层的刻蚀速率选择比的取值范围为[0.8, 1]，第二步刻蚀中平坦层与钝化层的刻蚀速率选择比的取值范围为[1.8, 2]。
7.根据权利要求5所述的制备方法，其特征在于，通过所述两步刻蚀，刻蚀掉的平坦层厚度与刻蚀掉的钝化层厚度之比为1.2~1.5。
8.根据权利要求5所述的制备方法，其特征在于，对所述金属层上的平坦层和钝化层进行的两步刻蚀中，进一步包括：根据平坦层材质或钝化层膜质相应调整第一步或第二步的刻蚀时间。
9.根据权利要求8所述的制备方法，其特征在于，如果所述钝化层选用更致密的膜质，则增加第一步的刻蚀时间；如果平坦层选用刻蚀速率更快的材质，则减少第二步的刻蚀时间。
10.根据权利要求8所述的制备方法，其特征在于，如果所述钝化层选用更疏松的膜质，则减少第一步的刻蚀时间；如果平坦层选用刻蚀速率更慢的材质，则增加第二步的刻蚀时间。
CN201711461754.7A 2017-12-28 2017-12-28 一种阵列基板及其制备方法 Active CN108155196B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201711461754.7A CN108155196B (zh) 2017-12-28 2017-12-28 一种阵列基板及其制备方法
US15/749,473 US10797083B2 (en) 2017-12-28 2018-01-04 Array substrate with contact hole having hole walls forming an obtuse angle
PCT/CN2018/071381 WO2019127636A1 (zh) 2017-12-28 2018-01-04 一种阵列基板及其制备方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201711461754.7A CN108155196B (zh) 2017-12-28 2017-12-28 一种阵列基板及其制备方法

Publications (2)

Publication Number Publication Date
CN108155196A true CN108155196A (zh) 2018-06-12
CN108155196B CN108155196B (zh) 2020-11-03

Family

ID=62462429

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711461754.7A Active CN108155196B (zh) 2017-12-28 2017-12-28 一种阵列基板及其制备方法

Country Status (3)

Country Link
US (1) US10797083B2 (zh)
CN (1) CN108155196B (zh)
WO (1) WO2019127636A1 (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109991787A (zh) * 2019-03-15 2019-07-09 惠科股份有限公司 一种阵列基板及其制作方法
CN110098200A (zh) * 2019-01-17 2019-08-06 友达光电股份有限公司 像素结构及其制造方法
CN110827667A (zh) * 2019-10-30 2020-02-21 深圳市华星光电半导体显示技术有限公司 一种显示面板及显示装置
WO2020215372A1 (zh) * 2019-04-22 2020-10-29 武汉华星光电技术有限公司 阵列基板
CN112542502A (zh) * 2020-12-04 2021-03-23 武汉华星光电半导体显示技术有限公司 阵列基板及其制备方法、显示面板
CN113156734A (zh) * 2021-03-11 2021-07-23 昆山龙腾光电股份有限公司 辅助散射面板及其制作方法和显示装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111697011B (zh) * 2020-07-24 2022-09-23 厦门天马微电子有限公司 阵列基板及显示装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104299942A (zh) * 2014-09-12 2015-01-21 京东方科技集团股份有限公司 过孔制作方法、阵列基板制作方法及阵列基板、显示装置
CN105097668A (zh) * 2015-06-30 2015-11-25 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置
CN106653697A (zh) * 2017-01-03 2017-05-10 京东方科技集团股份有限公司 阵列基板及其制造方法和显示面板

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002182243A (ja) * 2000-12-15 2002-06-26 Nec Corp 液晶表示装置用トランジスタ基板及びその製造方法
KR100731745B1 (ko) * 2005-06-22 2007-06-22 삼성에스디아이 주식회사 유기전계발광표시장치 및 그 제조방법
KR100712295B1 (ko) * 2005-06-22 2007-04-27 삼성에스디아이 주식회사 유기 전계 발광 소자 및 그 제조 방법
TWI518915B (zh) * 2012-03-30 2016-01-21 群康科技(深圳)有限公司 陣列基板結構與顯示面板及其製造方法
CN105590896A (zh) * 2016-03-01 2016-05-18 深圳市华星光电技术有限公司 阵列基板的制作方法及制得的阵列基板
CN105931995B (zh) * 2016-04-29 2018-11-23 京东方科技集团股份有限公司 阵列基板及其制作方法
CN106684097A (zh) * 2017-01-03 2017-05-17 京东方科技集团股份有限公司 一种基板及其制作方法、显示面板

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104299942A (zh) * 2014-09-12 2015-01-21 京东方科技集团股份有限公司 过孔制作方法、阵列基板制作方法及阵列基板、显示装置
CN105097668A (zh) * 2015-06-30 2015-11-25 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置
CN106653697A (zh) * 2017-01-03 2017-05-10 京东方科技集团股份有限公司 阵列基板及其制造方法和显示面板

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110098200A (zh) * 2019-01-17 2019-08-06 友达光电股份有限公司 像素结构及其制造方法
CN109991787A (zh) * 2019-03-15 2019-07-09 惠科股份有限公司 一种阵列基板及其制作方法
WO2020215372A1 (zh) * 2019-04-22 2020-10-29 武汉华星光电技术有限公司 阵列基板
CN110827667A (zh) * 2019-10-30 2020-02-21 深圳市华星光电半导体显示技术有限公司 一种显示面板及显示装置
CN110827667B (zh) * 2019-10-30 2021-12-28 深圳市华星光电半导体显示技术有限公司 一种显示面板及显示装置
CN112542502A (zh) * 2020-12-04 2021-03-23 武汉华星光电半导体显示技术有限公司 阵列基板及其制备方法、显示面板
CN112542502B (zh) * 2020-12-04 2022-08-02 武汉华星光电半导体显示技术有限公司 阵列基板及其制备方法、显示面板
CN113156734A (zh) * 2021-03-11 2021-07-23 昆山龙腾光电股份有限公司 辅助散射面板及其制作方法和显示装置
CN113156734B (zh) * 2021-03-11 2022-07-01 昆山龙腾光电股份有限公司 辅助散射面板及其制作方法和显示装置

Also Published As

Publication number Publication date
CN108155196B (zh) 2020-11-03
US10797083B2 (en) 2020-10-06
US20200091191A1 (en) 2020-03-19
WO2019127636A1 (zh) 2019-07-04

Similar Documents

Publication Publication Date Title
CN108155196A (zh) 一种阵列基板及其制备方法
US20120086013A1 (en) Thin film transistor, array substrate and manufacturing method thereof
CN103972075A (zh) 一种刻蚀方法和阵列基板
CN103928400A (zh) 阵列基板及其制作方法、显示装置
CN105047722A (zh) 一种薄膜晶体管及其制作方法、阵列基板、显示面板
WO2017140083A1 (zh) 配向膜厚度均一性的优化方法及液晶显示面板
WO2014205983A1 (zh) 过孔制作方法、显示面板制作方法及显示面板
WO2019179339A1 (zh) 阵列基板及其制造方法、显示面板、显示装置
US9134559B2 (en) Method for preparing conducting film on ultra-thin glass substrate, LCD substrate, liquid crystal panel and LCD device
WO2016206203A1 (zh) 导电结构及其制作方法、阵列基板、显示装置
CN105446037B (zh) 显示基板及其制作方法、显示器件
CN105097502B (zh) 一种薄膜图案的形成方法
CN104538413A (zh) 阵列基板及其制作方法、显示装置
CN108172505B (zh) 掩模板及制备方法、膜层制备方法和封装结构
CN103412444A (zh) 一种阵列基板及其制作方法和显示面板
CN102683266B (zh) 显示装置接触孔形成方法
CN107085330B (zh) Psva像素结构
WO2020133827A1 (zh) 蓝相液晶面板的制作方法及其立体电极的制作方法
CN105280552A (zh) 一种阵列基板的制备方法、阵列基板和显示装置
US5246468A (en) Method of fabricating a lateral metal-insulator-metal device compatible with liquid crystal displays
US11682679B2 (en) Manufacturing method of display substrate for removing residual sand
CN107170751A (zh) 阵列基板及其制造方法、显示装置
CN207624734U (zh) 掩模板和封装结构
US10615194B2 (en) Array substrates, manufacturing methods thereof, and liquid crystal display (LCD) panels
US10355026B2 (en) Method for manufacturing metal wire and array substrate using the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant