WO2019112953A1 - Semiconductor apparatus having stacked gates and method of manufacture thereof - Google Patents

Semiconductor apparatus having stacked gates and method of manufacture thereof Download PDF

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Publication number
WO2019112953A1
WO2019112953A1 PCT/US2018/063618 US2018063618W WO2019112953A1 WO 2019112953 A1 WO2019112953 A1 WO 2019112953A1 US 2018063618 W US2018063618 W US 2018063618W WO 2019112953 A1 WO2019112953 A1 WO 2019112953A1
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WIPO (PCT)
Prior art keywords
gate
fet
gates
semiconductor apparatus
semiconductor
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PCT/US2018/063618
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English (en)
French (fr)
Inventor
Jeffrey Smith
Anton J. Devillers
Kandabara N. Tapily
Subhadeep KAL
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Tokyo Electron Ltd
Tokyo Electron US Holdings Inc
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Tokyo Electron Ltd
Tokyo Electron US Holdings Inc
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Priority to CN201880085260.XA priority Critical patent/CN111542923A/zh
Priority to KR1020207018472A priority patent/KR102596118B1/ko
Priority to JP2020530562A priority patent/JP7205045B2/ja
Publication of WO2019112953A1 publication Critical patent/WO2019112953A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
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    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
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    • H10D30/611—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
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    • H10D30/67—Thin-film transistors [TFT]
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    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
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    • H10D62/118—Nanostructure semiconductor bodies
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    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01318—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
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    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0179—Manufacturing their gate conductors the gate conductors having different shapes or dimensions
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    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes

Definitions

  • Semiconductor devices are widely used in various electronic apparatuses, such as smart phones, computers, and the like.
  • a typical semiconductor device includes a substrate having active devices such as transistors, capacitors, inductors and other components.
  • active devices such as transistors, capacitors, inductors and other components.
  • This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Nevertheless, such scaling down has also increased the complexity of processing and manufacturing of the semiconductor devices. As dimensions of semiconductor devices scale to smaller sub-micron sizes in advanced technology nodes, it becomes more challenging to increase the density of semiconductor devices. Improved structures and methods for manufacturing same are needed.
  • Aspects of the disclosure provide a semiconductor apparatus that comprises a first field-effect transistor (FET) formed on a substrate and comprising a first gate, a second FET stacked on the first FET along a direction substantially perpendicular to the substrate and comprising a second gate.
  • the semiconductor apparatus also comprises a first routing track and a second routing track electrically isolated from the first routing track.
  • Each of the first and second routing tracks is provided on a routing plane stacked on the second FET along said direction.
  • the semiconductor apparatus also comprises a first conductive trace configured to conductively couple the first gate of the first FET to the first routing track, and a second conductive trace configured to conductively couple the second gate of the second FET to the second routing track.
  • the second gate is stacked directly above the first gate along the direction substantially perpendicular to the substrate.
  • the first and second routing tracks are provided on above the second gate along the direction substantially perpendicular to the substrate.
  • the first conductive trace bypasses the second gate and the second
  • the semiconductor apparatus further comprises a third FET formed on the substrate and comprising a third gate, a fourth FET stacked on the third FET along the direction substantially perpendicular to the substrate and comprising a fourth gate.
  • the semiconductor apparatus also comprises a third conductive trace configured to conductively couple the third gate of the third FET to the second routing track, and a fourth conductive trace configured to conductively couple the fourth gate of the fourth FET to the first routing track.
  • the fourth gate can be stacked on the third gate along the direction. The third conductive trace can bypass the fourth gate and the fourth FET.
  • the second gate is stacked on the first gate and the fourth gate is stacked on the third gate.
  • the first and second tracks are provided on one or more routing planes above the first, second, third, and fourth gates along the direction.
  • the first and second conductive traces are spatially separated, and the first conductive trace bypasses the second gate and the second FET.
  • the second conductive trace bypasses the first gate and the first FET.
  • the third and fourth conductive traces are spatially separated, the third conductive trace bypasses the fourth gate and the fourth FET, and the fourth conductive trace bypasses the third gate and the third FET.
  • the first and fourth gates are conductively coupled to the first track via the first and fourth conductive traces, respectively, and the second and third gates are conductively coupled to the second track via the second and third conductive traces, respectively.
  • At least one of the first and the second gates may include a conductive material having an anisotropic etching property.
  • the first and the second FETs are complementary FETs including a n-type FET and a p-type FET.
  • a second gate area that is a gate area being a maximum cross- sectional area of the gate intersecting with a plane substantially perpendicular to the direction substantially perpendicular to the substrate, is equal to or larger than a first gate area, and a fourth gate area is equal to or larger than a third gate area, the second gate is staggered above the first gate, and the fourth gate is staggered above the third gate.
  • a second gate area is less than a first gate area
  • a fourth gate area is less than a third gate area
  • the second gate is staggered above the first gate
  • the fourth gate is staggered above the third gate.
  • the first FET further comprises a first set of semiconductor bars stacked along the direction in which the first gate surrounds and is attached to the first set of semiconductor bars, and wherein the second FET further comprises a second set of
  • semiconductor bars stacked along the direction in which the second gate surrounds and is attached to the second set of semiconductor bars.
  • the second set of semiconductor bars is stacked on the first set of semiconductors bars along the direction.
  • At least one of the first gate and the second gate includes a transition metal such as Ruthenium.
  • the first gate and the second gate are separated and conductively isolated by a dielectric layer including one or more dielectric materials.
  • At least one of the first gate and the second gate includes a first structure covering at least one of the first set and second set of semiconductor bars, a second structure covering the first structure, and a third structure covering the second structure.
  • the first structure includes a layer having high dielectric constant (high-k layer) and a barrier layer that prevents diffusion between the high-k layer and the second structure
  • the second structure includes a work-function layer that adjusts a work-function of the respective gate and a blocking layer that prevents diffusion between the work-function layer and the third structure
  • the third structure includes one or more conductive materials.
  • the high-k layer can be formed over the at least one of the first set and second set of semiconductor bars using a selective deposition process.
  • the barrier layer can be formed over the high-k layer using a selective deposition process.
  • the second structure can be formed over the first structure using a selective deposition process.
  • at least one of the selective deposition processes is a selective atomic layer deposition.
  • FIG. 1 A-1B show a cross sectional and a top view of an exemplary semiconductor apparatus 100 according to an embodiment of the disclosure
  • FIGs. 2A-2B show a cross sectional and a top view of an exemplary
  • FIGs. 3 A-3C show two cross sectional views and a top view of an exemplary semiconductor apparatus according to an embodiment of the disclosure
  • FIG. 4 shows a perspective view of an exemplary semiconductor apparatus according to an embodiment of the disclosure
  • FIGs. 5-21 show exemplary schematic views of various intermediary steps of a manufacturing process according to some embodiments of the disclosure.
  • Fig. 22 shows an exemplary process flow to form a semiconductor device according to an embodiment of the disclosure.
  • 3D Complementary FET devices can include three-dimensionally stacked cells (or standard cells, or logic standard cells) in which the complements n-channel FET, or nFET (such as n-channel metal-oxide-semiconductor FET or NMOSFET or NMOS) and p-channel FET or pFET (such as p-channel metal-oxide-semiconductor FET or PMOSFET or PMOS) are positioned overtop each other.
  • nFET such as n-channel metal-oxide-semiconductor FET or NMOSFET or NMOS
  • p-channel FET or pFET such as p-channel metal-oxide-semiconductor FET or PMOSFET or PMOS
  • 3D CFET designs herein provide area scaling and reduction in metallization.
  • NMOS is positioned in one area of a wafer while PMOS is positioned in a different area of the wafer.
  • 3D CFET logic standard cells herein the source and drain electrodes can be staggered or“stair-cased” as a mechanism that enables access to either lower or upper source and drain electrodes from a common routing line or routing track. Such configuration avoids the need for additional metallization that would be required in planar CFET devices to create nFET to pFET crossing. With designs herein, such nFET and pFET crossing is created internal within a device.
  • a routing track can be connected to both the upper source and drain electrode, or upper metal drain (MD) as well as the lower source and drain electrode, or lower metal drain (MD).
  • Technologies to stack or stair-case source and drain electrodes include a means to selectively deposit dielectric material such as SiO, SiOC, SiOCN, SiON, SiN, AlO, HfO, and SiC, and doped versions of each, onto common conductors used in the metallization of source and drain contacts which can include tungsten, copper, cobalt, and ruthenium.
  • Another technique includes a method to pattern a stair-case orientation of the bottom source and drain electrode with respect to the upper source and drain electrode which can optionally include the application of a reverse contact application.
  • Another technique is a method to create metal depositions with fine precision to final height of the metal.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • Extending CFET designs from relatively simple cells such as AOI cells to more complex cells such as flip-flops and latches show that staggering or stair-casing of the source- and-drain electrodes is a component of a larger solution to maintain efficient area scaling.
  • an AOI cell one technique is reducing the area of a cell to as few as the pitch of three routing tracks (3T), referred to as a cell height of 3T.
  • 3T three routing tracks
  • a more complex cell, such as a flip-flop techniques can reduce the number of routing tracks to a minimum. For example, a four routing track (4T) cell height is used in conjunction with buried power rails.
  • the source and drain electrodes can be staggered to enable both nFET and pFET connections up to a single routing track. Functioning of transistors can occur through a common gate for both NMOS and PMOS. This means that a single gate structure contains both gate-all-around NMOS and PMOS channels. Thus a single connection to the common gate is used.
  • example embodiments herein describe a 3D CFET integration method for more complex cell designs in which connections to a single routing line are used not only for staggered NMOS and PMOS source and drain electrodes, but also for staggered NMOS and PMOS gates as well.
  • the staggered or stair-cased NMOS and PMOS gates are referred to as split gates since there is a dielectric barrier (or dielectric separation layer) physically and electrically separating the NMOS and PMOS gates from one another.
  • connections of both individual NMOS and PMOS gates can be made to a common routing track.
  • Embodiments herein also show integration methods for fabrication of a split gate in an exemplary device.
  • the main challenge with having individual, staggered nFET and pFET gates within a 3D CFET device is that the channels are already formed when the gate structure including metallization is formed, which does not occur for the source and drain regions of a cell.
  • Forming staggered source and drain nFET and pFET electrodes benefits from the channel still being embedded within the gate low-k spacer (or the low-k gate spacer, or the low-k spacer) and not suspended within the opened contact region.
  • the source and drain can be formed from the embedded channel and then metalized. This flow can be sequential for both the lower source and drain electrode and also for the upper source and drain electrode.
  • Example embodiments herein focus on incorporating a 3D CFET device in which one or more of the nFET or pFET transistors are vertically stacked overtop one another in a 3D CFET design, the individual nFET and pFET gates are staggered or stair-cased with respect to one another such that access to either gate is possible by one or more routing tracks, for example, in the back-end-of-line (BEOL) metallization, and that the staggering or stair-casing of the individual nFET and pFET gates can be done to provide access to a common routing track in the BEOL.
  • BEOL back-end-of-line
  • a common gate can also be used in cell designs. Therefore, a combination of split gates and common gates can be used in designing a complex standard cell.
  • a common gate in this disclosure is referred to as a gate in which nFET and pFET transistors share a common gate structure so that a connection to the common gate turns both the nFET and pFET gates either on or off.
  • stacked gates can have independent connections, for example, to be connected to different electrical signals.
  • semiconductor devices such as transistors
  • a substrate plane such as a planar working surface of a substrate.
  • the semiconductor device can be formed on a plane parallel to the substrate plane, and a second semiconductor device can be formed on a different plane also parallel to the substrate plane in order to increase a number of semiconductor devices per unit area of the substrate plane.
  • the second semiconductor device can be stacked over the first semiconductor device along a first direction perpendicular to the substrate plane.
  • the first semiconductor device can be a first FET
  • the second semiconductor device can be a second FET.
  • a second gate of the second FET can be further stacked over and separated from a first gate of the first FET along the first direction.
  • a first via-to-gate connection, or conductive trace can be configured to couple the first gate to a first routing track
  • a second conductive trace can be configured to couple the second gate to a second routing track.
  • the first and second routing tracks conduct separate electric signals, and are located on a plane above the first and second gate along the first direction.
  • a routing track can be conductively coupled to multiple gates including gates of n-type FETs (nFETs) formed on a plane parallel to the substrate plane and gates of p-type FETs (pFETs) formed on another plane parallel to the substrate plane, alleviating routing congestions.
  • Figs. 1 A-1B show a cross sectional and a top view of an embodiment of a semiconductor apparatus 100 according to some embodiments.
  • the cross sectional view of the semiconductor apparatus 100 in Fig. 1 A is sectioned along AA’ in Fig. 1B.
  • the semiconductor apparatus 100 includes a stack of FETs having a first and a second FET.
  • the first FET is formed on a first plane Pl parallel to a substrate plane 105 of a substrate 101.
  • the second FET is formed on a second plane P2 parallel to the substrate plane 105. Further, the second FET is stacked over the first FET along a first direction 102 perpendicular to the substrate plane 105.
  • the first FET can include a first set of semiconductor bars and multiple terminals, such as a first source, a first drain, a first gate 112, and the like.
  • the first gate 112 can be formed over the first set of semiconductor bars.
  • the second FET can include a second set of
  • the semiconductor bars and multiple terminals such as a second source, a second drain, a second gate 122, and the like.
  • the second gate 122 can be formed over the second set of semiconductor bars.
  • a first channel can be formed based on the first set of semiconductor bars when the first FET is in operation.
  • a second channel can be formed based on the second set of semiconductor bars when the second FET is in operation. Therefore, the first set of
  • the first gate 112 is formed on the first plane Pl, and the second gate 122, stacked above and spatially separated from the first gate 112, is formed on the second plane P2.
  • the first gate 112 and the second gate 122 overlap, resulting in an overlapped area 191 (i.e., designated by cross-hatch) between the first gate 112 and the second gate 122, as seen in the top view of Fig 1B.
  • an overlapped area 191 i.e., designated by cross-hatch
  • a first conductive trace 113 can be configured to connect the first gate 112 to a first routing track 114, and a second conductive trace
  • the first and second routing tracks 114 and 124 are located above the first and second gate on a third plane P3 parallel to the substrate plane 105.
  • one or more portions of the first and second routing tracks 114 and 124 are substantially parallel to a first axis 104 shown in Fig. 1B.
  • the first axis 104 is parallel to the substrate plane 105.
  • the first gate 112 and the second gate 122 form split gates.
  • Split gates can refer to a stack of gates separated physically and electrically, and can be conductively connected to separate routing tracks via separate conductive traces.
  • a routing track can be located in any suitable locations of the semiconductor apparatus 100, such as a plane above (Fig. 1A) or a plane below the stack of FETs.
  • a routing track can have any suitable structure and materials.
  • a routing track can be conductively coupled to multiple terminals, such as gates, sources, drains, or the like of various FETs and semiconductor devices, or any suitable combination thereof.
  • additional routing tracks can be included in the semiconductor apparatus 100 to conduct additional electric signals.
  • four routing tracks can be used in a standard cell, such as a flip-flop.
  • multiple routing tracks can be conductively coupled to conduct the same electric signal.
  • the semiconductor apparatus 100 can include one or more power rails, such as a first and second power rail 13 l(l)-(2) to provide power supply to the semiconductor apparatus 100, such as to supply a positive voltage and a negative voltage to the semiconductor apparatus 100.
  • power rails can be located in a same plane where the routing tracks are positioned, such as the third plane P3.
  • power rails can be located in one or more planes different from where the routing tracks are, thus, the routing tracks can be stacked above or below power rails to reduce an area occupied by the semiconductor apparatus 100 and increase the number of semiconductor devices per unit area of the substrate plane 105.
  • the first and second power rail 13 l(l)-(2) are located beneath the third plane P3 and in the substrate plane 105.
  • the first and second power rail can, alternatively, be positioned at locations indicated by 132(l)-(2).
  • the first and second FET are CFETs having an nFET and a pFET.
  • the first FET is an nFET
  • the second FET is a pFET.
  • one or more FETs can be stacked above the second FET.
  • one or more gates can be stacked above the second gate 122. Each gate can be coupled to a different electric signal by using a different conductive trace configured to connect each gate to a different routing track.
  • the second gate 122 is sandwiched between the third plane P3 where the first routing track 114 is positioned and the first gate 112.
  • the first and second gate 112 and 122 can be staggered with respect to each other.
  • an exposed area 192 on the first gate 112 can be used to connect the first conductive trace 113 to the first gate 112, as seen in the top view of Fig. 1B.
  • the second conductive trace 123 can be positioned at any suitable locations on the second gate 122, and the first conductive trace 113 can be positioned at any suitable locations in the exposed area 192 on the first gate 112. In an example, locations of the first and second conductive traces 113 and 123 can be adjusted according to the locations of the routing tracks 114 and 124.
  • a second cross sectional area of the second gate 122 is set to be smaller than a first cross sectional area of the first gate 112, resulting in the first and second gate, 112 and 122, respectively, being staggered.
  • a cross sectional area of a gate is the largest cross sectional area when the gate is sliced with planes parallel to the substrate plane 105.
  • the second cross sectional area is equal to or larger than the first cross sectional area.
  • FIGs. 2A-2B show a cross sectional and a top view of an exemplary semiconductor apparatus 200 according to some embodiments.
  • the cross sectional view of the semiconductor apparatus 200 in Fig. 2A is sectioned along AA’ of Fig. 2B.
  • the semiconductor apparatus 200 includes a stack of FETs having a first and second FET, a first and a second conductive trace 213 and 223, a first and second routing track, 214 and 224, respectively, and one or more power rails, and the like.
  • the semiconductor apparatus 200 includes similar structure and components as those of the semiconductor apparatus 100 described in Figs. 1A-1B.
  • a component 2xx in Figs. 2A-2B is identical to a component lxx in Figs. 1 A-1B where xx is a number from 01 to 24, and thus, the description of the components in Figs. 2A-2B that are identical to those in Figs. 1 A-1B is omitted for purposes of clarity.
  • the second cross sectional area of the second gate 222 is set to be equal to or larger than that of the first gate 242. Therefore, the second gate 222 in Figs. 2A-2B is staggered with respect to the first gate 242 by shifting the second gate 222 with respect to the first gate 242 along one or more axes parallel to the substrate plane 205, such as along an axis 203 and 204, resulting in an exposed area 292 on the first gate 242.
  • the first gate 242 and the second gate 222 also overlap, resulting in an overlapped area 291 (i.e., designated by cross-hatch).
  • the first conductive trace 213 can be positioned above the exposed area 292 to conductively couple the first gate 242 to the first routing track 214 and to bypass the second gate 222.
  • the first gate 242 and the second gate 222 form split gates.
  • An upper gate such as the second gate 222, has the advantage of being able to connect to multiple routing tracks given a position of the upper gate overtop a bottom gate, such as the first gate 242.
  • the bottom gate can be staggered with respect to the upper gate so that the bottom gate can have connections to, for example, up to two different routing tracks.
  • the upper gate i.e., the second gate 222
  • the bottom gate i.e., the first gate 242
  • the first gate 242 can connect to the routing track 224 when the upper gate (i.e., the second gate 222) is positioned to the right of the first gate 242.
  • a routing track can be conductively coupled to multiple components of semiconductor devices formed on different planes parallel to the substrate plane.
  • the multiple components of semiconductor devices can include nFET source and drain, pFET source and drain, a merged nFET and pFET source and drain, a common gate, an nFET gate or a gate of nFET, a pFET gate or a gate of pFET, and the like.
  • gates of nFETs and pFETs can be formed in different planes parallel to the substrate plane, and share or access a same routing track, thus, alleviating the need for additional metallization, such as nFET to pFET crossing, and reducing routing congestion.
  • Fig. 3 A-3C show two cross sectional views and a top view of a semiconductor apparatus 300 according to some embodiments.
  • the cross sectional views of the semiconductor apparatus 300 in Fig. 3A and 3C are sectioned along AA’ and CC’ of Fig. 3B, respectively.
  • the semiconductor apparatus 300 includes two stacks of FETs, a first stack of FETs 398 including a first and second FET shown in Fig. 3 A and the top portion of Fig. 3B, and a second stack of FETs 399 including a third and fourth FET shown in Fig. 3C and the bottom portion of Fig. 3B.
  • the semiconductor apparatus 300 also includes a first, a second, a third, and a fourth conductive trace, 313,323, 353, and 363, respectively, a first and second routing track, 314 and 324, respectively, one or more power rails (not shown), and the like.
  • a first, a second, a third, and a fourth conductive trace 313,323, 353, and 363, respectively, a first and second routing track, 314 and 324, respectively, one or more power rails (not shown), and the like.
  • semiconductor apparatus 300 can be a part of a standard cell.
  • the first stack of FETs 398 in the semiconductor apparatus 300 includes the same structure and components as those of the stack of FETs in the semiconductor apparatus 200 shown in Figs. 2A-2B.
  • a component 3xx in Fig. 3A-3B is identical to a component 2xx in Figs. 2A-2B where xx is a number from 01 to 42 and from 91 to 92, and thus, the description of the components in the first stack of FETs 398 in Fig. 3 A is omitted for purposes of clarity.
  • the semiconductor apparatuses 300 further includes the second stack of FETs 399 where the third FET is formed on the first plane Pl, and the fourth FET is formed on the second plane P2. Further, the fourth FET is stacked above the third FET along the vertical direction 302.
  • the components of the third and fourth FETs are identical to those of the first and second FETs, and thus, the description of the components is omitted for purposes of clarity.
  • the fourth gate 362 is stacked above and spatially separated from the third gate 352.
  • the fourth cross sectional area of the fourth gate 362 can be the same as or larger than that of the third gate 352.
  • the fourth gate 362 is staggered with respect to the third gate 352 by shifting the fourth gate 362 along one or more axes parallel to the substrate plane 305, such as along an axis 303 and 304, resulting in an exposed area 394 on the third gate 352.
  • the third conductive trace 353 can be positioned above the exposed area 394 to conductively couple the third gate 352 to the second routing track 324 and to bypass the fourth gate 362.
  • the fourth conductive trace 363 is configured to conductively couple the fourth gate 362 to the first routing track 314.
  • the first gate 342 and the second gate 322 form split gates.
  • the third gate 352 and the fourth gate 362 form split gates.
  • multiple terminals such as the first and fourth gate
  • the multiple terminals sharing the same routing track can be formed in different planes parallel to the substrate plane 305, such as the first plane Pl and the second plane P2.
  • the multiple terminals sharing the same routing track can be from both nFETs and pFETs. As described above, accessing gates of nFETs and pFETs located in different planes from the same routing track can alleviate routing congestion.
  • additional routing tracks can be used to conduct more electrical signals.
  • two more routing tracks parallel to the routing tracks 314 and 324 can be positioned between the routing tracks 314 and 324 and above the overlapped areas 391 (i.e., designated by cross-hatch) and 393 (i.e., designated by cross-hatch).
  • Tipper gates formed in the second plane P2 such as the second gate 322 and the fourth gate 362 can access the two additional routing tracks and one of the routing tracks 314 and 324.
  • lower gates formed in the first plane Pl such as the first gate 342 and the third gate 352 cannot access the two additional routing tracks.
  • a lower gate such as the first gate 342 and the third gate 352 can access one of the routing tracks 314 and 324 depending on orientation of the lower gate with respect to the upper gate in respective split gates.
  • a routing track can be connected to bottom source and drain electrodes and upper source and drain electrodes.
  • the routing track can be connected to a bottom gate of a set of split gates, and an upper gate of another set of split gates. Additional bottom gates of split gates and additional upper gates of split gates can also be connected to the routing track. Further, the routing track can be connected to a common gate.
  • a complex standard cell design such as the flip flop, can use both common gates and split gates where nFET and pFET gates are stacked overtop one another, but with individual connections to respective routing tracks, including a common routing track.
  • Fig. 4 shows a perspective view of a semiconductor apparatus 400 according to an embodiment of the disclosure.
  • the semiconductor apparatus 400 includes two stacks of FETs separated by, for example, one or more dielectric materials located in trenches 1330 and 1720(3).
  • a first stack of FETs includes a first FET and a second FET.
  • the first stack of FETs can include the same structure and components as those of the stack of FETs in the semiconductor apparatus 100 shown in Fig. 1 A-1B.
  • the first FET includes a first gate 32 and a first set of semiconductor bars 22 or a first channel 22.
  • the second FET includes a second gate 34 and a second set of semiconductor bars 24 or a second channel 24.
  • the second gate 34 formed on a second plane is stacked above the first gate 32 formed on a first plane along a first direction 10.
  • the second gate 34 is physically separated from the first gate 32 using a dielectric separation layer 1410. Further, the first gate 32 and the second gate 34 are staggered with respect to each other.
  • the first gate 32 is conductively coupled to a routing track 2220(2) via a conductive trace 2230(2).
  • the second gate 34 is conductively coupled to a routing track 2220(4) via a conductive trace 2230(4).
  • the first gate 32 and the second gate 34 form split gates.
  • the second stack of FETs includes a third FET and a fourth FET.
  • the third FET includes a third gate 33 and a third set of semiconductor bars 23 or a third channel 23.
  • the fourth FET includes a fourth gate 35 and a fourth set of semiconductor bars 25 or a fourth channel 25.
  • the fourth gate 35 formed on the second plane is stacked above the third gate 33 formed on the first plane along the first direction 10.
  • the fourth gate 35 is physically separated from the third gate 33 using the dielectric separation layer 1410. Further, the third gate 33 and the fourth gate 35 are staggered with respect to each other.
  • the third gate 33 is conductively coupled to a routing track 2220(3) via a conductive trace 2230(3).
  • the fourth gate 35 is conductively coupled to a routing track 2220(5) via a conductive trace 2230(5).
  • the third gate 33 is conductively coupled to a routing track 2220(3) via a conductive trace 2230(3).
  • the fourth gate 35 is conductively coupled to a routing track 2220(5)
  • Gates formed on the first plane, such as the first gate 32 and the third gate 33, are referred to as lower gates, and gates formed on the second plane, such as the second gate 34 and the fourth gate 35, are referred to as upper gates.
  • FETs having the lower gates are referred to as lower FETs, and FETs having the upper gates are referred to as upper FETs.
  • the semiconductor apparatus 400 also includes power rails (or buried power rails) 13 covered with interconnect caps (or buried power rail caps) 14, substrate strips 11 isolated from the power rails 13 by shallow trench isolations (STIs) 12.
  • the substrate strips 11 can be a portion of a substrate (not shown) of the semiconductor apparatus 400.
  • the semiconductor apparatus 400 also includes a gate cap layer 1920 to isolate the upper gates 34 and 35 from other components of the semiconductor apparatus 400.
  • the routing tracks 2220 are formed in a dielectric layer 2030.
  • the first stack of FETs can be part of a first standard cell, such as a flip-flop including three routing tracks 2220(l)-(2) and 2220(4).
  • the second stack of FETs can be part of a second standard cell including three routing tracks 2220(3) and 2220(5)-(6).
  • the routing tracks 2220 are parallel to a second direction 11. Additional routing tracks (not shown) can be included in the first and the second standard cells.
  • the first to fourth gates 32, 34, 33, and35, respectively are located within a region 19(1). Additional gates can be located in regions l9(2)-(3), and share the routing tracks 2220.
  • the semiconductor apparatus 400 can include any suitable number of standard cells, and any suitable number of FETs and other components including power rails, routing tracks, and the like.
  • the regions l9(l)-(3) are separated by structures 18 including one or more dielectric materials.
  • the structures 18 can include source-and-drain contacts that are separated from the regions l9(l)-(3) through a low-k dielectric material.
  • a diffusion break 20 including one or more dielectric materials can also be included to separate, for example, adjacent standard cells. In an example, formation of the diffusion break 20 is described in US patent No. 9,721,793, which is incorporated herein by reference in its entirety. The
  • semiconductor apparatus 400 can include any suitable number of the regions l9(l)-(3) separated by any suitable number of the structures 18 and the diffusion breaks 20. Addition split gates are located within the region 19(2). In addition to split gates, the semiconductor apparatus 400 can also include a stack of FETs sharing a common gate.
  • the common gate refers to gates of a stack of FETs physically connected and conductively coupled to form a common gate structure, thus, any connection to the common gate structure can turn the gates either on or off. Referring to Fig. 4, common gates are located within the regions 19(3).
  • a third stack of FETs including a fifth gate (a lower gate) formed on the first plane and a sixth gate (an upper gate) formed on the second plane, similar to the second stack of FETs is located within the region 19(2).
  • the fifth gate is connected to the routing track 2220(4), and the sixth gate is connected to the routing track 2220(2).
  • the upper FETs are p-type and the lower FETs are n- type, and thus, the routing track 2220(2) can be connected to both nFETs and pFETs, alleviating the routing congestion.
  • the substrate can be any suitable semiconductor material, such as silicon (Si), silicon carbide (SiC), sapphire, germanium(Ge), gallium arsenide (GaAs), silicon germanium (SiGe), indium phosphide (InP), diamond, and the like.
  • the substrate can be doped with an n- type and a p-type impurity.
  • the substrate can include various layers, such as conductive or insulating layers formed on a semiconductor substrate, a silicon-on-insulator (SOI) structure, and the like.
  • SOI silicon-on-insulator
  • the substrate can also be strained.
  • the power rails 13 can provide suitable power supplies, such as positive and negative power supplies, to the semiconductor apparatus 400.
  • the power rails 13 can be formed by any suitable one or more conductive materials, such as ruthenium (Ru), copper (Cu), and the like.
  • the power rails 13 can be formed using any suitable structure, such as disclosed in ETS patent application 15/875,442, filed on January 19, 2018 which is incorporated herein by reference in its entirety.
  • the power rails 13 can be formed in any suitable plane, such as that shown in Fig. 4, or formed on the same level as the routing tracks 2220, or the like.
  • the interconnect caps 14 can isolate the power rails 13 from FETs and the like.
  • the interconnect caps 14 can include one or more dielectric materials fabricated in any suitable structures.
  • the interconnect caps 14 can include materials such as SiO, SiCO, SiCN, SiC, SiN, and the like.
  • the STIs 12 can prevent electric current leakage, for example, between the power rails 13 and the substrate strips 11.
  • the STI 12 can be fabricated using any suitable one or more dielectric materials and any suitable structure.
  • the STIs can include Si0 2 , silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low-k dielectric, other suitable materials, or combinations thereof, and/or other suitable material know in the art.
  • FSG fluorine-doped silicate glass
  • PSG phosphosilicate glass
  • BPSG borophosphosilicate glass
  • the second stack of FETs and other FETs having split gates are similar to the first stack of FETs in terms of the structure and materials.
  • the first FET includes a first source, a first drain, the first channel 22, and the first gate 32.
  • the second FET includes a second source, a second drain, the second channel 24, and the second gate 34.
  • the first and second sources and the first and second drains can have any suitable semiconductor material or combination of semiconductor materials, such as Si, AlGaAs, Ge, GaAs, GaAsP, SiGe, InP, and the like.
  • the second source and drain can be positioned over the first source and drain, such as disclosed in ETS patent application 15/654,327, filed on July 19, 2017 which is incorporated herein by reference in its entirety.
  • the first channel 22 can include any suitable structure and material systems to provide a semiconductor channel when the first FET is in operation.
  • the second channel 24 can include any suitable structure and material systems to provide a semiconductor channel when the second FET is in operation.
  • the first channel 22 and the second channel 24 can have any suitable semiconductor material, including an elementary semiconductor such as silicon, germanium, or the like, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or the like, an alloy semiconductor such as silicon germanium, or a combination thereof.
  • the first and second channels 22 and 24 include different semiconductor materials.
  • the first channel 22 and the second channel 24 can include any suitable structure, such as one or more semiconductor bars.
  • a semiconductor bar can be a nanowire, a nanosheet, any other suitable shape, or the like.
  • the first and second channel 22 and 24 can be physically separated. Referring to Fig. 5, which illustrates an example structure, three nanosheets are stacked along the first direction 10 to form the first channel 22 or the second channel 24. Further, the second channel 24 is stacked over and physically separated from the first channel 22 along the first direction 10.
  • the first channel 22 includes Si
  • the second channel 24 includes SiGe.
  • the first FET can be a pFET having a p-channel
  • the second FET can be a nFET having a n-channel.
  • the first FET can be a nFET having a n-channel
  • the second FET can be a pFET having a p-channel.
  • the first channel 22 as a n-channel in a nFET and the second channel 24 as a p-channel in a pFET in operation are used as an example, the disclosure can be suitably modified to apply to, for example, the first channel 22 as a p-channel in a pFET and the second channel 24 as a n-channel in a nFET in operation.
  • the first gate 32 can be formed over the first channel 22.
  • the second gate 34 can be formed over the second channel 34.
  • the first and second gate 32 and 34 can include any suitable semiconductor gate structures and material systems used for a nFET and a pFET, respectively.
  • the first gate 32 can cover the first channel 22 and the second gate 34 can cover the second channel 24 in any suitable configuration, such as that used in Fin FET (FinFET), Gate All Around (GAA), tri-gate, Pi-gate, and the like.
  • the gate materials can surround the channel on all sides in the GAA configuration.
  • the first gate 32 includes a first structure 612, a second structure 812, and a third structure 1312.
  • the first structure 612 can include a high-dielectric (high-k) layer (or high-k film or high-k films) as a gate insulator over the first channel 22 and a barrier layer over the high-k layer.
  • the high-k layer can include any suitable dielectric material having a high dielectric constant, such as hafnium oxide (HfO).
  • the barrier layer can be any suitable dielectric material, such as TiN, preventing diffusion between the high-k layer and a work-function (WF) layer or a WF structure used in the second gate 34.
  • the second structure 812, covering the first structure 612 can include a WF layer and a blocking layer.
  • the WF layer can adjust the work-function and affect a threshold voltage of the first gate 32, and can include AlTiC and AlTiO.
  • the WF layer can include any suitable work function materials and is not limited to AlTiC and AlTiO.
  • the blocking layer can have any suitable materials, such as TiN, to prevent diffusion between the WF layer and the third structures 1312.
  • the third structure 1312, covering the second structure 812 can include any suitable one or more conductive materials as a gate fill, such as a transition metal including Ru.
  • the second gate 34 includes a first structure 614, a WF structure 714, a second structure 814, and a third structure 1714.
  • the first structure 614, the second structure 814, and the third structure 1714 of the second gate 34 can be identical to the first structure 612, the second structure 812, and the third structure 1312 of the first gate 32, respectively.
  • the WF structure 714 can be inserted between the first structure 614 and the second structure 814.
  • the WF structure 714 can include AlTiN.
  • the WF structure 714 can include any suitable work function materials and is not limited to AlTiN.
  • the channels refer to a plurality of channels including the first to the fourth channels 22-25.
  • the first structures refer to a plurality of first structures including the first structures 612 and 614.
  • the WF structures refer to a plurality of WF structures including the WF structure 714.
  • the second structures refer to a plurality of second structures including the second structures 812 and 814.
  • the third structures refer to a plurality of third structures including the third structures 1312 and 1714.
  • Figs. 5-21 show examples of schematic views of various intermediary steps of a manufacturing process according to some embodiments of the disclosure.
  • the semiconductor apparatus 400 is fabricated by the manufacturing process. Referring to Fig. 5 when the manufacturing process starts, sources and drains of FETs in the semiconductor apparatus 400 are manufactured and metalized. The channels sandwiched between the gate low- k spacers 15, located on adjacent structures 18, are exposed. Residual FIN dielectric liner 510 can facilitate formation of the first to the fourth channels 22-25. .
  • a first example is used to illustrate a manufacturing process.
  • the integration flow starts with opening of a replacement gate where there are upper pFET nanowires/nanosheets and lower nFET nanowires/nanosheets.
  • the nFET is placed over the pFET.
  • the nanowires are open within the replacement gate and are sealed by a gate low-k spacer. Further beyond the gate low-k spacer is the upper and lower source and drains which are activated and metalized.
  • the CFET device has power rails that have been positioned below the active device. For the example shown below, the perspective view shows two side-by-side standard cells.
  • a CFET replacement gate is opened showing the floating upper and lower channel nanowires / nanosheets that are sealed at both ends of the opened replacement gate by the gate low-k spacer 15.
  • the upper channel nanowires/nanosheets correspond to the second channel 24.
  • nanowires/nanosheets correspond to the first channel 22.
  • the manufacturing process is configured to form split gates based on the exposed channels and to further form the conductive traces and routing tracks.
  • trenches such as the trenches 1330 and 1720(3) are formed in the third structures to separate adjacent gates, to stagger the split gates, and the like.
  • the trenches can be deep.
  • split gates such as the first gate 32 and the second gate 34, are physically and electrically separated.
  • the challenges described above can be addressed by implementing a series of selective depositions of gate materials over the previous gate materials or channels including selective deposition of high-k films directly onto silicon, SiGe, Ge channels.
  • the high-k films can include HfO.
  • the high-k films can include any high-k films used for established HKMG (high-k metal gate) devices.
  • a gate oxide layer can be grown or deposited through the high-k film after the selective deposition of the high-k film directly on the silicon, SiGe, or Ge channels is completed.
  • selectively depositing various work function and liner metals such as materials used in the barrier layer of the first structures, the second structures, the WF structures selectively on other conductors and on high-k films without deposition onto dielectric materials such as the gate low-k spacer can also be used.
  • films for gate-all-around metallization such as materials used in the second structures include but are not limited to TiN, TaN, TiAl, Ru, TiON, and the like.
  • one or more conductive materials having anisotropic etching property in the third structures can be used.
  • a bottom-fill deposition of one or more conductive materials used in the third structure can be used.
  • a method of deposit gate metals described above through bottom-fill deposition methods can be used to simplify the full integration process.
  • Anisotropic and selective etching process in forming trenches can be used.
  • Another method includes selective deposition of dielectric materials over conductive materials of the lower gates.
  • the dielectric materials or the dielectric separation layer can be used to physically separate the lower metalized gates from the upper metalized gates.
  • Such dielectric materials can include, but are not be limited to, SiO, SiCO, SiCN, SiN, SiOCN, SiC, SiON, AlO, HfO, on metal surface such as Ru or other gate metals.
  • a split gate structure is formed through direct anisotropic etching of the third structure of the gates, or the gate metal, such as Ruthenium.
  • the lower gate can optionally be staggered with respect to the upper gate, as shown in Fig. 2A-2B, or as shown in Fig. 1 A-1B and Fig. 4.
  • the series of selective depositions of gate materials can be used to prevent shorting the split gates.
  • a current gate material can be selectively deposited on a previous gate material or channels where a deposition rate on the previous gate material or channels is much larger than a deposition rate on the dielectric materials including the gate low-k spacer 15, the interconnect caps 14, the STIs 12, the residual FIN dielectric liner 510 embedded within the low-k spacer 15, and the like.
  • a ratio of the deposition rate on the previous gate material over the deposition rate on the dielectric materials can be 10: 1.
  • the small amount of the current gate materials when a small amount of the current gate materials is deposited on the dielectric materials, the small amount of the current gate materials can be removed from the dielectric materials without affecting the current gate materials over the previous gate materials or channels, for example, by an etching process. Therefore, a selective deposition of the current gate materials can be followed by an etching process that removes the small amount of the current gate materials over the dielectric materials. Additionally or alternatively, the selective deposition can be done in a sequential manner in which multiple periods of selective depositions are followed by respective periods of etching processes in order to provide a selective deposition. In another example, the deposition rate on the dielectric materials can be minimal and set to zero, and thus, an etching process can be omitted.
  • the series of selective depositions of gate materials can include a first, a second, a third, and a fourth selective deposition.
  • the first selective deposition the high-k layer is selectively deposited over the semiconductor materials forming the channels, such as Si, SiGe, and/or the like.
  • the barrier layer is selectively deposited over the high-k layer.
  • the WF structure is selectively deposited over the barrier layer.
  • the fourth selective deposition the second structure is selectively deposited over the barrier layer or the WF structure.
  • an etching process can follow the first, the second, the third, and the fourth selective deposition, respectively to remove a small amount of gate materials deposited over the dielectric materials.
  • one or more of the series of selective depositions can be done in a sequential manner in which multiple periods of selective depositions are followed by respective periods of etching processes.
  • the high-k layer can be selective to the channel material (e.g., either Si, SiGe, or Ge) and not to other dielectric materials within a replacement gate (such as low-k gate spacer 15, filled-in blocks within a gate, or dielectric caps such as the interconnect caps 14 overtop metalized contacts).
  • a replacement gate such as low-k gate spacer 15, filled-in blocks within a gate, or dielectric caps such as the interconnect caps 14 overtop metalized contacts.
  • the high- k layer is deposited through ALD that not only deposits over the channel material (e.g, either Si, SiGe, or Ge), but along the surface of the gate low-k spacer 15 as well as any cut surfaces within the gate.
  • Such non-selective deposition can cause shorting between the upper gate and lower gate of split gates because the high-k layer is to be selectively removed in the intended separation region between upper and lower gates without removing any material from the upper gate.
  • selective ALD herein addresses the issue by not depositing any high-k layer in the area between the intended gates.
  • gate metals such as liners and nFET and pFET work function metals (such as materials used in the barrier layer of the first structures, the second structures, the WF structures on the high-k layer and other conductive or metal- containing materials is used.
  • work function metals such as materials used in the barrier layer of the first structures, the second structures, the WF structures on the high-k layer and other conductive or metal- containing materials.
  • all other gate metals will thus selectively deposit on the channel as well and not along the gate low-k spacer or any dielectric cuts already formed within the gate. Such a technique prevents shorting between upper and lower intended gates.
  • an etching process can be used to remove the one or more conductive materials of the third structures.
  • the etching process can be anisotropic where a vertical etching rate along the first direction 10 in Fig. 4 is much larger than a horizontal etching rate within a plane perpendicular to the first direction 10. Therefore, one or more conductive materials having anisotropic etching property can be used in the third structures.
  • transition metals such as Ru, having an anisotropic etching property, can be used to form the third structures.
  • the etching process can also be selective where an etching rate of the one or more conductive materials is much larger than an etching rate of the dielectric materials and previous gate materials.
  • the dielectric materials can include the gate low-k spacer 15, the interconnect caps 14, the dielectric separation layer 1410, and the like.
  • the previous gate materials can include the first structures, the WF structures, and the second structures.
  • a bottom-fill deposition of one or more conductive materials used in the third structure can be implemented to simplify the
  • a bottom-fill deposition of one or more transition metals can be used to form the third structures of the lower gates where the lower gates are filled with the one or more transition metals having minimal voids.
  • the bottom-fill deposition can be implemented using chemical vapor deposition (CVD).
  • CVD chemical vapor deposition
  • an etching process can be used to remove the small amount of the one or more transition metals in the upper gates.
  • the etching process can be an isotropic etching process, such as a CERTAS platform of etch equipment manufactured by Tokyo Electron Ltd.
  • the selective deposition of the dielectric separation layer 1410 over conductive materials of the lower gates can be used to physically and electrically separate split gates, such as the first gate 32 and the second gate 34.
  • a deposition rate on the conductive materials of the lower gates is much larger than a deposition rate on the previous gate materials and the dielectric materials.
  • a ratio of the deposition rate on the conductive materials over the deposition rate on the previous gate materials and the dielectric materials can be 10: 1.
  • the deposition rate on the previous gate materials and the dielectric materials can be minimal and set to zero.
  • the small amount of the dielectric separation layer 1410 that is deposited on the previous gate materials and the dielectric materials can be removed without affecting the dielectric separation layer 1410 over the lower gates, for example, by an etching process. Therefore, a selective deposition of the dielectric separation layer 1410 can be followed by an etching process. Alternatively, a bottom-fill deposition of the dielectric separation layer 1410 can be used.
  • a bottom -up deposition of the dielectric separation layer 1410 such as SiO can be used to separate, for example, the gates 32 and 34, where a higher amount of the dielectric material, such as SiO is deposited over the gate 32 to form the dielectric separation layer 1410 as compared to the gate low-k spacers 15 and the second structure 814. Therefore, a selective isotropic etch can be used to remove the dielectric materials from the gate low-k spacers 15 and the second structure 814 with minimal effect on the dielectric separation layer 1410 between the gates 32 and 34.
  • a method includes filling in a gate with a metal, for example, through CVD, bottom-fill CVD, PVD, or the like, that can be easily recessed with excellent selectivity to the final gate metal (such as the blocking layer of the third structures) that is part of the gate-all-around deposition, for example, TiN.
  • a metal for example, through CVD, bottom-fill CVD, PVD, or the like
  • the gate filling metal is a transition metal such as Ru using the CERTAS etch platform developed by Tokyo Electron Ltd.
  • the purpose of the etch- selective isotropic recess is to fill in the patterned upper and lower individual gates and then to recess the filling metal down below the upper gate before growing a dielectric film (or the dielectric separation layer 1410) which can separate the upper and lower gates from one another.
  • An alternative method herein is a bottom-fill CVD deposition of a transition metal such as Ru that can fill the lower gate entirely and the upper gate partially.
  • a vapor-phase etch process e.g. using CERTAS
  • isotropic etch is then used to clean off the transition metal fill or Ru from the intended upper gate regions.
  • a dielectric film such as the dielectric separation layer 1410 can be selectively deposited directly on a conductive surface such as that of the transition metal such as Ru.
  • transition metal such as Ru is recessed down to define the lower gate, a dielectric film is then deposited onto the surface of the transition metal such as Ru and not along the final gate metal such as TiN that is on the upper gate.
  • the dielectric film is also not deposited on other dielectric surfaces such as the low-k gate spacer or dielectric filled cuts within a metal gate.
  • a bottom-fill deposition of dielectric barrier or a quasi- selective deposition process can be implemented where the bottom of the recessed metal gate can have a higher amount deposition of the dielectric barrier compared to sidewalls or along the upper gate.
  • a selective isotropic etch can be used to remove the dielectric barrier from the sidewalls or along the upper gate while preserving the amount of the dielectric barrier at the bottom of the recessed gate.
  • the manufacturing process can fabricate the first structures of the split gates simultaneously. Similarly, the second structures, and the third structures of the split gates can be fabricated simultaneously.
  • the WF structures are fabricated over the upper gates. For purposes of clarity, the description is given for the first gate 32 except for describing the WF structures.
  • the first structures such as the first structures 612 and 614, can be formed over the channels, such as the first channel 22 and second channel 24,
  • the first structures include the high-k layer and the barrier layer.
  • the high-k layer can include any suitable material system and structure.
  • the high-k layer can include dielectric material having a high dielectric constant, for example, greater than that of silicon oxide (3.9).
  • the high-k layer can be HfO.
  • the first selective deposition is used to form the high-k layer.
  • the high-k layer is selectively deposited over semiconductor materials, such as Si, Ge, SiGe, and the like.
  • the first selective deposition can be implemented using a selective atomic layer deposition (ALD) on the semiconductor materials.
  • ALD selective atomic layer deposition
  • the high-k layer is deposited over the channels and the substrate strips 11.
  • the small amount of high-k layer can be removed from the dielectric materials without affecting the high-k layer over the semiconductor materials using, for example, an etching process.
  • an interfacial layer such as Si0 2
  • the interfacial layer can include a dielectric material such as Si0 2 , HfSiO, SiON, and the like.
  • the interfacial layer can be formed by chemical oxidation, thermal oxidation, ALD, CVD, and the like.
  • a gate oxide layer can be grown or deposited through the high-k film after the selective deposition of the high-k film directly on the silicon, SiGe, or Ge channels is completed.
  • the barrier layer can be selectively deposited over the high-k layer.
  • the barrier layer can include any material system and structure to prevent diffusion between the high-k layer and the WF layer.
  • the barrier layer can include TiN.
  • a small amount of barrier layer over the dielectric materials can be removed without affecting the barrier layer over the semiconductor materials.
  • a high-k layer such as HfO directly onto the nFET and pFET channels (in an example, a nFET channel includes Si and a pFET channel includes SiGe) and not on the dielectric materials such as the gate low-k spacers 15, exposed cap materials over source/drain region, the STIs 12, the interconnect caps 14 over the buried power rails 13, and the like.
  • the first TiN layer is then selectively deposited over the high-k layer and not on the dielectric materials.
  • Conventional ALD can be used for gate-all-around metallization.
  • High-k and TiN layers can be deposited along surfaces of the gate low-k spacers 15 as well as along the channels.
  • the presence of metal along the gate low-k spacers 15 can lead to shorting between the individual pFET and nFET gates down-stream in the integration. Accordingly, using selective deposition capability to deposit the high-k layer directly on Si, SiGe, or Ge channels is beneficial as well as the ability to deposit gate metals directly on top of other gate metals.
  • the WF structure 714 can be formed over the channels of the upper gates, such as the second channel 24.
  • the channels of the lower gates can be blocked using, for example, a non-conductive fill material 710 recessed to a first recess level 715 between the first channel 22 and the second channel 24.
  • the non-conductive fill material 710 is spin-on carbon (SoC).
  • SoC spin-on carbon
  • the WF structure 714 can be selectively deposited over the barrier layer using the third selective deposition.
  • the WF structure 714 can adjust the work-function of the upper gates.
  • the WF structure 714 includes TaN followed by TiN.
  • the third selective deposition can be implemented using a selective ALD. Similarly, a small amount of WF structures over the dielectric materials can be removed without affecting the WF structures over the first structures. [0096] Referring to Fig.
  • blocking of a lower nFET gate with non- conductive fill material such as SoC and recessed down to a certain height, such as the first recess level 715, of lower channel followed by selective deposition of pFET gate metals (TaN / TiN) onto the exposed TiN already on the pFET channel can be implemented.
  • the second structures can be selectively deposited over the first structures of the lower gates, and the second structures can be selectively deposited over the WF adjustment structures of the upper gates.
  • the second structures 812 and 814 include the WF layer, such as AlTiC and AlTiO, and the blocking layer, such as TiN.
  • the WF layer such as AlTiC and AlTiO
  • the blocking layer such as TiN.
  • a small amount of the second structures over the dielectric materials can be removed without affecting the second structures over the first structures or the WF structures.
  • the first structures, the WF structures, and the second structures are formed over the channels, and are not formed over the dielectric materials, thus, preventing shorting the split gates.
  • one or more etching processes can be used in one or more of the first, the second, the third, and the fourth selective depositions, respectively to remove a small amount of gate materials deposited over the dielectric materials.
  • the upper pFET gate metals there are several options of how the upper pFET gate metals are treated. Because the downstream integration, in some embodiments, metalizes the lower gate to be metalized with transition metals including Ru before selectively depositing a dielectric layer (or dielectric separation layer 1410) to isolate the lower gate from the upper gate, a manner of selective deposition of the dielectric layer can be identified. For an embodiment of a dielectric material that grows equally on transition metal as well as on the TiN of the upper gate, suitable process steps can be executed. The non-conductive fill is again deposited into the gate and recessed down to the lower gate level. A particular type of dielectric material is selectively grown on the surface of the TiN on the upper gate.
  • the non-conductive filling material is removed from the bottom gate.
  • the dielectric material on the upper gate metals can be selected to provide a certain film difference in order that a dielectric material is grown selectively on the transition metal fill, but not on the TiN of the upper gate.
  • the dielectric material deposited can be removed by, for example, vapor-phase etch or through atomic-layer etching before the upper gate is metalized.
  • the deposition amount on the transition metal surface can be adjusted to be significantly more than the dielectric material initially deposited on the TiN surface so that when a simple atomic layer etch is done, there will be an adequate amount of dielectric material separating the upper gate from the lower gate.
  • the choice of Ru for the lower and upper gates allows for direct anisotropic etch which is not common to other gate metals.
  • the choice of Ru for the metal gate fills enables the split gate configuration.
  • the direct etched patterning into the Ru can be simple cuts to define gate separations, or the cuts can be more extensive in order to provide a staggered pattern for the lower gate relative to the upper gate. In embodiments used in the first example, simple gate cuts are shown that can isolate the lower gates in adjacent cells.
  • Figs. 9-10 show steps related to forming the common gates.
  • the third structures of the common gates and the third structures of the split gates can include different materials.
  • the third structures of the common gates and the split gates can include the same materials.
  • the third structures of the common gates and the split gates including the same materials is used as an example, however, the disclosure can be suitably modified to apply to the third structures of the common gates and the split gates including different materials.
  • one or more conductive materials 910 of the third structures are deposited within the regions l9(l)-(3).
  • transition metals such as Ru, having an anisotropic etching property, can be used to form the third structures.
  • the third structures of the common gates are formed within the regions 19(3), followed by covering the third structures of the common gates with common gate caps 1010.
  • the common gate caps 1010 can include any suitable dielectric materials and structure that can isolate the common gates.
  • the common gate caps 1010 include SiN.
  • the one or more conductive materials 910 correspond to gate metal fill using transition metal such as Ru.
  • transition metal such as Ru.
  • the top of the common gates is recessed and capped with the common gate caps 1010 such as SiN.
  • Figs. 11-13 show steps of forming the third structures of the lower gates, such as the third structure 1312 of the first gate.
  • the one or more suitable conductive materials 910 can be recessed to a second recess level 1115.
  • the second recess level 1115 and the first recess level 715 are identical.
  • the selective etching process can be used in order not to etch the dielectric materials including the gate low-k spacer 15 and other gate structures including the second structures, thus, preserving properties, such as the work-function, of the upper gates.
  • the selective etching process can be selective plasma etching implemented using, for example, a Certas equipment manufactured by Tokyo Electron Ltd.
  • the Ru gate metal is isotropically recessed with high selectivity to the pFET gate metals and the low-k gate spacer 15 using a vapor-phase etch process.
  • chemistry used in the vapor-phase etch process is selected not to etch the pFET gate metals, the gate metals wrapping around the channel, work function materials/structures, and the like.
  • one or more patterning materials 1210 such as SoC are formed on top of the semiconductor apparatus 400. Patterns 1230 are then generated. Referring to Fig. 12, in the first example, the upper replacement gate is filled with a patterning film corresponding to the one or more patterning materials 1210 where gate cuts intended for the bottom gate are patterned.
  • Fig. 13 illustrates an embodiment where the patterns 1230 are transferred to form the third structures of the lower gates including the third structure 1312 of the first gate 32.
  • the trench 1330 can have a large aspect ratio of a depth 1331 over a width 1332.
  • the anisotropic etching process can be used to form the trench 1330, thus separating adjacent gates, such as the first gate 32 and the third gate 33 of different standard cells.
  • the etching process is also selective in order not to etch the dielectric materials including the gate low-k spacer 15, as described above.
  • the selective etching process can be selective plasma etching implemented using, for example, a CERTAS etching equipment platform manufactured by Tokyo Electron Ltd.
  • the lower gates are formed. Referring to Fig. 13, in the first example, the patterned gate cuts are then transferred directly into the lower gates.
  • the dielectric separation layer 1410 including one or more dielectric materials can be formed to physically and electrically separate split gates, such as the first gate 32 and the second gate 34.
  • the selective deposition of the dielectric separation layer 1410 over conductive materials of the lower gates can be used.
  • the conductive materials can include a transition metal such as Ru.
  • the one or more dielectric materials can also be formed in the trenches (e.g., the trench 1330 in Fig. 13) between adjacent lower gates, such as the first gate 32 and the third gate 33.
  • a width of the trenches can depend on one or more dielectric constants of the one or more dielectric materials used to fill the trenches.
  • the width of the trenches can be as small as 5nm.
  • the width 1332 of the trench 1330 between the adjacent gates 32 and 33 can be equal to a separation between the routing tracks 2220(5) and 2220(6).
  • the separation between the routing tracks 2220(5) and 2220(6) can be 1/2 of a critical metal pitch, for example, between 10 and l6nm.
  • dielectric material corresponding to the dielectric separation layer 1410 is selectively deposited overtop the recessed and patterned Ru in the lower gates.
  • the TiN on the pFET wrap-around gate can be deposited with a dielectric in order to have the selective deposition on the interface of Ru.
  • Selective deposition of dielectric on metal also exhibits certain conformity within the upper replacement gate, but the deposition at the bottom of the opened trench is much higher than along the sidewall of the trench, and thus, an isotropic dielectric etch may be subsequently executed to keep the dielectric at the exposed surfaces of Ru.
  • Figs. 15-17 show an embodiment of steps of forming the third structures of the upper gates, such as the third structure 1714 of the third gate 34.
  • one or more conductive materials having anisotropic etching property can be used.
  • transition metals such as Ru
  • the one or more conductive materials, such as transition metals 1510 including Ru can be deposited within the regions l9(l)-(2) on top of the dielectric separation layer 1410.
  • upper gates are metalized with Ru or other transition metal that can be directly etched anisotropically.
  • a patterning film 1610 such as SoC, can be formed on top of the semiconductor apparatus 400.
  • Patterns l620(l)-(3) can be formed.
  • upper gates patterning includes gate cuts as well as the staggering pattern that enables direct connection to be formed from the lower gates to the respective routing tracks.
  • the patterns l620(l)-(3) are transferred to form trenches l720(l)-(3).
  • the one or more conductive materials 1510 can be etched by an anisotropic and selective etching process to form the trenches l720(l)-(3).
  • the third structures of the upper gates such as the third structure 1714 of the second gate 34, are formed, and thus, the split gates 32 and 34 and the split gates 33 and 35 are formed, respectively.
  • the upper gate patterning is transferred to the upper gate Ru metal.
  • Direct anisotropic etching of Ru can enable the staggering or stair-casing of the upper and lower gates with respect to one another.
  • a lower gate can have access to up to a minimum of two routing tracks depending on how the upper gate is patterned (left-hand or right-hand orientation with respect to the lower gate).
  • An upper gate in the first example can have access to up to three routing tracks.
  • the first structures 612 and 614, the WF structure 714, and the second structures 812 and 814 have a relatively lower conductance than that of the third structures 1312 and 1714, and are referred to as low conductance structures of the gates 32 and 34.
  • the low conductance structures can be formed around the first and second channels 22 and 24, respectively, and not on sidewalls of the gates 32 and 34 because the low conductance structures can be formed by the series of selective depositions.
  • the third structures 1312 and 1714 having a high conductance are formed around the first and second channels 22 and 24 and on the sidewalls of the gates 32 and 34, thus, improving conductance of the gates 32 and 34, respectively.
  • Figs. 18-21 and Fig. 4 show an embodiment of steps to form separate conductive traces for the split gates, and to connect the separating conductive traces to respective routing tracks.
  • a dielectric material 1810 is used to fill gaps between the FETs.
  • dielectric material corresponding to the dielectric material 1810 is used to fill between the metal gates.
  • Fig. 19 shows that the dielectric material 1810 is recessed to a third recess level 1915.
  • the third recess level 1915 is within the upper gates and is above the channels of the upper gates.
  • a gate cap 1910 is formed above the upper gates, for example, to provide self-alignment when forming the conductive traces.
  • the gate cap 1910 can be SiN where an etch rate of SiN can be significantly different from an etch rate of the low-k gate spacer 15, the interconnect caps 14, and the like.
  • the dielectric fill within the metal gate is recessed and a common gate cap is placed within standard cells.
  • the common gate cap can provide self-alignment for the placement of via-to-gate and via-to-source/drain.
  • a single gate cap material such as SiN
  • etch selectivity to the gate low-k spacers 15 and to caps placed over metal contacts (such as SiO/ SiC/ SiCO/ SiCN).
  • Fig. 20 shows an example where patterning material 2010 is formed over the gate cap 1910. Further, channels 2020(l)-(2) connecting the patterning material 2010 to the lower gates and the upper gates are formed. In an example, a selective etching process can be used to form the channels 2020(l)-(2). Referring to Fig. 20, in the first example, via-to-upper gate and via-to-lower gate patterning and transfer through the gate dielectric selective to the gate low-k spacer and to the cap materials are used over the metal contact are implemented.
  • the dielectric fill material used in the metal gate is not a material used for capping the metal contacts.
  • the gate cap is opened selectively to the metal contact cap and gate low-k spacers and punched through.
  • the etch can then be transitioned to that of the dielectric fill material so that the via-to-lower-gate can make contact to the lower gate without further erosion of the gate low-k spacer or the metal contact cap.
  • Fig. 21 shows an embodiment where patterns 2120 are formed in the patterning material 2010.
  • the routing tracks 2220(l)-(6) and the conducting traces 2230(2)-(5) can be formed by depositing one or more conductive materials, such as transition metals including Ru.
  • Figs. 4-21 show various intermediary steps of the manufacturing process in one sequence, however, the manufacturing process can be implemented using any suitable sequence of the various intermediary steps.
  • the common gates can be formed after forming the split gates in Fig. 18.
  • the manufacturing process can be
  • M0 trench definition making contact from via-to-lower-gate, via-to- upper-gate, via-to-lower source/drain electrode and via-to-upper source/drain electrode to M0 can be implemented.
  • connections to the split gates can come from the initial metal layer.
  • Any suitable integration flows can be used in a manufacturing process to form the semiconductor apparatus 400 or other semiconductor devices.
  • An integration flows can include a plurality of the intermediate steps described in the disclosure executed in any suitable order.
  • one or more intermediary steps of the manufacturing process can be suitably modified for various situations.
  • an alternative manufacturing process can be employed. Referring to Fig. 8, the lower gates can be covered by a non- conductive filling material, such as SOC recessed to the first recess level 715. Subsequently, a first dielectric layer can be selectively formed over the second structures of the upper gates.
  • the non-conductive filling material can then be removed, for example, by an etching process that removes the non-conductive filling material selectively without removing the first dielectric layer.
  • the first dielectric layer can provide selectivity in the subsequent manufacturing process.
  • a bottom-fill deposition of the one or more conductive materials such as transition metals including Ru, can be implemented to form the third structures of the lower gates.
  • the bottom-fill deposition is selective such that the deposition of the one or more conductive materials over the first dielectric layer is minimal.
  • a selective deposition of the dielectric separation layer 1410 can be implemented, and thus, the deposition of the dielectric separation layer 1410 over the first dielectric layer is also minimal.
  • the one or more conductive materials and the dielectric separation layer 1410 over the first dielectric layer can be removed by, for example, a CERTAS etching process, or atomic-layer etching.
  • the lower gate is filled with a non-conductive filling material prior to deposition of transition metal such as Ru in order to expose the upper TiN on the upper gate-all-around structure.
  • a dielectric film is selectively deposited onto the TiN surface.
  • the non-conductive filling material can be removed from the lower gate prior to filling in the gate with transition metal and recess.
  • the dielectric film selectively deposited along the TiN surface is significantly less than the selective deposition to be done on the transition metal surface and is then removed through a vapor-phase selective etching along with a thin, controlled portion of the dielectric film selectively deposited along the surface of the transition metal.
  • Fig. 22 shows an exemplary process flow 2200 to form a semiconductor device according to an embodiment of the disclosure.
  • the process flow 2200 can be configured to form a first stack of CFETs and a third stack of CFETs.
  • the first stack of CFETs includes split gates, a first gate of the first FET, and a second gate of the second FET.
  • the third stack of CFETs includes split gates, a fifth gate of the fifth FET, and a sixth gate of the sixth FET.
  • each gate is connected to either a first routing track or a second routing track via a separated conductive trace.
  • Each routing track is connected to multiple gates where one gate is based on an nFET and another gate is based on a pFET.
  • the first stack of CFETs and the third stack of CFETs formed by the process flow 2200 are the first stack of FETs 398 and the second stack of FETs 399 shown in Figs. 3A-3C.
  • the first stack of CFETs and the third stack of CFETs formed by the process flow 2200 are the first stack of FETs (Fig. 4) and the third stack of FETs of the semiconductor apparatus 400, respectively.
  • the process flow 2200 is illustrated using the first stack of FETS and the third stack of FETs of the semiconductor apparatus 400, the disclosure can be suitably modified to apply to other scenarios.
  • the process flow 2200 starts at S2201 and proceeds to S2210.
  • the first stack of CFETs including the first FET and the second FET is formed, as shown in Fig. 5.
  • the third stack of CFETs including the fifth FET and the sixth FET is formed.
  • the first FET and the fifth FET are formed on a first plane
  • the second FET and the sixth FET are formed on a second plane above the first plane.
  • the second FET is stacked above the first FET
  • the sixth FET is stacked above the fifth FET.
  • sources and drains of FETs in the first stack and the second stack are manufactured and metalized.
  • the channels are exposed.
  • the channels are sandwiched between the gate low-k spacers 15 located on adjacent structures 18.
  • the residual FIN dielectric liner 510 can facilitate formation of the first to the fourth channels 22-25.
  • split gates are formed.
  • the first gate 32 of the first FET and the second gate 34 of the second FET form split gates in the region 19(1).
  • the second gate 34, formed on the second plane is stacked above the first gate 32 formed on the first plane.
  • the fifth gate of the fifth FET and the sixth gate of the sixth FET form split gates in the region 19(2).
  • the sixth gate, formed on the second plane is stacked above the fifth gate formed on the first plane.
  • the lower gates such as the first gate 32 and the fifth gate
  • the upper gates such as the second gate 34 and the sixth gate
  • the first structures can be formed on the lower gates and the upper gates simultaneously using the first and second selective depositions as shown in Figs. 6.
  • the WF structures can be formed on the upper gates as shown in Fig. 7 using the third selective deposition.
  • the second structures can be formed simultaneously on the lower gates and the upper gates using the fourth selective deposition as shown in Fig. 8.
  • the lower gates can be fabricated by using one or more conductive materials having anisotropic etching property as the third structures and by implementing the anisotropic and selective etching process, as shown in Figs. 11-13. Subsequently, the selective deposition of the dielectric separation layer 1410 can be implemented to physically and electrically separate the lower gates from the upper gates, as shown in Fig. 14. Similarly, the upper gates can be fabricated by using one or more conductive materials having anisotropic etching property as the third structures and by implementing the anisotropic and selective etching process, as shown in Figs. 15-18. The process flow 2200 then proceeds to S2230.
  • first routing track 2220(2) and the second routing track 2220(4) are formed, as shown in Figs. 19-21 and Fig. 4.
  • the first conductive trace 2230(2) is formed to connect the first gate 32 to the first routing track 2220(2)
  • the second conductive trace 2230(4) is formed to connect the second gate 34 to the second routing track 2220(4)
  • the fifth conductive trace is formed to connect the fifth gate to the second routing track 2220(4)
  • the sixth conductive trace is formed to connect the sixth gate to the first routing track 2220(2).
  • the process flow 2200 shows an embodiment of a process flow in one sequence of steps, however, the process flow can be implemented using any suitable sequence of steps.
  • the process flow 2200 can be implemented using the series of selective depositions of gate materials, using the one or more conductive materials having anisotropic etching property in the third structures, using the anisotropic and selective etching process in forming trenches, using the selective deposition of dielectric materials over the conductive materials of the lower gates, and the like.
  • the process flow 2200 is described using a stack of FETs such as the first stack of FETs in the semiconductor apparatus 400 where the upper gate has a smaller cross sectional area than that of the lower gate.
  • the process flow 2200 can be suitably adjusted to form a stack of FETs similar to the stack of FETs shown in Figs. 2A-2B and 3A-3C where the upper gate can have the same or larger cross sectional area than that of the lower gate.
  • the patterns 1230 in Fig. 12, the trenches 1330 in Fig. 13, the patterns 1620 in Fig. 16, and the trenches 1720 in Fig. 17 can be modified to form the stack of FETs shown in Figs. 2A- 2B and 3A-3C.
  • substrate or“target substrate” as used herein generically refers to an object being processed in accordance with the invention.
  • the substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a layer on or overlying a base substrate structure such as a thin film.
  • substrate is not limited to any particular base structure, underlying layer or overlying layer, patterned or un-patterned, but rather, is contemplated to include any such layer or base structure, and any combination of layers and/or base structures.
  • the description may reference particular types of substrates, but this is for illustrative purposes only.

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US12237332B2 (en) 2019-04-12 2025-02-25 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit
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TWI895561B (zh) * 2020-12-04 2025-09-01 日商東京威力科創股份有限公司 指叉式裝置堆疊
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US20190172828A1 (en) 2019-06-06
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US11444082B2 (en) 2022-09-13
CN111542923A (zh) 2020-08-14
JP7205045B2 (ja) 2023-01-17
TW201935661A (zh) 2019-09-01
US20210028169A1 (en) 2021-01-28
KR102596118B1 (ko) 2023-10-30
US10833078B2 (en) 2020-11-10
TWI784099B (zh) 2022-11-21

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